NAND: davinci: choose correct 1-bit h/w ECC reg

In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.

Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.

Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FFFFFF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d41579c9cefb9e96531508e6f0ac95ed641799b6..e8506ddd9bdde79aac0acf6c9cddbda1858b2290 100644 (file)
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -176,35 +176,35 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
 
 #ifdef CONFIG_SYS_NAND_HW_ECC
 
-static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
+static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
 {
-       u_int32_t       val;
+       u_int32_t       ecc = 0;
 
-       (void)__raw_readl(&(davinci_emif_regs->nandfecc[
+       ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
                                CONFIG_SYS_NAND_CS - 2]));
 
-       val = __raw_readl(&davinci_emif_regs->nandfcr);
-       val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
-       val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
-       __raw_writel(val, &davinci_emif_regs->nandfcr);
+       return ecc;
 }
 
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
+static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 {
-       u_int32_t       ecc = 0;
+       u_int32_t       val;
 
-       ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
+       /* reading the ECC result register resets the ECC calculation */
+       nand_davinci_readecc(mtd);
 
-       return ecc;
+       val = __raw_readl(&davinci_emif_regs->nandfcr);
+       val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
+       val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+       __raw_writel(val, &davinci_emif_regs->nandfcr);
 }
 
 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
                u_char *ecc_code)
 {
        u_int32_t               tmp;
-       const int region = 1;
 
-       tmp = nand_davinci_readecc(mtd, region);
+       tmp = nand_davinci_readecc(mtd);
 
        /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
         * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */