void pic_enable(void)
{
-
#if (UIC_MAX > 1)
/* Install the UIC1 handlers */
- irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt,
- 0);
- irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt,
- 0);
+ irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
+ irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
#endif
#if (UIC_MAX > 2)
- irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt,
- 0);
- irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt,
- 0);
+ irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
+ irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
#endif
#if (UIC_MAX > 3)
- irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt,
- 0);
- irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt,
- 0);
+ irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
+ irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
#endif
-
}
/* Handler for UIC interrupt */
void pic_irq_ack(unsigned int vec)
{
-
if ((vec >= 0) && (vec < 32))
mtdcr(uicsr, UIC_MASK(vec));
-#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1sr, UIC_MASK(vec));
-#endif
-#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2sr, UIC_MASK(vec));
-#endif
-#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3sr, UIC_MASK(vec));
-#endif
}
/*
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
-#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
-#endif
-#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
-#endif
-#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
-#endif
debug("Install interrupt for vector %d ==> %p\n", vec, handler);
}
void pic_irq_disable(unsigned int vec)
{
-
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
-#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
-#endif
-#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
-#endif
-#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
-#endif
-
}
{
if (c == '\n')
serial_putc('\r');
- while (in_be32(UARTLITE_STATUS) & SR_TX_FIFO_FULL);
- out_be32(UARTLITE_TX_FIFO, (unsigned char) (c & 0xff));
+ while (in_be32((void *)UARTLITE_STATUS) & SR_TX_FIFO_FULL);
+ out_be32((void *)UARTLITE_TX_FIFO, (unsigned char) (c & 0xff));
}
void serial_puts(const char * s)
int serial_getc(void)
{
- while (!(in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA));
- return in_be32(UARTLITE_RX_FIFO) & 0xff;
+ while (!(in_be32((void *)UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA));
+ return in_be32((void *)UARTLITE_RX_FIFO) & 0xff;
}
int serial_tstc(void)
{
- return (in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA);
+ return (in_be32((void *)UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA);
}
#endif /* CONFIG_MICROBLZE */
#ifndef XILINX_IRQ_H
#define XILINX_IRQ_H
-#define intc XPAR_INTC_0_BASEADDR
-#define ISR (intc+(0*4)) /* Interrupt Status Register */
-#define IPR (intc+(1*4)) /* Interrupt Pending Register */
-#define IER (intc+(2*4)) /* Interrupt Enable Register */
-#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */
-#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */
-#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */
-#define IVR (intc+(6*4)) /* Interrupt Vector Register */
-#define MER (intc+(7*4)) /* Master Enable Register */
+#define intc XPAR_INTC_0_BASEADDR
+#define ISR (intc + (0 * 4)) /* Interrupt Status Register */
+#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
+#define IER (intc + (2 * 4)) /* Interrupt Enable Register */
+#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
+#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
+#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
+#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
+#define MER (intc + (7 * 4)) /* Master Enable Register */
-#define IRQ_MASK(irq) (1<<(irq&0x1f))
+#define IRQ_MASK(irq) (1 << (irq & 0x1f))
-#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
+#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
#endif