}
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
 
        gd->cpu_clk = (gd->bus_clk * 2);
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
 
 #endif
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #ifdef CONFIG_SYS_I2C2_OFFSET
-       gd->i2c2_clk = gd->bus_clk;
+       gd->arch.i2c2_clk = gd->bus_clk;
 #endif
 #endif
 
 
        gd->cpu_clk = (gd->bus_clk * 3);
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
 
        }
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 }
 #endif
 #endif
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
 
        gd->cpu_clk = (gd->bus_clk * 2);
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
 
 
 /* Architecture-specific global data */
 struct arch_global_data {
+#ifdef CONFIG_FSL_I2C
+       unsigned long   i2c1_clk;
+       unsigned long   i2c2_clk;
+#endif
 };
 
 /*
        unsigned long   inp_clk;
        unsigned long   vco_clk;
        unsigned long   flb_clk;
-#endif
-#ifdef CONFIG_FSL_I2C
-       unsigned long   i2c1_clk;
-       unsigned long   i2c2_clk;
 #endif
        phys_size_t     ram_size;       /* RAM size */
        unsigned long   reloc_off;      /* Relocation Offset */
 
        gd->sdhc_clk = sdhc_clk;
 #endif
        gd->arch.core_clk = core_clk;
-       gd->i2c1_clk = i2c1_clk;
+       gd->arch.i2c1_clk = i2c1_clk;
 #if !defined(CONFIG_MPC832x)
-       gd->i2c2_clk = i2c2_clk;
+       gd->arch.i2c2_clk = i2c2_clk;
 #endif
 #if !defined(CONFIG_MPC8309)
        gd->arch.enc_clk = enc_clk;
        printf("  SEC:                 %-4s MHz\n",
               strmhz(buf, gd->arch.enc_clk));
 #endif
-       printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
+       printf("  I2C1:                %-4s MHz\n",
+              strmhz(buf, gd->arch.i2c1_clk));
 #if !defined(CONFIG_MPC832x)
-       printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
+       printf("  I2C2:                %-4s MHz\n",
+              strmhz(buf, gd->arch.i2c2_clk));
 #endif
 #if defined(CONFIG_MPC8315)
        printf("  TDM:                 %-4s MHz\n",
 
         */
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
        defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
-       gd->i2c1_clk = sys_info.freqSystemBus;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus;
 #elif defined(CONFIG_MPC8544)
        /*
         * On the 8544, the I2C clock is the same as the SEC clock.  This can be
         * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
         */
        if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
-               gd->i2c1_clk = sys_info.freqSystemBus / 3;
+               gd->arch.i2c1_clk = sys_info.freqSystemBus / 3;
        else
-               gd->i2c1_clk = sys_info.freqSystemBus / 2;
+               gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #else
        /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
-       gd->i2c1_clk = sys_info.freqSystemBus / 2;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #endif
-       gd->i2c2_clk = gd->i2c1_clk;
+       gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 #if defined(CONFIG_FSL_ESDHC)
 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
 
         * AN2919.
         */
 #ifdef CONFIG_MPC8610
-       gd->i2c1_clk = sys_info.freqSystemBus;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus;
 #else
-       gd->i2c1_clk = sys_info.freqSystemBus / 2;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #endif
-       gd->i2c2_clk = gd->i2c1_clk;
+       gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
        if (gd->cpu_clk != 0)
                return 0;
 
        u32 lbc_clk;
        void *cpu;
 #endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+               defined(CONFIG_MPC86xx)
+       u32 i2c1_clk;
+       u32 i2c2_clk;
+#endif
 };
 
 /*
 #if defined(CONFIG_FSL_ESDHC)
        u32 sdhc_clk;
 #endif
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
-       u32 i2c1_clk;
-       u32 i2c2_clk;
-#endif
 #if defined(CONFIG_QE)
        u32 qe_clk;
        uint mp_alloc_base;
 
 static unsigned int get_i2c_clock(int bus)
 {
        if (bus)
-               return gd->i2c2_clk;    /* I2C2 clock */
+               return gd->arch.i2c2_clk;       /* I2C2 clock */
        else
-               return gd->i2c1_clk;    /* I2C1 clock */
+               return gd->arch.i2c1_clk;       /* I2C1 clock */
 }
 
 void
 
 int i2c_set_bus_speed(unsigned int speed)
 {
-       unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
+       unsigned int i2c_clk = (i2c_bus_num == 1)
+                       ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
 
        writeb(0, &i2c_dev[i2c_bus_num]->cr);           /* stop controller */
        i2c_bus_speed[i2c_bus_num] =