Enable SDHCI interface on AP and CP0 in A80x0 DTS files
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Evan Wang <xswang@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
1 3 0 0 0 0 0 0 0 3 >;
};
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
+
&cpm_pinctl {
/* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins
status = "okay";
};
+&cpm_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sdhci_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&cps_pinctl {
/* MPP Bus:
* [0-11] RGMII0
status = "okay";
};
+/* uSD slot */
+&cpm_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sdhci_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&cpm_comphy {
/*
* CP0 Serdes Configuration: