--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky\r
+ * style project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds...and so on.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles an LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 200 ) )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* The LED toggled by the Rx task. */\r
+#define mainTASK_LED ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
+ * main.c.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+const unsigned long ulExpectedValue = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ vParTestToggleLED( mainTASK_LED );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ * http://www.freertos.org/a00110.html\r
+ *----------------------------------------------------------*/\r
+\r
+/* The array used as the heap is declared by the application to allow the\r
+__persistent keyword to be used. See http://www.freertos.org/a00111.html#heap_4 */\r
+#define configAPPLICATION_ALLOCATED_HEAP 1\r
+ \r
+#define configUSE_PREEMPTION 1\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */\r
+#define configTOTAL_HEAP_SIZE ( 5 * 1024 )\r
+#define configMAX_TASK_NAME_LEN ( 15 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configUSE_ALTERNATIVE_API 0\r
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0\r
+#define configENABLE_BACKWARD_COMPATIBILITY 0\r
+\r
+#if __DATA_MODEL__ == __DATA_MODEL_SMALL__\r
+ #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 110 )\r
+#else\r
+ #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 80 )\r
+#endif\r
+\r
+/* Hook function related definitions. */\r
+#define configUSE_TICK_HOOK 0\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+\r
+/* Software timer related definitions. */\r
+#define configUSE_TIMERS 0\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Event group related definitions. */\r
+#define configUSE_EVENT_GROUPS 0\r
+\r
+/* Run time stats gathering definitions. */\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. The IAR linker will remove unused functions\r
+anyway, so any INCLUDE_ definition that doesn't have another dependency can be\r
+left at 1 with no impact on the code size. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+#define INCLUDE_xTimerGetTimerTaskHandle 1\r
+#define INCLUDE_xTaskGetIdleTaskHandle 1\r
+#define INCLUDE_xQueueGetMutexHolder 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xEventGroupSetBitFromISR 0\r
+#define INCLUDE_xTimerPendFunctionCall 0\r
+#define INCLUDE_pcTaskGetTaskName 1\r
+\r
+/* Not using stats, so no need to include the formatting functions. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0\r
+\r
+/* Assert call defined for debug builds. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* The MSP430X port uses a callback function to configure its tick interrupt.\r
+This allows the application to choose the tick interrupt source.\r
+configTICK_VECTOR must also be set in FreeRTOSConfig.h to the correct\r
+interrupt vector for the chosen tick interrupt source. This implementation of\r
+vApplicationSetupTimerInterrupt() generates the tick from timer A0, so in this\r
+case configTICK__VECTOR is set to TIMER0_A0_VECTOR. */\r
+#define configTICK_VECTOR TIMER0_A0_VECTOR\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* TI includes. */\r
+#include "driverlib.h"\r
+\r
+/* Port/pin definitions. */\r
+#define partstNUM_LEDS 2\r
+const uint8_t ucPorts[ partstNUM_LEDS ] = { GPIO_PORT_P1, GPIO_PORT_P4 };\r
+const uint16_t usPins[ partstNUM_LEDS ] = { GPIO_PIN0, GPIO_PIN6 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue )\r
+{\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ if( xValue == pdFALSE )\r
+ {\r
+ GPIO_setOutputLowOnPin( ucPorts[ uxLED ], usPins[ uxLED ] );\r
+ }\r
+ else\r
+ {\r
+ GPIO_setOutputHighOnPin( ucPorts[ uxLED ], usPins[ uxLED ] );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ GPIO_toggleOutputOnPin( ucPorts[ uxLED ], usPins[ uxLED ] );\r
+ }\r
+}\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>MSP430</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>5</archiveVersion>\r
+ <data>\r
+ <version>27</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GoToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GoToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>DynDriver</name>\r
+ <state>430FET</state>\r
+ </option>\r
+ <option>\r
+ <name>dDllSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DdfFileSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>DdfOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DdfFileName</name>\r
+ <state>$TOOLKIT_DIR$\config\debugger\msp430fr5969.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>ProcTMS</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ProcMSP430X</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerDataModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IVBASE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CPUTAG</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>L092Mode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ENERGYTRACE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FETIPE</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>430FET</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <version>29</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CFetMandatory</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Erase</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EMUVerifyDownloadP7</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EraseOptionSlaveP7</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExitBreakpointP7</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PutcharBreakpointP7</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GetcharBreakpointP7</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>derivativeP7</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ParallelPortP7</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TargetVoltage</name>\r
+ <state>3.3</state>\r
+ </option>\r
+ <option>\r
+ <name>AllowLockedFlashAccessP7</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EMUAttach</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AttachOptionSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRadioProtocolType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRadioModuleTypeSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>EEMLevel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DiasbleMemoryCache</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NeedLockedFlashAccess</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UsbComPort</name>\r
+ <state>Automatic</state>\r
+ </option>\r
+ <option>\r
+ <name>FetConnection</name>\r
+ <version>4</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SoftwareBreakpointEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RadioSoftwareBreakpointType</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TargetSettlingtime</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AllowAccessToBSL</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OTargetVccTypeDefault</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCBetaDll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GPassword</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DebugLPM5</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LPM5Slave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRadioAutoManualType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExternalCodeDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCVCCDefault</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Retain</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jstatebit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RadioJtagSpeedType</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>memoryTypeSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>fuseBlowDisabledSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>eraseTypeSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DataSampleBpReservation</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>cycleCounterLevel</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>SIM430</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <version>4</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>SimOddAddressCheckP7</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CSimMandatory</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>derivativeSim</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SimPspConfigFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\test.psp.config</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\lcd\lcd.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>MSP430</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>17</archiveVersion>\r
+ <data>\r
+ <version>33</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OGCore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Hardware Multiplier</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AssemblerOnly</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGDouble</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/EC++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\lib\dlib\dl430xllfn.h</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\lib\dlib\dl430xllfn.r43</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>2</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float or long long.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a or A.</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectMenu</name>\r
+ <state>MSP430FR5969 MSP430FR5969</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackHeapOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackSize2</name>\r
+ <state>160</state>\r
+ </option>\r
+ <option>\r
+ <name>GHeapSize2</name>\r
+ <state>160</state>\r
+ </option>\r
+ <option>\r
+ <name>RadioDataModelType</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>GHeap20Size</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RadioHeapSizeType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RadioHardwareMultiplierType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RadioL092ModelType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Ropi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NoRwDynamicInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibThreads</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MathLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RadioCodeModelType</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEnableMpu</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GESupportMpu</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GELockMpu</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GENMIViolationMpu</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEAssertMpu</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEInfoReadMpu</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEInfoWriteMpu</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEInfoExecuteMpu</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEInfoAssertMpu</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEnableIpe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GESupportIpe</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GAssertIpe</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GLockIpe</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Math variant</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Math description</name>\r
+ <state>Default variants of cos, sin, tan, log, log10, pow, and exp.</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICC430</name>\r
+ <archiveVersion>4</archiveVersion>\r
+ <data>\r
+ <version>37</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>Pa082</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IObjPrefix2</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>00000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjUseModuleName</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjModuleName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCharIs</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCExt</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMigrationPreprocExtentions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IDoubleSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.r43</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCR4Utilize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCR5Utilize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCOverrideModuleTypeDefault</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRadioModuleType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRadioModuleTypeSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>newCCIncludePaths</name>\r
+ <state>$PROJ_DIR$\</state>\r
+ <state>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx</state>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\MSP430X</state>\r
+ <state>$PROJ_DIR$\..\Common\include</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OI430X</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ReduceStack</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Save20bit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerDataModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategy</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevelSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPUTAG</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeFunctions</name>\r
+ <state>CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCData16</name>\r
+ <state>DATA16</state>\r
+ </option>\r
+ <option>\r
+ <name>CCData20</name>\r
+ <state>DATA20</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIntvec</name>\r
+ <state>INTVEC</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCstack</name>\r
+ <state>CSTACK</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRamFuncCode</name>\r
+ <state>RAMFUNC_CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIsrCode</name>\r
+ <state>ISR_CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDifunct</name>\r
+ <state>DIFUNCT</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CROPI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CNoRwDynamicInit</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationNoSizeConstraints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCGuardCalls</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCGuardCallsSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerCodeModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>A430</name>\r
+ <archiveVersion>5</archiveVersion>\r
+ <data>\r
+ <version>14</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state>__DATA_MODEL_LARGE__</state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ADebugType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AMaxErrOn</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AMaxErrNum</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.r43</state>\r
+ </option>\r
+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OA1M</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AStdIncludes</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\MSP430X</state>\r
+ <state>$PROJ_DIR$</state>\r
+ </option>\r
+ <option>\r
+ <name>ACPUTAG</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XLINK</name>\r
+ <archiveVersion>4</archiveVersion>\r
+ <data>\r
+ <version>29</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>XOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>RTOSDemo.d43</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFormat</name>\r
+ <version>11</version>\r
+ <state>33</state>\r
+ </option>\r
+ <option>\r
+ <name>FormatVariant</name>\r
+ <version>8</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>SecondaryOutputFile</name>\r
+ <state>(None for the selected format)</state>\r
+ </option>\r
+ <option>\r
+ <name>XDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AlwaysOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlapWarnings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NoGlobalCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SegmentMap</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ListSymbols</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>XIncludes</name>\r
+ <state>$TOOLKIT_DIR$\LIB\</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleStatus</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XclOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFile</name>\r
+ <state>$TOOLKIT_DIR$\config\linker\lnk430fr5969.xcl</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RangeCheckAlternatives</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressAllWarn</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressDiags</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleLocalSym</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XHardwareMul</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IncludeSuppressed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleSummary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkStackSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkCodeModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabel</name>\r
+ <state>__program_start</state>\r
+ </option>\r
+ <option>\r
+ <name>DebugInformation</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RuntimeControl</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IoEmulation</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XcRTLibraryFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OXLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XLibraryHeap</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AllowExtraOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenerateExtraOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFile</name>\r
+ <state>RTOSDemo.a43</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFormat</name>\r
+ <version>11</version>\r
+ <state>23</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraFormatVariant</name>\r
+ <version>8</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>xcOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ListOutputFormat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BufferedTermOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverlaySystemMap</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>XLibraryHeap20</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcUnitSize</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LinkMathLib</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkThreadsSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkMPU</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkIPE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkLogEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkLogInputFiles</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkLogModuleSelection</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkLogPrintfScanf</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkLogSegmentSelection</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkLogStackDepth</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkStackUsageEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkControlFiles</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkCallGraphFileEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XlinkCallGraphFileName</name>\r
+ <state>$LIST_DIR$\$PROJ_FNAME$.call_graph.cgx</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XAR</name>\r
+ <archiveVersion>4</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>XAROutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XARInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ULP430</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CUTest</name>\r
+ <state>-I$TOOLKIT_DIR$\inc</state>\r
+ <state>-@$TOOLKIT_DIR$\bin\iar.cmd</state>\r
+ <state>-@$PROJ_DIR$\source.txt</state>\r
+ <state>-@$PROJ_DIR$\include.txt</state>\r
+ <state>--preinclude=$PROJ_DIR$\IAR_ULPAdvisor_Defs.h</state>\r
+ </option>\r
+ <option>\r
+ <name>ULPRules</name>\r
+ <version>0</version>\r
+ <state>1111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>ULPEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$PROJ_FNAME$.ulp</state>\r
+ </option>\r
+ <option>\r
+ <name>ULPStatus</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Blinky_Demo</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Blinky_Demo\main_blinky.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>driverlib</name>\r
+ <group>\r
+ <name>MSP430FR5xx_6xx</name>\r
+ <group>\r
+ <name>deprecated</name>\r
+ <group>\r
+ <name>CCS</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\deprecated\CCS\msp430fr5xx_6xxgeneric.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>IAR</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\deprecated\IAR\msp430fr5xx_6xxgeneric.h</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <group>\r
+ <name>inc</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\inc\hw_memmap.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\inc\hw_regaccess.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\inc\hw_types.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\inc\version.h</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\adc12_b.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\adc12_b.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\aes256.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\aes256.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\comp_e.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\comp_e.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\crc.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\crc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\crc32.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\crc32.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\cs.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\cs.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\dma.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\dma.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\driverlib.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\esi.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\esi.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_a_spi.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_a_spi.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_a_uart.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_a_uart.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_b_i2c.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_b_i2c.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_b_spi.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_b_spi.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\framctl.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\framctl.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\gpio.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\gpio.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\lcd_c.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\lcd_c.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\mpu.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\mpu.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\mpy32.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\mpy32.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\pmm.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\pmm.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\ram.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\ram.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\ref_a.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\ref_a.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\rtc_b.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\rtc_b.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\rtc_c.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\rtc_c.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\sfr.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\sfr.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\sysctl.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\sysctl.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\timer_a.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\timer_a.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\timer_b.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\timer_b.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\tlv.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\tlv.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\wdt_a.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\driverlib\MSP430FR5xx_6xx\wdt_a.h</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS_Source</name>\r
+ <group>\r
+ <name>portable</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\MSP430X\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\MSP430X\portext.s43</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\event_groups.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\FRAMLogMode.c</name>\r
+ <excluded>\r
+ <configuration>Debug</configuration>\r
+ </excluded>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\FRAMLogMode.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\FreeRTOSConfig.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LEDs.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LiveTempMode.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LiveTempMode.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\low_level_init_iar.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.h</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// adc12_b.c - Driver for the adc12_b Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup adc12_b_api adc12_b\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_ADC12_B__\r
+#include "adc12_b.h"\r
+\r
+#include <assert.h>\r
+\r
+bool ADC12_B_init(uint16_t baseAddress,\r
+ ADC12_B_initParam *param)\r
+{\r
+ //Make sure the ENC bit is cleared before initializing the ADC12\r
+ HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC;\r
+\r
+ bool retVal = STATUS_SUCCESS;\r
+\r
+ //Turn OFF ADC12B Module & Clear Interrupt Registers\r
+ HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12ON + ADC12ENC + ADC12SC);\r
+ HWREG16(baseAddress + OFS_ADC12IER0) &= 0x0000; //Reset ALL interrupt enables\r
+ HWREG16(baseAddress + OFS_ADC12IER1) &= 0x0000;\r
+ HWREG16(baseAddress + OFS_ADC12IER2) &= 0x0000;\r
+ HWREG16(baseAddress + OFS_ADC12IFGR0) &= 0x0000; //Reset ALL interrupt flags\r
+ HWREG16(baseAddress + OFS_ADC12IFGR1) &= 0x0000;\r
+ HWREG16(baseAddress + OFS_ADC12IFGR2) &= 0x0000;\r
+\r
+ //Set ADC12B Control 1\r
+ HWREG16(baseAddress + OFS_ADC12CTL1) =\r
+ param->sampleHoldSignalSourceSelect //Setup the Sample-and-Hold Source\r
+ + (param->clockSourceDivider & ADC12DIV_7) //Set Clock Divider\r
+ + (param->clockSourcePredivider & ADC12PDIV__64)\r
+ + param->clockSourceSelect; //Setup Clock Source\r
+\r
+ //Set ADC12B Control 2\r
+ HWREG16(baseAddress + OFS_ADC12CTL2) =\r
+ ADC12RES_2; //Default resolution to 12-bits\r
+\r
+ //Set ADC12B Control 3\r
+ HWREG16(baseAddress + OFS_ADC12CTL3) =\r
+ param->internalChannelMap; // Map internal channels\r
+\r
+ return (retVal);\r
+}\r
+\r
+void ADC12_B_enable(uint16_t baseAddress)\r
+{\r
+ // Clear ENC bit\r
+ HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC;\r
+\r
+ //Enable the ADC12B Module\r
+ HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ON;\r
+}\r
+\r
+void ADC12_B_disable(uint16_t baseAddress)\r
+{\r
+ // Clear ENC bit\r
+ HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC;\r
+\r
+ //Disable ADC12B module\r
+ HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ON;\r
+}\r
+\r
+void ADC12_B_setupSamplingTimer(uint16_t baseAddress,\r
+ uint16_t clockCycleHoldCountLowMem,\r
+ uint16_t clockCycleHoldCountHighMem,\r
+ uint16_t multipleSamplesEnabled)\r
+{\r
+ HWREG16(baseAddress + OFS_ADC12CTL1) |= ADC12SHP;\r
+\r
+ //Reset clock cycle hold counts and msc bit before setting them\r
+ HWREG16(baseAddress + OFS_ADC12CTL0) &=\r
+ ~(ADC12SHT0_15 + ADC12SHT1_15 + ADC12MSC);\r
+\r
+ //Set clock cycle hold counts and msc bit\r
+ HWREG16(baseAddress + OFS_ADC12CTL0) |= clockCycleHoldCountLowMem\r
+ + (clockCycleHoldCountHighMem << 4)\r
+ + multipleSamplesEnabled;\r
+}\r
+\r
+void ADC12_B_disableSamplingTimer(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12SHP);\r
+}\r
+\r
+void ADC12_B_configureMemory(uint16_t baseAddress,\r
+ ADC12_B_configureMemoryParam *param)\r
+{\r
+ //Set the offset in respect to ADC12MCTL0\r
+ uint16_t memoryBufferControlOffset =\r
+ (OFS_ADC12MCTL0 + param->memoryBufferControlIndex);\r
+\r
+ //Reset the memory buffer control and Set the input source\r
+ HWREG16(baseAddress + memoryBufferControlOffset) =\r
+ param->inputSourceSelect //Set Input Source\r
+ + param->refVoltageSourceSelect //Set Vref+/-\r
+ + param->endOfSequence; //Set End of Sequence\r
+\r
+ HWREG16(baseAddress + memoryBufferControlOffset)\r
+ &= ~(ADC12WINC);\r
+\r
+ HWREG16(baseAddress + memoryBufferControlOffset)\r
+ |= param->windowComparatorSelect;\r
+ //(OFS_ADC12MCTL0_H + memoryIndex) == offset of OFS_ADC12MCTLX_H\r
+\r
+ HWREG16(baseAddress + memoryBufferControlOffset)\r
+ &= ~(ADC12DIF);\r
+\r
+ HWREG16(baseAddress + memoryBufferControlOffset)\r
+ |= param->differentialModeSelect;\r
+ //(OFS_ADC12MCTL0_H + memoryIndex) == offset of OFS_ADC12MCTLX_H\r
+}\r
+\r
+void ADC12_B_setWindowCompAdvanced(uint16_t baseAddress,\r
+ uint16_t highThreshold,\r
+ uint16_t lowThreshold)\r
+{\r
+ HWREG16(baseAddress + OFS_ADC12HI) = highThreshold;\r
+ HWREG16(baseAddress + OFS_ADC12LO) = lowThreshold;\r
+}\r
+\r
+void ADC12_B_enableInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptMask0,\r
+ uint16_t interruptMask1,\r
+ uint16_t interruptMask2)\r
+{\r
+ HWREG16(baseAddress + OFS_ADC12IER0) |= interruptMask0;\r
+ HWREG16(baseAddress + OFS_ADC12IER1) |= interruptMask1;\r
+ HWREG16(baseAddress + OFS_ADC12IER2) |= interruptMask2;\r
+}\r
+\r
+void ADC12_B_disableInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptMask0,\r
+ uint16_t interruptMask1,\r
+ uint16_t interruptMask2)\r
+{\r
+ HWREG16(baseAddress + OFS_ADC12IER0) &= ~(interruptMask0);\r
+ HWREG16(baseAddress + OFS_ADC12IER1) &= ~(interruptMask1);\r
+ HWREG16(baseAddress + OFS_ADC12IER2) &= ~(interruptMask2);\r
+}\r
+\r
+void ADC12_B_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptRegisterChoice,\r
+ uint16_t memoryInterruptFlagMask)\r
+{\r
+ HWREG16(baseAddress + OFS_ADC12IFGR0 + 2 * interruptRegisterChoice) &=\r
+ ~(memoryInterruptFlagMask);\r
+}\r
+\r
+uint16_t ADC12_B_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t interruptRegisterChoice,\r
+ uint16_t memoryInterruptFlagMask)\r
+{\r
+ return (HWREG16(baseAddress + OFS_ADC12IFGR0 + 2 * interruptRegisterChoice)\r
+ & memoryInterruptFlagMask);\r
+}\r
+\r
+void ADC12_B_startConversion(uint16_t baseAddress,\r
+ uint16_t startingMemoryBufferIndex,\r
+ uint8_t conversionSequenceModeSelect)\r
+{\r
+ //Reset the ENC bit to set the starting memory address and conversion mode\r
+ //sequence\r
+ HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);\r
+ //Reset the bits about to be set\r
+ HWREG16(baseAddress + OFS_ADC12CTL3) &= ~(ADC12CSTARTADD_31);\r
+ HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12CONSEQ_3);\r
+\r
+ HWREG16(baseAddress + OFS_ADC12CTL3) |= startingMemoryBufferIndex;\r
+ HWREG16(baseAddress + OFS_ADC12CTL1) |= conversionSequenceModeSelect;\r
+ HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ENC + ADC12SC;\r
+}\r
+\r
+void ADC12_B_disableConversions(uint16_t baseAddress,\r
+ bool preempt)\r
+{\r
+ if(ADC12_B_PREEMPTCONVERSION == preempt)\r
+ {\r
+ HWREG8(baseAddress + OFS_ADC12CTL1_L) &= ~(ADC12CONSEQ_3);\r
+ //Reset conversion sequence mode to single-channel, single-conversion\r
+ }\r
+ else if(~(HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12CONSEQ_3))\r
+ {\r
+ //To prevent preemption of a single-channel, single-conversion we must\r
+ //wait for the ADC core to finish the conversion.\r
+ while(ADC12_B_isBusy(baseAddress))\r
+ {\r
+ ;\r
+ }\r
+ }\r
+\r
+ HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);\r
+}\r
+\r
+uint16_t ADC12_B_getResults(uint16_t baseAddress,\r
+ uint8_t memoryBufferIndex)\r
+{\r
+ return (HWREG16(baseAddress + (OFS_ADC12MEM0 + memoryBufferIndex)));\r
+ //(0x60 + memoryBufferIndex) == offset of ADC12MEMx\r
+}\r
+\r
+void ADC12_B_setResolution(uint16_t baseAddress,\r
+ uint8_t resolutionSelect)\r
+{\r
+ HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12RES_3);\r
+ HWREG8(baseAddress + OFS_ADC12CTL2_L) |= resolutionSelect;\r
+}\r
+\r
+void ADC12_B_setSampleHoldSignalInversion(uint16_t baseAddress,\r
+ uint16_t invertedSignal)\r
+{\r
+ HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12ISSH);\r
+ HWREG16(baseAddress + OFS_ADC12CTL1) |= invertedSignal;\r
+}\r
+\r
+void ADC12_B_setDataReadBackFormat(uint16_t baseAddress,\r
+ uint8_t readBackFormat)\r
+{\r
+ HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12DF);\r
+ HWREG8(baseAddress + OFS_ADC12CTL2_L) |= readBackFormat;\r
+}\r
+\r
+void ADC12_B_setAdcPowerMode(uint16_t baseAddress,\r
+ uint8_t powerMode)\r
+{\r
+ HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12PWRMD);\r
+ HWREG8(baseAddress + OFS_ADC12CTL2_L) |= powerMode;\r
+}\r
+\r
+uint32_t ADC12_B_getMemoryAddressForDMA(uint16_t baseAddress,\r
+ uint8_t memoryIndex)\r
+{\r
+ return (baseAddress + (OFS_ADC12MEM0 + memoryIndex));\r
+ //(0x60 + memoryIndex) == offset of ADC12MEMx\r
+}\r
+\r
+uint8_t ADC12_B_isBusy(uint16_t baseAddress)\r
+{\r
+ return (HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12BUSY);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for adc12_b_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// adc12_b.h - Driver for the ADC12_B Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_ADC12_B_H__\r
+#define __MSP430WARE_ADC12_B_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_ADC12_B__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the ADC12_B_init() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct ADC12_B_initParam\r
+{\r
+ //! Is the signal that will trigger a sample-and-hold for an input signal\r
+ //! to be converted.\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_SAMPLEHOLDSOURCE_SC [Default]\r
+ //! - \b ADC12_B_SAMPLEHOLDSOURCE_1\r
+ //! - \b ADC12_B_SAMPLEHOLDSOURCE_2\r
+ //! - \b ADC12_B_SAMPLEHOLDSOURCE_3\r
+ //! - \b ADC12_B_SAMPLEHOLDSOURCE_4\r
+ //! - \b ADC12_B_SAMPLEHOLDSOURCE_5\r
+ //! - \b ADC12_B_SAMPLEHOLDSOURCE_6\r
+ //! - \b ADC12_B_SAMPLEHOLDSOURCE_7\r
+ uint16_t sampleHoldSignalSourceSelect;\r
+ //! Selects the clock that will be used by the ADC12B core, and the\r
+ //! sampling timer if a sampling pulse mode is enabled.\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_CLOCKSOURCE_ADC12OSC [Default]\r
+ //! - \b ADC12_B_CLOCKSOURCE_ACLK\r
+ //! - \b ADC12_B_CLOCKSOURCE_MCLK\r
+ //! - \b ADC12_B_CLOCKSOURCE_SMCLK\r
+ uint8_t clockSourceSelect;\r
+ //! Selects the amount that the clock will be divided.\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_CLOCKDIVIDER_1 [Default]\r
+ //! - \b ADC12_B_CLOCKDIVIDER_2\r
+ //! - \b ADC12_B_CLOCKDIVIDER_3\r
+ //! - \b ADC12_B_CLOCKDIVIDER_4\r
+ //! - \b ADC12_B_CLOCKDIVIDER_5\r
+ //! - \b ADC12_B_CLOCKDIVIDER_6\r
+ //! - \b ADC12_B_CLOCKDIVIDER_7\r
+ //! - \b ADC12_B_CLOCKDIVIDER_8\r
+ uint16_t clockSourceDivider;\r
+ //! Selects the amount that the clock will be predivided.\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_CLOCKPREDIVIDER__1 [Default]\r
+ //! - \b ADC12_B_CLOCKPREDIVIDER__4\r
+ //! - \b ADC12_B_CLOCKPREDIVIDER__32\r
+ //! - \b ADC12_B_CLOCKPREDIVIDER__64\r
+ uint16_t clockSourcePredivider;\r
+ //! Selects what internal channel to map for ADC input channels\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_MAPINTCH3\r
+ //! - \b ADC12_B_MAPINTCH2\r
+ //! - \b ADC12_B_MAPINTCH1\r
+ //! - \b ADC12_B_MAPINTCH0\r
+ //! - \b ADC12_B_TEMPSENSEMAP\r
+ //! - \b ADC12_B_BATTMAP\r
+ //! - \b ADC12_B_NOINTCH\r
+ uint16_t internalChannelMap;\r
+} ADC12_B_initParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the ADC12_B_configureMemory() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct ADC12_B_configureMemoryParam\r
+{\r
+ //! Is the selected memory buffer to set the configuration for.\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_MEMORY_0\r
+ //! - \b ADC12_B_MEMORY_1\r
+ //! - \b ADC12_B_MEMORY_2\r
+ //! - \b ADC12_B_MEMORY_3\r
+ //! - \b ADC12_B_MEMORY_4\r
+ //! - \b ADC12_B_MEMORY_5\r
+ //! - \b ADC12_B_MEMORY_6\r
+ //! - \b ADC12_B_MEMORY_7\r
+ //! - \b ADC12_B_MEMORY_8\r
+ //! - \b ADC12_B_MEMORY_9\r
+ //! - \b ADC12_B_MEMORY_10\r
+ //! - \b ADC12_B_MEMORY_11\r
+ //! - \b ADC12_B_MEMORY_12\r
+ //! - \b ADC12_B_MEMORY_13\r
+ //! - \b ADC12_B_MEMORY_14\r
+ //! - \b ADC12_B_MEMORY_15\r
+ //! - \b ADC12_B_MEMORY_16\r
+ //! - \b ADC12_B_MEMORY_17\r
+ //! - \b ADC12_B_MEMORY_18\r
+ //! - \b ADC12_B_MEMORY_19\r
+ //! - \b ADC12_B_MEMORY_20\r
+ //! - \b ADC12_B_MEMORY_21\r
+ //! - \b ADC12_B_MEMORY_22\r
+ //! - \b ADC12_B_MEMORY_23\r
+ //! - \b ADC12_B_MEMORY_24\r
+ //! - \b ADC12_B_MEMORY_25\r
+ //! - \b ADC12_B_MEMORY_26\r
+ //! - \b ADC12_B_MEMORY_27\r
+ //! - \b ADC12_B_MEMORY_28\r
+ //! - \b ADC12_B_MEMORY_29\r
+ //! - \b ADC12_B_MEMORY_30\r
+ //! - \b ADC12_B_MEMORY_31\r
+ uint8_t memoryBufferControlIndex;\r
+ //! Is the input that will store the converted data into the specified\r
+ //! memory buffer.\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_INPUT_A0 [Default]\r
+ //! - \b ADC12_B_INPUT_A1\r
+ //! - \b ADC12_B_INPUT_A2\r
+ //! - \b ADC12_B_INPUT_A3\r
+ //! - \b ADC12_B_INPUT_A4\r
+ //! - \b ADC12_B_INPUT_A5\r
+ //! - \b ADC12_B_INPUT_A6\r
+ //! - \b ADC12_B_INPUT_A7\r
+ //! - \b ADC12_B_INPUT_A8\r
+ //! - \b ADC12_B_INPUT_A9\r
+ //! - \b ADC12_B_INPUT_A10\r
+ //! - \b ADC12_B_INPUT_A11\r
+ //! - \b ADC12_B_INPUT_A12\r
+ //! - \b ADC12_B_INPUT_A13\r
+ //! - \b ADC12_B_INPUT_A14\r
+ //! - \b ADC12_B_INPUT_A15\r
+ //! - \b ADC12_B_INPUT_A16\r
+ //! - \b ADC12_B_INPUT_A17\r
+ //! - \b ADC12_B_INPUT_A18\r
+ //! - \b ADC12_B_INPUT_A19\r
+ //! - \b ADC12_B_INPUT_A20\r
+ //! - \b ADC12_B_INPUT_A21\r
+ //! - \b ADC12_B_INPUT_A22\r
+ //! - \b ADC12_B_INPUT_A23\r
+ //! - \b ADC12_B_INPUT_A24\r
+ //! - \b ADC12_B_INPUT_A25\r
+ //! - \b ADC12_B_INPUT_A26\r
+ //! - \b ADC12_B_INPUT_A27\r
+ //! - \b ADC12_B_INPUT_A28\r
+ //! - \b ADC12_B_INPUT_A29\r
+ //! - \b ADC12_B_INPUT_TCMAP\r
+ //! - \b ADC12_B_INPUT_BATMAP\r
+ uint8_t inputSourceSelect;\r
+ //! Is the reference voltage source to set as the upper/lower limits for\r
+ //! the conversion stored in the specified memory.\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_VSS [Default]\r
+ //! - \b ADC12_B_VREFPOS_INTBUF_VREFNEG_VSS\r
+ //! - \b ADC12_B_VREFPOS_EXTNEG_VREFNEG_VSS\r
+ //! - \b ADC12_B_VREFPOS_EXTBUF_VREFNEG_VSS\r
+ //! - \b ADC12_B_VREFPOS_EXTPOS_VREFNEG_VSS\r
+ //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_EXTBUF\r
+ //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_EXTPOS\r
+ //! - \b ADC12_B_VREFPOS_INTBUF_VREFNEG_EXTPOS\r
+ //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_INTBUF\r
+ //! - \b ADC12_B_VREFPOS_EXTPOS_VREFNEG_INTBUF\r
+ //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_EXTNEG\r
+ //! - \b ADC12_B_VREFPOS_INTBUF_VREFNEG_EXTNEG\r
+ //! - \b ADC12_B_VREFPOS_EXTPOS_VREFNEG_EXTNEG\r
+ //! - \b ADC12_B_VREFPOS_EXTBUF_VREFNEG_EXTNEG\r
+ uint16_t refVoltageSourceSelect;\r
+ //! Indicates that the specified memory buffer will be the end of the\r
+ //! sequence if a sequenced conversion mode is selected\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_NOTENDOFSEQUENCE [Default]\r
+ //! - \b ADC12_B_ENDOFSEQUENCE\r
+ uint16_t endOfSequence;\r
+ //! Sets the window comparator mode\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_WINDOW_COMPARATOR_DISABLE [Default]\r
+ //! - \b ADC12_B_WINDOW_COMPARATOR_ENABLE\r
+ uint16_t windowComparatorSelect;\r
+ //! Sets the differential mode\r
+ //! \n Valid values are:\r
+ //! - \b ADC12_B_DIFFERENTIAL_MODE_DISABLE [Default]\r
+ //! - \b ADC12_B_DIFFERENTIAL_MODE_ENABLE\r
+ uint16_t differentialModeSelect;\r
+} ADC12_B_configureMemoryParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockSourceDivider\r
+// parameter for functions: ADC12_B_init(); the param parameter for functions:\r
+// ADC12_B_init().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_CLOCKDIVIDER_1 (ADC12DIV_0)\r
+#define ADC12_B_CLOCKDIVIDER_2 (ADC12DIV_1)\r
+#define ADC12_B_CLOCKDIVIDER_3 (ADC12DIV_2)\r
+#define ADC12_B_CLOCKDIVIDER_4 (ADC12DIV_3)\r
+#define ADC12_B_CLOCKDIVIDER_5 (ADC12DIV_4)\r
+#define ADC12_B_CLOCKDIVIDER_6 (ADC12DIV_5)\r
+#define ADC12_B_CLOCKDIVIDER_7 (ADC12DIV_6)\r
+#define ADC12_B_CLOCKDIVIDER_8 (ADC12DIV_7)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockSourceSelect\r
+// parameter for functions: ADC12_B_init(); the param parameter for functions:\r
+// ADC12_B_init().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_CLOCKSOURCE_ADC12OSC (ADC12SSEL_0)\r
+#define ADC12_B_CLOCKSOURCE_ACLK (ADC12SSEL_1)\r
+#define ADC12_B_CLOCKSOURCE_MCLK (ADC12SSEL_2)\r
+#define ADC12_B_CLOCKSOURCE_SMCLK (ADC12SSEL_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockSourcePredivider\r
+// parameter for functions: ADC12_B_init(); the param parameter for functions:\r
+// ADC12_B_init().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_CLOCKPREDIVIDER__1 (ADC12PDIV__1)\r
+#define ADC12_B_CLOCKPREDIVIDER__4 (ADC12PDIV__4)\r
+#define ADC12_B_CLOCKPREDIVIDER__32 (ADC12PDIV__32)\r
+#define ADC12_B_CLOCKPREDIVIDER__64 (ADC12PDIV__64)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: ADC12_B_init(); the sampleHoldSignalSourceSelect parameter for\r
+// functions: ADC12_B_init().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_SAMPLEHOLDSOURCE_SC (ADC12SHS_0)\r
+#define ADC12_B_SAMPLEHOLDSOURCE_1 (ADC12SHS_1)\r
+#define ADC12_B_SAMPLEHOLDSOURCE_2 (ADC12SHS_2)\r
+#define ADC12_B_SAMPLEHOLDSOURCE_3 (ADC12SHS_3)\r
+#define ADC12_B_SAMPLEHOLDSOURCE_4 (ADC12SHS_4)\r
+#define ADC12_B_SAMPLEHOLDSOURCE_5 (ADC12SHS_5)\r
+#define ADC12_B_SAMPLEHOLDSOURCE_6 (ADC12SHS_6)\r
+#define ADC12_B_SAMPLEHOLDSOURCE_7 (ADC12SHS_7)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the internalChannelMap\r
+// parameter for functions: ADC12_B_init(); the param parameter for functions:\r
+// ADC12_B_init().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_MAPINTCH3 (ADC12ICH3MAP)\r
+#define ADC12_B_MAPINTCH2 (ADC12ICH2MAP)\r
+#define ADC12_B_MAPINTCH1 (ADC12ICH1MAP)\r
+#define ADC12_B_MAPINTCH0 (ADC12ICH0MAP)\r
+#define ADC12_B_TEMPSENSEMAP (ADC12TCMAP)\r
+#define ADC12_B_BATTMAP (ADC12BATMAP)\r
+#define ADC12_B_NOINTCH (0x00)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockCycleHoldCountLowMem\r
+// parameter for functions: ADC12_B_setupSamplingTimer(); the\r
+// clockCycleHoldCountHighMem parameter for functions:\r
+// ADC12_B_setupSamplingTimer().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_CYCLEHOLD_4_CYCLES (ADC12SHT0_0)\r
+#define ADC12_B_CYCLEHOLD_8_CYCLES (ADC12SHT0_1)\r
+#define ADC12_B_CYCLEHOLD_16_CYCLES (ADC12SHT0_2)\r
+#define ADC12_B_CYCLEHOLD_32_CYCLES (ADC12SHT0_3)\r
+#define ADC12_B_CYCLEHOLD_64_CYCLES (ADC12SHT0_4)\r
+#define ADC12_B_CYCLEHOLD_96_CYCLES (ADC12SHT0_5)\r
+#define ADC12_B_CYCLEHOLD_128_CYCLES (ADC12SHT0_6)\r
+#define ADC12_B_CYCLEHOLD_192_CYCLES (ADC12SHT0_7)\r
+#define ADC12_B_CYCLEHOLD_256_CYCLES (ADC12SHT0_8)\r
+#define ADC12_B_CYCLEHOLD_384_CYCLES (ADC12SHT0_9)\r
+#define ADC12_B_CYCLEHOLD_512_CYCLES (ADC12SHT0_10)\r
+#define ADC12_B_CYCLEHOLD_768_CYCLES (ADC12SHT0_11)\r
+#define ADC12_B_CYCLEHOLD_1024_CYCLES (ADC12SHT0_12)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the multipleSamplesEnabled\r
+// parameter for functions: ADC12_B_setupSamplingTimer().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_MULTIPLESAMPLESDISABLE (!(ADC12MSC))\r
+#define ADC12_B_MULTIPLESAMPLESENABLE (ADC12MSC)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: ADC12_B_configureMemory().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_DIFFERENTIAL_MODE_DISABLE (0x00)\r
+#define ADC12_B_DIFFERENTIAL_MODE_ENABLE (ADC12DIF)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: ADC12_B_configureMemory().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_NOTENDOFSEQUENCE (!(ADC12EOS))\r
+#define ADC12_B_ENDOFSEQUENCE (ADC12EOS)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: ADC12_B_configureMemory().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_VREFPOS_AVCC_VREFNEG_VSS (ADC12VRSEL_0)\r
+#define ADC12_B_VREFPOS_INTBUF_VREFNEG_VSS (ADC12VRSEL_1)\r
+#define ADC12_B_VREFPOS_EXTNEG_VREFNEG_VSS (ADC12VRSEL_2)\r
+#define ADC12_B_VREFPOS_EXTBUF_VREFNEG_VSS (ADC12VRSEL_3)\r
+#define ADC12_B_VREFPOS_EXTPOS_VREFNEG_VSS (ADC12VRSEL_4)\r
+#define ADC12_B_VREFPOS_AVCC_VREFNEG_EXTBUF (ADC12VRSEL_5)\r
+#define ADC12_B_VREFPOS_AVCC_VREFNEG_EXTPOS (ADC12VRSEL_6)\r
+#define ADC12_B_VREFPOS_INTBUF_VREFNEG_EXTPOS (ADC12VRSEL_7)\r
+#define ADC12_B_VREFPOS_AVCC_VREFNEG_INTBUF (ADC12VRSEL_9)\r
+#define ADC12_B_VREFPOS_EXTPOS_VREFNEG_INTBUF (ADC12VRSEL_11)\r
+#define ADC12_B_VREFPOS_AVCC_VREFNEG_EXTNEG (ADC12VRSEL_12)\r
+#define ADC12_B_VREFPOS_INTBUF_VREFNEG_EXTNEG (ADC12VRSEL_13)\r
+#define ADC12_B_VREFPOS_EXTPOS_VREFNEG_EXTNEG (ADC12VRSEL_14)\r
+#define ADC12_B_VREFPOS_EXTBUF_VREFNEG_EXTNEG (ADC12VRSEL_15)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: ADC12_B_configureMemory().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_INPUT_A0 (ADC12INCH_0)\r
+#define ADC12_B_INPUT_A1 (ADC12INCH_1)\r
+#define ADC12_B_INPUT_A2 (ADC12INCH_2)\r
+#define ADC12_B_INPUT_A3 (ADC12INCH_3)\r
+#define ADC12_B_INPUT_A4 (ADC12INCH_4)\r
+#define ADC12_B_INPUT_A5 (ADC12INCH_5)\r
+#define ADC12_B_INPUT_A6 (ADC12INCH_6)\r
+#define ADC12_B_INPUT_A7 (ADC12INCH_7)\r
+#define ADC12_B_INPUT_A8 (ADC12INCH_8)\r
+#define ADC12_B_INPUT_A9 (ADC12INCH_9)\r
+#define ADC12_B_INPUT_A10 (ADC12INCH_10)\r
+#define ADC12_B_INPUT_A11 (ADC12INCH_11)\r
+#define ADC12_B_INPUT_A12 (ADC12INCH_12)\r
+#define ADC12_B_INPUT_A13 (ADC12INCH_13)\r
+#define ADC12_B_INPUT_A14 (ADC12INCH_14)\r
+#define ADC12_B_INPUT_A15 (ADC12INCH_15)\r
+#define ADC12_B_INPUT_A16 (ADC12INCH_16)\r
+#define ADC12_B_INPUT_A17 (ADC12INCH_17)\r
+#define ADC12_B_INPUT_A18 (ADC12INCH_18)\r
+#define ADC12_B_INPUT_A19 (ADC12INCH_19)\r
+#define ADC12_B_INPUT_A20 (ADC12INCH_20)\r
+#define ADC12_B_INPUT_A21 (ADC12INCH_21)\r
+#define ADC12_B_INPUT_A22 (ADC12INCH_22)\r
+#define ADC12_B_INPUT_A23 (ADC12INCH_23)\r
+#define ADC12_B_INPUT_A24 (ADC12INCH_24)\r
+#define ADC12_B_INPUT_A25 (ADC12INCH_25)\r
+#define ADC12_B_INPUT_A26 (ADC12INCH_26)\r
+#define ADC12_B_INPUT_A27 (ADC12INCH_27)\r
+#define ADC12_B_INPUT_A28 (ADC12INCH_28)\r
+#define ADC12_B_INPUT_A29 (ADC12INCH_29)\r
+#define ADC12_B_INPUT_TCMAP (ADC12INCH_30)\r
+#define ADC12_B_INPUT_BATMAP (ADC12INCH_31)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: ADC12_B_configureMemory().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_WINDOW_COMPARATOR_DISABLE (0x00)\r
+#define ADC12_B_WINDOW_COMPARATOR_ENABLE (ADC12WINC)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the memoryIndex parameter for\r
+// functions: ADC12_B_getMemoryAddressForDMA(); the memoryBufferIndex parameter\r
+// for functions: ADC12_B_getResults(); the param parameter for functions:\r
+// ADC12_B_configureMemory().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_MEMORY_0 (0x00)\r
+#define ADC12_B_MEMORY_1 (0x02)\r
+#define ADC12_B_MEMORY_2 (0x04)\r
+#define ADC12_B_MEMORY_3 (0x06)\r
+#define ADC12_B_MEMORY_4 (0x08)\r
+#define ADC12_B_MEMORY_5 (0x0A)\r
+#define ADC12_B_MEMORY_6 (0x0C)\r
+#define ADC12_B_MEMORY_7 (0x0E)\r
+#define ADC12_B_MEMORY_8 (0x10)\r
+#define ADC12_B_MEMORY_9 (0x12)\r
+#define ADC12_B_MEMORY_10 (0x14)\r
+#define ADC12_B_MEMORY_11 (0x16)\r
+#define ADC12_B_MEMORY_12 (0x18)\r
+#define ADC12_B_MEMORY_13 (0x1A)\r
+#define ADC12_B_MEMORY_14 (0x1C)\r
+#define ADC12_B_MEMORY_15 (0x1E)\r
+#define ADC12_B_MEMORY_16 (0x20)\r
+#define ADC12_B_MEMORY_17 (0x22)\r
+#define ADC12_B_MEMORY_18 (0x24)\r
+#define ADC12_B_MEMORY_19 (0x26)\r
+#define ADC12_B_MEMORY_20 (0x28)\r
+#define ADC12_B_MEMORY_21 (0x2A)\r
+#define ADC12_B_MEMORY_22 (0x2C)\r
+#define ADC12_B_MEMORY_23 (0x2E)\r
+#define ADC12_B_MEMORY_24 (0x30)\r
+#define ADC12_B_MEMORY_25 (0x32)\r
+#define ADC12_B_MEMORY_26 (0x34)\r
+#define ADC12_B_MEMORY_27 (0x36)\r
+#define ADC12_B_MEMORY_28 (0x38)\r
+#define ADC12_B_MEMORY_29 (0x3A)\r
+#define ADC12_B_MEMORY_30 (0x3C)\r
+#define ADC12_B_MEMORY_31 (0x3E)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptMask0 parameter\r
+// for functions: ADC12_B_enableInterrupt(), and ADC12_B_disableInterrupt().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_IE0 (ADC12IE0)\r
+#define ADC12_B_IE1 (ADC12IE1)\r
+#define ADC12_B_IE2 (ADC12IE2)\r
+#define ADC12_B_IE3 (ADC12IE3)\r
+#define ADC12_B_IE4 (ADC12IE4)\r
+#define ADC12_B_IE5 (ADC12IE5)\r
+#define ADC12_B_IE6 (ADC12IE6)\r
+#define ADC12_B_IE7 (ADC12IE7)\r
+#define ADC12_B_IE8 (ADC12IE8)\r
+#define ADC12_B_IE9 (ADC12IE9)\r
+#define ADC12_B_IE10 (ADC12IE10)\r
+#define ADC12_B_IE11 (ADC12IE11)\r
+#define ADC12_B_IE12 (ADC12IE12)\r
+#define ADC12_B_IE13 (ADC12IE13)\r
+#define ADC12_B_IE14 (ADC12IE14)\r
+#define ADC12_B_IE15 (ADC12IE15)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptMask1 parameter\r
+// for functions: ADC12_B_enableInterrupt(), and ADC12_B_disableInterrupt().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_IE16 (ADC12IE16)\r
+#define ADC12_B_IE17 (ADC12IE17)\r
+#define ADC12_B_IE18 (ADC12IE18)\r
+#define ADC12_B_IE19 (ADC12IE19)\r
+#define ADC12_B_IE20 (ADC12IE20)\r
+#define ADC12_B_IE21 (ADC12IE21)\r
+#define ADC12_B_IE22 (ADC12IE22)\r
+#define ADC12_B_IE23 (ADC12IE23)\r
+#define ADC12_B_IE24 (ADC12IE24)\r
+#define ADC12_B_IE25 (ADC12IE25)\r
+#define ADC12_B_IE26 (ADC12IE26)\r
+#define ADC12_B_IE27 (ADC12IE27)\r
+#define ADC12_B_IE28 (ADC12IE28)\r
+#define ADC12_B_IE29 (ADC12IE29)\r
+#define ADC12_B_IE30 (ADC12IE30)\r
+#define ADC12_B_IE31 (ADC12IE31)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptMask2 parameter\r
+// for functions: ADC12_B_enableInterrupt(), and ADC12_B_disableInterrupt().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_INIE (ADC12INIE)\r
+#define ADC12_B_LOIE (ADC12LOIE)\r
+#define ADC12_B_HIIE (ADC12HIIE)\r
+#define ADC12_B_OVIE (ADC12OVIE)\r
+#define ADC12_B_TOVIE (ADC12TOVIE)\r
+#define ADC12_B_RDYIE (ADC12RDYIE)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the memoryInterruptFlagMask\r
+// parameter for functions: ADC12_B_clearInterrupt(), and\r
+// ADC12_B_getInterruptStatus().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_IFG0 (ADC12IFG0)\r
+#define ADC12_B_IFG1 (ADC12IFG1)\r
+#define ADC12_B_IFG2 (ADC12IFG2)\r
+#define ADC12_B_IFG3 (ADC12IFG3)\r
+#define ADC12_B_IFG4 (ADC12IFG4)\r
+#define ADC12_B_IFG5 (ADC12IFG5)\r
+#define ADC12_B_IFG6 (ADC12IFG6)\r
+#define ADC12_B_IFG7 (ADC12IFG7)\r
+#define ADC12_B_IFG8 (ADC12IFG8)\r
+#define ADC12_B_IFG9 (ADC12IFG9)\r
+#define ADC12_B_IFG10 (ADC12IFG10)\r
+#define ADC12_B_IFG11 (ADC12IFG11)\r
+#define ADC12_B_IFG12 (ADC12IFG12)\r
+#define ADC12_B_IFG13 (ADC12IFG13)\r
+#define ADC12_B_IFG14 (ADC12IFG14)\r
+#define ADC12_B_IFG15 (ADC12IFG15)\r
+#define ADC12_B_IFG16 (ADC12IFG16)\r
+#define ADC12_B_IFG17 (ADC12IFG17)\r
+#define ADC12_B_IFG18 (ADC12IFG18)\r
+#define ADC12_B_IFG19 (ADC12IFG19)\r
+#define ADC12_B_IFG20 (ADC12IFG20)\r
+#define ADC12_B_IFG21 (ADC12IFG21)\r
+#define ADC12_B_IFG22 (ADC12IFG22)\r
+#define ADC12_B_IFG23 (ADC12IFG23)\r
+#define ADC12_B_IFG24 (ADC12IFG24)\r
+#define ADC12_B_IFG25 (ADC12IFG25)\r
+#define ADC12_B_IFG26 (ADC12IFG26)\r
+#define ADC12_B_IFG27 (ADC12IFG27)\r
+#define ADC12_B_IFG28 (ADC12IFG28)\r
+#define ADC12_B_IFG29 (ADC12IFG29)\r
+#define ADC12_B_IFG30 (ADC12IFG30)\r
+#define ADC12_B_IFG31 (ADC12IFG31)\r
+#define ADC12_B_INIFG (ADC12INIFG)\r
+#define ADC12_B_LOIFG (ADC12LOIFG)\r
+#define ADC12_B_HIIFG (ADC12HIIFG)\r
+#define ADC12_B_OVIFG (ADC12OVIFG)\r
+#define ADC12_B_TOVIFG (ADC12TOVIFG)\r
+#define ADC12_B_RDYIFG (ADC12RDYIFG)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the startingMemoryBufferIndex\r
+// parameter for functions: ADC12_B_startConversion().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_START_AT_ADC12MEM0 (ADC12CSTARTADD_0)\r
+#define ADC12_B_START_AT_ADC12MEM1 (ADC12CSTARTADD_1)\r
+#define ADC12_B_START_AT_ADC12MEM2 (ADC12CSTARTADD_2)\r
+#define ADC12_B_START_AT_ADC12MEM3 (ADC12CSTARTADD_3)\r
+#define ADC12_B_START_AT_ADC12MEM4 (ADC12CSTARTADD_4)\r
+#define ADC12_B_START_AT_ADC12MEM5 (ADC12CSTARTADD_5)\r
+#define ADC12_B_START_AT_ADC12MEM6 (ADC12CSTARTADD_6)\r
+#define ADC12_B_START_AT_ADC12MEM7 (ADC12CSTARTADD_7)\r
+#define ADC12_B_START_AT_ADC12MEM8 (ADC12CSTARTADD_8)\r
+#define ADC12_B_START_AT_ADC12MEM9 (ADC12CSTARTADD_9)\r
+#define ADC12_B_START_AT_ADC12MEM10 (ADC12CSTARTADD_10)\r
+#define ADC12_B_START_AT_ADC12MEM11 (ADC12CSTARTADD_11)\r
+#define ADC12_B_START_AT_ADC12MEM12 (ADC12CSTARTADD_12)\r
+#define ADC12_B_START_AT_ADC12MEM13 (ADC12CSTARTADD_13)\r
+#define ADC12_B_START_AT_ADC12MEM14 (ADC12CSTARTADD_14)\r
+#define ADC12_B_START_AT_ADC12MEM15 (ADC12CSTARTADD_15)\r
+#define ADC12_B_START_AT_ADC12MEM16 (ADC12CSTARTADD_16)\r
+#define ADC12_B_START_AT_ADC12MEM17 (ADC12CSTARTADD_17)\r
+#define ADC12_B_START_AT_ADC12MEM18 (ADC12CSTARTADD_18)\r
+#define ADC12_B_START_AT_ADC12MEM19 (ADC12CSTARTADD_19)\r
+#define ADC12_B_START_AT_ADC12MEM20 (ADC12CSTARTADD_20)\r
+#define ADC12_B_START_AT_ADC12MEM21 (ADC12CSTARTADD_21)\r
+#define ADC12_B_START_AT_ADC12MEM22 (ADC12CSTARTADD_22)\r
+#define ADC12_B_START_AT_ADC12MEM23 (ADC12CSTARTADD_23)\r
+#define ADC12_B_START_AT_ADC12MEM24 (ADC12CSTARTADD_24)\r
+#define ADC12_B_START_AT_ADC12MEM25 (ADC12CSTARTADD_25)\r
+#define ADC12_B_START_AT_ADC12MEM26 (ADC12CSTARTADD_26)\r
+#define ADC12_B_START_AT_ADC12MEM27 (ADC12CSTARTADD_27)\r
+#define ADC12_B_START_AT_ADC12MEM28 (ADC12CSTARTADD_28)\r
+#define ADC12_B_START_AT_ADC12MEM29 (ADC12CSTARTADD_29)\r
+#define ADC12_B_START_AT_ADC12MEM30 (ADC12CSTARTADD_30)\r
+#define ADC12_B_START_AT_ADC12MEM31 (ADC12CSTARTADD_31)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// conversionSequenceModeSelect parameter for functions:\r
+// ADC12_B_startConversion().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_SINGLECHANNEL (ADC12CONSEQ_0)\r
+#define ADC12_B_SEQOFCHANNELS (ADC12CONSEQ_1)\r
+#define ADC12_B_REPEATED_SINGLECHANNEL (ADC12CONSEQ_2)\r
+#define ADC12_B_REPEATED_SEQOFCHANNELS (ADC12CONSEQ_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the preempt parameter for\r
+// functions: ADC12_B_disableConversions().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_COMPLETECONVERSION false\r
+#define ADC12_B_PREEMPTCONVERSION true\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the resolutionSelect\r
+// parameter for functions: ADC12_B_setResolution().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_RESOLUTION_8BIT (ADC12RES__8BIT)\r
+#define ADC12_B_RESOLUTION_10BIT (ADC12RES__10BIT)\r
+#define ADC12_B_RESOLUTION_12BIT (ADC12RES__12BIT)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the invertedSignal parameter\r
+// for functions: ADC12_B_setSampleHoldSignalInversion().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_NONINVERTEDSIGNAL (!(ADC12ISSH))\r
+#define ADC12_B_INVERTEDSIGNAL (ADC12ISSH)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the readBackFormat parameter\r
+// for functions: ADC12_B_setDataReadBackFormat().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_UNSIGNED_BINARY (!(ADC12DF))\r
+#define ADC12_B_SIGNED_2SCOMPLEMENT (ADC12DF)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the powerMode parameter for\r
+// functions: ADC12_B_setAdcPowerMode().\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_REGULARPOWERMODE (!(ADC12PWRMD))\r
+#define ADC12_B_LOWPOWERMODE (ADC12PWRMD)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the ADC12_B_isBusy() function.\r
+//\r
+//*****************************************************************************\r
+#define ADC12_B_NOTBUSY 0x00\r
+#define ADC12_B_BUSY ADC12BUSY\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the ADC12B Module.\r
+//!\r
+//! This function initializes the ADC module to allow for analog-to-digital\r
+//! conversions. Specifically this function sets up the sample-and-hold signal\r
+//! and clock sources for the ADC core to use for conversions. Upon successful\r
+//! completion of the initialization all of the ADC control registers will be\r
+//! reset, excluding the memory controls and reference module bits, the given\r
+//! parameters will be set, and the ADC core will be turned on (Note, that the\r
+//! ADC core only draws power during conversions and remains off when not\r
+//! converting).Note that sample/hold signal sources are device dependent. Note\r
+//! that if re-initializing the ADC after starting a conversion with the\r
+//! startConversion() function, the disableConversion() must be called BEFORE\r
+//! this function can be called.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param param is the pointer to struct for initialization.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process.\r
+//\r
+//*****************************************************************************\r
+extern bool ADC12_B_init(uint16_t baseAddress,\r
+ ADC12_B_initParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the ADC12B block.\r
+//!\r
+//! This will enable operation of the ADC12B block.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//!\r
+//! Modified bits are \b ADC12ON of \b ADC12CTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_enable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the ADC12B block.\r
+//!\r
+//! This will disable operation of the ADC12B block.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//!\r
+//! Modified bits are \b ADC12ON of \b ADC12CTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_disable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets up and enables the Sampling Timer Pulse Mode.\r
+//!\r
+//! This function sets up the sampling timer pulse mode which allows the\r
+//! sample/hold signal to trigger a sampling timer to sample-and-hold an input\r
+//! signal for a specified number of clock cycles without having to hold the\r
+//! sample/hold signal for the entire period of sampling. Note that if a\r
+//! conversion has been started with the startConversion() function, then a\r
+//! call to disableConversions() is required before this function may be\r
+//! called.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param clockCycleHoldCountLowMem sets the amount of clock cycles to sample-\r
+//! and-hold for the higher memory buffers 0-7.\r
+//! Valid values are:\r
+//! - \b ADC12_B_CYCLEHOLD_4_CYCLES [Default]\r
+//! - \b ADC12_B_CYCLEHOLD_8_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_16_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_32_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_64_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_96_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_128_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_192_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_256_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_384_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_512_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_768_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_1024_CYCLES\r
+//! \n Modified bits are \b ADC12SHT0x of \b ADC12CTL0 register.\r
+//! \param clockCycleHoldCountHighMem sets the amount of clock cycles to\r
+//! sample-and-hold for the higher memory buffers 8-15.\r
+//! Valid values are:\r
+//! - \b ADC12_B_CYCLEHOLD_4_CYCLES [Default]\r
+//! - \b ADC12_B_CYCLEHOLD_8_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_16_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_32_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_64_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_96_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_128_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_192_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_256_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_384_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_512_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_768_CYCLES\r
+//! - \b ADC12_B_CYCLEHOLD_1024_CYCLES\r
+//! \n Modified bits are \b ADC12SHT1x of \b ADC12CTL0 register.\r
+//! \param multipleSamplesEnabled allows multiple conversions to start without\r
+//! a trigger signal from the sample/hold signal\r
+//! Valid values are:\r
+//! - \b ADC12_B_MULTIPLESAMPLESDISABLE [Default] - a timer trigger will\r
+//! be needed to start every ADC conversion.\r
+//! - \b ADC12_B_MULTIPLESAMPLESENABLE - during a sequenced and/or\r
+//! repeated conversion mode, after the first conversion, no\r
+//! sample/hold signal is necessary to start subsequent sample/hold\r
+//! and convert processes.\r
+//! \n Modified bits are \b ADC12MSC of \b ADC12CTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_setupSamplingTimer(uint16_t baseAddress,\r
+ uint16_t clockCycleHoldCountLowMem,\r
+ uint16_t clockCycleHoldCountHighMem,\r
+ uint16_t multipleSamplesEnabled);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables Sampling Timer Pulse Mode.\r
+//!\r
+//! Disables the Sampling Timer Pulse Mode. Note that if a conversion has been\r
+//! started with the startConversion() function, then a call to\r
+//! disableConversions() is required before this function may be called.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_disableSamplingTimer(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures the controls of the selected memory buffer.\r
+//!\r
+//! Maps an input signal conversion into the selected memory buffer, as well as\r
+//! the positive and negative reference voltages for each conversion being\r
+//! stored into this memory buffer. If the internal reference is used for the\r
+//! positive reference voltage, the internal REF module must be used to control\r
+//! the voltage level. Note that if a conversion has been started with the\r
+//! startConversion() function, then a call to disableConversions() is required\r
+//! before this function may be called.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param param is the pointer to struct for ADC12B memory configuration.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_configureMemory(uint16_t baseAddress,\r
+ ADC12_B_configureMemoryParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the high and low threshold for the window comparator feature.\r
+//!\r
+//! Sets the high and low threshold for the window comparator feature. Use the\r
+//! ADC12HIIE, ADC12INIE, ADC12LOIE interrupts to utilize this feature.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param highThreshold is the upper bound that could trip an interrupt for\r
+//! the window comparator.\r
+//! \param lowThreshold is the lower bound that could trip on interrupt for the\r
+//! window comparator.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_setWindowCompAdvanced(uint16_t baseAddress,\r
+ uint16_t highThreshold,\r
+ uint16_t lowThreshold);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables selected ADC12B interrupt sources.\r
+//!\r
+//! Enables the indicated ADC12B interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor. <b>Does not clear interrupt flags.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param interruptMask0 is the bit mask of the memory buffer and overflow\r
+//! interrupt sources to be enabled. If the desired interrupt is not\r
+//! available in the selection for interruptMask0, then simply pass in a\r
+//! '0' for this value.\r
+//! Valid values are:\r
+//! - \b ADC12_B_IE0\r
+//! - \b ADC12_B_IE1\r
+//! - \b ADC12_B_IE2\r
+//! - \b ADC12_B_IE3\r
+//! - \b ADC12_B_IE4\r
+//! - \b ADC12_B_IE5\r
+//! - \b ADC12_B_IE6\r
+//! - \b ADC12_B_IE7\r
+//! - \b ADC12_B_IE8\r
+//! - \b ADC12_B_IE9\r
+//! - \b ADC12_B_IE10\r
+//! - \b ADC12_B_IE11\r
+//! - \b ADC12_B_IE12\r
+//! - \b ADC12_B_IE13\r
+//! - \b ADC12_B_IE14\r
+//! - \b ADC12_B_IE15\r
+//! \param interruptMask1 is the bit mask of the memory buffer and overflow\r
+//! interrupt sources to be enabled. If the desired interrupt is not\r
+//! available in the selection for interruptMask1, then simply pass in a\r
+//! '0' for this value.\r
+//! Valid values are:\r
+//! - \b ADC12_B_IE16\r
+//! - \b ADC12_B_IE17\r
+//! - \b ADC12_B_IE18\r
+//! - \b ADC12_B_IE19\r
+//! - \b ADC12_B_IE20\r
+//! - \b ADC12_B_IE21\r
+//! - \b ADC12_B_IE22\r
+//! - \b ADC12_B_IE23\r
+//! - \b ADC12_B_IE24\r
+//! - \b ADC12_B_IE25\r
+//! - \b ADC12_B_IE26\r
+//! - \b ADC12_B_IE27\r
+//! - \b ADC12_B_IE28\r
+//! - \b ADC12_B_IE29\r
+//! - \b ADC12_B_IE30\r
+//! - \b ADC12_B_IE31\r
+//! \param interruptMask2 is the bit mask of the memory buffer and overflow\r
+//! interrupt sources to be enabled. If the desired interrupt is not\r
+//! available in the selection for interruptMask2, then simply pass in a\r
+//! '0' for this value.\r
+//! Valid values are:\r
+//! - \b ADC12_B_INIE - Interrupt enable for a conversion in the result\r
+//! register is either greater than the ADC12LO or lower than the\r
+//! ADC12HI threshold. GIE bit must be set to enable the interrupt.\r
+//! - \b ADC12_B_LOIE - Interrupt enable for the falling short of the\r
+//! lower limit interrupt of the window comparator for the result\r
+//! register. GIE bit must be set to enable the interrupt.\r
+//! - \b ADC12_B_HIIE - Interrupt enable for the exceeding the upper\r
+//! limit of the window comparator for the result register. GIE bit\r
+//! must be set to enable the interrupt.\r
+//! - \b ADC12_B_OVIE - Interrupt enable for a conversion that is about\r
+//! to save to a memory buffer that has not been read out yet. GIE\r
+//! bit must be set to enable the interrupt.\r
+//! - \b ADC12_B_TOVIE - enable for a conversion that is about to start\r
+//! before the previous conversion has been completed. GIE bit must\r
+//! be set to enable the interrupt.\r
+//! - \b ADC12_B_RDYIE - enable for the local buffered reference ready\r
+//! signal. GIE bit must be set to enable the interrupt.\r
+//!\r
+//! Modified bits of \b ADC12IERx register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_enableInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptMask0,\r
+ uint16_t interruptMask1,\r
+ uint16_t interruptMask2);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables selected ADC12B interrupt sources.\r
+//!\r
+//! Disables the indicated ADC12B interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param interruptMask0 is the bit mask of the memory buffer and overflow\r
+//! interrupt sources to be disabled. If the desired interrupt is not\r
+//! available in the selection for interruptMask0, then simply pass in a\r
+//! '0' for this value.\r
+//! Valid values are:\r
+//! - \b ADC12_B_IE0\r
+//! - \b ADC12_B_IE1\r
+//! - \b ADC12_B_IE2\r
+//! - \b ADC12_B_IE3\r
+//! - \b ADC12_B_IE4\r
+//! - \b ADC12_B_IE5\r
+//! - \b ADC12_B_IE6\r
+//! - \b ADC12_B_IE7\r
+//! - \b ADC12_B_IE8\r
+//! - \b ADC12_B_IE9\r
+//! - \b ADC12_B_IE10\r
+//! - \b ADC12_B_IE11\r
+//! - \b ADC12_B_IE12\r
+//! - \b ADC12_B_IE13\r
+//! - \b ADC12_B_IE14\r
+//! - \b ADC12_B_IE15\r
+//! \param interruptMask1 is the bit mask of the memory buffer and overflow\r
+//! interrupt sources to be disabled. If the desired interrupt is not\r
+//! available in the selection for interruptMask1, then simply pass in a\r
+//! '0' for this value.\r
+//! Valid values are:\r
+//! - \b ADC12_B_IE16\r
+//! - \b ADC12_B_IE17\r
+//! - \b ADC12_B_IE18\r
+//! - \b ADC12_B_IE19\r
+//! - \b ADC12_B_IE20\r
+//! - \b ADC12_B_IE21\r
+//! - \b ADC12_B_IE22\r
+//! - \b ADC12_B_IE23\r
+//! - \b ADC12_B_IE24\r
+//! - \b ADC12_B_IE25\r
+//! - \b ADC12_B_IE26\r
+//! - \b ADC12_B_IE27\r
+//! - \b ADC12_B_IE28\r
+//! - \b ADC12_B_IE29\r
+//! - \b ADC12_B_IE30\r
+//! - \b ADC12_B_IE31\r
+//! \param interruptMask2 is the bit mask of the memory buffer and overflow\r
+//! interrupt sources to be disabled. If the desired interrupt is not\r
+//! available in the selection for interruptMask2, then simply pass in a\r
+//! '0' for this value.\r
+//! Valid values are:\r
+//! - \b ADC12_B_INIE - Interrupt enable for a conversion in the result\r
+//! register is either greater than the ADC12LO or lower than the\r
+//! ADC12HI threshold. GIE bit must be set to enable the interrupt.\r
+//! - \b ADC12_B_LOIE - Interrupt enable for the falling short of the\r
+//! lower limit interrupt of the window comparator for the result\r
+//! register. GIE bit must be set to enable the interrupt.\r
+//! - \b ADC12_B_HIIE - Interrupt enable for the exceeding the upper\r
+//! limit of the window comparator for the result register. GIE bit\r
+//! must be set to enable the interrupt.\r
+//! - \b ADC12_B_OVIE - Interrupt enable for a conversion that is about\r
+//! to save to a memory buffer that has not been read out yet. GIE\r
+//! bit must be set to enable the interrupt.\r
+//! - \b ADC12_B_TOVIE - enable for a conversion that is about to start\r
+//! before the previous conversion has been completed. GIE bit must\r
+//! be set to enable the interrupt.\r
+//! - \b ADC12_B_RDYIE - enable for the local buffered reference ready\r
+//! signal. GIE bit must be set to enable the interrupt.\r
+//!\r
+//! Modified bits of \b ADC12IERx register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_disableInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptMask0,\r
+ uint16_t interruptMask1,\r
+ uint16_t interruptMask2);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears ADC12B selected interrupt flags.\r
+//!\r
+//! Modified registers are ADC12IFG .\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param interruptRegisterChoice is either 0, 1, or 2, to choose the correct\r
+//! interrupt register to update\r
+//! \param memoryInterruptFlagMask is the bit mask of the memory buffer and\r
+//! overflow interrupt flags to be cleared.\r
+//! Valid values are:\r
+//! - \b ADC12_B_IFG0 - interruptRegisterChoice = 0\r
+//! - \b ADC12_B_IFG1\r
+//! - \b ADC12_B_IFG2\r
+//! - \b ADC12_B_IFG3\r
+//! - \b ADC12_B_IFG4\r
+//! - \b ADC12_B_IFG5\r
+//! - \b ADC12_B_IFG6\r
+//! - \b ADC12_B_IFG7\r
+//! - \b ADC12_B_IFG8\r
+//! - \b ADC12_B_IFG9\r
+//! - \b ADC12_B_IFG10\r
+//! - \b ADC12_B_IFG11\r
+//! - \b ADC12_B_IFG12\r
+//! - \b ADC12_B_IFG13\r
+//! - \b ADC12_B_IFG14\r
+//! - \b ADC12_B_IFG15\r
+//! - \b ADC12_B_IFG16 - interruptRegisterChoice = 1\r
+//! - \b ADC12_B_IFG17\r
+//! - \b ADC12_B_IFG18\r
+//! - \b ADC12_B_IFG19\r
+//! - \b ADC12_B_IFG20\r
+//! - \b ADC12_B_IFG21\r
+//! - \b ADC12_B_IFG22\r
+//! - \b ADC12_B_IFG23\r
+//! - \b ADC12_B_IFG24\r
+//! - \b ADC12_B_IFG25\r
+//! - \b ADC12_B_IFG26\r
+//! - \b ADC12_B_IFG27\r
+//! - \b ADC12_B_IFG28\r
+//! - \b ADC12_B_IFG29\r
+//! - \b ADC12_B_IFG30\r
+//! - \b ADC12_B_IFG31\r
+//! - \b ADC12_B_INIFG - interruptRegisterChoice = 2\r
+//! - \b ADC12_B_LOIFG\r
+//! - \b ADC12_B_HIIFG\r
+//! - \b ADC12_B_OVIFG\r
+//! - \b ADC12_B_TOVIFG\r
+//! - \b ADC12_B_RDYIFG - The selected ADC12B interrupt flags are\r
+//! cleared, so that it no longer asserts. The memory buffer\r
+//! interrupt flags are only cleared when the memory buffer is\r
+//! accessed. Note that the overflow interrupts do not have an\r
+//! interrupt flag to clear; they must be accessed directly from the\r
+//! interrupt vector.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptRegisterChoice,\r
+ uint16_t memoryInterruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the status of the selected memory interrupt flags.\r
+//!\r
+//! Returns the status of the selected memory interrupt flags. Note that the\r
+//! overflow interrupts do not have an interrupt flag to clear; they must be\r
+//! accessed directly from the interrupt vector.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param interruptRegisterChoice is either 0, 1, or 2, to choose the correct\r
+//! interrupt register to update\r
+//! \param memoryInterruptFlagMask is the bit mask of the memory buffer and\r
+//! overflow interrupt flags to be cleared.\r
+//! Valid values are:\r
+//! - \b ADC12_B_IFG0 - interruptRegisterChoice = 0\r
+//! - \b ADC12_B_IFG1\r
+//! - \b ADC12_B_IFG2\r
+//! - \b ADC12_B_IFG3\r
+//! - \b ADC12_B_IFG4\r
+//! - \b ADC12_B_IFG5\r
+//! - \b ADC12_B_IFG6\r
+//! - \b ADC12_B_IFG7\r
+//! - \b ADC12_B_IFG8\r
+//! - \b ADC12_B_IFG9\r
+//! - \b ADC12_B_IFG10\r
+//! - \b ADC12_B_IFG11\r
+//! - \b ADC12_B_IFG12\r
+//! - \b ADC12_B_IFG13\r
+//! - \b ADC12_B_IFG14\r
+//! - \b ADC12_B_IFG15\r
+//! - \b ADC12_B_IFG16 - interruptRegisterChoice = 1\r
+//! - \b ADC12_B_IFG17\r
+//! - \b ADC12_B_IFG18\r
+//! - \b ADC12_B_IFG19\r
+//! - \b ADC12_B_IFG20\r
+//! - \b ADC12_B_IFG21\r
+//! - \b ADC12_B_IFG22\r
+//! - \b ADC12_B_IFG23\r
+//! - \b ADC12_B_IFG24\r
+//! - \b ADC12_B_IFG25\r
+//! - \b ADC12_B_IFG26\r
+//! - \b ADC12_B_IFG27\r
+//! - \b ADC12_B_IFG28\r
+//! - \b ADC12_B_IFG29\r
+//! - \b ADC12_B_IFG30\r
+//! - \b ADC12_B_IFG31\r
+//! - \b ADC12_B_INIFG - interruptRegisterChoice = 2\r
+//! - \b ADC12_B_LOIFG\r
+//! - \b ADC12_B_HIIFG\r
+//! - \b ADC12_B_OVIFG\r
+//! - \b ADC12_B_TOVIFG\r
+//! - \b ADC12_B_RDYIFG - The selected ADC12B interrupt flags are\r
+//! cleared, so that it no longer asserts. The memory buffer\r
+//! interrupt flags are only cleared when the memory buffer is\r
+//! accessed. Note that the overflow interrupts do not have an\r
+//! interrupt flag to clear; they must be accessed directly from the\r
+//! interrupt vector.\r
+//!\r
+//! \return The current interrupt flag status for the corresponding mask.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t ADC12_B_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t interruptRegisterChoice,\r
+ uint16_t memoryInterruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables/Starts an Analog-to-Digital Conversion.\r
+//!\r
+//! Enables/starts the conversion process of the ADC. If the sample/hold signal\r
+//! source chosen during initialization was ADC12OSC, then the conversion is\r
+//! started immediately, otherwise the chosen sample/hold signal source starts\r
+//! the conversion by a rising edge of the signal. Keep in mind when selecting\r
+//! conversion modes, that for sequenced and/or repeated modes, to keep the\r
+//! sample/hold-and-convert process continuing without a trigger from the\r
+//! sample/hold signal source, the multiple samples must be enabled using the\r
+//! ADC12_B_setupSamplingTimer() function. Note that after this function is\r
+//! called, the ADC12_B_stopConversions() has to be called to re-initialize the\r
+//! ADC, reconfigure a memory buffer control, enable/disable the sampling\r
+//! timer, or to change the internal reference voltage.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param startingMemoryBufferIndex is the memory buffer that will hold the\r
+//! first or only conversion.\r
+//! Valid values are:\r
+//! - \b ADC12_B_START_AT_ADC12MEM0 [Default]\r
+//! - \b ADC12_B_START_AT_ADC12MEM1\r
+//! - \b ADC12_B_START_AT_ADC12MEM2\r
+//! - \b ADC12_B_START_AT_ADC12MEM3\r
+//! - \b ADC12_B_START_AT_ADC12MEM4\r
+//! - \b ADC12_B_START_AT_ADC12MEM5\r
+//! - \b ADC12_B_START_AT_ADC12MEM6\r
+//! - \b ADC12_B_START_AT_ADC12MEM7\r
+//! - \b ADC12_B_START_AT_ADC12MEM8\r
+//! - \b ADC12_B_START_AT_ADC12MEM9\r
+//! - \b ADC12_B_START_AT_ADC12MEM10\r
+//! - \b ADC12_B_START_AT_ADC12MEM11\r
+//! - \b ADC12_B_START_AT_ADC12MEM12\r
+//! - \b ADC12_B_START_AT_ADC12MEM13\r
+//! - \b ADC12_B_START_AT_ADC12MEM14\r
+//! - \b ADC12_B_START_AT_ADC12MEM15\r
+//! - \b ADC12_B_START_AT_ADC12MEM16\r
+//! - \b ADC12_B_START_AT_ADC12MEM17\r
+//! - \b ADC12_B_START_AT_ADC12MEM18\r
+//! - \b ADC12_B_START_AT_ADC12MEM19\r
+//! - \b ADC12_B_START_AT_ADC12MEM20\r
+//! - \b ADC12_B_START_AT_ADC12MEM21\r
+//! - \b ADC12_B_START_AT_ADC12MEM22\r
+//! - \b ADC12_B_START_AT_ADC12MEM23\r
+//! - \b ADC12_B_START_AT_ADC12MEM24\r
+//! - \b ADC12_B_START_AT_ADC12MEM25\r
+//! - \b ADC12_B_START_AT_ADC12MEM26\r
+//! - \b ADC12_B_START_AT_ADC12MEM27\r
+//! - \b ADC12_B_START_AT_ADC12MEM28\r
+//! - \b ADC12_B_START_AT_ADC12MEM29\r
+//! - \b ADC12_B_START_AT_ADC12MEM30\r
+//! - \b ADC12_B_START_AT_ADC12MEM31\r
+//! \n Modified bits are \b ADC12CSTARTADDx of \b ADC12CTL1 register.\r
+//! \param conversionSequenceModeSelect determines the ADC operating mode.\r
+//! Valid values are:\r
+//! - \b ADC12_B_SINGLECHANNEL [Default] - one-time conversion of a\r
+//! single channel into a single memory buffer.\r
+//! - \b ADC12_B_SEQOFCHANNELS - one time conversion of multiple\r
+//! channels into the specified starting memory buffer and each\r
+//! subsequent memory buffer up until the conversion is stored in a\r
+//! memory buffer dedicated as the end-of-sequence by the memory's\r
+//! control register.\r
+//! - \b ADC12_B_REPEATED_SINGLECHANNEL - repeated conversions of one\r
+//! channel into a single memory buffer.\r
+//! - \b ADC12_B_REPEATED_SEQOFCHANNELS - repeated conversions of\r
+//! multiple channels into the specified starting memory buffer and\r
+//! each subsequent memory buffer up until the conversion is stored\r
+//! in a memory buffer dedicated as the end-of-sequence by the\r
+//! memory's control register.\r
+//! \n Modified bits are \b ADC12CONSEQx of \b ADC12CTL1 register.\r
+//!\r
+//! Modified bits of \b ADC12CTL1 register and bits of \b ADC12CTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_startConversion(uint16_t baseAddress,\r
+ uint16_t startingMemoryBufferIndex,\r
+ uint8_t conversionSequenceModeSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the ADC from converting any more signals.\r
+//!\r
+//! Disables the ADC from converting any more signals. If there is a conversion\r
+//! in progress, this function can stop it immediately if the preempt parameter\r
+//! is set as ADC12_B_PREEMPTCONVERSION, by changing the conversion mode to\r
+//! single-channel, single-conversion and disabling conversions. If the\r
+//! conversion mode is set as single-channel, single-conversion and this\r
+//! function is called without preemption, then the ADC core conversion status\r
+//! is polled until the conversion is complete before disabling conversions to\r
+//! prevent unpredictable data. If the ADC12_B_startConversion() has been\r
+//! called, then this function has to be called to re-initialize the ADC,\r
+//! reconfigure a memory buffer control, enable/disable the sampling pulse\r
+//! mode, or change the internal reference voltage.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param preempt specifies if the current conversion should be preemptively\r
+//! stopped before the end of the conversion.\r
+//! Valid values are:\r
+//! - \b ADC12_B_COMPLETECONVERSION - Allows the ADC12B to end the\r
+//! current conversion before disabling conversions.\r
+//! - \b ADC12_B_PREEMPTCONVERSION - Stops the ADC12B immediately, with\r
+//! unpredictable results of the current conversion.\r
+//!\r
+//! Modified bits of \b ADC12CTL1 register and bits of \b ADC12CTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_disableConversions(uint16_t baseAddress,\r
+ bool preempt);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the raw contents of the specified memory buffer.\r
+//!\r
+//! Returns the raw contents of the specified memory buffer. The format of the\r
+//! content depends on the read-back format of the data: if the data is in\r
+//! signed 2's complement format then the contents in the memory buffer will be\r
+//! left-justified with the least-significant bits as 0's, whereas if the data\r
+//! is in unsigned format then the contents in the memory buffer will be right-\r
+//! justified with the most-significant bits as 0's.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param memoryBufferIndex is the specified memory buffer to read.\r
+//! Valid values are:\r
+//! - \b ADC12_B_MEMORY_0\r
+//! - \b ADC12_B_MEMORY_1\r
+//! - \b ADC12_B_MEMORY_2\r
+//! - \b ADC12_B_MEMORY_3\r
+//! - \b ADC12_B_MEMORY_4\r
+//! - \b ADC12_B_MEMORY_5\r
+//! - \b ADC12_B_MEMORY_6\r
+//! - \b ADC12_B_MEMORY_7\r
+//! - \b ADC12_B_MEMORY_8\r
+//! - \b ADC12_B_MEMORY_9\r
+//! - \b ADC12_B_MEMORY_10\r
+//! - \b ADC12_B_MEMORY_11\r
+//! - \b ADC12_B_MEMORY_12\r
+//! - \b ADC12_B_MEMORY_13\r
+//! - \b ADC12_B_MEMORY_14\r
+//! - \b ADC12_B_MEMORY_15\r
+//! - \b ADC12_B_MEMORY_16\r
+//! - \b ADC12_B_MEMORY_17\r
+//! - \b ADC12_B_MEMORY_18\r
+//! - \b ADC12_B_MEMORY_19\r
+//! - \b ADC12_B_MEMORY_20\r
+//! - \b ADC12_B_MEMORY_21\r
+//! - \b ADC12_B_MEMORY_22\r
+//! - \b ADC12_B_MEMORY_23\r
+//! - \b ADC12_B_MEMORY_24\r
+//! - \b ADC12_B_MEMORY_25\r
+//! - \b ADC12_B_MEMORY_26\r
+//! - \b ADC12_B_MEMORY_27\r
+//! - \b ADC12_B_MEMORY_28\r
+//! - \b ADC12_B_MEMORY_29\r
+//! - \b ADC12_B_MEMORY_30\r
+//! - \b ADC12_B_MEMORY_31\r
+//!\r
+//! \return A signed integer of the contents of the specified memory buffer.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t ADC12_B_getResults(uint16_t baseAddress,\r
+ uint8_t memoryBufferIndex);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Use to change the resolution of the converted data.\r
+//!\r
+//! This function can be used to change the resolution of the converted data\r
+//! from the default of 12-bits.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param resolutionSelect determines the resolution of the converted data.\r
+//! Valid values are:\r
+//! - \b ADC12_B_RESOLUTION_8BIT\r
+//! - \b ADC12_B_RESOLUTION_10BIT\r
+//! - \b ADC12_B_RESOLUTION_12BIT [Default]\r
+//! \n Modified bits are \b ADC12RESx of \b ADC12CTL2 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_setResolution(uint16_t baseAddress,\r
+ uint8_t resolutionSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Use to invert or un-invert the sample/hold signal.\r
+//!\r
+//! This function can be used to invert or un-invert the sample/hold signal.\r
+//! Note that if a conversion has been started with the startConversion()\r
+//! function, then a call to disableConversions() is required before this\r
+//! function may be called.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param invertedSignal set if the sample/hold signal should be inverted\r
+//! Valid values are:\r
+//! - \b ADC12_B_NONINVERTEDSIGNAL [Default] - a sample-and-hold of an\r
+//! input signal for conversion will be started on a rising edge of\r
+//! the sample/hold signal.\r
+//! - \b ADC12_B_INVERTEDSIGNAL - a sample-and-hold of an input signal\r
+//! for conversion will be started on a falling edge of the\r
+//! sample/hold signal.\r
+//! \n Modified bits are \b ADC12ISSH of \b ADC12CTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_setSampleHoldSignalInversion(uint16_t baseAddress,\r
+ uint16_t invertedSignal);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Use to set the read-back format of the converted data.\r
+//!\r
+//! Sets the format of the converted data: how it will be stored into the\r
+//! memory buffer, and how it should be read back. The format can be set as\r
+//! right-justified (default), which indicates that the number will be\r
+//! unsigned, or left-justified, which indicates that the number will be signed\r
+//! in 2's complement format. This change affects all memory buffers for\r
+//! subsequent conversions.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param readBackFormat is the specified format to store the conversions in\r
+//! the memory buffer.\r
+//! Valid values are:\r
+//! - \b ADC12_B_UNSIGNED_BINARY [Default]\r
+//! - \b ADC12_B_SIGNED_2SCOMPLEMENT\r
+//! \n Modified bits are \b ADC12DF of \b ADC12CTL2 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_setDataReadBackFormat(uint16_t baseAddress,\r
+ uint8_t readBackFormat);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Use to set the ADC's power conservation mode if the sampling rate is\r
+//! at 50-ksps or less.\r
+//!\r
+//! Sets ADC's power mode. If the user has a sampling rate greater than\r
+//! 50-ksps, then he/she can only enable ADC12_B_REGULARPOWERMODE. If the\r
+//! sampling rate is 50-ksps or less, the user can enable ADC12_B_LOWPOWERMODE\r
+//! granting additional power savings.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param powerMode is the specified maximum sampling rate.\r
+//! Valid values are:\r
+//! - \b ADC12_B_REGULARPOWERMODE [Default] - If sampling rate is\r
+//! greater than 50-ksps, there is no power saving feature available.\r
+//! - \b ADC12_B_LOWPOWERMODE - If sampling rate is less than or equal\r
+//! to 50-ksps, select this value to save power\r
+//! \n Modified bits are \b ADC12SR of \b ADC12CTL2 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void ADC12_B_setAdcPowerMode(uint16_t baseAddress,\r
+ uint8_t powerMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the specified memory buffer for the DMA\r
+//! module.\r
+//!\r
+//! Returns the address of the specified memory buffer. This can be used in\r
+//! conjunction with the DMA to store the converted data directly to memory.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//! \param memoryIndex is the memory buffer to return the address of.\r
+//! Valid values are:\r
+//! - \b ADC12_B_MEMORY_0\r
+//! - \b ADC12_B_MEMORY_1\r
+//! - \b ADC12_B_MEMORY_2\r
+//! - \b ADC12_B_MEMORY_3\r
+//! - \b ADC12_B_MEMORY_4\r
+//! - \b ADC12_B_MEMORY_5\r
+//! - \b ADC12_B_MEMORY_6\r
+//! - \b ADC12_B_MEMORY_7\r
+//! - \b ADC12_B_MEMORY_8\r
+//! - \b ADC12_B_MEMORY_9\r
+//! - \b ADC12_B_MEMORY_10\r
+//! - \b ADC12_B_MEMORY_11\r
+//! - \b ADC12_B_MEMORY_12\r
+//! - \b ADC12_B_MEMORY_13\r
+//! - \b ADC12_B_MEMORY_14\r
+//! - \b ADC12_B_MEMORY_15\r
+//! - \b ADC12_B_MEMORY_16\r
+//! - \b ADC12_B_MEMORY_17\r
+//! - \b ADC12_B_MEMORY_18\r
+//! - \b ADC12_B_MEMORY_19\r
+//! - \b ADC12_B_MEMORY_20\r
+//! - \b ADC12_B_MEMORY_21\r
+//! - \b ADC12_B_MEMORY_22\r
+//! - \b ADC12_B_MEMORY_23\r
+//! - \b ADC12_B_MEMORY_24\r
+//! - \b ADC12_B_MEMORY_25\r
+//! - \b ADC12_B_MEMORY_26\r
+//! - \b ADC12_B_MEMORY_27\r
+//! - \b ADC12_B_MEMORY_28\r
+//! - \b ADC12_B_MEMORY_29\r
+//! - \b ADC12_B_MEMORY_30\r
+//! - \b ADC12_B_MEMORY_31\r
+//!\r
+//! \return address of the specified memory buffer\r
+//\r
+//*****************************************************************************\r
+extern uint32_t ADC12_B_getMemoryAddressForDMA(uint16_t baseAddress,\r
+ uint8_t memoryIndex);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the busy status of the ADC12B core.\r
+//!\r
+//! Returns the status of the ADC core if there is a conversion currently\r
+//! taking place.\r
+//!\r
+//! \param baseAddress is the base address of the ADC12B module.\r
+//!\r
+//! \return ADC12_B_BUSY or ADC12_B_NOTBUSY dependent if there is a conversion\r
+//! currently taking place.\r
+//! Return one of the following:\r
+//! - \b ADC12_B_NOTBUSY\r
+//! - \b ADC12_B_BUSY\r
+//! \n indicating if a conversion is taking place\r
+//\r
+//*****************************************************************************\r
+extern uint8_t ADC12_B_isBusy(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_ADC12_B_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// aes256.c - Driver for the aes256 Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup aes256_api aes256\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_AES256__\r
+#include "aes256.h"\r
+\r
+#include <assert.h>\r
+\r
+uint8_t AES256_setCipherKey(uint16_t baseAddress,\r
+ const uint8_t * cipherKey,\r
+ uint16_t keyLength)\r
+{\r
+ uint8_t i;\r
+ uint16_t sCipherKey;\r
+\r
+ HWREG16(baseAddress + OFS_AESACTL0) &= (~(AESKL_1 + AESKL_2));\r
+\r
+ switch(keyLength)\r
+ {\r
+ case AES256_KEYLENGTH_128BIT:\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__128;\r
+ break;\r
+\r
+ case AES256_KEYLENGTH_192BIT:\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__192;\r
+ break;\r
+\r
+ case AES256_KEYLENGTH_256BIT:\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__256;\r
+ break;\r
+\r
+ default:\r
+ return(STATUS_FAIL);\r
+ }\r
+\r
+ keyLength = keyLength / 8;\r
+\r
+ for(i = 0; i < keyLength; i = i + 2)\r
+ {\r
+ sCipherKey = (uint16_t)(cipherKey[i]);\r
+ sCipherKey = sCipherKey | ((uint16_t)(cipherKey[i + 1]) << 8);\r
+ HWREG16(baseAddress + OFS_AESAKEY) = sCipherKey;\r
+ }\r
+\r
+ // Wait until key is written\r
+ while(0x00 == (HWREG16(baseAddress + OFS_AESASTAT) & AESKEYWR))\r
+ {\r
+ ;\r
+ }\r
+ return(STATUS_SUCCESS);\r
+}\r
+\r
+void AES256_encryptData(uint16_t baseAddress,\r
+ const uint8_t * data,\r
+ uint8_t * encryptedData)\r
+{\r
+ uint8_t i;\r
+ uint16_t tempData = 0;\r
+ uint16_t tempVariable = 0;\r
+\r
+ // Set module to encrypt mode\r
+ HWREG16(baseAddress + OFS_AESACTL0) &= ~AESOP_3;\r
+\r
+ // Write data to encrypt to module\r
+ for(i = 0; i < 16; i = i + 2)\r
+ {\r
+ tempVariable = (uint16_t)(data[i]);\r
+ tempVariable = tempVariable | ((uint16_t)(data[i + 1]) << 8);\r
+ HWREG16(baseAddress + OFS_AESADIN) = tempVariable;\r
+ }\r
+\r
+ // Key that is already written shall be used\r
+ // Encryption is initialized by setting AESKEYWR to 1\r
+ HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR;\r
+\r
+ // Wait unit finished ~167 MCLK\r
+ while(AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY))\r
+ {\r
+ ;\r
+ }\r
+\r
+ // Write encrypted data back to variable\r
+ for(i = 0; i < 16; i = i + 2)\r
+ {\r
+ tempData = HWREG16(baseAddress + OFS_AESADOUT);\r
+ *(encryptedData + i) = (uint8_t)tempData;\r
+ *(encryptedData + i + 1) = (uint8_t)(tempData >> 8);\r
+ }\r
+}\r
+\r
+void AES256_decryptData(uint16_t baseAddress,\r
+ const uint8_t * data,\r
+ uint8_t * decryptedData)\r
+{\r
+ uint8_t i;\r
+ uint16_t tempData = 0;\r
+ uint16_t tempVariable = 0;\r
+\r
+ // Set module to decrypt mode\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= (AESOP_3);\r
+\r
+ // Write data to decrypt to module\r
+ for(i = 0; i < 16; i = i + 2)\r
+ {\r
+ tempVariable = (uint16_t)(data[i + 1] << 8);\r
+ tempVariable = tempVariable | ((uint16_t)(data[i]));\r
+ HWREG16(baseAddress + OFS_AESADIN) = tempVariable;\r
+ }\r
+\r
+ // Key that is already written shall be used\r
+ // Now decryption starts\r
+ HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR;\r
+\r
+ // Wait unit finished ~167 MCLK\r
+ while(AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY))\r
+ {\r
+ ;\r
+ }\r
+\r
+ // Write encrypted data back to variable\r
+ for(i = 0; i < 16; i = i + 2)\r
+ {\r
+ tempData = HWREG16(baseAddress + OFS_AESADOUT);\r
+ *(decryptedData + i) = (uint8_t)tempData;\r
+ *(decryptedData + i + 1) = (uint8_t)(tempData >> 8);\r
+ }\r
+}\r
+\r
+uint8_t AES256_setDecipherKey(uint16_t baseAddress,\r
+ const uint8_t * cipherKey,\r
+ uint16_t keyLength)\r
+{\r
+ uint8_t i;\r
+ uint16_t tempVariable = 0;\r
+\r
+ // Set module to decrypt mode\r
+ HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP0);\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESOP1;\r
+\r
+ switch(keyLength)\r
+ {\r
+ case AES256_KEYLENGTH_128BIT:\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__128;\r
+ break;\r
+\r
+ case AES256_KEYLENGTH_192BIT:\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__192;\r
+ break;\r
+\r
+ case AES256_KEYLENGTH_256BIT:\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__256;\r
+ break;\r
+\r
+ default:\r
+ return(STATUS_FAIL);\r
+ }\r
+\r
+ keyLength = keyLength / 8;\r
+\r
+ // Write cipher key to key register\r
+ for(i = 0; i < keyLength; i = i + 2)\r
+ {\r
+ tempVariable = (uint16_t)(cipherKey[i]);\r
+ tempVariable = tempVariable | ((uint16_t)(cipherKey[i + 1]) << 8);\r
+ HWREG16(baseAddress + OFS_AESAKEY) = tempVariable;\r
+ }\r
+\r
+ // Wait until key is processed ~52 MCLK\r
+ while((HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY) == AESBUSY)\r
+ {\r
+ ;\r
+ }\r
+\r
+ return(STATUS_SUCCESS);\r
+}\r
+\r
+void AES256_clearInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_AESACTL0) &= ~AESRDYIFG;\r
+}\r
+\r
+uint32_t AES256_getInterruptStatus(uint16_t baseAddress)\r
+{\r
+ return ((HWREG16(baseAddress + OFS_AESACTL0) & AESRDYIFG) << 0x04);\r
+}\r
+\r
+void AES256_enableInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESRDYIE;\r
+}\r
+\r
+void AES256_disableInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_AESACTL0) &= ~AESRDYIE;\r
+}\r
+\r
+void AES256_reset(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESSWRST;\r
+}\r
+\r
+void AES256_startEncryptData(uint16_t baseAddress,\r
+ const uint8_t * data)\r
+{\r
+ uint8_t i;\r
+ uint16_t tempVariable = 0;\r
+\r
+ // Set module to encrypt mode\r
+ HWREG16(baseAddress + OFS_AESACTL0) &= ~AESOP_3;\r
+\r
+ // Write data to encrypt to module\r
+ for(i = 0; i < 16; i = i + 2)\r
+ {\r
+ tempVariable = (uint16_t)(data[i]);\r
+ tempVariable = tempVariable | ((uint16_t)(data[i + 1 ]) << 8);\r
+ HWREG16(baseAddress + OFS_AESADIN) = tempVariable;\r
+ }\r
+\r
+ // Key that is already written shall be used\r
+ // Encryption is initialized by setting AESKEYWR to 1\r
+ HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR;\r
+}\r
+\r
+void AES256_startDecryptData(uint16_t baseAddress,\r
+ const uint8_t * data)\r
+{\r
+ uint8_t i;\r
+ uint16_t tempVariable = 0;\r
+\r
+ // Set module to decrypt mode\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= (AESOP_3);\r
+\r
+ // Write data to decrypt to module\r
+ for(i = 0; i < 16; i = i + 2)\r
+ {\r
+ tempVariable = (uint16_t)(data[i + 1] << 8);\r
+ tempVariable = tempVariable | ((uint16_t)(data[i]));\r
+ HWREG16(baseAddress + OFS_AESADIN) = tempVariable;\r
+ }\r
+\r
+ // Key that is already written shall be used\r
+ // Now decryption starts\r
+ HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR;\r
+}\r
+\r
+uint8_t AES256_startSetDecipherKey(uint16_t baseAddress,\r
+ const uint8_t * cipherKey,\r
+ uint16_t keyLength)\r
+{\r
+ uint8_t i;\r
+ uint16_t tempVariable = 0;\r
+\r
+ HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP0);\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESOP1;\r
+\r
+ switch(keyLength)\r
+ {\r
+ case AES256_KEYLENGTH_128BIT:\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__128;\r
+ break;\r
+\r
+ case AES256_KEYLENGTH_192BIT:\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__192;\r
+ break;\r
+\r
+ case AES256_KEYLENGTH_256BIT:\r
+ HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__256;\r
+ break;\r
+\r
+ default:\r
+ return(STATUS_FAIL);\r
+ }\r
+\r
+ keyLength = keyLength / 8;\r
+\r
+ // Write cipher key to key register\r
+ for(i = 0; i < keyLength; i = i + 2)\r
+ {\r
+ tempVariable = (uint16_t)(cipherKey[i]);\r
+ tempVariable = tempVariable | ((uint16_t)(cipherKey[i + 1]) << 8);\r
+ HWREG16(baseAddress + OFS_AESAKEY) = tempVariable;\r
+ }\r
+\r
+ return(STATUS_SUCCESS);\r
+}\r
+\r
+uint8_t AES256_getDataOut(uint16_t baseAddress,\r
+ uint8_t *outputData)\r
+{\r
+ uint8_t i;\r
+ uint16_t tempData = 0;\r
+\r
+ // If module is busy, exit and return failure\r
+ if(AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY))\r
+ {\r
+ return(STATUS_FAIL);\r
+ }\r
+\r
+ // Write encrypted data back to variable\r
+ for(i = 0; i < 16; i = i + 2)\r
+ {\r
+ tempData = HWREG16(baseAddress + OFS_AESADOUT);\r
+ *(outputData + i) = (uint8_t)tempData;\r
+ *(outputData + i + 1) = (uint8_t)(tempData >> 8);\r
+ }\r
+\r
+ return(STATUS_SUCCESS);\r
+}\r
+\r
+uint16_t AES256_isBusy(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY);\r
+}\r
+\r
+void AES256_clearErrorFlag(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_AESACTL0) &= ~AESERRFG;\r
+}\r
+\r
+uint32_t AES256_getErrorFlagStatus(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_AESACTL0) & AESERRFG);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for aes256_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// aes256.h - Driver for the AES256 Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_AES256_H__\r
+#define __MSP430WARE_AES256_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_AES256__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the keyLength parameter for\r
+// functions: AES256_setCipherKey(), AES256_setDecipherKey(), and\r
+// AES256_startSetDecipherKey().\r
+//\r
+//*****************************************************************************\r
+#define AES256_KEYLENGTH_128BIT 128\r
+#define AES256_KEYLENGTH_192BIT 192\r
+#define AES256_KEYLENGTH_256BIT 256\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the AES256_getErrorFlagStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define AES256_ERROR_OCCURRED AESERRFG\r
+#define AES256_NO_ERROR 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the AES256_isBusy() function.\r
+//\r
+//*****************************************************************************\r
+#define AES256_BUSY AESBUSY\r
+#define AES256_NOT_BUSY 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the AES256_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define AES256_READY_INTERRUPT AESRDYIE\r
+#define AES256_NOTREADY_INTERRUPT 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Loads a 128, 192 or 256 bit cipher key to AES256 module.\r
+//!\r
+//! This function loads a 128, 192 or 256 bit cipher key to AES256 module.\r
+//! Requires both a key as well as the length of the key provided. Acceptable\r
+//! key lengths are AES256_KEYLENGTH_128BIT, AES256_KEYLENGTH_192BIT, or\r
+//! AES256_KEYLENGTH_256BIT\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes\r
+//! that contains a 128 bit cipher key.\r
+//! \param keyLength is the length of the key.\r
+//! Valid values are:\r
+//! - \b AES256_KEYLENGTH_128BIT\r
+//! - \b AES256_KEYLENGTH_192BIT\r
+//! - \b AES256_KEYLENGTH_256BIT\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL of key loading\r
+//\r
+//*****************************************************************************\r
+extern uint8_t AES256_setCipherKey(uint16_t baseAddress,\r
+ const uint8_t *cipherKey,\r
+ uint16_t keyLength);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Encrypts a block of data using the AES256 module.\r
+//!\r
+//! The cipher key that is used for encryption should be loaded in advance by\r
+//! using function AES256_setCipherKey()\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that\r
+//! contains data to be encrypted.\r
+//! \param encryptedData is a pointer to an uint8_t array with a length of 16\r
+//! bytes in that the encrypted data will be written.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void AES256_encryptData(uint16_t baseAddress,\r
+ const uint8_t *data,\r
+ uint8_t *encryptedData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Decrypts a block of data using the AES256 module.\r
+//!\r
+//! This function requires a pregenerated decryption key. A key can be loaded\r
+//! and pregenerated by using function AES256_setDecipherKey() or\r
+//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that\r
+//! contains encrypted data to be decrypted.\r
+//! \param decryptedData is a pointer to an uint8_t array with a length of 16\r
+//! bytes in that the decrypted data will be written.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void AES256_decryptData(uint16_t baseAddress,\r
+ const uint8_t *data,\r
+ uint8_t *decryptedData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the decipher key.\r
+//!\r
+//! The API AES256_startSetDecipherKey or AES256_setDecipherKey must be invoked\r
+//! before invoking AES256_startDecryptData.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes\r
+//! that contains a 128 bit cipher key.\r
+//! \param keyLength is the length of the key.\r
+//! Valid values are:\r
+//! - \b AES256_KEYLENGTH_128BIT\r
+//! - \b AES256_KEYLENGTH_192BIT\r
+//! - \b AES256_KEYLENGTH_256BIT\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL of key loading\r
+//\r
+//*****************************************************************************\r
+extern uint8_t AES256_setDecipherKey(uint16_t baseAddress,\r
+ const uint8_t *cipherKey,\r
+ uint16_t keyLength);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the AES256 ready interrupt flag.\r
+//!\r
+//! This function clears the AES256 ready interrupt flag. This flag is\r
+//! automatically cleared when AES256ADOUT is read, or when AES256AKEY or\r
+//! AES256ADIN is written. This function should be used when the flag needs to\r
+//! be reset and it has not been automatically cleared by one of the previous\r
+//! actions.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//!\r
+//! Modified bits are \b AESRDYIFG of \b AESACTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void AES256_clearInterrupt(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the AES256 ready interrupt flag status.\r
+//!\r
+//! This function checks the AES256 ready interrupt flag. This flag is\r
+//! automatically cleared when AES256ADOUT is read, or when AES256AKEY or\r
+//! AES256ADIN is written. This function can be used to confirm that this has\r
+//! been done.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b AES256_READY_INTERRUPT\r
+//! - \b AES256_NOTREADY_INTERRUPT\r
+//! \n indicating the status of the AES256 ready status\r
+//\r
+//*****************************************************************************\r
+extern uint32_t AES256_getInterruptStatus(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables AES256 ready interrupt.\r
+//!\r
+//! Enables AES256 ready interrupt. This interrupt is reset by a PUC, but not\r
+//! reset by AES256_reset.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//!\r
+//! Modified bits are \b AESRDYIE of \b AESACTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void AES256_enableInterrupt(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables AES256 ready interrupt.\r
+//!\r
+//! Disables AES256 ready interrupt. This interrupt is reset by a PUC, but not\r
+//! reset by AES256_reset.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//!\r
+//! Modified bits are \b AESRDYIE of \b AESACTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void AES256_disableInterrupt(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Resets AES256 Module immediately.\r
+//!\r
+//! This function performs a software reset on the AES256 Module, note that\r
+//! this does not affect the AES256 ready interrupt.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//!\r
+//! Modified bits are \b AESSWRST of \b AESACTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void AES256_reset(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts an encryption process on the AES256 module.\r
+//!\r
+//! The cipher key that is used for decryption should be loaded in advance by\r
+//! using function AES256_setCipherKey(). This is a non-blocking equivalent of\r
+//! AES256_encryptData(). It is recommended to use the interrupt functionality\r
+//! to check for procedure completion then use the AES256_getDataOut() API to\r
+//! retrieve the encrypted data.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that\r
+//! contains data to be encrypted.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void AES256_startEncryptData(uint16_t baseAddress,\r
+ const uint8_t *data);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Decrypts a block of data using the AES256 module.\r
+//!\r
+//! This is the non-blocking equivalent of AES256_decryptData(). This function\r
+//! requires a pregenerated decryption key. A key can be loaded and\r
+//! pregenerated by using function AES256_setDecipherKey() or\r
+//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK. It is\r
+//! recommended to use interrupt to check for procedure completion then use the\r
+//! AES256_getDataOut() API to retrieve the decrypted data.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that\r
+//! contains encrypted data to be decrypted.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void AES256_startDecryptData(uint16_t baseAddress,\r
+ const uint8_t *data);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the decipher key\r
+//!\r
+//! The API AES256_startSetDecipherKey() or AES256_setDecipherKey() must be\r
+//! invoked before invoking AES256_startDecryptData.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes\r
+//! that contains a 128 bit cipher key.\r
+//! \param keyLength is the length of the key.\r
+//! Valid values are:\r
+//! - \b AES256_KEYLENGTH_128BIT\r
+//! - \b AES256_KEYLENGTH_192BIT\r
+//! - \b AES256_KEYLENGTH_256BIT\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL of key loading\r
+//\r
+//*****************************************************************************\r
+extern uint8_t AES256_startSetDecipherKey(uint16_t baseAddress,\r
+ const uint8_t *cipherKey,\r
+ uint16_t keyLength);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Reads back the output data from AES256 module.\r
+//!\r
+//! This function is meant to use after an encryption or decryption process\r
+//! that was started and finished by initiating an interrupt by use of\r
+//! AES256_startEncryptData or AES256_startDecryptData functions.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//! \param outputData is a pointer to an uint8_t array with a length of 16\r
+//! bytes in that the data will be written.\r
+//!\r
+//! \return STATUS_SUCCESS if data is valid, otherwise STATUS_FAIL\r
+//\r
+//*****************************************************************************\r
+extern uint8_t AES256_getDataOut(uint16_t baseAddress,\r
+ uint8_t *outputData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the AES256 module busy status.\r
+//!\r
+//! Gets the AES256 module busy status. If a key or data are written while the\r
+//! AES256 module is busy, an error flag will be thrown.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b AES256_BUSY\r
+//! - \b AES256_NOT_BUSY\r
+//! \n indicating if the AES256 module is busy\r
+//\r
+//*****************************************************************************\r
+extern uint16_t AES256_isBusy(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the AES256 error flag.\r
+//!\r
+//! Clears the AES256 error flag that results from a key or data being written\r
+//! while the AES256 module is busy.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//!\r
+//! Modified bits are \b AESERRFG of \b AESACTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void AES256_clearErrorFlag(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the AES256 error flag status.\r
+//!\r
+//! Checks the AES256 error flag that results from a key or data being written\r
+//! while the AES256 module is busy. If the flag is set, it needs to be cleared\r
+//! using AES256_clearErrorFlag.\r
+//!\r
+//! \param baseAddress is the base address of the AES256 module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b AES256_ERROR_OCCURRED\r
+//! - \b AES256_NO_ERROR\r
+//! \n indicating the error flag status\r
+//\r
+//*****************************************************************************\r
+extern uint32_t AES256_getErrorFlagStatus(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_AES256_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// comp_e.c - Driver for the comp_e Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup comp_e_api comp_e\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_COMP_E__\r
+#include "comp_e.h"\r
+\r
+#include <assert.h>\r
+\r
+static uint16_t __getRegisterSettingForInput(uint32_t input)\r
+{\r
+ switch(input)\r
+ {\r
+ case COMP_E_INPUT0:\r
+ return(CEIPSEL_0);\r
+ case COMP_E_INPUT1:\r
+ return(CEIPSEL_1);\r
+ case COMP_E_INPUT2:\r
+ return(CEIPSEL_2);\r
+ case COMP_E_INPUT3:\r
+ return(CEIPSEL_3);\r
+ case COMP_E_INPUT4:\r
+ return(CEIPSEL_4);\r
+ case COMP_E_INPUT5:\r
+ return(CEIPSEL_5);\r
+ case COMP_E_INPUT6:\r
+ return(CEIPSEL_6);\r
+ case COMP_E_INPUT7:\r
+ return(CEIPSEL_7);\r
+ case COMP_E_INPUT8:\r
+ return(CEIPSEL_8);\r
+ case COMP_E_INPUT9:\r
+ return(CEIPSEL_9);\r
+ case COMP_E_INPUT10:\r
+ return(CEIPSEL_10);\r
+ case COMP_E_INPUT11:\r
+ return(CEIPSEL_11);\r
+ case COMP_E_INPUT12:\r
+ return(CEIPSEL_12);\r
+ case COMP_E_INPUT13:\r
+ return(CEIPSEL_13);\r
+ case COMP_E_INPUT14:\r
+ return(CEIPSEL_14);\r
+ case COMP_E_INPUT15:\r
+ return(CEIPSEL_15);\r
+ case COMP_E_VREF:\r
+ return(COMP_E_VREF);\r
+ default:\r
+ return(0x11);\r
+ }\r
+}\r
+\r
+bool Comp_E_init(uint16_t baseAddress,\r
+ Comp_E_initParam *param)\r
+{\r
+ uint8_t positiveTerminalInput = __getRegisterSettingForInput(\r
+ param->posTerminalInput);\r
+ uint8_t negativeTerminalInput = __getRegisterSettingForInput(\r
+ param->negTerminalInput);\r
+ bool retVal = STATUS_SUCCESS;\r
+\r
+ //Reset COMPE Control 1 & Interrupt Registers for initialization (OFS_CECTL3\r
+ //is not reset because it controls the input buffers of the analog signals\r
+ //and may cause parasitic effects if an analog signal is still attached and\r
+ //the buffer is re-enabled\r
+ HWREG16(baseAddress + OFS_CECTL0) &= 0x0000;\r
+ HWREG16(baseAddress + OFS_CEINT) &= 0x0000;\r
+\r
+ //Set the Positive Terminal\r
+ if(COMP_E_VREF != positiveTerminalInput)\r
+ {\r
+ //Enable Positive Terminal Input Mux and Set it to the appropriate input\r
+ HWREG16(baseAddress + OFS_CECTL0) |= CEIPEN + positiveTerminalInput;\r
+\r
+ //Disable the input buffer\r
+ HWREG16(baseAddress + OFS_CECTL3) |= (1 << positiveTerminalInput);\r
+ }\r
+ else\r
+ {\r
+ //Reset and Set COMPE Control 2 Register\r
+ HWREG16(baseAddress + OFS_CECTL2) &= ~(CERSEL); //Set Vref to go to (+)terminal\r
+ }\r
+\r
+ //Set the Negative Terminal\r
+ if(COMP_E_VREF != negativeTerminalInput)\r
+ {\r
+ //Enable Negative Terminal Input Mux and Set it to the appropriate input\r
+ HWREG16(baseAddress +\r
+ OFS_CECTL0) |= CEIMEN + (negativeTerminalInput << 8);\r
+\r
+ //Disable the input buffer\r
+ HWREG16(baseAddress + OFS_CECTL3) |= (1 << negativeTerminalInput);\r
+ }\r
+ else\r
+ {\r
+ //Reset and Set COMPE Control 2 Register\r
+ HWREG16(baseAddress + OFS_CECTL2) |= CERSEL; //Set Vref to go to (-) terminal\r
+ }\r
+\r
+ //Reset and Set COMPE Control 1 Register\r
+ HWREG16(baseAddress + OFS_CECTL1) =\r
+ +param->outputFilterEnableAndDelayLevel //Set the filter enable bit and delay\r
+ + param->invertedOutputPolarity; //Set the polarity of the output\r
+\r
+ return (retVal);\r
+}\r
+\r
+void Comp_E_setReferenceVoltage(uint16_t baseAddress,\r
+ uint16_t supplyVoltageReferenceBase,\r
+ uint16_t lowerLimitSupplyVoltageFractionOf32,\r
+ uint16_t upperLimitSupplyVoltageFractionOf32)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL1) &= ~(CEMRVS); //Set to VREF0\r
+\r
+ //Reset COMPE Control 2 Bits (Except for CERSEL which is set in Comp_Init() )\r
+ HWREG16(baseAddress + OFS_CECTL2) &= CERSEL;\r
+\r
+ //Set Voltage Source (Vcc | Vref, resistor ladder or not)\r
+ if(COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase)\r
+ {\r
+ HWREG16(baseAddress + OFS_CECTL2) |= CERS_1; //Vcc with resistor ladder\r
+ }\r
+ else if(lowerLimitSupplyVoltageFractionOf32 == 32)\r
+ {\r
+ //If the lower limit is 32, then the upper limit has to be 32 due to the\r
+ //assertion that upper must be >= to the lower limit. If the numerator is\r
+ //equal to 32, then the equation would be 32/32 == 1, therefore no resistor\r
+ //ladder is needed\r
+ HWREG16(baseAddress + OFS_CECTL2) |= CERS_3; //Vref, no resistor ladder\r
+ }\r
+ else\r
+ {\r
+ HWREG16(baseAddress + OFS_CECTL2) |= CERS_2; //Vref with resistor ladder\r
+ }\r
+\r
+ //Set COMPE Control 2 Register\r
+ HWREG16(baseAddress + OFS_CECTL2) |=\r
+ supplyVoltageReferenceBase //Set Supply Voltage Base\r
+ + ((upperLimitSupplyVoltageFractionOf32 - 1) << 8) //Set Supply Voltage Num.\r
+ + (lowerLimitSupplyVoltageFractionOf32 - 1);\r
+}\r
+\r
+void Comp_E_setReferenceAccuracy(uint16_t baseAddress,\r
+ uint16_t referenceAccuracy)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL2) &= ~(CEREFACC);\r
+ HWREG16(baseAddress + OFS_CECTL2) |= referenceAccuracy;\r
+}\r
+\r
+void Comp_E_setPowerMode(uint16_t baseAddress,\r
+ uint16_t powerMode)\r
+{\r
+ HWREG16(baseAddress +\r
+ OFS_CECTL1) &= ~(COMP_E_NORMAL_MODE | COMP_E_ULTRA_LOW_POWER_MODE);\r
+ HWREG16(baseAddress + OFS_CECTL1) |= powerMode;\r
+}\r
+\r
+void Comp_E_enableInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptMask)\r
+{\r
+ //Set the Interrupt enable bit\r
+ HWREG16(baseAddress + OFS_CEINT) |= interruptMask;\r
+}\r
+\r
+void Comp_E_disableInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptMask)\r
+{\r
+ HWREG16(baseAddress + OFS_CEINT) &= ~(interruptMask);\r
+}\r
+\r
+void Comp_E_clearInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptFlagMask)\r
+{\r
+ HWREG16(baseAddress + OFS_CEINT) &= ~(interruptFlagMask);\r
+}\r
+\r
+uint8_t Comp_E_getInterruptStatus(uint16_t baseAddress,\r
+ uint16_t interruptFlagMask)\r
+{\r
+ return (HWREG16(baseAddress + OFS_CEINT) & interruptFlagMask);\r
+}\r
+\r
+void Comp_E_setInterruptEdgeDirection(uint16_t baseAddress,\r
+ uint16_t edgeDirection)\r
+{\r
+ //Set the edge direction that will trigger an interrupt\r
+ if(COMP_E_RISINGEDGE == edgeDirection)\r
+ {\r
+ HWREG16(baseAddress + OFS_CECTL1) |= CEIES;\r
+ }\r
+ else if(COMP_E_FALLINGEDGE == edgeDirection)\r
+ {\r
+ HWREG16(baseAddress + OFS_CECTL1) &= ~(CEIES);\r
+ }\r
+}\r
+\r
+void Comp_E_toggleInterruptEdgeDirection(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL1) ^= CEIES;\r
+}\r
+\r
+void Comp_E_enable(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL1) |= CEON;\r
+}\r
+\r
+void Comp_E_disable(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL1) &= ~(CEON);\r
+}\r
+\r
+void Comp_E_shortInputs(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL1) |= CESHORT;\r
+}\r
+\r
+void Comp_E_unshortInputs(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL1) &= ~(CESHORT);\r
+}\r
+\r
+void Comp_E_disableInputBuffer(uint16_t baseAddress,\r
+ uint16_t inputPort)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL3) |= (inputPort);\r
+}\r
+\r
+void Comp_E_enableInputBuffer(uint16_t baseAddress,\r
+ uint16_t inputPort)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL3) &= ~(inputPort);\r
+}\r
+\r
+void Comp_E_swapIO(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_CECTL1) ^= CEEX; //Toggle CEEX bit\r
+}\r
+\r
+uint16_t Comp_E_outputValue(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_CECTL1) & CEOUT);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for comp_e_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// comp_e.h - Driver for the COMP_E Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_COMP_E_H__\r
+#define __MSP430WARE_COMP_E_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_COMP_E__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Comp_E_init() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Comp_E_initParam\r
+{\r
+ //! Selects the input to the positive terminal.\r
+ //! \n Valid values are:\r
+ //! - \b COMP_E_INPUT0 [Default]\r
+ //! - \b COMP_E_INPUT1\r
+ //! - \b COMP_E_INPUT2\r
+ //! - \b COMP_E_INPUT3\r
+ //! - \b COMP_E_INPUT4\r
+ //! - \b COMP_E_INPUT5\r
+ //! - \b COMP_E_INPUT6\r
+ //! - \b COMP_E_INPUT7\r
+ //! - \b COMP_E_INPUT8\r
+ //! - \b COMP_E_INPUT9\r
+ //! - \b COMP_E_INPUT10\r
+ //! - \b COMP_E_INPUT11\r
+ //! - \b COMP_E_INPUT12\r
+ //! - \b COMP_E_INPUT13\r
+ //! - \b COMP_E_INPUT14\r
+ //! - \b COMP_E_INPUT15\r
+ //! - \b COMP_E_VREF\r
+ uint16_t posTerminalInput;\r
+ //! Selects the input to the negative terminal.\r
+ //! \n Valid values are:\r
+ //! - \b COMP_E_INPUT0 [Default]\r
+ //! - \b COMP_E_INPUT1\r
+ //! - \b COMP_E_INPUT2\r
+ //! - \b COMP_E_INPUT3\r
+ //! - \b COMP_E_INPUT4\r
+ //! - \b COMP_E_INPUT5\r
+ //! - \b COMP_E_INPUT6\r
+ //! - \b COMP_E_INPUT7\r
+ //! - \b COMP_E_INPUT8\r
+ //! - \b COMP_E_INPUT9\r
+ //! - \b COMP_E_INPUT10\r
+ //! - \b COMP_E_INPUT11\r
+ //! - \b COMP_E_INPUT12\r
+ //! - \b COMP_E_INPUT13\r
+ //! - \b COMP_E_INPUT14\r
+ //! - \b COMP_E_INPUT15\r
+ //! - \b COMP_E_VREF\r
+ uint16_t negTerminalInput;\r
+ //! Controls the output filter delay state, which is either off or enabled\r
+ //! with a specified delay level. This parameter is device specific and\r
+ //! delay levels should be found in the device's datasheet.\r
+ //! \n Valid values are:\r
+ //! - \b COMP_E_FILTEROUTPUT_OFF [Default]\r
+ //! - \b COMP_E_FILTEROUTPUT_DLYLVL1\r
+ //! - \b COMP_E_FILTEROUTPUT_DLYLVL2\r
+ //! - \b COMP_E_FILTEROUTPUT_DLYLVL3\r
+ //! - \b COMP_E_FILTEROUTPUT_DLYLVL4\r
+ uint8_t outputFilterEnableAndDelayLevel;\r
+ //! Controls if the output will be inverted or not\r
+ //! \n Valid values are:\r
+ //! - \b COMP_E_NORMALOUTPUTPOLARITY\r
+ //! - \b COMP_E_INVERTEDOUTPUTPOLARITY\r
+ uint16_t invertedOutputPolarity;\r
+} Comp_E_initParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// outputFilterEnableAndDelayLevel parameter for functions: Comp_E_init(); the\r
+// param parameter for functions: Comp_E_init().\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_FILTEROUTPUT_OFF 0x00\r
+#define COMP_E_FILTEROUTPUT_DLYLVL1 (CEF + CEFDLY_0)\r
+#define COMP_E_FILTEROUTPUT_DLYLVL2 (CEF + CEFDLY_1)\r
+#define COMP_E_FILTEROUTPUT_DLYLVL3 (CEF + CEFDLY_2)\r
+#define COMP_E_FILTEROUTPUT_DLYLVL4 (CEF + CEFDLY_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the posTerminalInput\r
+// parameter for functions: Comp_E_init(); the inputPort parameter for\r
+// functions: Comp_E_disableInputBuffer(), and Comp_E_enableInputBuffer(); the\r
+// param parameter for functions: Comp_E_init(), and Comp_E_init(); the\r
+// negTerminalInput parameter for functions: Comp_E_init().\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_INPUT0 (0x01)\r
+#define COMP_E_INPUT1 (0x02)\r
+#define COMP_E_INPUT2 (0x04)\r
+#define COMP_E_INPUT3 (0x08)\r
+#define COMP_E_INPUT4 (0x10)\r
+#define COMP_E_INPUT5 (0x20)\r
+#define COMP_E_INPUT6 (0x40)\r
+#define COMP_E_INPUT7 (0x80)\r
+#define COMP_E_INPUT8 (0x100)\r
+#define COMP_E_INPUT9 (0x200)\r
+#define COMP_E_INPUT10 (0x400)\r
+#define COMP_E_INPUT11 (0x800)\r
+#define COMP_E_INPUT12 (0x1000)\r
+#define COMP_E_INPUT13 (0x2000)\r
+#define COMP_E_INPUT14 (0x4000)\r
+#define COMP_E_INPUT15 (0x8000)\r
+#define COMP_E_VREF (0x9F)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the invertedOutputPolarity\r
+// parameter for functions: Comp_E_init(); the param parameter for functions:\r
+// Comp_E_init().\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_NORMALOUTPUTPOLARITY (!(CEOUTPOL))\r
+#define COMP_E_INVERTEDOUTPUTPOLARITY (CEOUTPOL)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// supplyVoltageReferenceBase parameter for functions:\r
+// Comp_E_setReferenceVoltage().\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (CEREFL_0)\r
+#define COMP_E_VREFBASE1_2V (CEREFL_1)\r
+#define COMP_E_VREFBASE2_0V (CEREFL_2)\r
+#define COMP_E_VREFBASE2_5V (CEREFL_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the referenceAccuracy\r
+// parameter for functions: Comp_E_setReferenceAccuracy().\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_ACCURACY_STATIC (!CEREFACC)\r
+#define COMP_E_ACCURACY_CLOCKED (CEREFACC)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the powerMode parameter for\r
+// functions: Comp_E_setPowerMode().\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_HIGH_SPEED_MODE (CEPWRMD_0)\r
+#define COMP_E_NORMAL_MODE (CEPWRMD_1)\r
+#define COMP_E_ULTRA_LOW_POWER_MODE (CEPWRMD_2)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptMask parameter\r
+// for functions: Comp_E_enableInterrupt(), and Comp_E_disableInterrupt().\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_OUTPUT_INTERRUPT (CEIE)\r
+#define COMP_E_INVERTED_POLARITY_INTERRUPT (CEIIE)\r
+#define COMP_E_READY_INTERRUPT (CERDYIE)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptFlagMask\r
+// parameter for functions: Comp_E_clearInterrupt(), and\r
+// Comp_E_getInterruptStatus() as well as returned by the\r
+// Comp_E_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_OUTPUT_INTERRUPT_FLAG (CEIFG)\r
+#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (CEIIFG)\r
+#define COMP_E_INTERRUPT_FLAG_READY (CERDYIFG)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the edgeDirection parameter\r
+// for functions: Comp_E_setInterruptEdgeDirection().\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_FALLINGEDGE (!(CEIES))\r
+#define COMP_E_RISINGEDGE (CEIES)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the Comp_E_outputValue() function.\r
+//\r
+//*****************************************************************************\r
+#define COMP_E_LOW (0x0)\r
+#define COMP_E_HIGH (CEOUT)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the Comp_E Module.\r
+//!\r
+//! Upon successful initialization of the Comp_E module, this function will\r
+//! have reset all necessary register bits and set the given options in the\r
+//! registers. To actually use the Comp_E module, the Comp_E_enable() function\r
+//! must be explicitly called before use. If a Reference Voltage is set to a\r
+//! terminal, the Voltage should be set using the setReferenceVoltage()\r
+//! function.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param param is the pointer to struct for initialization.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process\r
+//\r
+//*****************************************************************************\r
+extern bool Comp_E_init(uint16_t baseAddress,\r
+ Comp_E_initParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Generates a Reference Voltage to the terminal selected during\r
+//! initialization.\r
+//!\r
+//! Use this function to generate a voltage to serve as a reference to the\r
+//! terminal selected at initialization. The voltage is determined by the\r
+//! equation: Vbase * (Numerator / 32). If the upper and lower limit voltage\r
+//! numerators are equal, then a static reference is defined, whereas they are\r
+//! different then a hysteresis effect is generated.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param supplyVoltageReferenceBase decides the source and max amount of\r
+//! Voltage that can be used as a reference.\r
+//! Valid values are:\r
+//! - \b COMP_E_REFERENCE_AMPLIFIER_DISABLED\r
+//! - \b COMP_E_VREFBASE1_2V\r
+//! - \b COMP_E_VREFBASE2_0V\r
+//! - \b COMP_E_VREFBASE2_5V\r
+//! \n Modified bits are \b CEREFL of \b CECTL2 register.\r
+//! \param lowerLimitSupplyVoltageFractionOf32 is the numerator of the equation\r
+//! to generate the reference voltage for the lower limit reference\r
+//! voltage.\r
+//! \n Modified bits are \b CEREF0 of \b CECTL2 register.\r
+//! \param upperLimitSupplyVoltageFractionOf32 is the numerator of the equation\r
+//! to generate the reference voltage for the upper limit reference\r
+//! voltage.\r
+//! \n Modified bits are \b CEREF1 of \b CECTL2 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_setReferenceVoltage(uint16_t baseAddress,\r
+ uint16_t supplyVoltageReferenceBase,\r
+ uint16_t lowerLimitSupplyVoltageFractionOf32,\r
+ uint16_t upperLimitSupplyVoltageFractionOf32);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the reference accuracy\r
+//!\r
+//! The reference accuracy is set to the desired setting. Clocked is better for\r
+//! low power operations but has a lower accuracy.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param referenceAccuracy is the reference accuracy setting of the COMP_E.\r
+//! Valid values are:\r
+//! - \b COMP_E_ACCURACY_STATIC\r
+//! - \b COMP_E_ACCURACY_CLOCKED - for low power / low accuracy\r
+//! \n Modified bits are \b CEREFACC of \b CECTL2 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_setReferenceAccuracy(uint16_t baseAddress,\r
+ uint16_t referenceAccuracy);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the power mode\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param powerMode decides the power mode\r
+//! Valid values are:\r
+//! - \b COMP_E_HIGH_SPEED_MODE\r
+//! - \b COMP_E_NORMAL_MODE\r
+//! - \b COMP_E_ULTRA_LOW_POWER_MODE\r
+//! \n Modified bits are \b CEPWRMD of \b CECTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_setPowerMode(uint16_t baseAddress,\r
+ uint16_t powerMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables selected Comp_E interrupt sources.\r
+//!\r
+//! Enables the indicated Comp_E interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor. <b>Does not clear interrupt flags.</b>\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param interruptMask\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt\r
+//! - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted\r
+//! polarity\r
+//! - \b COMP_E_READY_INTERRUPT - Ready interrupt\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_enableInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables selected Comp_E interrupt sources.\r
+//!\r
+//! Disables the indicated Comp_E interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param interruptMask\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt\r
+//! - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted\r
+//! polarity\r
+//! - \b COMP_E_READY_INTERRUPT - Ready interrupt\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_disableInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears Comp_E interrupt flags.\r
+//!\r
+//! The Comp_E interrupt source is cleared, so that it no longer asserts. The\r
+//! highest interrupt flag is automatically cleared when an interrupt vector\r
+//! generator is used.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param interruptFlagMask\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b COMP_E_OUTPUT_INTERRUPT_FLAG - Output interrupt flag\r
+//! - \b COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY - Output interrupt flag\r
+//! inverted polarity\r
+//! - \b COMP_E_INTERRUPT_FLAG_READY - Ready interrupt flag\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_clearInterrupt(uint16_t baseAddress,\r
+ uint16_t interruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the current Comp_E interrupt status.\r
+//!\r
+//! This returns the interrupt status for the Comp_E module based on which flag\r
+//! is passed.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param interruptFlagMask\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b COMP_E_OUTPUT_INTERRUPT_FLAG - Output interrupt flag\r
+//! - \b COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY - Output interrupt flag\r
+//! inverted polarity\r
+//! - \b COMP_E_INTERRUPT_FLAG_READY - Ready interrupt flag\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b Comp_E_OUTPUT_INTERRUPT_FLAG Output interrupt flag\r
+//! - \b Comp_E_INTERRUPT_FLAG_INVERTED_POLARITY Output interrupt flag\r
+//! inverted polarity\r
+//! - \b Comp_E_INTERRUPT_FLAG_READY Ready interrupt flag\r
+//! \n indicating the status of the masked flags\r
+//\r
+//*****************************************************************************\r
+extern uint8_t Comp_E_getInterruptStatus(uint16_t baseAddress,\r
+ uint16_t interruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Explicitly sets the edge direction that would trigger an interrupt.\r
+//!\r
+//! This function will set which direction the output will have to go, whether\r
+//! rising or falling, to generate an interrupt based on a non-inverted\r
+//! interrupt.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param edgeDirection determines which direction the edge would have to go\r
+//! to generate an interrupt based on the non-inverted interrupt flag.\r
+//! Valid values are:\r
+//! - \b COMP_E_FALLINGEDGE [Default] - sets the bit to generate an\r
+//! interrupt when the output of the Comp_E falls from HIGH to LOW if\r
+//! the normal interrupt bit is set(and LOW to HIGH if the inverted\r
+//! interrupt enable bit is set).\r
+//! - \b COMP_E_RISINGEDGE - sets the bit to generate an interrupt when\r
+//! the output of the Comp_E rises from LOW to HIGH if the normal\r
+//! interrupt bit is set(and HIGH to LOW if the inverted interrupt\r
+//! enable bit is set).\r
+//! \n Modified bits are \b CEIES of \b CECTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_setInterruptEdgeDirection(uint16_t baseAddress,\r
+ uint16_t edgeDirection);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Toggles the edge direction that would trigger an interrupt.\r
+//!\r
+//! This function will toggle which direction the output will have to go,\r
+//! whether rising or falling, to generate an interrupt based on a non-inverted\r
+//! interrupt. If the direction was rising, it is now falling, if it was\r
+//! falling, it is now rising.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//!\r
+//! Modified bits are \b CEIES of \b CECTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_toggleInterruptEdgeDirection(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Turns on the Comp_E module.\r
+//!\r
+//! This function sets the bit that enables the operation of the Comp_E module.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_enable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Turns off the Comp_E module.\r
+//!\r
+//! This function clears the CEON bit disabling the operation of the Comp_E\r
+//! module, saving from excess power consumption.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//!\r
+//! Modified bits are \b CEON of \b CECTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_disable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Shorts the two input pins chosen during initialization.\r
+//!\r
+//! This function sets the bit that shorts the devices attached to the input\r
+//! pins chosen from the initialization of the Comp_E.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//!\r
+//! Modified bits are \b CESHORT of \b CECTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_shortInputs(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the short of the two input pins chosen during\r
+//! initialization.\r
+//!\r
+//! This function clears the bit that shorts the devices attached to the input\r
+//! pins chosen from the initialization of the Comp_E.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//!\r
+//! Modified bits are \b CESHORT of \b CECTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_unshortInputs(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the input buffer of the selected input port to effectively\r
+//! allow for analog signals.\r
+//!\r
+//! This function sets the bit to disable the buffer for the specified input\r
+//! port to allow for analog signals from any of the Comp_E input pins. This\r
+//! bit is automatically set when the input is initialized to be used with the\r
+//! Comp_E module. This function should be used whenever an analog input is\r
+//! connected to one of these pins to prevent parasitic voltage from causing\r
+//! unexpected results.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param inputPort is the port in which the input buffer will be disabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b COMP_E_INPUT0 [Default]\r
+//! - \b COMP_E_INPUT1\r
+//! - \b COMP_E_INPUT2\r
+//! - \b COMP_E_INPUT3\r
+//! - \b COMP_E_INPUT4\r
+//! - \b COMP_E_INPUT5\r
+//! - \b COMP_E_INPUT6\r
+//! - \b COMP_E_INPUT7\r
+//! - \b COMP_E_INPUT8\r
+//! - \b COMP_E_INPUT9\r
+//! - \b COMP_E_INPUT10\r
+//! - \b COMP_E_INPUT11\r
+//! - \b COMP_E_INPUT12\r
+//! - \b COMP_E_INPUT13\r
+//! - \b COMP_E_INPUT14\r
+//! - \b COMP_E_INPUT15\r
+//! - \b COMP_E_VREF\r
+//! \n Modified bits are \b CEPDx of \b CECTL3 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_disableInputBuffer(uint16_t baseAddress,\r
+ uint16_t inputPort);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the input buffer of the selected input port to allow for\r
+//! digital signals.\r
+//!\r
+//! This function clears the bit to enable the buffer for the specified input\r
+//! port to allow for digital signals from any of the Comp_E input pins. This\r
+//! should not be reset if there is an analog signal connected to the specified\r
+//! input pin to prevent from unexpected results.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//! \param inputPort is the port in which the input buffer will be enabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b COMP_E_INPUT0 [Default]\r
+//! - \b COMP_E_INPUT1\r
+//! - \b COMP_E_INPUT2\r
+//! - \b COMP_E_INPUT3\r
+//! - \b COMP_E_INPUT4\r
+//! - \b COMP_E_INPUT5\r
+//! - \b COMP_E_INPUT6\r
+//! - \b COMP_E_INPUT7\r
+//! - \b COMP_E_INPUT8\r
+//! - \b COMP_E_INPUT9\r
+//! - \b COMP_E_INPUT10\r
+//! - \b COMP_E_INPUT11\r
+//! - \b COMP_E_INPUT12\r
+//! - \b COMP_E_INPUT13\r
+//! - \b COMP_E_INPUT14\r
+//! - \b COMP_E_INPUT15\r
+//! - \b COMP_E_VREF\r
+//! \n Modified bits are \b CEPDx of \b CECTL3 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_enableInputBuffer(uint16_t baseAddress,\r
+ uint16_t inputPort);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Toggles the bit that swaps which terminals the inputs go to, while\r
+//! also inverting the output of the Comp_E.\r
+//!\r
+//! This function toggles the bit that controls which input goes to which\r
+//! terminal. After initialization, this bit is set to 0, after toggling it\r
+//! once the inputs are routed to the opposite terminal and the output is\r
+//! inverted.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Comp_E_swapIO(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the output value of the Comp_E module.\r
+//!\r
+//! Returns the output value of the Comp_E module.\r
+//!\r
+//! \param baseAddress is the base address of the COMP_E module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b Comp_E_LOW\r
+//! - \b Comp_E_HIGH\r
+//! \n indicating the output value of the Comp_E module\r
+//\r
+//*****************************************************************************\r
+extern uint16_t Comp_E_outputValue(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_COMP_E_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// crc.c - Driver for the crc Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup crc_api crc\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_CRC__\r
+#include "crc.h"\r
+\r
+#include <assert.h>\r
+\r
+void CRC_setSeed(uint16_t baseAddress,\r
+ uint16_t seed)\r
+{\r
+ HWREG16(baseAddress + OFS_CRCINIRES) = seed;\r
+}\r
+\r
+void CRC_set16BitData(uint16_t baseAddress,\r
+ uint16_t dataIn)\r
+{\r
+ HWREG16(baseAddress + OFS_CRCDI) = dataIn;\r
+}\r
+\r
+void CRC_set8BitData(uint16_t baseAddress,\r
+ uint8_t dataIn)\r
+{\r
+ HWREG8(baseAddress + OFS_CRCDI_L) = dataIn;\r
+}\r
+\r
+void CRC_set16BitDataReversed(uint16_t baseAddress,\r
+ uint16_t dataIn)\r
+{\r
+ HWREG16(baseAddress + OFS_CRCDIRB) = dataIn;\r
+}\r
+\r
+void CRC_set8BitDataReversed(uint16_t baseAddress,\r
+ uint8_t dataIn)\r
+{\r
+ HWREG8(baseAddress + OFS_CRCDIRB_L) = dataIn;\r
+}\r
+\r
+uint16_t CRC_getData(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_CRCDI));\r
+}\r
+\r
+uint16_t CRC_getResult(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_CRCINIRES));\r
+}\r
+\r
+uint16_t CRC_getResultBitsReversed(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_CRCRESR));\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for crc_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// crc.h - Driver for the CRC Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_CRC_H__\r
+#define __MSP430WARE_CRC_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_CRC__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the seed for the CRC.\r
+//!\r
+//! This function sets the seed for the CRC to begin generating a signature\r
+//! with the given seed and all passed data. Using this function resets the CRC\r
+//! signature.\r
+//!\r
+//! \param baseAddress is the base address of the CRC module.\r
+//! \param seed is the seed for the CRC to start generating a signature from.\r
+//! \n Modified bits are \b CRCINIRES of \b CRCINIRES register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC_setSeed(uint16_t baseAddress,\r
+ uint16_t seed);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the 16 bit data to add into the CRC module to generate a new\r
+//! signature.\r
+//!\r
+//! This function sets the given data into the CRC module to generate the new\r
+//! signature from the current signature and new data.\r
+//!\r
+//! \param baseAddress is the base address of the CRC module.\r
+//! \param dataIn is the data to be added, through the CRC module, to the\r
+//! signature.\r
+//! \n Modified bits are \b CRCDI of \b CRCDI register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC_set16BitData(uint16_t baseAddress,\r
+ uint16_t dataIn);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the 8 bit data to add into the CRC module to generate a new\r
+//! signature.\r
+//!\r
+//! This function sets the given data into the CRC module to generate the new\r
+//! signature from the current signature and new data.\r
+//!\r
+//! \param baseAddress is the base address of the CRC module.\r
+//! \param dataIn is the data to be added, through the CRC module, to the\r
+//! signature.\r
+//! \n Modified bits are \b CRCDI of \b CRCDI register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC_set8BitData(uint16_t baseAddress,\r
+ uint8_t dataIn);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Translates the 16 bit data by reversing the bits in each byte and\r
+//! then sets this data to add into the CRC module to generate a new signature.\r
+//!\r
+//! This function first reverses the bits in each byte of the data and then\r
+//! generates the new signature from the current signature and new translated\r
+//! data.\r
+//!\r
+//! \param baseAddress is the base address of the CRC module.\r
+//! \param dataIn is the data to be added, through the CRC module, to the\r
+//! signature.\r
+//! \n Modified bits are \b CRCDIRB of \b CRCDIRB register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC_set16BitDataReversed(uint16_t baseAddress,\r
+ uint16_t dataIn);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Translates the 8 bit data by reversing the bits in each byte and\r
+//! then sets this data to add into the CRC module to generate a new signature.\r
+//!\r
+//! This function first reverses the bits in each byte of the data and then\r
+//! generates the new signature from the current signature and new translated\r
+//! data.\r
+//!\r
+//! \param baseAddress is the base address of the CRC module.\r
+//! \param dataIn is the data to be added, through the CRC module, to the\r
+//! signature.\r
+//! \n Modified bits are \b CRCDIRB of \b CRCDIRB register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC_set8BitDataReversed(uint16_t baseAddress,\r
+ uint8_t dataIn);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the value currently in the Data register.\r
+//!\r
+//! This function returns the value currently in the data register. If set in\r
+//! byte bits reversed format, then the translated data would be returned.\r
+//!\r
+//! \param baseAddress is the base address of the CRC module.\r
+//!\r
+//! \return The value currently in the data register\r
+//\r
+//*****************************************************************************\r
+extern uint16_t CRC_getData(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the value pf the Signature Result.\r
+//!\r
+//! This function returns the value of the signature result generated by the\r
+//! CRC.\r
+//!\r
+//! \param baseAddress is the base address of the CRC module.\r
+//!\r
+//! \return The value currently in the data register\r
+//\r
+//*****************************************************************************\r
+extern uint16_t CRC_getResult(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the bit-wise reversed format of the Signature Result.\r
+//!\r
+//! This function returns the bit-wise reversed format of the Signature Result.\r
+//!\r
+//! \param baseAddress is the base address of the CRC module.\r
+//!\r
+//! \return The bit-wise reversed format of the Signature Result\r
+//\r
+//*****************************************************************************\r
+extern uint16_t CRC_getResultBitsReversed(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_CRC_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// crc32.c - Driver for the crc32 Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup crc32_api crc32\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_CRC32__\r
+#include "crc32.h"\r
+\r
+#include <assert.h>\r
+\r
+void CRC32_setSeed(uint32_t seed,\r
+ uint8_t crcMode)\r
+{\r
+ if(CRC16_MODE == crcMode)\r
+ {\r
+ HWREG16(CRC32_BASE + OFS_CRC16INIRESW0) = seed;\r
+ }\r
+ else\r
+ {\r
+ HWREG16(CRC32_BASE + OFS_CRC32INIRESW1) = ((seed & 0xFFFF0000)\r
+ >> 16);\r
+ HWREG16(CRC32_BASE + OFS_CRC32INIRESW0) = (seed & 0xFFFF);\r
+ }\r
+}\r
+\r
+void CRC32_set8BitData(uint8_t dataIn,\r
+ uint8_t crcMode)\r
+{\r
+ if(CRC16_MODE == crcMode)\r
+ {\r
+ HWREG8(CRC32_BASE + OFS_CRC16DIW0_L) = dataIn;\r
+ }\r
+ else\r
+ {\r
+ HWREG8(CRC32_BASE + OFS_CRC32DIW0_L) = dataIn;\r
+ }\r
+}\r
+\r
+void CRC32_set16BitData(uint16_t dataIn,\r
+ uint8_t crcMode)\r
+{\r
+ if(CRC16_MODE == crcMode)\r
+ {\r
+ HWREG16(CRC32_BASE + OFS_CRC16DIW0) = dataIn;\r
+ }\r
+ else\r
+ {\r
+ HWREG16(CRC32_BASE + OFS_CRC32DIW0) = dataIn;\r
+ }\r
+}\r
+\r
+void CRC32_set32BitData(uint32_t dataIn)\r
+{\r
+ HWREG16(CRC32_BASE + OFS_CRC32DIW0) = dataIn & 0xFFFF;\r
+ HWREG16(CRC32_BASE + OFS_CRC32DIW1) = (uint16_t) ((dataIn & 0xFFFF0000)\r
+ >> 16);\r
+}\r
+\r
+void CRC32_set8BitDataReversed(uint8_t dataIn,\r
+ uint8_t crcMode)\r
+{\r
+ if(CRC16_MODE == crcMode)\r
+ {\r
+ HWREG8(CRC32_BASE + OFS_CRC16DIRBW1_L) = dataIn;\r
+ }\r
+ else\r
+ {\r
+ HWREG8(CRC32_BASE + OFS_CRC32DIRBW1_L) = dataIn;\r
+ }\r
+}\r
+\r
+void CRC32_set16BitDataReversed(uint16_t dataIn,\r
+ uint8_t crcMode)\r
+{\r
+ if(CRC16_MODE == crcMode)\r
+ {\r
+ HWREG16(CRC32_BASE + OFS_CRC16DIRBW1) = dataIn;\r
+ }\r
+ else\r
+ {\r
+ HWREG16(CRC32_BASE + OFS_CRC32DIRBW1) = dataIn;\r
+ }\r
+}\r
+\r
+void CRC32_set32BitDataReversed(uint32_t dataIn)\r
+{\r
+ HWREG16(CRC32_BASE + OFS_CRC32DIRBW1) = dataIn & 0xFFFF;\r
+ HWREG16(CRC32_BASE + OFS_CRC32DIRBW0) = (uint16_t) ((dataIn & 0xFFFF0000)\r
+ >> 16);\r
+}\r
+\r
+uint32_t CRC32_getResult(uint8_t crcMode)\r
+{\r
+ if(CRC16_MODE == crcMode)\r
+ {\r
+ return (HWREG16(CRC32_BASE + OFS_CRC16INIRESW0));\r
+ }\r
+ else\r
+ {\r
+ uint32_t result = 0;\r
+ result = HWREG16(CRC32_BASE + OFS_CRC32INIRESW1);\r
+ result = (result << 16);\r
+ result |= HWREG16(CRC32_BASE + OFS_CRC32INIRESW0);\r
+ return (result);\r
+ }\r
+}\r
+\r
+uint32_t CRC32_getResultReversed(uint8_t crcMode)\r
+{\r
+ if(CRC16_MODE == crcMode)\r
+ {\r
+ return (HWREG16(CRC32_BASE + OFS_CRC16RESRW0));\r
+ }\r
+ else\r
+ {\r
+ uint32_t result = 0;\r
+ result = HWREG16(CRC32_BASE + OFS_CRC32RESRW0);\r
+ result = (result << 16);\r
+ result |= HWREG16(CRC32_BASE + OFS_CRC32RESRW1);\r
+ return (result);\r
+ }\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for crc32_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// crc32.h - Driver for the CRC32 Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_CRC32_H__\r
+#define __MSP430WARE_CRC32_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_CRC32__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the crcMode parameter for\r
+// functions: CRC32_setSeed(), CRC32_getResult(), CRC32_getResultReversed(),\r
+// CRC32_set8BitDataReversed(), CRC32_set16BitDataReversed(),\r
+// CRC32_set8BitData(), and CRC32_set16BitData().\r
+//\r
+//*****************************************************************************\r
+#define CRC32_MODE (0x01)\r
+#define CRC16_MODE (0x00)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the seed for the CRC32.\r
+//!\r
+//! This function sets the seed for the CRC32 to begin generating a signature\r
+//! with the given seed and all passed data. Using this function resets the\r
+//! CRC32 signature.\r
+//!\r
+//! \param seed is the seed for the CRC32 to start generating a signature from.\r
+//! \n Modified bits are \b CRC32INIRESL0 of \b CRC32INIRESL0 register.\r
+//! \param crcMode selects the mode of operation for the CRC32\r
+//! Valid values are:\r
+//! - \b CRC32_MODE - 32 Bit Mode\r
+//! - \b CRC16_MODE - 16 Bit Mode\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC32_setSeed(uint32_t seed,\r
+ uint8_t crcMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the 8 bit data to add into the CRC32 module to generate a new\r
+//! signature.\r
+//!\r
+//! This function sets the given data into the CRC32 module to generate the new\r
+//! signature from the current signature and new data. Bit 0 is treated as the\r
+//! LSB.\r
+//!\r
+//! \param dataIn is the data to be added, through the CRC32 module, to the\r
+//! signature.\r
+//! \param crcMode selects the mode of operation for the CRC32\r
+//! Valid values are:\r
+//! - \b CRC32_MODE - 32 Bit Mode\r
+//! - \b CRC16_MODE - 16 Bit Mode\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC32_set8BitData(uint8_t dataIn,\r
+ uint8_t crcMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the 16 bit data to add into the CRC32 module to generate a new\r
+//! signature.\r
+//!\r
+//! This function sets the given data into the CRC32 module to generate the new\r
+//! signature from the current signature and new data. Bit 0 is treated as the\r
+//! LSB.\r
+//!\r
+//! \param dataIn is the data to be added, through the CRC32 module, to the\r
+//! signature.\r
+//! \param crcMode selects the mode of operation for the CRC32\r
+//! Valid values are:\r
+//! - \b CRC32_MODE - 32 Bit Mode\r
+//! - \b CRC16_MODE - 16 Bit Mode\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC32_set16BitData(uint16_t dataIn,\r
+ uint8_t crcMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the 32 bit data to add into the CRC32 module to generate a new\r
+//! signature.\r
+//!\r
+//! This function sets the given data into the CRC32 module to generate the new\r
+//! signature from the current signature and new data. Bit 0 is treated as the\r
+//! LSB.\r
+//!\r
+//! \param dataIn is the data to be added, through the CRC32 module, to the\r
+//! signature.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC32_set32BitData(uint32_t dataIn);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Translates the data by reversing the bits in each 8 bit data and\r
+//! then sets this data to add into the CRC32 module to generate a new\r
+//! signature.\r
+//!\r
+//! This function first reverses the bits in each byte of the data and then\r
+//! generates the new signature from the current signature and new translated\r
+//! data. Bit 0 is treated as the MSB.\r
+//!\r
+//! \param dataIn is the data to be added, through the CRC32 module, to the\r
+//! signature.\r
+//! \param crcMode selects the mode of operation for the CRC32\r
+//! Valid values are:\r
+//! - \b CRC32_MODE - 32 Bit Mode\r
+//! - \b CRC16_MODE - 16 Bit Mode\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC32_set8BitDataReversed(uint8_t dataIn,\r
+ uint8_t crcMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Translates the data by reversing the bits in each 16 bit data and\r
+//! then sets this data to add into the CRC32 module to generate a new\r
+//! signature.\r
+//!\r
+//! This function first reverses the bits in each byte of the data and then\r
+//! generates the new signature from the current signature and new translated\r
+//! data. Bit 0 is treated as the MSB.\r
+//!\r
+//! \param dataIn is the data to be added, through the CRC32 module, to the\r
+//! signature.\r
+//! \param crcMode selects the mode of operation for the CRC32\r
+//! Valid values are:\r
+//! - \b CRC32_MODE - 32 Bit Mode\r
+//! - \b CRC16_MODE - 16 Bit Mode\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC32_set16BitDataReversed(uint16_t dataIn,\r
+ uint8_t crcMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Translates the data by reversing the bits in each 32 bit data and\r
+//! then sets this data to add into the CRC32 module to generate a new\r
+//! signature.\r
+//!\r
+//! This function first reverses the bits in each byte of the data and then\r
+//! generates the new signature from the current signature and new translated\r
+//! data. Bit 0 is treated as the MSB.\r
+//!\r
+//! \param dataIn is the data to be added, through the CRC32 module, to the\r
+//! signature.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CRC32_set32BitDataReversed(uint32_t dataIn);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the value of the signature result.\r
+//!\r
+//! This function returns the value of the signature result generated by the\r
+//! CRC32. Bit 0 is treated as LSB.\r
+//!\r
+//! \param crcMode selects the mode of operation for the CRC32\r
+//! Valid values are:\r
+//! - \b CRC32_MODE - 32 Bit Mode\r
+//! - \b CRC16_MODE - 16 Bit Mode\r
+//!\r
+//! \return The signature result\r
+//\r
+//*****************************************************************************\r
+extern uint32_t CRC32_getResult(uint8_t crcMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the bit-wise reversed format of the 32 bit signature result.\r
+//!\r
+//! This function returns the bit-wise reversed format of the signature result.\r
+//! Bit 0 is treated as MSB.\r
+//!\r
+//! \param crcMode selects the mode of operation for the CRC32\r
+//! Valid values are:\r
+//! - \b CRC32_MODE - 32 Bit Mode\r
+//! - \b CRC16_MODE - 16 Bit Mode\r
+//!\r
+//! \return The bit-wise reversed format of the signature result\r
+//\r
+//*****************************************************************************\r
+extern uint32_t CRC32_getResultReversed(uint8_t crcMode);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_CRC32_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// cs.c - Driver for the cs Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup cs_api cs\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#if defined(__MSP430_HAS_CS__) || defined(__MSP430_HAS_SFR__)\r
+#include "cs.h"\r
+\r
+#include <assert.h>\r
+\r
+//*****************************************************************************\r
+//\r
+// The following value is used by CS_getACLK, CS_getSMCLK, CS_getMCLK to\r
+// determine the operating frequency based on the available DCO frequencies.\r
+//\r
+//*****************************************************************************\r
+#define CS_DCO_FREQ_1 1000000\r
+#define CS_DCO_FREQ_2 2670000\r
+#define CS_DCO_FREQ_3 3330000\r
+#define CS_DCO_FREQ_4 4000000\r
+#define CS_DCO_FREQ_5 5330000\r
+#define CS_DCO_FREQ_6 6670000\r
+#define CS_DCO_FREQ_7 8000000\r
+#define CS_DCO_FREQ_8 16000000\r
+#define CS_DCO_FREQ_9 20000000\r
+#define CS_DCO_FREQ_10 24000000\r
+\r
+//*****************************************************************************\r
+//\r
+// Internal very low power VLOCLK, low frequency oscillator with 10kHz typical\r
+// frequency, internal low-power oscillator MODCLK with 5 MHz typical\r
+// frequency and LFMODCLK is MODCLK divided by 128.\r
+//\r
+//*****************************************************************************\r
+#define CS_VLOCLK_FREQUENCY 10000\r
+#define CS_MODCLK_FREQUENCY 5000000\r
+#define CS_LFMODCLK_FREQUENCY 39062\r
+\r
+//*****************************************************************************\r
+//\r
+// The following value is used by CS_XT1Start, CS_bypassXT1,\r
+// CS_XT1StartWithTimeout, CS_bypassXT1WithTimeout to properly set the XTS\r
+// bit. This frequnecy threshold is specified in the User's Guide.\r
+//\r
+//*****************************************************************************\r
+#define LFXT_FREQUENCY_THRESHOLD 50000\r
+\r
+//*****************************************************************************\r
+//\r
+// LFXT crystal frequency. Should be set with\r
+// CS_externalClockSourceInit if LFXT is used and user intends to invoke\r
+// CS_getSMCLK, CS_getMCLK, CS_getACLK and\r
+// CS_turnOnLFXT, CS_LFXTByPass, CS_turnOnLFXTWithTimeout,\r
+// CS_LFXTByPassWithTimeout.\r
+//\r
+//*****************************************************************************\r
+static uint32_t privateLFXTClockFrequency = 0;\r
+\r
+//*****************************************************************************\r
+//\r
+// The HFXT crystal frequency. Should be set with\r
+// CS_externalClockSourceInit if HFXT is used and user intends to invoke\r
+// CS_getSMCLK, CS_getMCLK, CS_getACLK,\r
+// CS_turnOnLFXT, CS_LFXTByPass, CS_turnOnLFXTWithTimeout,\r
+// CS_LFXTByPassWithTimeout.\r
+//\r
+//*****************************************************************************\r
+static uint32_t privateHFXTClockFrequency = 0;\r
+\r
+static uint32_t privateCSASourceClockFromDCO(uint8_t clockdivider)\r
+{\r
+ uint32_t CLKFrequency = 0;\r
+\r
+ if(HWREG16(CS_BASE + OFS_CSCTL1) & DCORSEL)\r
+ {\r
+ switch(HWREG16(CS_BASE + OFS_CSCTL1) & DCOFSEL_7)\r
+ {\r
+ case DCOFSEL_0:\r
+ CLKFrequency = CS_DCO_FREQ_1 / clockdivider;\r
+ break;\r
+ case DCOFSEL_1:\r
+ CLKFrequency = CS_DCO_FREQ_5 / clockdivider;\r
+ break;\r
+ case DCOFSEL_2:\r
+ CLKFrequency = CS_DCO_FREQ_6 / clockdivider;\r
+ break;\r
+ case DCOFSEL_3:\r
+ CLKFrequency = CS_DCO_FREQ_7 / clockdivider;\r
+ break;\r
+ case DCOFSEL_4:\r
+ CLKFrequency = CS_DCO_FREQ_8 / clockdivider;\r
+ break;\r
+ case DCOFSEL_5:\r
+ CLKFrequency = CS_DCO_FREQ_9 / clockdivider;\r
+ break;\r
+ case DCOFSEL_6:\r
+ case DCOFSEL_7:\r
+ CLKFrequency = CS_DCO_FREQ_10 / clockdivider;\r
+ break;\r
+ default:\r
+ CLKFrequency = 0;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ switch(HWREG16(CS_BASE + OFS_CSCTL1) & DCOFSEL_7)\r
+ {\r
+ case DCOFSEL_0:\r
+ CLKFrequency = CS_DCO_FREQ_1 / clockdivider;\r
+ break;\r
+ case DCOFSEL_1:\r
+ CLKFrequency = CS_DCO_FREQ_2 / clockdivider;\r
+ break;\r
+ case DCOFSEL_2:\r
+ CLKFrequency = CS_DCO_FREQ_3 / clockdivider;\r
+ break;\r
+ case DCOFSEL_3:\r
+ CLKFrequency = CS_DCO_FREQ_4 / clockdivider;\r
+ break;\r
+ case DCOFSEL_4:\r
+ CLKFrequency = CS_DCO_FREQ_5 / clockdivider;\r
+ break;\r
+ case DCOFSEL_5:\r
+ CLKFrequency = CS_DCO_FREQ_6 / clockdivider;\r
+ break;\r
+ case DCOFSEL_6:\r
+ case DCOFSEL_7:\r
+ CLKFrequency = CS_DCO_FREQ_7 / clockdivider;\r
+ break;\r
+ default:\r
+ CLKFrequency = 0;\r
+ break;\r
+ }\r
+ }\r
+\r
+ return (CLKFrequency);\r
+}\r
+\r
+static uint32_t privateCSAComputeCLKFrequency(uint16_t CLKSource,\r
+ uint16_t CLKSourceDivider)\r
+{\r
+ uint32_t CLKFrequency = 0;\r
+ uint8_t CLKSourceFrequencyDivider = 1;\r
+ uint8_t i = 0;\r
+\r
+ // Determine Frequency divider\r
+ for(i = 0; i < CLKSourceDivider; i++)\r
+ {\r
+ CLKSourceFrequencyDivider *= 2;\r
+ }\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ // Determine clock source based on CLKSource\r
+ switch(CLKSource)\r
+ {\r
+ // If LFXT is selected as clock source\r
+ case SELM__LFXTCLK:\r
+ CLKFrequency = (privateLFXTClockFrequency /\r
+ CLKSourceFrequencyDivider);\r
+\r
+ //Check if LFXTOFFG is not set. If fault flag is set\r
+ //VLO is used as source clock\r
+ if(HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG)\r
+ {\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG);\r
+ //Clear OFIFG fault flag\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+\r
+ if(HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG)\r
+ {\r
+ CLKFrequency = CS_LFMODCLK_FREQUENCY;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case SELM__VLOCLK:\r
+ CLKFrequency =\r
+ (CS_VLOCLK_FREQUENCY / CLKSourceFrequencyDivider);\r
+ break;\r
+\r
+ case SELM__LFMODOSC:\r
+ CLKFrequency =\r
+ (CS_LFMODCLK_FREQUENCY / CLKSourceFrequencyDivider);\r
+\r
+ break;\r
+\r
+ case SELM__DCOCLK:\r
+ CLKFrequency =\r
+ privateCSASourceClockFromDCO(CLKSourceFrequencyDivider);\r
+\r
+ break;\r
+\r
+ case SELM__MODOSC:\r
+ CLKFrequency =\r
+ (CS_MODCLK_FREQUENCY / CLKSourceFrequencyDivider);\r
+\r
+ break;\r
+\r
+ case SELM__HFXTCLK:\r
+ CLKFrequency =\r
+ (privateHFXTClockFrequency / CLKSourceFrequencyDivider);\r
+\r
+ if(HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG)\r
+ {\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~HFXTOFFG;\r
+ //Clear OFIFG fault flag\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+ }\r
+\r
+ if(HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG)\r
+ {\r
+ CLKFrequency = CS_MODCLK_FREQUENCY;\r
+ }\r
+ break;\r
+ }\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+\r
+ return (CLKFrequency);\r
+}\r
+\r
+void CS_setExternalClockSource(uint32_t LFXTCLK_frequency,\r
+ uint32_t HFXTCLK_frequency)\r
+{\r
+ privateLFXTClockFrequency = LFXTCLK_frequency;\r
+ privateHFXTClockFrequency = HFXTCLK_frequency;\r
+}\r
+\r
+void CS_initClockSignal(uint8_t selectedClockSignal,\r
+ uint16_t clockSource,\r
+ uint16_t clockSourceDivider)\r
+{\r
+ //Verify User has selected a valid Frequency divider\r
+ assert(\r
+ (CS_CLOCK_DIVIDER_1 == clockSourceDivider) ||\r
+ (CS_CLOCK_DIVIDER_2 == clockSourceDivider) ||\r
+ (CS_CLOCK_DIVIDER_4 == clockSourceDivider) ||\r
+ (CS_CLOCK_DIVIDER_8 == clockSourceDivider) ||\r
+ (CS_CLOCK_DIVIDER_16 == clockSourceDivider) ||\r
+ (CS_CLOCK_DIVIDER_32 == clockSourceDivider)\r
+ );\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ switch(selectedClockSignal)\r
+ {\r
+ case CS_ACLK:\r
+ assert(\r
+ (CS_LFXTCLK_SELECT == clockSource) ||\r
+ (CS_VLOCLK_SELECT == clockSource) ||\r
+ (CS_LFMODOSC_SELECT == clockSource)\r
+ );\r
+\r
+ clockSourceDivider = clockSourceDivider << 8;\r
+ clockSource = clockSource << 8;\r
+\r
+ HWREG16(CS_BASE + OFS_CSCTL2) &= ~(SELA_7);\r
+ HWREG16(CS_BASE + OFS_CSCTL2) |= (clockSource);\r
+ HWREG16(CS_BASE + OFS_CSCTL3) &= ~(DIVA0 + DIVA1 + DIVA2);\r
+ HWREG16(CS_BASE + OFS_CSCTL3) |= clockSourceDivider;\r
+ break;\r
+ case CS_SMCLK:\r
+ assert(\r
+ (CS_LFXTCLK_SELECT == clockSource) ||\r
+ (CS_VLOCLK_SELECT == clockSource) ||\r
+ (CS_DCOCLK_SELECT == clockSource) ||\r
+ (CS_HFXTCLK_SELECT == clockSource) ||\r
+ (CS_LFMODOSC_SELECT == clockSource)||\r
+ (CS_MODOSC_SELECT == clockSource)\r
+ );\r
+\r
+ clockSource = clockSource << 4;\r
+ clockSourceDivider = clockSourceDivider << 4;\r
+\r
+ HWREG16(CS_BASE + OFS_CSCTL2) &= ~(SELS_7);\r
+ HWREG16(CS_BASE + OFS_CSCTL2) |= clockSource;\r
+ HWREG16(CS_BASE + OFS_CSCTL3) &= ~(DIVS0 + DIVS1 + DIVS2);\r
+ HWREG16(CS_BASE + OFS_CSCTL3) |= clockSourceDivider;\r
+ break;\r
+ case CS_MCLK:\r
+ assert(\r
+ (CS_LFXTCLK_SELECT == clockSource) ||\r
+ (CS_VLOCLK_SELECT == clockSource) ||\r
+ (CS_DCOCLK_SELECT == clockSource) ||\r
+ (CS_HFXTCLK_SELECT == clockSource) ||\r
+ (CS_LFMODOSC_SELECT == clockSource)||\r
+ (CS_MODOSC_SELECT == clockSource)\r
+ );\r
+\r
+ HWREG16(CS_BASE + OFS_CSCTL2) &= ~(SELM_7);\r
+ HWREG16(CS_BASE + OFS_CSCTL2) |= clockSource;\r
+ HWREG16(CS_BASE + OFS_CSCTL3) &= ~(DIVM0 + DIVM1 + DIVM2);\r
+ HWREG16(CS_BASE + OFS_CSCTL3) |= clockSourceDivider;\r
+ break;\r
+ }\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+void CS_turnOnLFXT(uint16_t lfxtdrive)\r
+{\r
+ assert(privateLFXTClockFrequency != 0);\r
+\r
+ assert((lfxtdrive == CS_LFXT_DRIVE_0) ||\r
+ (lfxtdrive == CS_LFXT_DRIVE_1) ||\r
+ (lfxtdrive == CS_LFXT_DRIVE_2) ||\r
+ (lfxtdrive == CS_LFXT_DRIVE_3));\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ //Switch ON LFXT oscillator\r
+ HWREG16(CS_BASE + OFS_CSCTL4) &= ~LFXTOFF;\r
+\r
+ //Highest drive setting for LFXTstartup\r
+ HWREG16(CS_BASE + OFS_CSCTL4_L) |= LFXTDRIVE1_L + LFXTDRIVE0_L;\r
+\r
+ HWREG16(CS_BASE + OFS_CSCTL4) &= ~LFXTBYPASS;\r
+\r
+ //Wait for Crystal to stabilize\r
+ while(HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG)\r
+ {\r
+ //Clear OSC flaut Flags fault flags\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG);\r
+\r
+ //Clear OFIFG fault flag\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+ }\r
+\r
+ //set requested Drive mode\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = (HWREG16(CS_BASE + OFS_CSCTL4) &\r
+ ~(LFXTDRIVE_3)\r
+ ) |\r
+ (lfxtdrive);\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+void CS_bypassLFXT(void)\r
+{\r
+ //Verify user has set frequency of LFXT with SetExternalClockSource\r
+ assert(privateLFXTClockFrequency != 0);\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ assert(privateLFXTClockFrequency < LFXT_FREQUENCY_THRESHOLD);\r
+\r
+ // Set LFXT in LF mode Switch off LFXT oscillator and enable BYPASS mode\r
+ HWREG16(CS_BASE + OFS_CSCTL4) |= (LFXTBYPASS + LFXTOFF);\r
+\r
+ //Wait until LFXT stabilizes\r
+ while(HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG)\r
+ {\r
+ //Clear OSC flaut Flags fault flags\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG);\r
+\r
+ // Clear the global fault flag. In case the LFXT caused the global fault\r
+ // flag to get set this will clear the global error condition. If any\r
+ // error condition persists, global flag will get again.\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+ }\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+bool CS_turnOnLFXTWithTimeout(uint16_t lfxtdrive,\r
+ uint32_t timeout)\r
+{\r
+ assert(privateLFXTClockFrequency != 0);\r
+\r
+ assert((lfxtdrive == CS_LFXT_DRIVE_0) ||\r
+ (lfxtdrive == CS_LFXT_DRIVE_1) ||\r
+ (lfxtdrive == CS_LFXT_DRIVE_2) ||\r
+ (lfxtdrive == CS_LFXT_DRIVE_3));\r
+\r
+ assert(timeout > 0);\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ //Switch ON LFXT oscillator\r
+ HWREG16(CS_BASE + OFS_CSCTL4) &= ~LFXTOFF;\r
+\r
+ //Highest drive setting for LFXTstartup\r
+ HWREG16(CS_BASE + OFS_CSCTL4_L) |= LFXTDRIVE1_L + LFXTDRIVE0_L;\r
+\r
+ HWREG16(CS_BASE + OFS_CSCTL4) &= ~LFXTBYPASS;\r
+\r
+ while((HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG) && --timeout)\r
+ {\r
+ //Clear OSC fault Flags fault flags\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG);\r
+\r
+ // Clear the global fault flag. In case the LFXT caused the global fault\r
+ // flag to get set this will clear the global error condition. If any\r
+ // error condition persists, global flag will get again.\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+ }\r
+\r
+ if(timeout)\r
+ {\r
+ //set requested Drive mode\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = (HWREG16(CS_BASE + OFS_CSCTL4) &\r
+ ~(LFXTDRIVE_3)\r
+ ) |\r
+ (lfxtdrive);\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+ return (STATUS_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+ return (STATUS_FAIL);\r
+ }\r
+}\r
+\r
+bool CS_bypassLFXTWithTimeout(uint32_t timeout)\r
+{\r
+ assert(privateLFXTClockFrequency != 0);\r
+\r
+ assert(privateLFXTClockFrequency < LFXT_FREQUENCY_THRESHOLD);\r
+\r
+ assert(timeout > 0);\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ // Set LFXT in LF mode Switch off LFXT oscillator and enable BYPASS mode\r
+ HWREG16(CS_BASE + OFS_CSCTL4) |= (LFXTBYPASS + LFXTOFF);\r
+\r
+ while((HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG) && --timeout)\r
+ {\r
+ //Clear OSC fault Flags fault flags\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG);\r
+\r
+ // Clear the global fault flag. In case the LFXT caused the global fault\r
+ // flag to get set this will clear the global error condition. If any\r
+ // error condition persists, global flag will get again.\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+ }\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+\r
+ if(timeout)\r
+ {\r
+ return (STATUS_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+}\r
+\r
+void CS_turnOffLFXT(void)\r
+{\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ //Switch off LFXT oscillator\r
+ HWREG16(CS_BASE + OFS_CSCTL4) |= LFXTOFF;\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+void CS_turnOnHFXT(uint16_t hfxtdrive)\r
+{\r
+ assert(privateHFXTClockFrequency != 0);\r
+\r
+ assert((hfxtdrive == CS_HFXT_DRIVE_4MHZ_8MHZ) ||\r
+ (hfxtdrive == CS_HFXT_DRIVE_8MHZ_16MHZ) ||\r
+ (hfxtdrive == CS_HFXT_DRIVE_16MHZ_24MHZ)||\r
+ (hfxtdrive == CS_HFXT_DRIVE_24MHZ_32MHZ));\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ // Switch ON HFXT oscillator\r
+ HWREG16(CS_BASE + OFS_CSCTL4) &= ~HFXTOFF;\r
+\r
+ //Disable HFXTBYPASS mode and Switch on HFXT oscillator\r
+ HWREG16(CS_BASE + OFS_CSCTL4) &= ~HFXTBYPASS;\r
+\r
+ //If HFFrequency is 16MHz or above\r
+ if(privateHFXTClockFrequency > 16000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_3;\r
+ }\r
+ //If HFFrequency is between 8MHz and 16MHz\r
+ else if(privateHFXTClockFrequency > 8000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_2;\r
+ }\r
+ //If HFFrequency is between 0MHz and 4MHz\r
+ else if(privateHFXTClockFrequency < 4000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_0;\r
+ }\r
+ //If HFFrequency is between 4MHz and 8MHz\r
+ else\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_1;\r
+ }\r
+\r
+ while(HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG)\r
+ {\r
+ //Clear OSC flaut Flags\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(HFXTOFFG);\r
+\r
+ //Clear OFIFG fault flag\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+ }\r
+\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = (HWREG16(CS_BASE + OFS_CSCTL4) &\r
+ ~(CS_HFXT_DRIVE_24MHZ_32MHZ)\r
+ ) |\r
+ (hfxtdrive);\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+void CS_bypassHFXT(void)\r
+{\r
+ //Verify user has initialized value of HFXTClock\r
+ assert(privateHFXTClockFrequency != 0);\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ //Switch off HFXT oscillator and set it to BYPASS mode\r
+ HWREG16(CS_BASE + OFS_CSCTL4) |= (HFXTBYPASS + HFXTOFF);\r
+\r
+ //Set correct HFFREQ bit for FR58xx/FR59xx devices\r
+\r
+ //If HFFrequency is 16MHz or above\r
+ if(privateHFXTClockFrequency > 16000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_3;\r
+ }\r
+ //If HFFrequency is between 8MHz and 16MHz\r
+ else if(privateHFXTClockFrequency > 8000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_2;\r
+ }\r
+ //If HFFrequency is between 0MHz and 4MHz\r
+ else if(privateHFXTClockFrequency < 4000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_0;\r
+ }\r
+ //If HFFrequency is between 4MHz and 8MHz\r
+ else\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_1;\r
+ }\r
+\r
+ while(HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG)\r
+ {\r
+ //Clear OSC fault Flags\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(HFXTOFFG);\r
+\r
+ //Clear OFIFG fault flag\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+ }\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+bool CS_turnOnHFXTWithTimeout(uint16_t hfxtdrive,\r
+ uint32_t timeout)\r
+{\r
+ //Verify user has initialized value of HFXTClock\r
+ assert(privateHFXTClockFrequency != 0);\r
+\r
+ assert(timeout > 0);\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ //Switch on HFXT oscillator\r
+ HWREG16(CS_BASE + OFS_CSCTL4) &= ~HFXTOFF;\r
+\r
+ // Disable HFXTBYPASS mode\r
+ HWREG16(CS_BASE + OFS_CSCTL4) &= ~HFXTBYPASS;\r
+\r
+ //Set correct HFFREQ bit for FR58xx/FR59xx devices based\r
+ //on HFXTClockFrequency\r
+\r
+ //If HFFrequency is 16MHz or above\r
+ if(privateHFXTClockFrequency > 16000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_3;\r
+ }\r
+ //If HFFrequency is between 8MHz and 16MHz\r
+ else if(privateHFXTClockFrequency > 8000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_2;\r
+ }\r
+ //If HFFrequency is between 0MHz and 4MHz\r
+ else if(privateHFXTClockFrequency < 4000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_0;\r
+ }\r
+ //If HFFrequency is between 4MHz and 8MHz\r
+ else\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_1;\r
+ }\r
+\r
+ while((HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG) && --timeout)\r
+ {\r
+ //Clear OSC fault Flags fault flags\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(HFXTOFFG);\r
+\r
+ // Clear the global fault flag. In case the LFXT caused the global fault\r
+ // flag to get set this will clear the global error condition. If any\r
+ // error condition persists, global flag will get again.\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+ }\r
+\r
+ if(timeout)\r
+ {\r
+ //Set drive strength for HFXT\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = (HWREG16(CS_BASE + OFS_CSCTL4) &\r
+ ~(CS_HFXT_DRIVE_24MHZ_32MHZ)\r
+ ) |\r
+ (hfxtdrive);\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+ return (STATUS_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+ return (STATUS_FAIL);\r
+ }\r
+}\r
+\r
+bool CS_bypassHFXTWithTimeout(uint32_t timeout)\r
+{\r
+ //Verify user has initialized value of HFXTClock\r
+ assert(privateHFXTClockFrequency != 0);\r
+\r
+ assert(timeout > 0);\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ //If HFFrequency is 16MHz or above\r
+ if(privateHFXTClockFrequency > 16000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_3;\r
+ }\r
+ //If HFFrequency is between 8MHz and 16MHz\r
+ else if(privateHFXTClockFrequency > 8000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_2;\r
+ }\r
+ //If HFFrequency is between 0MHz and 4MHz\r
+ else if(privateHFXTClockFrequency < 4000000)\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_0;\r
+ }\r
+ //If HFFrequency is between 4MHz and 8MHz\r
+ else\r
+ {\r
+ HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_1;\r
+ }\r
+\r
+ //Switch off HFXT oscillator and enable BYPASS mode\r
+ HWREG16(CS_BASE + OFS_CSCTL4) |= (HFXTBYPASS + HFXTOFF);\r
+\r
+ while((HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG) && --timeout)\r
+ {\r
+ //Clear OSC fault Flags fault flags\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(HFXTOFFG);\r
+\r
+ // Clear the global fault flag. In case the LFXT caused the global fault\r
+ // flag to get set this will clear the global error condition. If any\r
+ // error condition persists, global flag will get again.\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+ }\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+\r
+ if(timeout)\r
+ {\r
+ return (STATUS_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+}\r
+\r
+void CS_turnOffHFXT(void)\r
+{\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ //Switch off HFXT oscillator\r
+ HWREG16(CS_BASE + OFS_CSCTL4) |= HFXTOFF;\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+void CS_enableClockRequest(uint8_t selectClock)\r
+{\r
+ assert(\r
+ (CS_ACLK == selectClock)||\r
+ (CS_SMCLK == selectClock)||\r
+ (CS_MCLK == selectClock)||\r
+ (CS_MODOSC == selectClock));\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ HWREG8(CS_BASE + OFS_CSCTL6) |= selectClock;\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+void CS_disableClockRequest(uint8_t selectClock)\r
+{\r
+ assert(\r
+ (CS_ACLK == selectClock)||\r
+ (CS_SMCLK == selectClock)||\r
+ (CS_MCLK == selectClock)||\r
+ (CS_MODOSC == selectClock));\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ HWREG8(CS_BASE + OFS_CSCTL6) &= ~selectClock;\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+uint8_t CS_getFaultFlagStatus(uint8_t mask)\r
+{\r
+ assert(\r
+ (CS_HFXTOFFG == mask)||\r
+ (CS_LFXTOFFG == mask)\r
+ );\r
+ return (HWREG8(CS_BASE + OFS_CSCTL5) & mask);\r
+}\r
+\r
+void CS_clearFaultFlag(uint8_t mask)\r
+{\r
+ assert(\r
+ (CS_HFXTOFFG == mask)||\r
+ (CS_LFXTOFFG == mask)\r
+ );\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~mask;\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+uint32_t CS_getACLK(void)\r
+{\r
+ //Find ACLK source\r
+ uint16_t ACLKSource = (HWREG16(CS_BASE + OFS_CSCTL2) & SELA_7);\r
+ ACLKSource = ACLKSource >> 8;\r
+\r
+ //Find ACLK frequency divider\r
+ uint16_t ACLKSourceDivider = HWREG16(CS_BASE + OFS_CSCTL3) & SELA_7;\r
+ ACLKSourceDivider = ACLKSourceDivider >> 8;\r
+\r
+ return (privateCSAComputeCLKFrequency(\r
+ ACLKSource,\r
+ ACLKSourceDivider));\r
+}\r
+\r
+uint32_t CS_getSMCLK(void)\r
+{\r
+ //Find SMCLK source\r
+ uint16_t SMCLKSource = HWREG8(CS_BASE + OFS_CSCTL2) & SELS_7;\r
+\r
+ SMCLKSource = SMCLKSource >> 4;\r
+\r
+ //Find SMCLK frequency divider\r
+ uint16_t SMCLKSourceDivider = HWREG16(CS_BASE + OFS_CSCTL3) & SELS_7;\r
+ SMCLKSourceDivider = SMCLKSourceDivider >> 4;\r
+\r
+ return (privateCSAComputeCLKFrequency(\r
+ SMCLKSource,\r
+ SMCLKSourceDivider)\r
+ );\r
+}\r
+\r
+uint32_t CS_getMCLK(void)\r
+{\r
+ //Find MCLK source\r
+ uint16_t MCLKSource = (HWREG16(CS_BASE + OFS_CSCTL2) & SELM_7);\r
+ //Find MCLK frequency divider\r
+ uint16_t MCLKSourceDivider = HWREG16(CS_BASE + OFS_CSCTL3) & SELM_7;\r
+\r
+ return (privateCSAComputeCLKFrequency(\r
+ MCLKSource,\r
+ MCLKSourceDivider)\r
+ );\r
+}\r
+\r
+void CS_turnOffVLO(void)\r
+{\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ HWREG16(CS_BASE + OFS_CSCTL4) |= VLOOFF;\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+uint16_t CS_clearAllOscFlagsWithTimeout(uint32_t timeout)\r
+{\r
+ assert(timeout > 0);\r
+\r
+ // Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ do\r
+ {\r
+ // Clear all osc fault flags\r
+ HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG + HFXTOFFG);\r
+\r
+ // Clear the global osc fault flag.\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;\r
+\r
+ // Check LFXT fault flags\r
+ }\r
+ while((HWREG8(SFR_BASE + OFS_SFRIFG1) & OFIFG) && --timeout);\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+\r
+ return (HWREG8(CS_BASE + OFS_CSCTL5) & (LFXTOFFG + HFXTOFFG));\r
+}\r
+\r
+void CS_setDCOFreq(uint16_t dcorsel,\r
+ uint16_t dcofsel)\r
+{\r
+ assert(\r
+ (dcofsel == CS_DCOFSEL_0)||\r
+ (dcofsel == CS_DCOFSEL_1)||\r
+ (dcofsel == CS_DCOFSEL_2)||\r
+ (dcofsel == CS_DCOFSEL_3)||\r
+ (dcofsel == CS_DCOFSEL_4)||\r
+ (dcofsel == CS_DCOFSEL_5)||\r
+ (dcofsel == CS_DCOFSEL_6)\r
+ );\r
+\r
+ //Verify user has selected a valid DCO Frequency Range option\r
+ assert(\r
+ (dcorsel == CS_DCORSEL_0)||\r
+ (dcorsel == CS_DCORSEL_1));\r
+\r
+ //Unlock CS control register\r
+ HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;\r
+\r
+ // Set user's frequency selection for DCO\r
+ HWREG16(CS_BASE + OFS_CSCTL1) = (dcorsel + dcofsel);\r
+\r
+ // Lock CS control register\r
+ HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for cs_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// cs.h - Driver for the CS Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_CS_H__\r
+#define __MSP430WARE_CS_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#if defined(__MSP430_HAS_CS__) || defined(__MSP430_HAS_SFR__)\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockSourceDivider\r
+// parameter for functions: CS_initClockSignal().\r
+//\r
+//*****************************************************************************\r
+#define CS_CLOCK_DIVIDER_1 DIVM__1\r
+#define CS_CLOCK_DIVIDER_2 DIVM__2\r
+#define CS_CLOCK_DIVIDER_4 DIVM__4\r
+#define CS_CLOCK_DIVIDER_8 DIVM__8\r
+#define CS_CLOCK_DIVIDER_16 DIVM__16\r
+#define CS_CLOCK_DIVIDER_32 DIVM__32\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the selectClock parameter for\r
+// functions: CS_enableClockRequest(), and CS_disableClockRequest(); the\r
+// selectedClockSignal parameter for functions: CS_initClockSignal().\r
+//\r
+//*****************************************************************************\r
+#define CS_ACLK 0x01\r
+#define CS_MCLK 0x02\r
+#define CS_SMCLK 0x04\r
+#define CS_MODOSC MODCLKREQEN\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockSource parameter for\r
+// functions: CS_initClockSignal().\r
+//\r
+//*****************************************************************************\r
+#define CS_VLOCLK_SELECT SELM__VLOCLK\r
+#define CS_DCOCLK_SELECT SELM__DCOCLK\r
+#define CS_LFXTCLK_SELECT SELM__LFXTCLK\r
+#define CS_HFXTCLK_SELECT SELM__HFXTCLK\r
+#define CS_LFMODOSC_SELECT SELM__LFMODOSC\r
+#define CS_MODOSC_SELECT SELM__MODOSC\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the lfxtdrive parameter for\r
+// functions: CS_turnOnLFXT(), and CS_turnOnLFXTWithTimeout().\r
+//\r
+//*****************************************************************************\r
+#define CS_LFXT_DRIVE_0 LFXTDRIVE_0\r
+#define CS_LFXT_DRIVE_1 LFXTDRIVE_1\r
+#define CS_LFXT_DRIVE_2 LFXTDRIVE_2\r
+#define CS_LFXT_DRIVE_3 LFXTDRIVE_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the hfxtdrive parameter for\r
+// functions: CS_turnOnHFXT(), and CS_turnOnHFXTWithTimeout().\r
+//\r
+//*****************************************************************************\r
+#define CS_HFXT_DRIVE_4MHZ_8MHZ HFXTDRIVE_0\r
+#define CS_HFXT_DRIVE_8MHZ_16MHZ HFXTDRIVE_1\r
+#define CS_HFXT_DRIVE_16MHZ_24MHZ HFXTDRIVE_2\r
+#define CS_HFXT_DRIVE_24MHZ_32MHZ HFXTDRIVE_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: CS_getFaultFlagStatus(), and CS_clearFaultFlag() as well as\r
+// returned by the CS_getFaultFlagStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define CS_LFXTOFFG LFXTOFFG\r
+#define CS_HFXTOFFG HFXTOFFG\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the dcorsel parameter for\r
+// functions: CS_setDCOFreq().\r
+//\r
+//*****************************************************************************\r
+#define CS_DCORSEL_0 0x00\r
+#define CS_DCORSEL_1 DCORSEL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the dcofsel parameter for\r
+// functions: CS_setDCOFreq().\r
+//\r
+//*****************************************************************************\r
+#define CS_DCOFSEL_0 DCOFSEL_0\r
+#define CS_DCOFSEL_1 DCOFSEL_1\r
+#define CS_DCOFSEL_2 DCOFSEL_2\r
+#define CS_DCOFSEL_3 DCOFSEL_3\r
+#define CS_DCOFSEL_4 DCOFSEL_4\r
+#define CS_DCOFSEL_5 DCOFSEL_5\r
+#define CS_DCOFSEL_6 DCOFSEL_6\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the external clock source\r
+//!\r
+//! This function sets the external clock sources LFXT and HFXT crystal\r
+//! oscillator frequency values. This function must be called if an external\r
+//! crystal LFXT or HFXT is used and the user intends to call CS_getMCLK,\r
+//! CS_getSMCLK, CS_getACLK and CS_turnOnLFXT, CS_LFXTByPass,\r
+//! CS_turnOnLFXTWithTimeout, CS_LFXTByPassWithTimeout, CS_turnOnHFXT,\r
+//! CS_HFXTByPass, CS_turnOnHFXTWithTimeout, CS_HFXTByPassWithTimeout.\r
+//!\r
+//! \param LFXTCLK_frequency is the LFXT crystal frequencies in Hz\r
+//! \param HFXTCLK_frequency is the HFXT crystal frequencies in Hz\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_setExternalClockSource(uint32_t LFXTCLK_frequency,\r
+ uint32_t HFXTCLK_frequency);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes clock signal\r
+//!\r
+//! This function initializes each of the clock signals. The user must ensure\r
+//! that this function is called for each clock signal. If not, the default\r
+//! state is assumed for the particular clock signal. Refer to MSP430ware\r
+//! documentation for CS module or Device Family User's Guide for details of\r
+//! default clock signal states.\r
+//!\r
+//! \param selectedClockSignal Selected clock signal\r
+//! Valid values are:\r
+//! - \b CS_ACLK\r
+//! - \b CS_MCLK\r
+//! - \b CS_SMCLK\r
+//! - \b CS_MODOSC\r
+//! \param clockSource is the selected clock signal\r
+//! Valid values are:\r
+//! - \b CS_VLOCLK_SELECT\r
+//! - \b CS_DCOCLK_SELECT - [Not available for ACLK]\r
+//! - \b CS_LFXTCLK_SELECT\r
+//! - \b CS_HFXTCLK_SELECT - [Not available for ACLK]\r
+//! - \b CS_LFMODOSC_SELECT\r
+//! - \b CS_MODOSC_SELECT - [Not available for ACLK]\r
+//! \param clockSourceDivider is the selected clock divider to calculate clock\r
+//! signal from clock source.\r
+//! Valid values are:\r
+//! - \b CS_CLOCK_DIVIDER_1 - [Default for ACLK]\r
+//! - \b CS_CLOCK_DIVIDER_2\r
+//! - \b CS_CLOCK_DIVIDER_4\r
+//! - \b CS_CLOCK_DIVIDER_8 - [Default for SMCLK and MCLK]\r
+//! - \b CS_CLOCK_DIVIDER_16\r
+//! - \b CS_CLOCK_DIVIDER_32\r
+//!\r
+//! Modified bits of \b CSCTL0 register, bits of \b CSCTL3 register and bits of\r
+//! \b CSCTL2 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_initClockSignal(uint8_t selectedClockSignal,\r
+ uint16_t clockSource,\r
+ uint16_t clockSourceDivider);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the LFXT crystal in low frequency mode.\r
+//!\r
+//! Initializes the LFXT crystal oscillator in low frequency mode. Loops until\r
+//! all oscillator fault flags are cleared, with no timeout. See the device-\r
+//! specific data sheet for appropriate drive settings. IMPORTANT: User must\r
+//! call CS_setExternalClockSource function to set frequency of external clocks\r
+//! before calling this function.\r
+//!\r
+//! \param lfxtdrive is the target drive strength for the LFXT crystal\r
+//! oscillator.\r
+//! Valid values are:\r
+//! - \b CS_LFXT_DRIVE_0\r
+//! - \b CS_LFXT_DRIVE_1\r
+//! - \b CS_LFXT_DRIVE_2\r
+//! - \b CS_LFXT_DRIVE_3 [Default]\r
+//!\r
+//! Modified bits of \b CSCTL0 register, bits of \b CSCTL5 register, bits of \b\r
+//! CSCTL4 register and bits of \b SFRIFG1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_turnOnLFXT(uint16_t lfxtdrive);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Bypasses the LFXT crystal oscillator.\r
+//!\r
+//! Bypasses the LFXT crystal oscillator. Loops until all oscillator fault\r
+//! flags are cleared, with no timeout. IMPORTANT: User must call\r
+//! CS_setExternalClockSource function to set frequency of external clocks\r
+//! before calling this function.\r
+//!\r
+//!\r
+//! Modified bits of \b CSCTL0 register, bits of \b CSCTL5 register, bits of \b\r
+//! CSCTL4 register and bits of \b SFRIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_bypassLFXT(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the LFXT crystal oscillator in low frequency mode with\r
+//! timeout.\r
+//!\r
+//! Initializes the LFXT crystal oscillator in low frequency mode with timeout.\r
+//! Loops until all oscillator fault flags are cleared or until a timeout\r
+//! counter is decremented and equals to zero. See the device-specific\r
+//! datasheet for appropriate drive settings. IMPORTANT: User must call\r
+//! CS_setExternalClockSource to set frequency of external clocks before\r
+//! calling this function.\r
+//!\r
+//! \param lfxtdrive is the target drive strength for the LFXT crystal\r
+//! oscillator.\r
+//! Valid values are:\r
+//! - \b CS_LFXT_DRIVE_0\r
+//! - \b CS_LFXT_DRIVE_1\r
+//! - \b CS_LFXT_DRIVE_2\r
+//! - \b CS_LFXT_DRIVE_3 [Default]\r
+//! \param timeout is the count value that gets decremented every time the loop\r
+//! that clears oscillator fault flags gets executed.\r
+//!\r
+//! Modified bits of \b CSCTL0 register, bits of \b CSCTL5 register, bits of \b\r
+//! CSCTL4 register and bits of \b SFRIFG1 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL indicating if the LFXT crystal\r
+//! oscillator was initialized successfully\r
+//\r
+//*****************************************************************************\r
+extern bool CS_turnOnLFXTWithTimeout(uint16_t lfxtdrive,\r
+ uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Bypass the LFXT crystal oscillator with timeout.\r
+//!\r
+//! Bypasses the LFXT crystal oscillator with timeout. Loops until all\r
+//! oscillator fault flags are cleared or until a timeout counter is\r
+//! decremented and equals to zero. NOTE: User must call\r
+//! CS_setExternalClockSource to set frequency of external clocks before\r
+//! calling this function.\r
+//!\r
+//! \param timeout is the count value that gets decremented every time the loop\r
+//! that clears oscillator fault flags gets executed.\r
+//!\r
+//! Modified bits of \b CSCTL0 register, bits of \b CSCTL5 register, bits of \b\r
+//! CSCTL4 register and bits of \b SFRIFG register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL\r
+//\r
+//*****************************************************************************\r
+extern bool CS_bypassLFXTWithTimeout(uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Stops the LFXT oscillator using the LFXTOFF bit.\r
+//!\r
+//!\r
+//! Modified bits of \b CSCTL4 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_turnOffLFXT(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts the HFXFT crystal\r
+//!\r
+//! Initializes the HFXT crystal oscillator, which supports crystal frequencies\r
+//! between 0 MHz and 24 MHz, depending on the selected drive strength. Loops\r
+//! until all oscillator fault flags are cleared, with no timeout. See the\r
+//! device-specific data sheet for appropriate drive settings. NOTE: User must\r
+//! call CS_setExternalClockSource to set frequency of external clocks before\r
+//! calling this function.\r
+//!\r
+//! \param hfxtdrive is the target drive strength for the HFXT crystal\r
+//! oscillator.\r
+//! Valid values are:\r
+//! - \b CS_HFXT_DRIVE_4MHZ_8MHZ\r
+//! - \b CS_HFXT_DRIVE_8MHZ_16MHZ\r
+//! - \b CS_HFXT_DRIVE_16MHZ_24MHZ\r
+//! - \b CS_HFXT_DRIVE_24MHZ_32MHZ [Default]\r
+//!\r
+//! Modified bits of \b CSCTL5 register, bits of \b CSCTL4 register and bits of\r
+//! \b SFRIFG1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_turnOnHFXT(uint16_t hfxtdrive);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Bypasses the HFXT crystal oscillator\r
+//!\r
+//! Bypasses the HFXT crystal oscillator, which supports crystal frequencies\r
+//! between 0 MHz and 24 MHz. Loops until all oscillator fault flags are\r
+//! cleared, with no timeout.NOTE: User must call CS_setExternalClockSource to\r
+//! set frequency of external clocks before calling this function.\r
+//!\r
+//!\r
+//! Modified bits of \b CSCTL5 register, bits of \b CSCTL4 register and bits of\r
+//! \b SFRIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_bypassHFXT(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the HFXT crystal oscillator with timeout.\r
+//!\r
+//! Initializes the HFXT crystal oscillator, which supports crystal frequencies\r
+//! between 0 MHz and 24 MHz, depending on the selected drive strength. Loops\r
+//! until all oscillator fault flags are cleared or until a timeout counter is\r
+//! decremented and equals to zero. See the device-specific data sheet for\r
+//! appropriate drive settings. NOTE: User must call CS_setExternalClockSource\r
+//! to set frequency of external clocks before calling this function.\r
+//!\r
+//! \param hfxtdrive is the target drive strength for the HFXT crystal\r
+//! oscillator.\r
+//! Valid values are:\r
+//! - \b CS_HFXT_DRIVE_4MHZ_8MHZ\r
+//! - \b CS_HFXT_DRIVE_8MHZ_16MHZ\r
+//! - \b CS_HFXT_DRIVE_16MHZ_24MHZ\r
+//! - \b CS_HFXT_DRIVE_24MHZ_32MHZ [Default]\r
+//! \param timeout is the count value that gets decremented every time the loop\r
+//! that clears oscillator fault flags gets executed.\r
+//!\r
+//! Modified bits of \b CSCTL5 register, bits of \b CSCTL4 register and bits of\r
+//! \b SFRIFG1 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL\r
+//\r
+//*****************************************************************************\r
+extern bool CS_turnOnHFXTWithTimeout(uint16_t hfxtdrive,\r
+ uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Bypasses the HFXT crustal oscillator with timeout\r
+//!\r
+//! Bypasses the HFXT crystal oscillator, which supports crystal frequencies\r
+//! between 0 MHz and 24 MHz. Loops until all oscillator fault flags are\r
+//! cleared or until a timeout counter is decremented and equals to zero. NOTE:\r
+//! User must call CS_setExternalClockSource to set frequency of external\r
+//! clocks before calling this function.\r
+//!\r
+//! \param timeout is the count value that gets decremented every time the loop\r
+//! that clears oscillator fault flags gets executed.\r
+//!\r
+//! Modified bits of \b CSCTL5 register, bits of \b CSCTL4 register and bits of\r
+//! \b SFRIFG1 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL\r
+//\r
+//*****************************************************************************\r
+extern bool CS_bypassHFXTWithTimeout(uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Stops the HFXT oscillator using the HFXTOFF bit.\r
+//!\r
+//!\r
+//! Modified bits of \b CSCTL4 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_turnOffHFXT(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables conditional module requests\r
+//!\r
+//! \param selectClock selects specific request enables.\r
+//! Valid values are:\r
+//! - \b CS_ACLK\r
+//! - \b CS_MCLK\r
+//! - \b CS_SMCLK\r
+//! - \b CS_MODOSC\r
+//!\r
+//! Modified bits of \b CSCTL6 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_enableClockRequest(uint8_t selectClock);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables conditional module requests\r
+//!\r
+//! \param selectClock selects specific request enables.\r
+//! Valid values are:\r
+//! - \b CS_ACLK\r
+//! - \b CS_MCLK\r
+//! - \b CS_SMCLK\r
+//! - \b CS_MODOSC\r
+//!\r
+//! Modified bits of \b CSCTL6 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_disableClockRequest(uint8_t selectClock);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the current CS fault flag status.\r
+//!\r
+//! \param mask is the masked interrupt flag status to be returned. Mask\r
+//! parameter can be either any of the following selection.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b CS_LFXTOFFG - LFXT oscillator fault flag\r
+//! - \b CS_HFXTOFFG - HFXT oscillator fault flag\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b CS_LFXTOFFG LFXT oscillator fault flag\r
+//! - \b CS_HFXTOFFG HFXT oscillator fault flag\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint8_t CS_getFaultFlagStatus(uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the current CS fault flag status for the masked bit.\r
+//!\r
+//! \param mask is the masked interrupt flag status to be returned. mask\r
+//! parameter can be any one of the following\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b CS_LFXTOFFG - LFXT oscillator fault flag\r
+//! - \b CS_HFXTOFFG - HFXT oscillator fault flag\r
+//!\r
+//! Modified bits of \b CSCTL5 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_clearFaultFlag(uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get the current ACLK frequency.\r
+//!\r
+//! If a oscillator fault is set, the frequency returned will be based on the\r
+//! fail safe mechanism of CS module. The user of this API must ensure that\r
+//! CS_externalClockSourceInit API was invoked before in case LFXT or HFXT is\r
+//! being used.\r
+//!\r
+//!\r
+//! \return Current ACLK frequency in Hz\r
+//\r
+//*****************************************************************************\r
+extern uint32_t CS_getACLK(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get the current SMCLK frequency.\r
+//!\r
+//! If a oscillator fault is set, the frequency returned will be based on the\r
+//! fail safe mechanism of CS module. The user of this API must ensure that\r
+//! CS_externalClockSourceInit API was invoked before in case LFXT or HFXT is\r
+//! being used.\r
+//!\r
+//!\r
+//! \return Current SMCLK frequency in Hz\r
+//\r
+//*****************************************************************************\r
+extern uint32_t CS_getSMCLK(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get the current MCLK frequency.\r
+//!\r
+//! If a oscillator fault is set, the frequency returned will be based on the\r
+//! fail safe mechanism of CS module. The user of this API must ensure that\r
+//! CS_externalClockSourceInit API was invoked before in case LFXT or HFXT is\r
+//! being used.\r
+//!\r
+//!\r
+//! \return Current MCLK frequency in Hz\r
+//\r
+//*****************************************************************************\r
+extern uint32_t CS_getMCLK(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Turns off VLO\r
+//!\r
+//!\r
+//! Modified bits of \b CSCTL4 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_turnOffVLO(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears all the Oscillator Flags\r
+//!\r
+//! \param timeout is the count value that gets decremented every time the loop\r
+//! that clears oscillator fault flags gets executed.\r
+//!\r
+//! Modified bits of \b CSCTL5 register and bits of \b SFRIFG1 register.\r
+//!\r
+//! \return the mask of the oscillator flag status\r
+//\r
+//*****************************************************************************\r
+extern uint16_t CS_clearAllOscFlagsWithTimeout(uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Set DCO frequency\r
+//!\r
+//! \param dcorsel selects frequency range option.\r
+//! Valid values are:\r
+//! - \b CS_DCORSEL_0 [Default] - Low Frequency Option\r
+//! - \b CS_DCORSEL_1 - High Frequency Option\r
+//! \param dcofsel selects valid frequency options based on dco frequency range\r
+//! selection (dcorsel)\r
+//! Valid values are:\r
+//! - \b CS_DCOFSEL_0 - Low frequency option 1MHz. High frequency option\r
+//! 1MHz.\r
+//! - \b CS_DCOFSEL_1 - Low frequency option 2.67MHz. High frequency\r
+//! option 5.33MHz.\r
+//! - \b CS_DCOFSEL_2 - Low frequency option 3.33MHz. High frequency\r
+//! option 6.67MHz.\r
+//! - \b CS_DCOFSEL_3 - Low frequency option 4MHz. High frequency option\r
+//! 8MHz.\r
+//! - \b CS_DCOFSEL_4 - Low frequency option 5.33MHz. High frequency\r
+//! option 16MHz.\r
+//! - \b CS_DCOFSEL_5 - Low frequency option 6.67MHz. High frequency\r
+//! option 20MHz.\r
+//! - \b CS_DCOFSEL_6 - Low frequency option 8MHz. High frequency option\r
+//! 24MHz.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void CS_setDCOFreq(uint16_t dcorsel,\r
+ uint16_t dcofsel);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_CS_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+/* ============================================================================ */\r
+/* Copyright (c) 2013, Texas Instruments Incorporated */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* */\r
+/* * Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* */\r
+/* * Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the */\r
+/* documentation and/or other materials provided with the distribution. */\r
+/* */\r
+/* * Neither the name of Texas Instruments Incorporated nor the names of */\r
+/* its contributors may be used to endorse or promote products derived */\r
+/* from this software without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */\r
+/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */\r
+/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */\r
+/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */\r
+/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */\r
+/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */\r
+/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */\r
+/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ============================================================================ */\r
+\r
+/********************************************************************\r
+*\r
+* Standard register and bit definitions for the Texas Instruments\r
+* MSP430 microcontroller.\r
+*\r
+* This file supports assembler and C development for\r
+* MSP430FR5XX_FR6XXGENERIC device.\r
+*\r
+* Texas Instruments, Version 1.0\r
+*\r
+* Rev. 1.0, Setup\r
+*\r
+*\r
+********************************************************************/\r
+\r
+#ifndef __msp430FR5XX_FR6XXGENERIC\r
+#define __msp430FR5XX_FR6XXGENERIC\r
+\r
+//#define __MSP430_HEADER_VERSION__ 1125\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* PERIPHERAL FILE MAP */\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#ifndef SFR_8BIT\r
+/* External references resolved by a device-specific linker command file */\r
+#define SFR_8BIT(address) extern volatile unsigned char address\r
+#define SFR_16BIT(address) extern volatile unsigned int address\r
+//#define SFR_20BIT(address) extern volatile unsigned int address\r
+typedef void (* __SFR_FARPTR)();\r
+#define SFR_20BIT(address) extern __SFR_FARPTR address\r
+#define SFR_32BIT(address) extern volatile unsigned long address\r
+\r
+#endif\r
+\r
+\r
+/************************************************************\r
+* STANDARD BITS\r
+************************************************************/\r
+\r
+#define BIT0 (0x0001)\r
+#define BIT1 (0x0002)\r
+#define BIT2 (0x0004)\r
+#define BIT3 (0x0008)\r
+#define BIT4 (0x0010)\r
+#define BIT5 (0x0020)\r
+#define BIT6 (0x0040)\r
+#define BIT7 (0x0080)\r
+#define BIT8 (0x0100)\r
+#define BIT9 (0x0200)\r
+#define BITA (0x0400)\r
+#define BITB (0x0800)\r
+#define BITC (0x1000)\r
+#define BITD (0x2000)\r
+#define BITE (0x4000)\r
+#define BITF (0x8000)\r
+\r
+/************************************************************\r
+* STATUS REGISTER BITS\r
+************************************************************/\r
+\r
+#define C (0x0001)\r
+#define Z (0x0002)\r
+#define N (0x0004)\r
+#define V (0x0100)\r
+#define GIE (0x0008)\r
+#define CPUOFF (0x0010)\r
+#define OSCOFF (0x0020)\r
+#define SCG0 (0x0040)\r
+#define SCG1 (0x0080)\r
+\r
+/* Low Power Modes coded with Bits 4-7 in SR */\r
+\r
+#ifdef __ASM_HEADER__ /* Begin #defines for assembler */\r
+#define LPM0 (CPUOFF)\r
+#define LPM1 (SCG0+CPUOFF)\r
+#define LPM2 (SCG1+CPUOFF)\r
+#define LPM3 (SCG1+SCG0+CPUOFF)\r
+#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)\r
+/* End #defines for assembler */\r
+\r
+#else /* Begin #defines for C */\r
+#define LPM0_bits (CPUOFF)\r
+#define LPM1_bits (SCG0+CPUOFF)\r
+#define LPM2_bits (SCG1+CPUOFF)\r
+#define LPM3_bits (SCG1+SCG0+CPUOFF)\r
+#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)\r
+\r
+#include "in430.h"\r
+#include <intrinsics.h>\r
+\r
+#if __MSP430_HEADER_VERSION__ < 1107\r
+ #define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */\r
+ #define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */\r
+ #define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */\r
+ #define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */\r
+ #define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */\r
+ #define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */\r
+ #define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */\r
+ #define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */\r
+ #define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */\r
+ #define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */\r
+#else\r
+ #define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */\r
+ #define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */\r
+ #define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */\r
+ #define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */\r
+ #define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */\r
+ #define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */\r
+ #define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */\r
+ #define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */\r
+ #define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */\r
+ #define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */\r
+#endif\r
+#endif /* End #defines for C */\r
+\r
+/************************************************************\r
+* CPU\r
+************************************************************/\r
+#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */\r
+\r
+#if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \\r
+ || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \\r
+ || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \\r
+ || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__)\r
+ #define __MSP430_HAS_TxA7__\r
+#endif\r
+#if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \\r
+ || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__)\r
+ #define __MSP430_HAS_TxB7__\r
+#endif\r
+#if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \\r
+ || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__)\r
+ #define __MSP430_HAS_TxD7__\r
+#endif\r
+#if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__)\r
+ #define __MSP430_HAS_USCI_Ax__\r
+#endif\r
+#if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__)\r
+ #define __MSP430_HAS_USCI_Bx__\r
+#endif\r
+#if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__)\r
+ #define __MSP430_HAS_EUSCI_Ax__\r
+#endif\r
+#if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__)\r
+ #define __MSP430_HAS_EUSCI_Bx__\r
+#endif\r
+#ifdef __MSP430_HAS_EUSCI_B0__\r
+ #define __MSP430_HAS_EUSCI_Bx__\r
+#endif\r
+\r
+/************************************************************\r
+* ADC12_B\r
+************************************************************/\r
+#ifdef __MSP430_HAS_ADC12_B__ /* Definition to show that Module is available */\r
+\r
+#define OFS_ADC12CTL0 (0x0000) /* ADC12 B Control 0 */\r
+#define OFS_ADC12CTL0_L OFS_ADC12CTL0\r
+#define OFS_ADC12CTL0_H OFS_ADC12CTL0+1\r
+#define OFS_ADC12CTL1 (0x0002) /* ADC12 B Control 1 */\r
+#define OFS_ADC12CTL1_L OFS_ADC12CTL1\r
+#define OFS_ADC12CTL1_H OFS_ADC12CTL1+1\r
+#define OFS_ADC12CTL2 (0x0004) /* ADC12 B Control 2 */\r
+#define OFS_ADC12CTL2_L OFS_ADC12CTL2\r
+#define OFS_ADC12CTL2_H OFS_ADC12CTL2+1\r
+#define OFS_ADC12CTL3 (0x0006) /* ADC12 B Control 3 */\r
+#define OFS_ADC12CTL3_L OFS_ADC12CTL3\r
+#define OFS_ADC12CTL3_H OFS_ADC12CTL3+1\r
+#define OFS_ADC12LO (0x0008) /* ADC12 B Window Comparator High Threshold */\r
+#define OFS_ADC12LO_L OFS_ADC12LO\r
+#define OFS_ADC12LO_H OFS_ADC12LO+1\r
+#define OFS_ADC12HI (0x000A) /* ADC12 B Window Comparator High Threshold */\r
+#define OFS_ADC12HI_L OFS_ADC12HI\r
+#define OFS_ADC12HI_H OFS_ADC12HI+1\r
+#define OFS_ADC12IFGR0 (0x000C) /* ADC12 B Interrupt Flag 0 */\r
+#define OFS_ADC12IFGR0_L OFS_ADC12IFGR0\r
+#define OFS_ADC12IFGR0_H OFS_ADC12IFGR0+1\r
+#define OFS_ADC12IFGR1 (0x000E) /* ADC12 B Interrupt Flag 1 */\r
+#define OFS_ADC12IFGR1_L OFS_ADC12IFGR1\r
+#define OFS_ADC12IFGR1_H OFS_ADC12IFGR1+1\r
+#define OFS_ADC12IFGR2 (0x0010) /* ADC12 B Interrupt Flag 2 */\r
+#define OFS_ADC12IFGR2_L OFS_ADC12IFGR2\r
+#define OFS_ADC12IFGR2_H OFS_ADC12IFGR2+1\r
+#define OFS_ADC12IER0 (0x0012) /* ADC12 B Interrupt Enable 0 */\r
+#define OFS_ADC12IER0_L OFS_ADC12IER0\r
+#define OFS_ADC12IER0_H OFS_ADC12IER0+1\r
+#define OFS_ADC12IER1 (0x0014) /* ADC12 B Interrupt Enable 1 */\r
+#define OFS_ADC12IER1_L OFS_ADC12IER1\r
+#define OFS_ADC12IER1_H OFS_ADC12IER1+1\r
+#define OFS_ADC12IER2 (0x0016) /* ADC12 B Interrupt Enable 2 */\r
+#define OFS_ADC12IER2_L OFS_ADC12IER2\r
+#define OFS_ADC12IER2_H OFS_ADC12IER2+1\r
+#define OFS_ADC12IV (0x0018) /* ADC12 B Interrupt Vector Word */\r
+#define OFS_ADC12IV_L OFS_ADC12IV\r
+#define OFS_ADC12IV_H OFS_ADC12IV+1\r
+\r
+#define OFS_ADC12MCTL0 (0x0020) /* ADC12 Memory Control 0 */\r
+#define OFS_ADC12MCTL0_L OFS_ADC12MCTL0\r
+#define OFS_ADC12MCTL0_H OFS_ADC12MCTL0+1\r
+#define OFS_ADC12MCTL1 (0x0022) /* ADC12 Memory Control 1 */\r
+#define OFS_ADC12MCTL1_L OFS_ADC12MCTL1\r
+#define OFS_ADC12MCTL1_H OFS_ADC12MCTL1+1\r
+#define OFS_ADC12MCTL2 (0x0024) /* ADC12 Memory Control 2 */\r
+#define OFS_ADC12MCTL2_L OFS_ADC12MCTL2\r
+#define OFS_ADC12MCTL2_H OFS_ADC12MCTL2+1\r
+#define OFS_ADC12MCTL3 (0x0026) /* ADC12 Memory Control 3 */\r
+#define OFS_ADC12MCTL3_L OFS_ADC12MCTL3\r
+#define OFS_ADC12MCTL3_H OFS_ADC12MCTL3+1\r
+#define OFS_ADC12MCTL4 (0x0028) /* ADC12 Memory Control 4 */\r
+#define OFS_ADC12MCTL4_L OFS_ADC12MCTL4\r
+#define OFS_ADC12MCTL4_H OFS_ADC12MCTL4+1\r
+#define OFS_ADC12MCTL5 (0x002A) /* ADC12 Memory Control 5 */\r
+#define OFS_ADC12MCTL5_L OFS_ADC12MCTL5\r
+#define OFS_ADC12MCTL5_H OFS_ADC12MCTL5+1\r
+#define OFS_ADC12MCTL6 (0x002C) /* ADC12 Memory Control 6 */\r
+#define OFS_ADC12MCTL6_L OFS_ADC12MCTL6\r
+#define OFS_ADC12MCTL6_H OFS_ADC12MCTL6+1\r
+#define OFS_ADC12MCTL7 (0x002E) /* ADC12 Memory Control 7 */\r
+#define OFS_ADC12MCTL7_L OFS_ADC12MCTL7\r
+#define OFS_ADC12MCTL7_H OFS_ADC12MCTL7+1\r
+#define OFS_ADC12MCTL8 (0x0030) /* ADC12 Memory Control 8 */\r
+#define OFS_ADC12MCTL8_L OFS_ADC12MCTL8\r
+#define OFS_ADC12MCTL8_H OFS_ADC12MCTL8+1\r
+#define OFS_ADC12MCTL9 (0x0032) /* ADC12 Memory Control 9 */\r
+#define OFS_ADC12MCTL9_L OFS_ADC12MCTL9\r
+#define OFS_ADC12MCTL9_H OFS_ADC12MCTL9+1\r
+#define OFS_ADC12MCTL10 (0x0034) /* ADC12 Memory Control 10 */\r
+#define OFS_ADC12MCTL10_L OFS_ADC12MCTL10\r
+#define OFS_ADC12MCTL10_H OFS_ADC12MCTL10+1\r
+#define OFS_ADC12MCTL11 (0x0036) /* ADC12 Memory Control 11 */\r
+#define OFS_ADC12MCTL11_L OFS_ADC12MCTL11\r
+#define OFS_ADC12MCTL11_H OFS_ADC12MCTL11+1\r
+#define OFS_ADC12MCTL12 (0x0038) /* ADC12 Memory Control 12 */\r
+#define OFS_ADC12MCTL12_L OFS_ADC12MCTL12\r
+#define OFS_ADC12MCTL12_H OFS_ADC12MCTL12+1\r
+#define OFS_ADC12MCTL13 (0x003A) /* ADC12 Memory Control 13 */\r
+#define OFS_ADC12MCTL13_L OFS_ADC12MCTL13\r
+#define OFS_ADC12MCTL13_H OFS_ADC12MCTL13+1\r
+#define OFS_ADC12MCTL14 (0x003C) /* ADC12 Memory Control 14 */\r
+#define OFS_ADC12MCTL14_L OFS_ADC12MCTL14\r
+#define OFS_ADC12MCTL14_H OFS_ADC12MCTL14+1\r
+#define OFS_ADC12MCTL15 (0x003E) /* ADC12 Memory Control 15 */\r
+#define OFS_ADC12MCTL15_L OFS_ADC12MCTL15\r
+#define OFS_ADC12MCTL15_H OFS_ADC12MCTL15+1\r
+#define OFS_ADC12MCTL16 (0x0040) /* ADC12 Memory Control 16 */\r
+#define OFS_ADC12MCTL16_L OFS_ADC12MCTL16\r
+#define OFS_ADC12MCTL16_H OFS_ADC12MCTL16+1\r
+#define OFS_ADC12MCTL17 (0x0042) /* ADC12 Memory Control 17 */\r
+#define OFS_ADC12MCTL17_L OFS_ADC12MCTL17\r
+#define OFS_ADC12MCTL17_H OFS_ADC12MCTL17+1\r
+#define OFS_ADC12MCTL18 (0x0044) /* ADC12 Memory Control 18 */\r
+#define OFS_ADC12MCTL18_L OFS_ADC12MCTL18\r
+#define OFS_ADC12MCTL18_H OFS_ADC12MCTL18+1\r
+#define OFS_ADC12MCTL19 (0x0046) /* ADC12 Memory Control 19 */\r
+#define OFS_ADC12MCTL19_L OFS_ADC12MCTL19\r
+#define OFS_ADC12MCTL19_H OFS_ADC12MCTL19+1\r
+#define OFS_ADC12MCTL20 (0x0048) /* ADC12 Memory Control 20 */\r
+#define OFS_ADC12MCTL20_L OFS_ADC12MCTL20\r
+#define OFS_ADC12MCTL20_H OFS_ADC12MCTL20+1\r
+#define OFS_ADC12MCTL21 (0x004A) /* ADC12 Memory Control 21 */\r
+#define OFS_ADC12MCTL21_L OFS_ADC12MCTL21\r
+#define OFS_ADC12MCTL21_H OFS_ADC12MCTL21+1\r
+#define OFS_ADC12MCTL22 (0x004C) /* ADC12 Memory Control 22 */\r
+#define OFS_ADC12MCTL22_L OFS_ADC12MCTL22\r
+#define OFS_ADC12MCTL22_H OFS_ADC12MCTL22+1\r
+#define OFS_ADC12MCTL23 (0x004E) /* ADC12 Memory Control 23 */\r
+#define OFS_ADC12MCTL23_L OFS_ADC12MCTL23\r
+#define OFS_ADC12MCTL23_H OFS_ADC12MCTL23+1\r
+#define OFS_ADC12MCTL24 (0x0050) /* ADC12 Memory Control 24 */\r
+#define OFS_ADC12MCTL24_L OFS_ADC12MCTL24\r
+#define OFS_ADC12MCTL24_H OFS_ADC12MCTL24+1\r
+#define OFS_ADC12MCTL25 (0x0052) /* ADC12 Memory Control 25 */\r
+#define OFS_ADC12MCTL25_L OFS_ADC12MCTL25\r
+#define OFS_ADC12MCTL25_H OFS_ADC12MCTL25+1\r
+#define OFS_ADC12MCTL26 (0x0054) /* ADC12 Memory Control 26 */\r
+#define OFS_ADC12MCTL26_L OFS_ADC12MCTL26\r
+#define OFS_ADC12MCTL26_H OFS_ADC12MCTL26+1\r
+#define OFS_ADC12MCTL27 (0x0056) /* ADC12 Memory Control 27 */\r
+#define OFS_ADC12MCTL27_L OFS_ADC12MCTL27\r
+#define OFS_ADC12MCTL27_H OFS_ADC12MCTL27+1\r
+#define OFS_ADC12MCTL28 (0x0058) /* ADC12 Memory Control 28 */\r
+#define OFS_ADC12MCTL28_L OFS_ADC12MCTL28\r
+#define OFS_ADC12MCTL28_H OFS_ADC12MCTL28+1\r
+#define OFS_ADC12MCTL29 (0x005A) /* ADC12 Memory Control 29 */\r
+#define OFS_ADC12MCTL29_L OFS_ADC12MCTL29\r
+#define OFS_ADC12MCTL29_H OFS_ADC12MCTL29+1\r
+#define OFS_ADC12MCTL30 (0x005C) /* ADC12 Memory Control 30 */\r
+#define OFS_ADC12MCTL30_L OFS_ADC12MCTL30\r
+#define OFS_ADC12MCTL30_H OFS_ADC12MCTL30+1\r
+#define OFS_ADC12MCTL31 (0x005E) /* ADC12 Memory Control 31 */\r
+#define OFS_ADC12MCTL31_L OFS_ADC12MCTL31\r
+#define OFS_ADC12MCTL31_H OFS_ADC12MCTL31+1\r
+#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */\r
+#ifdef __ASM_HEADER__\r
+#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */\r
+#else\r
+#define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */\r
+#endif\r
+\r
+#define OFS_ADC12MEM0 (0x0060) /* ADC12 Conversion Memory 0 */\r
+#define OFS_ADC12MEM0_L OFS_ADC12MEM0\r
+#define OFS_ADC12MEM0_H OFS_ADC12MEM0+1\r
+#define OFS_ADC12MEM1 (0x0062) /* ADC12 Conversion Memory 1 */\r
+#define OFS_ADC12MEM1_L OFS_ADC12MEM1\r
+#define OFS_ADC12MEM1_H OFS_ADC12MEM1+1\r
+#define OFS_ADC12MEM2 (0x0064) /* ADC12 Conversion Memory 2 */\r
+#define OFS_ADC12MEM2_L OFS_ADC12MEM2\r
+#define OFS_ADC12MEM2_H OFS_ADC12MEM2+1\r
+#define OFS_ADC12MEM3 (0x0066) /* ADC12 Conversion Memory 3 */\r
+#define OFS_ADC12MEM3_L OFS_ADC12MEM3\r
+#define OFS_ADC12MEM3_H OFS_ADC12MEM3+1\r
+#define OFS_ADC12MEM4 (0x0068) /* ADC12 Conversion Memory 4 */\r
+#define OFS_ADC12MEM4_L OFS_ADC12MEM4\r
+#define OFS_ADC12MEM4_H OFS_ADC12MEM4+1\r
+#define OFS_ADC12MEM5 (0x006A) /* ADC12 Conversion Memory 5 */\r
+#define OFS_ADC12MEM5_L OFS_ADC12MEM5\r
+#define OFS_ADC12MEM5_H OFS_ADC12MEM5+1\r
+#define OFS_ADC12MEM6 (0x006C) /* ADC12 Conversion Memory 6 */\r
+#define OFS_ADC12MEM6_L OFS_ADC12MEM6\r
+#define OFS_ADC12MEM6_H OFS_ADC12MEM6+1\r
+#define OFS_ADC12MEM7 (0x006E) /* ADC12 Conversion Memory 7 */\r
+#define OFS_ADC12MEM7_L OFS_ADC12MEM7\r
+#define OFS_ADC12MEM7_H OFS_ADC12MEM7+1\r
+#define OFS_ADC12MEM8 (0x0070) /* ADC12 Conversion Memory 8 */\r
+#define OFS_ADC12MEM8_L OFS_ADC12MEM8\r
+#define OFS_ADC12MEM8_H OFS_ADC12MEM8+1\r
+#define OFS_ADC12MEM9 (0x0072) /* ADC12 Conversion Memory 9 */\r
+#define OFS_ADC12MEM9_L OFS_ADC12MEM9\r
+#define OFS_ADC12MEM9_H OFS_ADC12MEM9+1\r
+#define OFS_ADC12MEM10 (0x0074) /* ADC12 Conversion Memory 10 */\r
+#define OFS_ADC12MEM10_L OFS_ADC12MEM10\r
+#define OFS_ADC12MEM10_H OFS_ADC12MEM10+1\r
+#define OFS_ADC12MEM11 (0x0076) /* ADC12 Conversion Memory 11 */\r
+#define OFS_ADC12MEM11_L OFS_ADC12MEM11\r
+#define OFS_ADC12MEM11_H OFS_ADC12MEM11+1\r
+#define OFS_ADC12MEM12 (0x0078) /* ADC12 Conversion Memory 12 */\r
+#define OFS_ADC12MEM12_L OFS_ADC12MEM12\r
+#define OFS_ADC12MEM12_H OFS_ADC12MEM12+1\r
+#define OFS_ADC12MEM13 (0x007A) /* ADC12 Conversion Memory 13 */\r
+#define OFS_ADC12MEM13_L OFS_ADC12MEM13\r
+#define OFS_ADC12MEM13_H OFS_ADC12MEM13+1\r
+#define OFS_ADC12MEM14 (0x007C) /* ADC12 Conversion Memory 14 */\r
+#define OFS_ADC12MEM14_L OFS_ADC12MEM14\r
+#define OFS_ADC12MEM14_H OFS_ADC12MEM14+1\r
+#define OFS_ADC12MEM15 (0x007E) /* ADC12 Conversion Memory 15 */\r
+#define OFS_ADC12MEM15_L OFS_ADC12MEM15\r
+#define OFS_ADC12MEM15_H OFS_ADC12MEM15+1\r
+#define OFS_ADC12MEM16 (0x0080) /* ADC12 Conversion Memory 16 */\r
+#define OFS_ADC12MEM16_L OFS_ADC12MEM16\r
+#define OFS_ADC12MEM16_H OFS_ADC12MEM16+1\r
+#define OFS_ADC12MEM17 (0x0082) /* ADC12 Conversion Memory 17 */\r
+#define OFS_ADC12MEM17_L OFS_ADC12MEM17\r
+#define OFS_ADC12MEM17_H OFS_ADC12MEM17+1\r
+#define OFS_ADC12MEM18 (0x0084) /* ADC12 Conversion Memory 18 */\r
+#define OFS_ADC12MEM18_L OFS_ADC12MEM18\r
+#define OFS_ADC12MEM18_H OFS_ADC12MEM18+1\r
+#define OFS_ADC12MEM19 (0x0086) /* ADC12 Conversion Memory 19 */\r
+#define OFS_ADC12MEM19_L OFS_ADC12MEM19\r
+#define OFS_ADC12MEM19_H OFS_ADC12MEM19+1\r
+#define OFS_ADC12MEM20 (0x0088) /* ADC12 Conversion Memory 20 */\r
+#define OFS_ADC12MEM20_L OFS_ADC12MEM20\r
+#define OFS_ADC12MEM20_H OFS_ADC12MEM20+1\r
+#define OFS_ADC12MEM21 (0x008A) /* ADC12 Conversion Memory 21 */\r
+#define OFS_ADC12MEM21_L OFS_ADC12MEM21\r
+#define OFS_ADC12MEM21_H OFS_ADC12MEM21+1\r
+#define OFS_ADC12MEM22 (0x008C) /* ADC12 Conversion Memory 22 */\r
+#define OFS_ADC12MEM22_L OFS_ADC12MEM22\r
+#define OFS_ADC12MEM22_H OFS_ADC12MEM22+1\r
+#define OFS_ADC12MEM23 (0x008E) /* ADC12 Conversion Memory 23 */\r
+#define OFS_ADC12MEM23_L OFS_ADC12MEM23\r
+#define OFS_ADC12MEM23_H OFS_ADC12MEM23+1\r
+#define OFS_ADC12MEM24 (0x0090) /* ADC12 Conversion Memory 24 */\r
+#define OFS_ADC12MEM24_L OFS_ADC12MEM24\r
+#define OFS_ADC12MEM24_H OFS_ADC12MEM24+1\r
+#define OFS_ADC12MEM25 (0x0092) /* ADC12 Conversion Memory 25 */\r
+#define OFS_ADC12MEM25_L OFS_ADC12MEM25\r
+#define OFS_ADC12MEM25_H OFS_ADC12MEM25+1\r
+#define OFS_ADC12MEM26 (0x0094) /* ADC12 Conversion Memory 26 */\r
+#define OFS_ADC12MEM26_L OFS_ADC12MEM26\r
+#define OFS_ADC12MEM26_H OFS_ADC12MEM26+1\r
+#define OFS_ADC12MEM27 (0x0096) /* ADC12 Conversion Memory 27 */\r
+#define OFS_ADC12MEM27_L OFS_ADC12MEM27\r
+#define OFS_ADC12MEM27_H OFS_ADC12MEM27+1\r
+#define OFS_ADC12MEM28 (0x0098) /* ADC12 Conversion Memory 28 */\r
+#define OFS_ADC12MEM28_L OFS_ADC12MEM28\r
+#define OFS_ADC12MEM28_H OFS_ADC12MEM28+1\r
+#define OFS_ADC12MEM29 (0x009A) /* ADC12 Conversion Memory 29 */\r
+#define OFS_ADC12MEM29_L OFS_ADC12MEM29\r
+#define OFS_ADC12MEM29_H OFS_ADC12MEM29+1\r
+#define OFS_ADC12MEM30 (0x009C) /* ADC12 Conversion Memory 30 */\r
+#define OFS_ADC12MEM30_L OFS_ADC12MEM30\r
+#define OFS_ADC12MEM30_H OFS_ADC12MEM30+1\r
+#define OFS_ADC12MEM31 (0x009E) /* ADC12 Conversion Memory 31 */\r
+#define OFS_ADC12MEM31_L OFS_ADC12MEM31\r
+#define OFS_ADC12MEM31_H OFS_ADC12MEM31+1\r
+#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */\r
+#ifdef __ASM_HEADER__\r
+#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */\r
+#else\r
+#define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */\r
+#endif\r
+\r
+/* ADC12CTL0 Control Bits */\r
+#define ADC12SC (0x0001) /* ADC12 Start Conversion */\r
+#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */\r
+#define ADC12ON (0x0010) /* ADC12 On/enable */\r
+#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */\r
+#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
+#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
+#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
+#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
+#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
+#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
+#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
+#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
+\r
+/* ADC12CTL0 Control Bits */\r
+#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */\r
+#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */\r
+#define ADC12ON_L (0x0010) /* ADC12 On/enable */\r
+#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */\r
+\r
+/* ADC12CTL0 Control Bits */\r
+#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
+#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
+#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
+#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
+#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
+#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
+#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
+#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
+\r
+#define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
+#define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
+#define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
+#define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
+#define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */\r
+#define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */\r
+#define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */\r
+#define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */\r
+#define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */\r
+#define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */\r
+#define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */\r
+#define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */\r
+#define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */\r
+#define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */\r
+#define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */\r
+#define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */\r
+\r
+#define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
+#define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
+#define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
+#define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
+#define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */\r
+#define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */\r
+#define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */\r
+#define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */\r
+#define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */\r
+#define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */\r
+#define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */\r
+#define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */\r
+#define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */\r
+#define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */\r
+#define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */\r
+#define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */\r
+\r
+/* ADC12CTL1 Control Bits */\r
+#define ADC12BUSY (0x0001) /* ADC12 Busy */\r
+#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */\r
+#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */\r
+#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */\r
+#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */\r
+#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */\r
+#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */\r
+#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */\r
+#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */\r
+#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */\r
+#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */\r
+#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */\r
+#define ADC12SHS2 (0x1000) /* ADC12 Sample/Hold Source Bit: 2 */\r
+#define ADC12PDIV0 (0x2000) /* ADC12 Predivider Bit: 0 */\r
+#define ADC12PDIV1 (0x4000) /* ADC12 Predivider Bit: 1 */\r
+\r
+/* ADC12CTL1 Control Bits */\r
+#define ADC12BUSY_L (0x0001) /* ADC12 Busy */\r
+#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */\r
+#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */\r
+#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */\r
+#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */\r
+#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */\r
+#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */\r
+#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */\r
+\r
+/* ADC12CTL1 Control Bits */\r
+#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */\r
+#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */\r
+#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */\r
+#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */\r
+#define ADC12SHS2_H (0x0010) /* ADC12 Sample/Hold Source Bit: 2 */\r
+#define ADC12PDIV0_H (0x0020) /* ADC12 Predivider Bit: 0 */\r
+#define ADC12PDIV1_H (0x0040) /* ADC12 Predivider Bit: 1 */\r
+\r
+#define ADC12CONSEQ_0 (0*0x0002u) /* ADC12 Conversion Sequence Select: 0 */\r
+#define ADC12CONSEQ_1 (1*0x0002u) /* ADC12 Conversion Sequence Select: 1 */\r
+#define ADC12CONSEQ_2 (2*0x0002u) /* ADC12 Conversion Sequence Select: 2 */\r
+#define ADC12CONSEQ_3 (3*0x0002u) /* ADC12 Conversion Sequence Select: 3 */\r
+\r
+#define ADC12SSEL_0 (0*0x0008u) /* ADC12 Clock Source Select: 0 */\r
+#define ADC12SSEL_1 (1*0x0008u) /* ADC12 Clock Source Select: 1 */\r
+#define ADC12SSEL_2 (2*0x0008u) /* ADC12 Clock Source Select: 2 */\r
+#define ADC12SSEL_3 (3*0x0008u) /* ADC12 Clock Source Select: 3 */\r
+\r
+#define ADC12DIV_0 (0*0x0020u) /* ADC12 Clock Divider Select: 0 */\r
+#define ADC12DIV_1 (1*0x0020u) /* ADC12 Clock Divider Select: 1 */\r
+#define ADC12DIV_2 (2*0x0020u) /* ADC12 Clock Divider Select: 2 */\r
+#define ADC12DIV_3 (3*0x0020u) /* ADC12 Clock Divider Select: 3 */\r
+#define ADC12DIV_4 (4*0x0020u) /* ADC12 Clock Divider Select: 4 */\r
+#define ADC12DIV_5 (5*0x0020u) /* ADC12 Clock Divider Select: 5 */\r
+#define ADC12DIV_6 (6*0x0020u) /* ADC12 Clock Divider Select: 6 */\r
+#define ADC12DIV_7 (7*0x0020u) /* ADC12 Clock Divider Select: 7 */\r
+\r
+#define ADC12SHS_0 (0*0x0400u) /* ADC12 Sample/Hold Source: 0 */\r
+#define ADC12SHS_1 (1*0x0400u) /* ADC12 Sample/Hold Source: 1 */\r
+#define ADC12SHS_2 (2*0x0400u) /* ADC12 Sample/Hold Source: 2 */\r
+#define ADC12SHS_3 (3*0x0400u) /* ADC12 Sample/Hold Source: 3 */\r
+#define ADC12SHS_4 (4*0x0400u) /* ADC12 Sample/Hold Source: 4 */\r
+#define ADC12SHS_5 (5*0x0400u) /* ADC12 Sample/Hold Source: 5 */\r
+#define ADC12SHS_6 (6*0x0400u) /* ADC12 Sample/Hold Source: 6 */\r
+#define ADC12SHS_7 (7*0x0400u) /* ADC12 Sample/Hold Source: 7 */\r
+\r
+#define ADC12PDIV_0 (0*0x2000u) /* ADC12 Clock predivider Select 0 */\r
+#define ADC12PDIV_1 (1*0x2000u) /* ADC12 Clock predivider Select 1 */\r
+#define ADC12PDIV_2 (2*0x2000u) /* ADC12 Clock predivider Select 2 */\r
+#define ADC12PDIV_3 (3*0x2000u) /* ADC12 Clock predivider Select 3 */\r
+#define ADC12PDIV__1 (0*0x2000u) /* ADC12 Clock predivider Select: /1 */\r
+#define ADC12PDIV__4 (1*0x2000u) /* ADC12 Clock predivider Select: /4 */\r
+#define ADC12PDIV__32 (2*0x2000u) /* ADC12 Clock predivider Select: /32 */\r
+#define ADC12PDIV__64 (3*0x2000u) /* ADC12 Clock predivider Select: /64 */\r
+\r
+/* ADC12CTL2 Control Bits */\r
+#define ADC12PWRMD (0x0001) /* ADC12 Power Mode */\r
+#define ADC12DF (0x0008) /* ADC12 Data Format */\r
+#define ADC12RES0 (0x0010) /* ADC12 Resolution Bit: 0 */\r
+#define ADC12RES1 (0x0020) /* ADC12 Resolution Bit: 1 */\r
+\r
+/* ADC12CTL2 Control Bits */\r
+#define ADC12PWRMD_L (0x0001) /* ADC12 Power Mode */\r
+#define ADC12DF_L (0x0008) /* ADC12 Data Format */\r
+#define ADC12RES0_L (0x0010) /* ADC12 Resolution Bit: 0 */\r
+#define ADC12RES1_L (0x0020) /* ADC12 Resolution Bit: 1 */\r
+\r
+#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */\r
+#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */\r
+#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */\r
+#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */\r
+\r
+#define ADC12RES__8BIT (0x0000) /* ADC12+ Resolution : 8 Bit */\r
+#define ADC12RES__10BIT (0x0010) /* ADC12+ Resolution : 10 Bit */\r
+#define ADC12RES__12BIT (0x0020) /* ADC12+ Resolution : 12 Bit */\r
+\r
+/* ADC12CTL3 Control Bits */\r
+#define ADC12CSTARTADD0 (0x0001) /* ADC12 Conversion Start Address Bit: 0 */\r
+#define ADC12CSTARTADD1 (0x0002) /* ADC12 Conversion Start Address Bit: 1 */\r
+#define ADC12CSTARTADD2 (0x0004) /* ADC12 Conversion Start Address Bit: 2 */\r
+#define ADC12CSTARTADD3 (0x0008) /* ADC12 Conversion Start Address Bit: 3 */\r
+#define ADC12CSTARTADD4 (0x0010) /* ADC12 Conversion Start Address Bit: 4 */\r
+#define ADC12BATMAP (0x0040) /* ADC12 Internal AVCC/2 select */\r
+#define ADC12TCMAP (0x0080) /* ADC12 Internal TempSensor select */\r
+#define ADC12ICH0MAP (0x0100) /* ADC12 Internal Channel 0 select */\r
+#define ADC12ICH1MAP (0x0200) /* ADC12 Internal Channel 1 select */\r
+#define ADC12ICH2MAP (0x0400) /* ADC12 Internal Channel 2 select */\r
+#define ADC12ICH3MAP (0x0800) /* ADC12 Internal Channel 3 select */\r
+\r
+/* ADC12CTL3 Control Bits */\r
+#define ADC12CSTARTADD0_L (0x0001) /* ADC12 Conversion Start Address Bit: 0 */\r
+#define ADC12CSTARTADD1_L (0x0002) /* ADC12 Conversion Start Address Bit: 1 */\r
+#define ADC12CSTARTADD2_L (0x0004) /* ADC12 Conversion Start Address Bit: 2 */\r
+#define ADC12CSTARTADD3_L (0x0008) /* ADC12 Conversion Start Address Bit: 3 */\r
+#define ADC12CSTARTADD4_L (0x0010) /* ADC12 Conversion Start Address Bit: 4 */\r
+#define ADC12BATMAP_L (0x0040) /* ADC12 Internal AVCC/2 select */\r
+#define ADC12TCMAP_L (0x0080) /* ADC12 Internal TempSensor select */\r
+\r
+/* ADC12CTL3 Control Bits */\r
+#define ADC12ICH0MAP_H (0x0001) /* ADC12 Internal Channel 0 select */\r
+#define ADC12ICH1MAP_H (0x0002) /* ADC12 Internal Channel 1 select */\r
+#define ADC12ICH2MAP_H (0x0004) /* ADC12 Internal Channel 2 select */\r
+#define ADC12ICH3MAP_H (0x0008) /* ADC12 Internal Channel 3 select */\r
+\r
+#define ADC12CSTARTADD_0 ( 0*0x0001u) /* ADC12 Conversion Start Address: 0 */\r
+#define ADC12CSTARTADD_1 ( 1*0x0001u) /* ADC12 Conversion Start Address: 1 */\r
+#define ADC12CSTARTADD_2 ( 2*0x0001u) /* ADC12 Conversion Start Address: 2 */\r
+#define ADC12CSTARTADD_3 ( 3*0x0001u) /* ADC12 Conversion Start Address: 3 */\r
+#define ADC12CSTARTADD_4 ( 4*0x0001u) /* ADC12 Conversion Start Address: 4 */\r
+#define ADC12CSTARTADD_5 ( 5*0x0001u) /* ADC12 Conversion Start Address: 5 */\r
+#define ADC12CSTARTADD_6 ( 6*0x0001u) /* ADC12 Conversion Start Address: 6 */\r
+#define ADC12CSTARTADD_7 ( 7*0x0001u) /* ADC12 Conversion Start Address: 7 */\r
+#define ADC12CSTARTADD_8 ( 8*0x0001u) /* ADC12 Conversion Start Address: 8 */\r
+#define ADC12CSTARTADD_9 ( 9*0x0001u) /* ADC12 Conversion Start Address: 9 */\r
+#define ADC12CSTARTADD_10 (10*0x0001u) /* ADC12 Conversion Start Address: 10 */\r
+#define ADC12CSTARTADD_11 (11*0x0001u) /* ADC12 Conversion Start Address: 11 */\r
+#define ADC12CSTARTADD_12 (12*0x0001u) /* ADC12 Conversion Start Address: 12 */\r
+#define ADC12CSTARTADD_13 (13*0x0001u) /* ADC12 Conversion Start Address: 13 */\r
+#define ADC12CSTARTADD_14 (14*0x0001u) /* ADC12 Conversion Start Address: 14 */\r
+#define ADC12CSTARTADD_15 (15*0x0001u) /* ADC12 Conversion Start Address: 15 */\r
+#define ADC12CSTARTADD_16 (16*0x0001u) /* ADC12 Conversion Start Address: 16 */\r
+#define ADC12CSTARTADD_17 (17*0x0001u) /* ADC12 Conversion Start Address: 17 */\r
+#define ADC12CSTARTADD_18 (18*0x0001u) /* ADC12 Conversion Start Address: 18 */\r
+#define ADC12CSTARTADD_19 (19*0x0001u) /* ADC12 Conversion Start Address: 19 */\r
+#define ADC12CSTARTADD_20 (20*0x0001u) /* ADC12 Conversion Start Address: 20 */\r
+#define ADC12CSTARTADD_21 (21*0x0001u) /* ADC12 Conversion Start Address: 21 */\r
+#define ADC12CSTARTADD_22 (22*0x0001u) /* ADC12 Conversion Start Address: 22 */\r
+#define ADC12CSTARTADD_23 (23*0x0001u) /* ADC12 Conversion Start Address: 23 */\r
+#define ADC12CSTARTADD_24 (24*0x0001u) /* ADC12 Conversion Start Address: 24 */\r
+#define ADC12CSTARTADD_25 (25*0x0001u) /* ADC12 Conversion Start Address: 25 */\r
+#define ADC12CSTARTADD_26 (26*0x0001u) /* ADC12 Conversion Start Address: 26 */\r
+#define ADC12CSTARTADD_27 (27*0x0001u) /* ADC12 Conversion Start Address: 27 */\r
+#define ADC12CSTARTADD_28 (28*0x0001u) /* ADC12 Conversion Start Address: 28 */\r
+#define ADC12CSTARTADD_29 (29*0x0001u) /* ADC12 Conversion Start Address: 29 */\r
+#define ADC12CSTARTADD_30 (30*0x0001u) /* ADC12 Conversion Start Address: 30 */\r
+#define ADC12CSTARTADD_31 (31*0x0001u) /* ADC12 Conversion Start Address: 31 */\r
+\r
+/* ADC12MCTLx Control Bits */\r
+#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */\r
+#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */\r
+#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */\r
+#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */\r
+#define ADC12INCH4 (0x0010) /* ADC12 Input Channel Select Bit 4 */\r
+#define ADC12EOS (0x0080) /* ADC12 End of Sequence */\r
+#define ADC12VRSEL0 (0x0100) /* ADC12 VR Select Bit 0 */\r
+#define ADC12VRSEL1 (0x0200) /* ADC12 VR Select Bit 1 */\r
+#define ADC12VRSEL2 (0x0400) /* ADC12 VR Select Bit 2 */\r
+#define ADC12VRSEL3 (0x0800) /* ADC12 VR Select Bit 3 */\r
+#define ADC12DIF (0x2000) /* ADC12 Differential mode (only for even Registers) */\r
+#define ADC12WINC (0x4000) /* ADC12 Comparator window enable */\r
+\r
+/* ADC12MCTLx Control Bits */\r
+#define ADC12INCH0_L (0x0001) /* ADC12 Input Channel Select Bit 0 */\r
+#define ADC12INCH1_L (0x0002) /* ADC12 Input Channel Select Bit 1 */\r
+#define ADC12INCH2_L (0x0004) /* ADC12 Input Channel Select Bit 2 */\r
+#define ADC12INCH3_L (0x0008) /* ADC12 Input Channel Select Bit 3 */\r
+#define ADC12INCH4_L (0x0010) /* ADC12 Input Channel Select Bit 4 */\r
+#define ADC12EOS_L (0x0080) /* ADC12 End of Sequence */\r
+\r
+/* ADC12MCTLx Control Bits */\r
+#define ADC12VRSEL0_H (0x0001) /* ADC12 VR Select Bit 0 */\r
+#define ADC12VRSEL1_H (0x0002) /* ADC12 VR Select Bit 1 */\r
+#define ADC12VRSEL2_H (0x0004) /* ADC12 VR Select Bit 2 */\r
+#define ADC12VRSEL3_H (0x0008) /* ADC12 VR Select Bit 3 */\r
+#define ADC12DIF_H (0x0020) /* ADC12 Differential mode (only for even Registers) */\r
+#define ADC12WINC_H (0x0040) /* ADC12 Comparator window enable */\r
+\r
+#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */\r
+#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */\r
+#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */\r
+#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */\r
+#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */\r
+#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */\r
+#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */\r
+#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */\r
+#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */\r
+#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */\r
+#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */\r
+#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */\r
+#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */\r
+#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */\r
+#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */\r
+#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */\r
+#define ADC12INCH_16 (0x0010) /* ADC12 Input Channel 16 */\r
+#define ADC12INCH_17 (0x0011) /* ADC12 Input Channel 17 */\r
+#define ADC12INCH_18 (0x0012) /* ADC12 Input Channel 18 */\r
+#define ADC12INCH_19 (0x0013) /* ADC12 Input Channel 19 */\r
+#define ADC12INCH_20 (0x0014) /* ADC12 Input Channel 20 */\r
+#define ADC12INCH_21 (0x0015) /* ADC12 Input Channel 21 */\r
+#define ADC12INCH_22 (0x0016) /* ADC12 Input Channel 22 */\r
+#define ADC12INCH_23 (0x0017) /* ADC12 Input Channel 23 */\r
+#define ADC12INCH_24 (0x0018) /* ADC12 Input Channel 24 */\r
+#define ADC12INCH_25 (0x0019) /* ADC12 Input Channel 25 */\r
+#define ADC12INCH_26 (0x001A) /* ADC12 Input Channel 26 */\r
+#define ADC12INCH_27 (0x001B) /* ADC12 Input Channel 27 */\r
+#define ADC12INCH_28 (0x001C) /* ADC12 Input Channel 28 */\r
+#define ADC12INCH_29 (0x001D) /* ADC12 Input Channel 29 */\r
+#define ADC12INCH_30 (0x001E) /* ADC12 Input Channel 30 */\r
+#define ADC12INCH_31 (0x001F) /* ADC12 Input Channel 31 */\r
+\r
+#define ADC12VRSEL_0 (0*0x100u) /* ADC12 Select Reference 0 */\r
+#define ADC12VRSEL_1 (1*0x100u) /* ADC12 Select Reference 1 */\r
+#define ADC12VRSEL_2 (2*0x100u) /* ADC12 Select Reference 2 */\r
+#define ADC12VRSEL_3 (3*0x100u) /* ADC12 Select Reference 3 */\r
+#define ADC12VRSEL_4 (4*0x100u) /* ADC12 Select Reference 4 */\r
+#define ADC12VRSEL_5 (5*0x100u) /* ADC12 Select Reference 5 */\r
+#define ADC12VRSEL_6 (6*0x100u) /* ADC12 Select Reference 6 */\r
+#define ADC12VRSEL_7 (7*0x100u) /* ADC12 Select Reference 7 */\r
+#define ADC12VRSEL_8 (8*0x100u) /* ADC12 Select Reference 8 */\r
+#define ADC12VRSEL_9 (9*0x100u) /* ADC12 Select Reference 9 */\r
+#define ADC12VRSEL_10 (10*0x100u) /* ADC12 Select Reference 10 */\r
+#define ADC12VRSEL_11 (11*0x100u) /* ADC12 Select Reference 11 */\r
+#define ADC12VRSEL_12 (12*0x100u) /* ADC12 Select Reference 12 */\r
+#define ADC12VRSEL_13 (13*0x100u) /* ADC12 Select Reference 13 */\r
+#define ADC12VRSEL_14 (14*0x100u) /* ADC12 Select Reference 14 */\r
+#define ADC12VRSEL_15 (15*0x100u) /* ADC12 Select Reference 15 */\r
+\r
+/* ADC12HI Control Bits */\r
+\r
+/* ADC12LO Control Bits */\r
+\r
+/* ADC12IER0 Control Bits */\r
+#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */\r
+#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */\r
+#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */\r
+#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */\r
+#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */\r
+#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */\r
+#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */\r
+#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */\r
+#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */\r
+#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */\r
+#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */\r
+#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */\r
+#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */\r
+#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */\r
+#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */\r
+#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */\r
+\r
+/* ADC12IER0 Control Bits */\r
+#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */\r
+#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */\r
+#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */\r
+#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */\r
+#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */\r
+#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */\r
+#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */\r
+#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */\r
+\r
+/* ADC12IER0 Control Bits */\r
+#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */\r
+#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */\r
+#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */\r
+#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */\r
+#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */\r
+#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */\r
+#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */\r
+#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */\r
+\r
+/* ADC12IER1 Control Bits */\r
+#define ADC12IE16 (0x0001) /* ADC12 Memory 16 Interrupt Enable */\r
+#define ADC12IE17 (0x0002) /* ADC12 Memory 17 Interrupt Enable */\r
+#define ADC12IE18 (0x0004) /* ADC12 Memory 18 Interrupt Enable */\r
+#define ADC12IE19 (0x0008) /* ADC12 Memory 19 Interrupt Enable */\r
+#define ADC12IE20 (0x0010) /* ADC12 Memory 20 Interrupt Enable */\r
+#define ADC12IE21 (0x0020) /* ADC12 Memory 21 Interrupt Enable */\r
+#define ADC12IE22 (0x0040) /* ADC12 Memory 22 Interrupt Enable */\r
+#define ADC12IE23 (0x0080) /* ADC12 Memory 23 Interrupt Enable */\r
+#define ADC12IE24 (0x0100) /* ADC12 Memory 24 Interrupt Enable */\r
+#define ADC12IE25 (0x0200) /* ADC12 Memory 25 Interrupt Enable */\r
+#define ADC12IE26 (0x0400) /* ADC12 Memory 26 Interrupt Enable */\r
+#define ADC12IE27 (0x0800) /* ADC12 Memory 27 Interrupt Enable */\r
+#define ADC12IE28 (0x1000) /* ADC12 Memory 28 Interrupt Enable */\r
+#define ADC12IE29 (0x2000) /* ADC12 Memory 29 Interrupt Enable */\r
+#define ADC12IE30 (0x4000) /* ADC12 Memory 30 Interrupt Enable */\r
+#define ADC12IE31 (0x8000) /* ADC12 Memory 31 Interrupt Enable */\r
+\r
+/* ADC12IER1 Control Bits */\r
+#define ADC12IE16_L (0x0001) /* ADC12 Memory 16 Interrupt Enable */\r
+#define ADC12IE17_L (0x0002) /* ADC12 Memory 17 Interrupt Enable */\r
+#define ADC12IE18_L (0x0004) /* ADC12 Memory 18 Interrupt Enable */\r
+#define ADC12IE19_L (0x0008) /* ADC12 Memory 19 Interrupt Enable */\r
+#define ADC12IE20_L (0x0010) /* ADC12 Memory 20 Interrupt Enable */\r
+#define ADC12IE21_L (0x0020) /* ADC12 Memory 21 Interrupt Enable */\r
+#define ADC12IE22_L (0x0040) /* ADC12 Memory 22 Interrupt Enable */\r
+#define ADC12IE23_L (0x0080) /* ADC12 Memory 23 Interrupt Enable */\r
+\r
+/* ADC12IER1 Control Bits */\r
+#define ADC12IE24_H (0x0001) /* ADC12 Memory 24 Interrupt Enable */\r
+#define ADC12IE25_H (0x0002) /* ADC12 Memory 25 Interrupt Enable */\r
+#define ADC12IE26_H (0x0004) /* ADC12 Memory 26 Interrupt Enable */\r
+#define ADC12IE27_H (0x0008) /* ADC12 Memory 27 Interrupt Enable */\r
+#define ADC12IE28_H (0x0010) /* ADC12 Memory 28 Interrupt Enable */\r
+#define ADC12IE29_H (0x0020) /* ADC12 Memory 29 Interrupt Enable */\r
+#define ADC12IE30_H (0x0040) /* ADC12 Memory 30 Interrupt Enable */\r
+#define ADC12IE31_H (0x0080) /* ADC12 Memory 31 Interrupt Enable */\r
+\r
+/* ADC12IER2 Control Bits */\r
+#define ADC12INIE (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */\r
+#define ADC12LOIE (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */\r
+#define ADC12HIIE (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */\r
+#define ADC12OVIE (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */\r
+#define ADC12TOVIE (0x0020) /* ADC12 Timer Overflow interrupt enable */\r
+#define ADC12RDYIE (0x0040) /* ADC12 local buffered reference ready interrupt enable */\r
+\r
+/* ADC12IER2 Control Bits */\r
+#define ADC12INIE_L (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */\r
+#define ADC12LOIE_L (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */\r
+#define ADC12HIIE_L (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */\r
+#define ADC12OVIE_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */\r
+#define ADC12TOVIE_L (0x0020) /* ADC12 Timer Overflow interrupt enable */\r
+#define ADC12RDYIE_L (0x0040) /* ADC12 local buffered reference ready interrupt enable */\r
+\r
+/* ADC12IFGR0 Control Bits */\r
+#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */\r
+#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */\r
+#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */\r
+#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */\r
+#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */\r
+#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */\r
+#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */\r
+#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */\r
+#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */\r
+#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */\r
+#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */\r
+#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */\r
+#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */\r
+#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */\r
+#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */\r
+#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */\r
+\r
+/* ADC12IFGR0 Control Bits */\r
+#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */\r
+#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */\r
+#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */\r
+#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */\r
+#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */\r
+#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */\r
+#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */\r
+#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */\r
+\r
+/* ADC12IFGR0 Control Bits */\r
+#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */\r
+#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */\r
+#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */\r
+#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */\r
+#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */\r
+#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */\r
+#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */\r
+#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */\r
+\r
+/* ADC12IFGR1 Control Bits */\r
+#define ADC12IFG16 (0x0001) /* ADC12 Memory 16 Interrupt Flag */\r
+#define ADC12IFG17 (0x0002) /* ADC12 Memory 17 Interrupt Flag */\r
+#define ADC12IFG18 (0x0004) /* ADC12 Memory 18 Interrupt Flag */\r
+#define ADC12IFG19 (0x0008) /* ADC12 Memory 19 Interrupt Flag */\r
+#define ADC12IFG20 (0x0010) /* ADC12 Memory 20 Interrupt Flag */\r
+#define ADC12IFG21 (0x0020) /* ADC12 Memory 21 Interrupt Flag */\r
+#define ADC12IFG22 (0x0040) /* ADC12 Memory 22 Interrupt Flag */\r
+#define ADC12IFG23 (0x0080) /* ADC12 Memory 23 Interrupt Flag */\r
+#define ADC12IFG24 (0x0100) /* ADC12 Memory 24 Interrupt Flag */\r
+#define ADC12IFG25 (0x0200) /* ADC12 Memory 25 Interrupt Flag */\r
+#define ADC12IFG26 (0x0400) /* ADC12 Memory 26 Interrupt Flag */\r
+#define ADC12IFG27 (0x0800) /* ADC12 Memory 27 Interrupt Flag */\r
+#define ADC12IFG28 (0x1000) /* ADC12 Memory 28 Interrupt Flag */\r
+#define ADC12IFG29 (0x2000) /* ADC12 Memory 29 Interrupt Flag */\r
+#define ADC12IFG30 (0x4000) /* ADC12 Memory 30 Interrupt Flag */\r
+#define ADC12IFG31 (0x8000) /* ADC12 Memory 31 Interrupt Flag */\r
+\r
+/* ADC12IFGR1 Control Bits */\r
+#define ADC12IFG16_L (0x0001) /* ADC12 Memory 16 Interrupt Flag */\r
+#define ADC12IFG17_L (0x0002) /* ADC12 Memory 17 Interrupt Flag */\r
+#define ADC12IFG18_L (0x0004) /* ADC12 Memory 18 Interrupt Flag */\r
+#define ADC12IFG19_L (0x0008) /* ADC12 Memory 19 Interrupt Flag */\r
+#define ADC12IFG20_L (0x0010) /* ADC12 Memory 20 Interrupt Flag */\r
+#define ADC12IFG21_L (0x0020) /* ADC12 Memory 21 Interrupt Flag */\r
+#define ADC12IFG22_L (0x0040) /* ADC12 Memory 22 Interrupt Flag */\r
+#define ADC12IFG23_L (0x0080) /* ADC12 Memory 23 Interrupt Flag */\r
+\r
+/* ADC12IFGR1 Control Bits */\r
+#define ADC12IFG24_H (0x0001) /* ADC12 Memory 24 Interrupt Flag */\r
+#define ADC12IFG25_H (0x0002) /* ADC12 Memory 25 Interrupt Flag */\r
+#define ADC12IFG26_H (0x0004) /* ADC12 Memory 26 Interrupt Flag */\r
+#define ADC12IFG27_H (0x0008) /* ADC12 Memory 27 Interrupt Flag */\r
+#define ADC12IFG28_H (0x0010) /* ADC12 Memory 28 Interrupt Flag */\r
+#define ADC12IFG29_H (0x0020) /* ADC12 Memory 29 Interrupt Flag */\r
+#define ADC12IFG30_H (0x0040) /* ADC12 Memory 30 Interrupt Flag */\r
+#define ADC12IFG31_H (0x0080) /* ADC12 Memory 31 Interrupt Flag */\r
+\r
+/* ADC12IFGR2 Control Bits */\r
+#define ADC12INIFG (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */\r
+#define ADC12LOIFG (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */\r
+#define ADC12HIIFG (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */\r
+#define ADC12OVIFG (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */\r
+#define ADC12TOVIFG (0x0020) /* ADC12 Timer Overflow interrupt Flag */\r
+#define ADC12RDYIFG (0x0040) /* ADC12 local buffered reference ready interrupt Flag */\r
+\r
+/* ADC12IFGR2 Control Bits */\r
+#define ADC12INIFG_L (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */\r
+#define ADC12LOIFG_L (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */\r
+#define ADC12HIIFG_L (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */\r
+#define ADC12OVIFG_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */\r
+#define ADC12TOVIFG_L (0x0020) /* ADC12 Timer Overflow interrupt Flag */\r
+#define ADC12RDYIFG_L (0x0040) /* ADC12 local buffered reference ready interrupt Flag */\r
+\r
+/* ADC12IV Definitions */\r
+#define ADC12IV_NONE (0x0000) /* No Interrupt pending */\r
+#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */\r
+#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */\r
+#define ADC12IV_ADC12HIIFG (0x0006) /* ADC12HIIFG */\r
+#define ADC12IV_ADC12LOIFG (0x0008) /* ADC12LOIFG */\r
+#define ADC12IV_ADC12INIFG (0x000A) /* ADC12INIFG */\r
+#define ADC12IV_ADC12IFG0 (0x000C) /* ADC12IFG0 */\r
+#define ADC12IV_ADC12IFG1 (0x000E) /* ADC12IFG1 */\r
+#define ADC12IV_ADC12IFG2 (0x0010) /* ADC12IFG2 */\r
+#define ADC12IV_ADC12IFG3 (0x0012) /* ADC12IFG3 */\r
+#define ADC12IV_ADC12IFG4 (0x0014) /* ADC12IFG4 */\r
+#define ADC12IV_ADC12IFG5 (0x0016) /* ADC12IFG5 */\r
+#define ADC12IV_ADC12IFG6 (0x0018) /* ADC12IFG6 */\r
+#define ADC12IV_ADC12IFG7 (0x001A) /* ADC12IFG7 */\r
+#define ADC12IV_ADC12IFG8 (0x001C) /* ADC12IFG8 */\r
+#define ADC12IV_ADC12IFG9 (0x001E) /* ADC12IFG9 */\r
+#define ADC12IV_ADC12IFG10 (0x0020) /* ADC12IFG10 */\r
+#define ADC12IV_ADC12IFG11 (0x0022) /* ADC12IFG11 */\r
+#define ADC12IV_ADC12IFG12 (0x0024) /* ADC12IFG12 */\r
+#define ADC12IV_ADC12IFG13 (0x0026) /* ADC12IFG13 */\r
+#define ADC12IV_ADC12IFG14 (0x0028) /* ADC12IFG14 */\r
+#define ADC12IV_ADC12IFG15 (0x002A) /* ADC12IFG15 */\r
+#define ADC12IV_ADC12IFG16 (0x002C) /* ADC12IFG16 */\r
+#define ADC12IV_ADC12IFG17 (0x002E) /* ADC12IFG17 */\r
+#define ADC12IV_ADC12IFG18 (0x0030) /* ADC12IFG18 */\r
+#define ADC12IV_ADC12IFG19 (0x0032) /* ADC12IFG19 */\r
+#define ADC12IV_ADC12IFG20 (0x0034) /* ADC12IFG20 */\r
+#define ADC12IV_ADC12IFG21 (0x0036) /* ADC12IFG21 */\r
+#define ADC12IV_ADC12IFG22 (0x0038) /* ADC12IFG22 */\r
+#define ADC12IV_ADC12IFG23 (0x003A) /* ADC12IFG23 */\r
+#define ADC12IV_ADC12IFG24 (0x003C) /* ADC12IFG24 */\r
+#define ADC12IV_ADC12IFG25 (0x003E) /* ADC12IFG25 */\r
+#define ADC12IV_ADC12IFG26 (0x0040) /* ADC12IFG26 */\r
+#define ADC12IV_ADC12IFG27 (0x0042) /* ADC12IFG27 */\r
+#define ADC12IV_ADC12IFG28 (0x0044) /* ADC12IFG28 */\r
+#define ADC12IV_ADC12IFG29 (0x0046) /* ADC12IFG29 */\r
+#define ADC12IV_ADC12IFG30 (0x0048) /* ADC12IFG30 */\r
+#define ADC12IV_ADC12IFG31 (0x004A) /* ADC12IFG31 */\r
+#define ADC12IV_ADC12RDYIFG (0x004C) /* ADC12RDYIFG */\r
+\r
+\r
+#endif\r
+/************************************************************\r
+* AES256 Accelerator\r
+************************************************************/\r
+#ifdef __MSP430_HAS_AES256__ /* Definition to show that Module is available */\r
+\r
+#define OFS_AESACTL0 (0x0000) /* AES accelerator control register 0 */\r
+#define OFS_AESACTL0_L OFS_AESACTL0\r
+#define OFS_AESACTL0_H OFS_AESACTL0+1\r
+#define OFS_AESACTL1 (0x0002) /* AES accelerator control register 1 */\r
+#define OFS_AESACTL1_L OFS_AESACTL1\r
+#define OFS_AESACTL1_H OFS_AESACTL1+1\r
+#define OFS_AESASTAT (0x0004) /* AES accelerator status register */\r
+#define OFS_AESASTAT_L OFS_AESASTAT\r
+#define OFS_AESASTAT_H OFS_AESASTAT+1\r
+#define OFS_AESAKEY (0x0006) /* AES accelerator key register */\r
+#define OFS_AESAKEY_L OFS_AESAKEY\r
+#define OFS_AESAKEY_H OFS_AESAKEY+1\r
+#define OFS_AESADIN (0x0008) /* AES accelerator data in register */\r
+#define OFS_AESADIN_L OFS_AESADIN\r
+#define OFS_AESADIN_H OFS_AESADIN+1\r
+#define OFS_AESADOUT (0x000A) /* AES accelerator data out register */\r
+#define OFS_AESADOUT_L OFS_AESADOUT\r
+#define OFS_AESADOUT_H OFS_AESADOUT+1\r
+#define OFS_AESAXDIN (0x000C) /* AES accelerator XORed data in register */\r
+#define OFS_AESAXDIN_L OFS_AESAXDIN\r
+#define OFS_AESAXDIN_H OFS_AESAXDIN+1\r
+#define OFS_AESAXIN (0x000E) /* AES accelerator XORed data in register (no trigger) */\r
+#define OFS_AESAXIN_L OFS_AESAXIN\r
+#define OFS_AESAXIN_H OFS_AESAXIN+1\r
+\r
+/* AESACTL0 Control Bits */\r
+#define AESOP0 (0x0001) /* AES Operation Bit: 0 */\r
+#define AESOP1 (0x0002) /* AES Operation Bit: 1 */\r
+#define AESKL0 (0x0004) /* AES Key length Bit: 0 */\r
+#define AESKL1 (0x0008) /* AES Key length Bit: 1 */\r
+#define AESTRIG (0x0010) /* AES Trigger Select */\r
+#define AESCM0 (0x0020) /* AES Cipher mode select Bit: 0 */\r
+#define AESCM1 (0x0040) /* AES Cipher mode select Bit: 1 */\r
+#define AESSWRST (0x0080) /* AES Software Reset */\r
+#define AESRDYIFG (0x0100) /* AES ready interrupt flag */\r
+#define AESERRFG (0x0800) /* AES Error Flag */\r
+#define AESRDYIE (0x1000) /* AES ready interrupt enable*/\r
+#define AESCMEN (0x8000) /* AES DMA cipher mode enable*/\r
+\r
+/* AESACTL0 Control Bits */\r
+#define AESOP0_L (0x0001) /* AES Operation Bit: 0 */\r
+#define AESOP1_L (0x0002) /* AES Operation Bit: 1 */\r
+#define AESKL0_L (0x0004) /* AES Key length Bit: 0 */\r
+#define AESKL1_L (0x0008) /* AES Key length Bit: 1 */\r
+#define AESTRIG_L (0x0010) /* AES Trigger Select */\r
+#define AESCM0_L (0x0020) /* AES Cipher mode select Bit: 0 */\r
+#define AESCM1_L (0x0040) /* AES Cipher mode select Bit: 1 */\r
+#define AESSWRST_L (0x0080) /* AES Software Reset */\r
+\r
+/* AESACTL0 Control Bits */\r
+#define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */\r
+#define AESERRFG_H (0x0008) /* AES Error Flag */\r
+#define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/\r
+#define AESCMEN_H (0x0080) /* AES DMA cipher mode enable*/\r
+\r
+#define AESOP_0 (0x0000) /* AES Operation: Encrypt */\r
+#define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */\r
+#define AESOP_2 (0x0002) /* AES Operation: Decrypt (frist round Key) */\r
+#define AESOP_3 (0x0003) /* AES Operation: Generate first round Key */\r
+\r
+#define AESKL_0 (0x0000) /* AES Key length: AES128 */\r
+#define AESKL_1 (0x0004) /* AES Key length: AES192 */\r
+#define AESKL_2 (0x0008) /* AES Key length: AES256 */\r
+#define AESKL__128 (0x0000) /* AES Key length: AES128 */\r
+#define AESKL__192 (0x0004) /* AES Key length: AES192 */\r
+#define AESKL__256 (0x0008) /* AES Key length: AES256 */\r
+\r
+#define AESCM_0 (0x0000) /* AES Cipher mode select: ECB */\r
+#define AESCM_1 (0x0020) /* AES Cipher mode select: CBC */\r
+#define AESCM_2 (0x0040) /* AES Cipher mode select: OFB */\r
+#define AESCM_3 (0x0060) /* AES Cipher mode select: CFB */\r
+#define AESCM__ECB (0x0000) /* AES Cipher mode select: ECB */\r
+#define AESCM__CBC (0x0020) /* AES Cipher mode select: CBC */\r
+#define AESCM__OFB (0x0040) /* AES Cipher mode select: OFB */\r
+#define AESCM__CFB (0x0060) /* AES Cipher mode select: CFB */\r
+\r
+/* AESACTL1 Control Bits */\r
+#define AESBLKCNT0 (0x0001) /* AES Cipher Block Counter Bit: 0 */\r
+#define AESBLKCNT1 (0x0002) /* AES Cipher Block Counter Bit: 1 */\r
+#define AESBLKCNT2 (0x0004) /* AES Cipher Block Counter Bit: 2 */\r
+#define AESBLKCNT3 (0x0008) /* AES Cipher Block Counter Bit: 3 */\r
+#define AESBLKCNT4 (0x0010) /* AES Cipher Block Counter Bit: 4 */\r
+#define AESBLKCNT5 (0x0020) /* AES Cipher Block Counter Bit: 5 */\r
+#define AESBLKCNT6 (0x0040) /* AES Cipher Block Counter Bit: 6 */\r
+#define AESBLKCNT7 (0x0080) /* AES Cipher Block Counter Bit: 7 */\r
+\r
+/* AESACTL1 Control Bits */\r
+#define AESBLKCNT0_L (0x0001) /* AES Cipher Block Counter Bit: 0 */\r
+#define AESBLKCNT1_L (0x0002) /* AES Cipher Block Counter Bit: 1 */\r
+#define AESBLKCNT2_L (0x0004) /* AES Cipher Block Counter Bit: 2 */\r
+#define AESBLKCNT3_L (0x0008) /* AES Cipher Block Counter Bit: 3 */\r
+#define AESBLKCNT4_L (0x0010) /* AES Cipher Block Counter Bit: 4 */\r
+#define AESBLKCNT5_L (0x0020) /* AES Cipher Block Counter Bit: 5 */\r
+#define AESBLKCNT6_L (0x0040) /* AES Cipher Block Counter Bit: 6 */\r
+#define AESBLKCNT7_L (0x0080) /* AES Cipher Block Counter Bit: 7 */\r
+\r
+/* AESASTAT Control Bits */\r
+#define AESBUSY (0x0001) /* AES Busy */\r
+#define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */\r
+#define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */\r
+#define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */\r
+#define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */\r
+#define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */\r
+#define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */\r
+#define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */\r
+#define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */\r
+#define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */\r
+#define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */\r
+#define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */\r
+#define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */\r
+#define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */\r
+#define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */\r
+#define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */\r
+\r
+/* AESASTAT Control Bits */\r
+#define AESBUSY_L (0x0001) /* AES Busy */\r
+#define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */\r
+#define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */\r
+#define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */\r
+#define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */\r
+#define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */\r
+#define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */\r
+#define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */\r
+\r
+/* AESASTAT Control Bits */\r
+#define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */\r
+#define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */\r
+#define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */\r
+#define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */\r
+#define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */\r
+#define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */\r
+#define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */\r
+#define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */\r
+\r
+#endif\r
+/************************************************************\r
+* Capacitive_Touch_IO 0\r
+************************************************************/\r
+#ifdef __MSP430_HAS_CAP_TOUCH_IO_0__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CAPTIO0CTL (0x000E) /* Capacitive_Touch_IO 0 control register */\r
+#define OFS_CAPTIO0CTL_L OFS_CAPTIO0CTL\r
+#define OFS_CAPTIO0CTL_H OFS_CAPTIO0CTL+1\r
+\r
+#define CAPSIO0CTL CAPTIO0CTL /* legacy define */\r
+\r
+/* CAPTIOxCTL Control Bits */\r
+#define CAPTIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */\r
+#define CAPTIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */\r
+#define CAPTIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */\r
+#define CAPTIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */\r
+#define CAPTIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */\r
+#define CAPTIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */\r
+#define CAPTIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */\r
+#define CAPTIOEN (0x0100) /* CapTouchIO Enable */\r
+#define CAPTIO (0x0200) /* CapTouchIO state */\r
+\r
+/* CAPTIOxCTL Control Bits */\r
+#define CAPTIOPISEL0_L (0x0002) /* CapTouchIO Pin Select Bit: 0 */\r
+#define CAPTIOPISEL1_L (0x0004) /* CapTouchIO Pin Select Bit: 1 */\r
+#define CAPTIOPISEL2_L (0x0008) /* CapTouchIO Pin Select Bit: 2 */\r
+#define CAPTIOPOSEL0_L (0x0010) /* CapTouchIO Port Select Bit: 0 */\r
+#define CAPTIOPOSEL1_L (0x0020) /* CapTouchIO Port Select Bit: 1 */\r
+#define CAPTIOPOSEL2_L (0x0040) /* CapTouchIO Port Select Bit: 2 */\r
+#define CAPTIOPOSEL3_L (0x0080) /* CapTouchIO Port Select Bit: 3 */\r
+\r
+/* CAPTIOxCTL Control Bits */\r
+#define CAPTIOEN_H (0x0001) /* CapTouchIO Enable */\r
+#define CAPTIO_H (0x0002) /* CapTouchIO state */\r
+\r
+/* Legacy defines */\r
+#define CAPSIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */\r
+#define CAPSIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */\r
+#define CAPSIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */\r
+#define CAPSIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */\r
+#define CAPSIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */\r
+#define CAPSIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */\r
+#define CAPSIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */\r
+#define CAPSIOEN (0x0100) /* CapTouchIO Enable */\r
+#define CAPSIO (0x0200) /* CapTouchIO state */\r
+\r
+#endif\r
+/************************************************************\r
+* Capacitive_Touch_IO 1\r
+************************************************************/\r
+#ifdef __MSP430_HAS_CAP_TOUCH_IO_1__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CAPTIO1CTL (0x000E) /* Capacitive_Touch_IO 1 control register */\r
+#define OFS_CAPTIO1CTL_L OFS_CAPTIO1CTL\r
+#define OFS_CAPTIO1CTL_H OFS_CAPTIO1CTL+1\r
+\r
+#define CAPSIO1CTL CAPTIO1CTL /* legacy define */\r
+\r
+#endif\r
+/************************************************************\r
+* Comparator E\r
+************************************************************/\r
+#ifdef __MSP430_HAS_COMP_E__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CECTL0 (0x0000) /* Comparator E Control Register 0 */\r
+#define OFS_CECTL0_L OFS_CECTL0\r
+#define OFS_CECTL0_H OFS_CECTL0+1\r
+#define OFS_CECTL1 (0x0002) /* Comparator E Control Register 1 */\r
+#define OFS_CECTL1_L OFS_CECTL1\r
+#define OFS_CECTL1_H OFS_CECTL1+1\r
+#define OFS_CECTL2 (0x0004) /* Comparator E Control Register 2 */\r
+#define OFS_CECTL2_L OFS_CECTL2\r
+#define OFS_CECTL2_H OFS_CECTL2+1\r
+#define OFS_CECTL3 (0x0006) /* Comparator E Control Register 3 */\r
+#define OFS_CECTL3_L OFS_CECTL3\r
+#define OFS_CECTL3_H OFS_CECTL3+1\r
+#define OFS_CEINT (0x000C) /* Comparator E Interrupt Register */\r
+#define OFS_CEINT_L OFS_CEINT\r
+#define OFS_CEINT_H OFS_CEINT+1\r
+#define OFS_CEIV (0x000E) /* Comparator E Interrupt Vector Word */\r
+#define OFS_CEIV_L OFS_CEIV\r
+#define OFS_CEIV_H OFS_CEIV+1\r
+\r
+/* CECTL0 Control Bits */\r
+#define CEIPSEL0 (0x0001) /* Comp. E Pos. Channel Input Select 0 */\r
+#define CEIPSEL1 (0x0002) /* Comp. E Pos. Channel Input Select 1 */\r
+#define CEIPSEL2 (0x0004) /* Comp. E Pos. Channel Input Select 2 */\r
+#define CEIPSEL3 (0x0008) /* Comp. E Pos. Channel Input Select 3 */\r
+//#define RESERVED (0x0010) /* Comp. E */\r
+//#define RESERVED (0x0020) /* Comp. E */\r
+//#define RESERVED (0x0040) /* Comp. E */\r
+#define CEIPEN (0x0080) /* Comp. E Pos. Channel Input Enable */\r
+#define CEIMSEL0 (0x0100) /* Comp. E Neg. Channel Input Select 0 */\r
+#define CEIMSEL1 (0x0200) /* Comp. E Neg. Channel Input Select 1 */\r
+#define CEIMSEL2 (0x0400) /* Comp. E Neg. Channel Input Select 2 */\r
+#define CEIMSEL3 (0x0800) /* Comp. E Neg. Channel Input Select 3 */\r
+//#define RESERVED (0x1000) /* Comp. E */\r
+//#define RESERVED (0x2000) /* Comp. E */\r
+//#define RESERVED (0x4000) /* Comp. E */\r
+#define CEIMEN (0x8000) /* Comp. E Neg. Channel Input Enable */\r
+\r
+/* CECTL0 Control Bits */\r
+#define CEIPSEL0_L (0x0001) /* Comp. E Pos. Channel Input Select 0 */\r
+#define CEIPSEL1_L (0x0002) /* Comp. E Pos. Channel Input Select 1 */\r
+#define CEIPSEL2_L (0x0004) /* Comp. E Pos. Channel Input Select 2 */\r
+#define CEIPSEL3_L (0x0008) /* Comp. E Pos. Channel Input Select 3 */\r
+//#define RESERVED (0x0010) /* Comp. E */\r
+//#define RESERVED (0x0020) /* Comp. E */\r
+//#define RESERVED (0x0040) /* Comp. E */\r
+#define CEIPEN_L (0x0080) /* Comp. E Pos. Channel Input Enable */\r
+//#define RESERVED (0x1000) /* Comp. E */\r
+//#define RESERVED (0x2000) /* Comp. E */\r
+//#define RESERVED (0x4000) /* Comp. E */\r
+\r
+/* CECTL0 Control Bits */\r
+//#define RESERVED (0x0010) /* Comp. E */\r
+//#define RESERVED (0x0020) /* Comp. E */\r
+//#define RESERVED (0x0040) /* Comp. E */\r
+#define CEIMSEL0_H (0x0001) /* Comp. E Neg. Channel Input Select 0 */\r
+#define CEIMSEL1_H (0x0002) /* Comp. E Neg. Channel Input Select 1 */\r
+#define CEIMSEL2_H (0x0004) /* Comp. E Neg. Channel Input Select 2 */\r
+#define CEIMSEL3_H (0x0008) /* Comp. E Neg. Channel Input Select 3 */\r
+//#define RESERVED (0x1000) /* Comp. E */\r
+//#define RESERVED (0x2000) /* Comp. E */\r
+//#define RESERVED (0x4000) /* Comp. E */\r
+#define CEIMEN_H (0x0080) /* Comp. E Neg. Channel Input Enable */\r
+\r
+#define CEIPSEL_0 (0x0000) /* Comp. E V+ terminal Input Select: Channel 0 */\r
+#define CEIPSEL_1 (0x0001) /* Comp. E V+ terminal Input Select: Channel 1 */\r
+#define CEIPSEL_2 (0x0002) /* Comp. E V+ terminal Input Select: Channel 2 */\r
+#define CEIPSEL_3 (0x0003) /* Comp. E V+ terminal Input Select: Channel 3 */\r
+#define CEIPSEL_4 (0x0004) /* Comp. E V+ terminal Input Select: Channel 4 */\r
+#define CEIPSEL_5 (0x0005) /* Comp. E V+ terminal Input Select: Channel 5 */\r
+#define CEIPSEL_6 (0x0006) /* Comp. E V+ terminal Input Select: Channel 6 */\r
+#define CEIPSEL_7 (0x0007) /* Comp. E V+ terminal Input Select: Channel 7 */\r
+#define CEIPSEL_8 (0x0008) /* Comp. E V+ terminal Input Select: Channel 8 */\r
+#define CEIPSEL_9 (0x0009) /* Comp. E V+ terminal Input Select: Channel 9 */\r
+#define CEIPSEL_10 (0x000A) /* Comp. E V+ terminal Input Select: Channel 10 */\r
+#define CEIPSEL_11 (0x000B) /* Comp. E V+ terminal Input Select: Channel 11 */\r
+#define CEIPSEL_12 (0x000C) /* Comp. E V+ terminal Input Select: Channel 12 */\r
+#define CEIPSEL_13 (0x000D) /* Comp. E V+ terminal Input Select: Channel 13 */\r
+#define CEIPSEL_14 (0x000E) /* Comp. E V+ terminal Input Select: Channel 14 */\r
+#define CEIPSEL_15 (0x000F) /* Comp. E V+ terminal Input Select: Channel 15 */\r
+\r
+#define CEIMSEL_0 (0x0000) /* Comp. E V- Terminal Input Select: Channel 0 */\r
+#define CEIMSEL_1 (0x0100) /* Comp. E V- Terminal Input Select: Channel 1 */\r
+#define CEIMSEL_2 (0x0200) /* Comp. E V- Terminal Input Select: Channel 2 */\r
+#define CEIMSEL_3 (0x0300) /* Comp. E V- Terminal Input Select: Channel 3 */\r
+#define CEIMSEL_4 (0x0400) /* Comp. E V- Terminal Input Select: Channel 4 */\r
+#define CEIMSEL_5 (0x0500) /* Comp. E V- Terminal Input Select: Channel 5 */\r
+#define CEIMSEL_6 (0x0600) /* Comp. E V- Terminal Input Select: Channel 6 */\r
+#define CEIMSEL_7 (0x0700) /* Comp. E V- Terminal Input Select: Channel 7 */\r
+#define CEIMSEL_8 (0x0800) /* Comp. E V- terminal Input Select: Channel 8 */\r
+#define CEIMSEL_9 (0x0900) /* Comp. E V- terminal Input Select: Channel 9 */\r
+#define CEIMSEL_10 (0x0A00) /* Comp. E V- terminal Input Select: Channel 10 */\r
+#define CEIMSEL_11 (0x0B00) /* Comp. E V- terminal Input Select: Channel 11 */\r
+#define CEIMSEL_12 (0x0C00) /* Comp. E V- terminal Input Select: Channel 12 */\r
+#define CEIMSEL_13 (0x0D00) /* Comp. E V- terminal Input Select: Channel 13 */\r
+#define CEIMSEL_14 (0x0E00) /* Comp. E V- terminal Input Select: Channel 14 */\r
+#define CEIMSEL_15 (0x0F00) /* Comp. E V- terminal Input Select: Channel 15 */\r
+\r
+/* CECTL1 Control Bits */\r
+#define CEOUT (0x0001) /* Comp. E Output */\r
+#define CEOUTPOL (0x0002) /* Comp. E Output Polarity */\r
+#define CEF (0x0004) /* Comp. E Enable Output Filter */\r
+#define CEIES (0x0008) /* Comp. E Interrupt Edge Select */\r
+#define CESHORT (0x0010) /* Comp. E Input Short */\r
+#define CEEX (0x0020) /* Comp. E Exchange Inputs */\r
+#define CEFDLY0 (0x0040) /* Comp. E Filter delay Bit 0 */\r
+#define CEFDLY1 (0x0080) /* Comp. E Filter delay Bit 1 */\r
+#define CEPWRMD0 (0x0100) /* Comp. E Power mode Bit 0 */\r
+#define CEPWRMD1 (0x0200) /* Comp. E Power mode Bit 1 */\r
+#define CEON (0x0400) /* Comp. E enable */\r
+#define CEMRVL (0x0800) /* Comp. E CEMRV Level */\r
+#define CEMRVS (0x1000) /* Comp. E Output selects between VREF0 or VREF1*/\r
+//#define RESERVED (0x2000) /* Comp. E */\r
+//#define RESERVED (0x4000) /* Comp. E */\r
+//#define RESERVED (0x8000) /* Comp. E */\r
+\r
+/* CECTL1 Control Bits */\r
+#define CEOUT_L (0x0001) /* Comp. E Output */\r
+#define CEOUTPOL_L (0x0002) /* Comp. E Output Polarity */\r
+#define CEF_L (0x0004) /* Comp. E Enable Output Filter */\r
+#define CEIES_L (0x0008) /* Comp. E Interrupt Edge Select */\r
+#define CESHORT_L (0x0010) /* Comp. E Input Short */\r
+#define CEEX_L (0x0020) /* Comp. E Exchange Inputs */\r
+#define CEFDLY0_L (0x0040) /* Comp. E Filter delay Bit 0 */\r
+#define CEFDLY1_L (0x0080) /* Comp. E Filter delay Bit 1 */\r
+//#define RESERVED (0x2000) /* Comp. E */\r
+//#define RESERVED (0x4000) /* Comp. E */\r
+//#define RESERVED (0x8000) /* Comp. E */\r
+\r
+/* CECTL1 Control Bits */\r
+#define CEPWRMD0_H (0x0001) /* Comp. E Power mode Bit 0 */\r
+#define CEPWRMD1_H (0x0002) /* Comp. E Power mode Bit 1 */\r
+#define CEON_H (0x0004) /* Comp. E enable */\r
+#define CEMRVL_H (0x0008) /* Comp. E CEMRV Level */\r
+#define CEMRVS_H (0x0010) /* Comp. E Output selects between VREF0 or VREF1*/\r
+//#define RESERVED (0x2000) /* Comp. E */\r
+//#define RESERVED (0x4000) /* Comp. E */\r
+//#define RESERVED (0x8000) /* Comp. E */\r
+\r
+#define CEPWRMD_0 (0x0000) /* Comp. E Power mode 0 */\r
+#define CEPWRMD_1 (0x0100) /* Comp. E Power mode 1 */\r
+#define CEPWRMD_2 (0x0200) /* Comp. E Power mode 2 */\r
+#define CEPWRMD_3 (0x0300) /* Comp. E Power mode 3*/\r
+\r
+#define CEFDLY_0 (0x0000) /* Comp. E Filter delay 0 : 450ns */\r
+#define CEFDLY_1 (0x0040) /* Comp. E Filter delay 1 : 900ns */\r
+#define CEFDLY_2 (0x0080) /* Comp. E Filter delay 2 : 1800ns */\r
+#define CEFDLY_3 (0x00C0) /* Comp. E Filter delay 3 : 3600ns */\r
+\r
+/* CECTL2 Control Bits */\r
+#define CEREF00 (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */\r
+#define CEREF01 (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */\r
+#define CEREF02 (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */\r
+#define CEREF03 (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */\r
+#define CEREF04 (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */\r
+#define CERSEL (0x0020) /* Comp. E Reference select */\r
+#define CERS0 (0x0040) /* Comp. E Reference Source Bit : 0 */\r
+#define CERS1 (0x0080) /* Comp. E Reference Source Bit : 1 */\r
+#define CEREF10 (0x0100) /* Comp. E Reference 1 Resistor Select Bit : 0 */\r
+#define CEREF11 (0x0200) /* Comp. E Reference 1 Resistor Select Bit : 1 */\r
+#define CEREF12 (0x0400) /* Comp. E Reference 1 Resistor Select Bit : 2 */\r
+#define CEREF13 (0x0800) /* Comp. E Reference 1 Resistor Select Bit : 3 */\r
+#define CEREF14 (0x1000) /* Comp. E Reference 1 Resistor Select Bit : 4 */\r
+#define CEREFL0 (0x2000) /* Comp. E Reference voltage level Bit : 0 */\r
+#define CEREFL1 (0x4000) /* Comp. E Reference voltage level Bit : 1 */\r
+#define CEREFACC (0x8000) /* Comp. E Reference Accuracy */\r
+\r
+/* CECTL2 Control Bits */\r
+#define CEREF00_L (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */\r
+#define CEREF01_L (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */\r
+#define CEREF02_L (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */\r
+#define CEREF03_L (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */\r
+#define CEREF04_L (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */\r
+#define CERSEL_L (0x0020) /* Comp. E Reference select */\r
+#define CERS0_L (0x0040) /* Comp. E Reference Source Bit : 0 */\r
+#define CERS1_L (0x0080) /* Comp. E Reference Source Bit : 1 */\r
+\r
+/* CECTL2 Control Bits */\r
+#define CEREF10_H (0x0001) /* Comp. E Reference 1 Resistor Select Bit : 0 */\r
+#define CEREF11_H (0x0002) /* Comp. E Reference 1 Resistor Select Bit : 1 */\r
+#define CEREF12_H (0x0004) /* Comp. E Reference 1 Resistor Select Bit : 2 */\r
+#define CEREF13_H (0x0008) /* Comp. E Reference 1 Resistor Select Bit : 3 */\r
+#define CEREF14_H (0x0010) /* Comp. E Reference 1 Resistor Select Bit : 4 */\r
+#define CEREFL0_H (0x0020) /* Comp. E Reference voltage level Bit : 0 */\r
+#define CEREFL1_H (0x0040) /* Comp. E Reference voltage level Bit : 1 */\r
+#define CEREFACC_H (0x0080) /* Comp. E Reference Accuracy */\r
+\r
+#define CEREF0_0 (0x0000) /* Comp. E Int. Ref.0 Select 0 : 1/32 */\r
+#define CEREF0_1 (0x0001) /* Comp. E Int. Ref.0 Select 1 : 2/32 */\r
+#define CEREF0_2 (0x0002) /* Comp. E Int. Ref.0 Select 2 : 3/32 */\r
+#define CEREF0_3 (0x0003) /* Comp. E Int. Ref.0 Select 3 : 4/32 */\r
+#define CEREF0_4 (0x0004) /* Comp. E Int. Ref.0 Select 4 : 5/32 */\r
+#define CEREF0_5 (0x0005) /* Comp. E Int. Ref.0 Select 5 : 6/32 */\r
+#define CEREF0_6 (0x0006) /* Comp. E Int. Ref.0 Select 6 : 7/32 */\r
+#define CEREF0_7 (0x0007) /* Comp. E Int. Ref.0 Select 7 : 8/32 */\r
+#define CEREF0_8 (0x0008) /* Comp. E Int. Ref.0 Select 0 : 9/32 */\r
+#define CEREF0_9 (0x0009) /* Comp. E Int. Ref.0 Select 1 : 10/32 */\r
+#define CEREF0_10 (0x000A) /* Comp. E Int. Ref.0 Select 2 : 11/32 */\r
+#define CEREF0_11 (0x000B) /* Comp. E Int. Ref.0 Select 3 : 12/32 */\r
+#define CEREF0_12 (0x000C) /* Comp. E Int. Ref.0 Select 4 : 13/32 */\r
+#define CEREF0_13 (0x000D) /* Comp. E Int. Ref.0 Select 5 : 14/32 */\r
+#define CEREF0_14 (0x000E) /* Comp. E Int. Ref.0 Select 6 : 15/32 */\r
+#define CEREF0_15 (0x000F) /* Comp. E Int. Ref.0 Select 7 : 16/32 */\r
+#define CEREF0_16 (0x0010) /* Comp. E Int. Ref.0 Select 0 : 17/32 */\r
+#define CEREF0_17 (0x0011) /* Comp. E Int. Ref.0 Select 1 : 18/32 */\r
+#define CEREF0_18 (0x0012) /* Comp. E Int. Ref.0 Select 2 : 19/32 */\r
+#define CEREF0_19 (0x0013) /* Comp. E Int. Ref.0 Select 3 : 20/32 */\r
+#define CEREF0_20 (0x0014) /* Comp. E Int. Ref.0 Select 4 : 21/32 */\r
+#define CEREF0_21 (0x0015) /* Comp. E Int. Ref.0 Select 5 : 22/32 */\r
+#define CEREF0_22 (0x0016) /* Comp. E Int. Ref.0 Select 6 : 23/32 */\r
+#define CEREF0_23 (0x0017) /* Comp. E Int. Ref.0 Select 7 : 24/32 */\r
+#define CEREF0_24 (0x0018) /* Comp. E Int. Ref.0 Select 0 : 25/32 */\r
+#define CEREF0_25 (0x0019) /* Comp. E Int. Ref.0 Select 1 : 26/32 */\r
+#define CEREF0_26 (0x001A) /* Comp. E Int. Ref.0 Select 2 : 27/32 */\r
+#define CEREF0_27 (0x001B) /* Comp. E Int. Ref.0 Select 3 : 28/32 */\r
+#define CEREF0_28 (0x001C) /* Comp. E Int. Ref.0 Select 4 : 29/32 */\r
+#define CEREF0_29 (0x001D) /* Comp. E Int. Ref.0 Select 5 : 30/32 */\r
+#define CEREF0_30 (0x001E) /* Comp. E Int. Ref.0 Select 6 : 31/32 */\r
+#define CEREF0_31 (0x001F) /* Comp. E Int. Ref.0 Select 7 : 32/32 */\r
+\r
+#define CERS_0 (0x0000) /* Comp. E Reference Source 0 : Off */\r
+#define CERS_1 (0x0040) /* Comp. E Reference Source 1 : Vcc */\r
+#define CERS_2 (0x0080) /* Comp. E Reference Source 2 : Shared Ref. */\r
+#define CERS_3 (0x00C0) /* Comp. E Reference Source 3 : Shared Ref. / Off */\r
+\r
+#define CEREF1_0 (0x0000) /* Comp. E Int. Ref.1 Select 0 : 1/32 */\r
+#define CEREF1_1 (0x0100) /* Comp. E Int. Ref.1 Select 1 : 2/32 */\r
+#define CEREF1_2 (0x0200) /* Comp. E Int. Ref.1 Select 2 : 3/32 */\r
+#define CEREF1_3 (0x0300) /* Comp. E Int. Ref.1 Select 3 : 4/32 */\r
+#define CEREF1_4 (0x0400) /* Comp. E Int. Ref.1 Select 4 : 5/32 */\r
+#define CEREF1_5 (0x0500) /* Comp. E Int. Ref.1 Select 5 : 6/32 */\r
+#define CEREF1_6 (0x0600) /* Comp. E Int. Ref.1 Select 6 : 7/32 */\r
+#define CEREF1_7 (0x0700) /* Comp. E Int. Ref.1 Select 7 : 8/32 */\r
+#define CEREF1_8 (0x0800) /* Comp. E Int. Ref.1 Select 0 : 9/32 */\r
+#define CEREF1_9 (0x0900) /* Comp. E Int. Ref.1 Select 1 : 10/32 */\r
+#define CEREF1_10 (0x0A00) /* Comp. E Int. Ref.1 Select 2 : 11/32 */\r
+#define CEREF1_11 (0x0B00) /* Comp. E Int. Ref.1 Select 3 : 12/32 */\r
+#define CEREF1_12 (0x0C00) /* Comp. E Int. Ref.1 Select 4 : 13/32 */\r
+#define CEREF1_13 (0x0D00) /* Comp. E Int. Ref.1 Select 5 : 14/32 */\r
+#define CEREF1_14 (0x0E00) /* Comp. E Int. Ref.1 Select 6 : 15/32 */\r
+#define CEREF1_15 (0x0F00) /* Comp. E Int. Ref.1 Select 7 : 16/32 */\r
+#define CEREF1_16 (0x1000) /* Comp. E Int. Ref.1 Select 0 : 17/32 */\r
+#define CEREF1_17 (0x1100) /* Comp. E Int. Ref.1 Select 1 : 18/32 */\r
+#define CEREF1_18 (0x1200) /* Comp. E Int. Ref.1 Select 2 : 19/32 */\r
+#define CEREF1_19 (0x1300) /* Comp. E Int. Ref.1 Select 3 : 20/32 */\r
+#define CEREF1_20 (0x1400) /* Comp. E Int. Ref.1 Select 4 : 21/32 */\r
+#define CEREF1_21 (0x1500) /* Comp. E Int. Ref.1 Select 5 : 22/32 */\r
+#define CEREF1_22 (0x1600) /* Comp. E Int. Ref.1 Select 6 : 23/32 */\r
+#define CEREF1_23 (0x1700) /* Comp. E Int. Ref.1 Select 7 : 24/32 */\r
+#define CEREF1_24 (0x1800) /* Comp. E Int. Ref.1 Select 0 : 25/32 */\r
+#define CEREF1_25 (0x1900) /* Comp. E Int. Ref.1 Select 1 : 26/32 */\r
+#define CEREF1_26 (0x1A00) /* Comp. E Int. Ref.1 Select 2 : 27/32 */\r
+#define CEREF1_27 (0x1B00) /* Comp. E Int. Ref.1 Select 3 : 28/32 */\r
+#define CEREF1_28 (0x1C00) /* Comp. E Int. Ref.1 Select 4 : 29/32 */\r
+#define CEREF1_29 (0x1D00) /* Comp. E Int. Ref.1 Select 5 : 30/32 */\r
+#define CEREF1_30 (0x1E00) /* Comp. E Int. Ref.1 Select 6 : 31/32 */\r
+#define CEREF1_31 (0x1F00) /* Comp. E Int. Ref.1 Select 7 : 32/32 */\r
+\r
+#define CEREFL_0 (0x0000) /* Comp. E Reference voltage level 0 : None */\r
+#define CEREFL_1 (0x2000) /* Comp. E Reference voltage level 1 : 1.2V */\r
+#define CEREFL_2 (0x4000) /* Comp. E Reference voltage level 2 : 2.0V */\r
+#define CEREFL_3 (0x6000) /* Comp. E Reference voltage level 3 : 2.5V */\r
+\r
+#define CEPD0 (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */\r
+#define CEPD1 (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */\r
+#define CEPD2 (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */\r
+#define CEPD3 (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */\r
+#define CEPD4 (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */\r
+#define CEPD5 (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */\r
+#define CEPD6 (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */\r
+#define CEPD7 (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */\r
+#define CEPD8 (0x0100) /* Comp. E Disable Input Buffer of Port Register .8 */\r
+#define CEPD9 (0x0200) /* Comp. E Disable Input Buffer of Port Register .9 */\r
+#define CEPD10 (0x0400) /* Comp. E Disable Input Buffer of Port Register .10 */\r
+#define CEPD11 (0x0800) /* Comp. E Disable Input Buffer of Port Register .11 */\r
+#define CEPD12 (0x1000) /* Comp. E Disable Input Buffer of Port Register .12 */\r
+#define CEPD13 (0x2000) /* Comp. E Disable Input Buffer of Port Register .13 */\r
+#define CEPD14 (0x4000) /* Comp. E Disable Input Buffer of Port Register .14 */\r
+#define CEPD15 (0x8000) /* Comp. E Disable Input Buffer of Port Register .15 */\r
+\r
+#define CEPD0_L (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */\r
+#define CEPD1_L (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */\r
+#define CEPD2_L (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */\r
+#define CEPD3_L (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */\r
+#define CEPD4_L (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */\r
+#define CEPD5_L (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */\r
+#define CEPD6_L (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */\r
+#define CEPD7_L (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */\r
+\r
+#define CEPD8_H (0x0001) /* Comp. E Disable Input Buffer of Port Register .8 */\r
+#define CEPD9_H (0x0002) /* Comp. E Disable Input Buffer of Port Register .9 */\r
+#define CEPD10_H (0x0004) /* Comp. E Disable Input Buffer of Port Register .10 */\r
+#define CEPD11_H (0x0008) /* Comp. E Disable Input Buffer of Port Register .11 */\r
+#define CEPD12_H (0x0010) /* Comp. E Disable Input Buffer of Port Register .12 */\r
+#define CEPD13_H (0x0020) /* Comp. E Disable Input Buffer of Port Register .13 */\r
+#define CEPD14_H (0x0040) /* Comp. E Disable Input Buffer of Port Register .14 */\r
+#define CEPD15_H (0x0080) /* Comp. E Disable Input Buffer of Port Register .15 */\r
+\r
+/* CEINT Control Bits */\r
+#define CEIFG (0x0001) /* Comp. E Interrupt Flag */\r
+#define CEIIFG (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */\r
+//#define RESERVED (0x0004) /* Comp. E */\r
+//#define RESERVED (0x0008) /* Comp. E */\r
+#define CERDYIFG (0x0010) /* Comp. E Comparator_E ready interrupt flag */\r
+//#define RESERVED (0x0020) /* Comp. E */\r
+//#define RESERVED (0x0040) /* Comp. E */\r
+//#define RESERVED (0x0080) /* Comp. E */\r
+#define CEIE (0x0100) /* Comp. E Interrupt Enable */\r
+#define CEIIE (0x0200) /* Comp. E Interrupt Enable Inverted Polarity */\r
+//#define RESERVED (0x0400) /* Comp. E */\r
+//#define RESERVED (0x0800) /* Comp. E */\r
+#define CERDYIE (0x1000) /* Comp. E Comparator_E ready interrupt enable */\r
+//#define RESERVED (0x2000) /* Comp. E */\r
+//#define RESERVED (0x4000) /* Comp. E */\r
+//#define RESERVED (0x8000) /* Comp. E */\r
+\r
+/* CEINT Control Bits */\r
+#define CEIFG_L (0x0001) /* Comp. E Interrupt Flag */\r
+#define CEIIFG_L (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */\r
+//#define RESERVED (0x0004) /* Comp. E */\r
+//#define RESERVED (0x0008) /* Comp. E */\r
+#define CERDYIFG_L (0x0010) /* Comp. E Comparator_E ready interrupt flag */\r
+//#define RESERVED (0x0020) /* Comp. E */\r
+//#define RESERVED (0x0040) /* Comp. E */\r
+//#define RESERVED (0x0080) /* Comp. E */\r
+//#define RESERVED (0x0400) /* Comp. E */\r
+//#define RESERVED (0x0800) /* Comp. E */\r
+//#define RESERVED (0x2000) /* Comp. E */\r
+//#define RESERVED (0x4000) /* Comp. E */\r
+//#define RESERVED (0x8000) /* Comp. E */\r
+\r
+/* CEINT Control Bits */\r
+//#define RESERVED (0x0004) /* Comp. E */\r
+//#define RESERVED (0x0008) /* Comp. E */\r
+//#define RESERVED (0x0020) /* Comp. E */\r
+//#define RESERVED (0x0040) /* Comp. E */\r
+//#define RESERVED (0x0080) /* Comp. E */\r
+#define CEIE_H (0x0001) /* Comp. E Interrupt Enable */\r
+#define CEIIE_H (0x0002) /* Comp. E Interrupt Enable Inverted Polarity */\r
+//#define RESERVED (0x0400) /* Comp. E */\r
+//#define RESERVED (0x0800) /* Comp. E */\r
+#define CERDYIE_H (0x0010) /* Comp. E Comparator_E ready interrupt enable */\r
+//#define RESERVED (0x2000) /* Comp. E */\r
+//#define RESERVED (0x4000) /* Comp. E */\r
+//#define RESERVED (0x8000) /* Comp. E */\r
+\r
+/* CEIV Definitions */\r
+#define CEIV_NONE (0x0000) /* No Interrupt pending */\r
+#define CEIV_CEIFG (0x0002) /* CEIFG */\r
+#define CEIV_CEIIFG (0x0004) /* CEIIFG */\r
+#define CEIV_CERDYIFG (0x000A) /* CERDYIFG */\r
+\r
+#endif\r
+/*************************************************************\r
+* CRC Module\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CRCDI (0x0000) /* CRC Data In Register */\r
+#define OFS_CRCDI_L OFS_CRCDI\r
+#define OFS_CRCDI_H OFS_CRCDI+1\r
+#define OFS_CRCDIRB (0x0002) /* CRC data in reverse byte Register */\r
+#define OFS_CRCDIRB_L OFS_CRCDIRB\r
+#define OFS_CRCDIRB_H OFS_CRCDIRB+1\r
+#define OFS_CRCINIRES (0x0004) /* CRC Initialisation Register and Result Register */\r
+#define OFS_CRCINIRES_L OFS_CRCINIRES\r
+#define OFS_CRCINIRES_H OFS_CRCINIRES+1\r
+#define OFS_CRCRESR (0x0006) /* CRC reverse result Register */\r
+#define OFS_CRCRESR_L OFS_CRCRESR\r
+#define OFS_CRCRESR_H OFS_CRCRESR+1\r
+\r
+#endif\r
+/*************************************************************\r
+* CRC Module\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_CRC32__ /* Definition to show that Module is available */\r
+\r
+\r
+//#define CRC32DIL0_O (0x0000) /* CRC32 Data In */\r
+#define OFS_CRC32DIW0 (0x0000) /* CRC32 Data In */\r
+#define OFS_CRC32DIW0_L OFS_CRC32DIW0\r
+#define OFS_CRC32DIW0_H OFS_CRC32DIW0+1\r
+#define OFS_CRC32DIW1 (0x0002) /* CRC32 Data In */\r
+#define OFS_CRC32DIW1_L OFS_CRC32DIW1\r
+#define OFS_CRC32DIW1_H OFS_CRC32DIW1+1\r
+#define CRC32DIB0 CRC32DIW0_L\r
+\r
+//#define CRC32DIRBL0_O (0x0004) /* CRC32 Data In Reversed Bit */\r
+#define OFS_CRC32DIRBW1 (0x0004) /* CRC32 Data In Reversed Bit */\r
+#define OFS_CRC32DIRBW1_L OFS_CRC32DIRBW1\r
+#define OFS_CRC32DIRBW1_H OFS_CRC32DIRBW1+1\r
+#define OFS_CRC32DIRBW0 (0x0006) /* CRC32 Data In Reversed Bit */\r
+#define OFS_CRC32DIRBW0_L OFS_CRC32DIRBW0\r
+#define OFS_CRC32DIRBW0_H OFS_CRC32DIRBW0+1\r
+#define CRC32DIRBB0 CRC32DIRBW0_H\r
+\r
+//#define CRC32INIRESL0_O (0x0008) /* CRC32 Initialization and Result */\r
+#define OFS_CRC32INIRESW0 (0x0008) /* CRC32 Initialization and Result */\r
+#define OFS_CRC32INIRESW0_L OFS_CRC32INIRESW0\r
+#define OFS_CRC32INIRESW0_H OFS_CRC32INIRESW0+1\r
+#define OFS_CRC32INIRESW1 (0x000A) /* CRC32 Initialization and Result */\r
+#define OFS_CRC32INIRESW1_L OFS_CRC32INIRESW1\r
+#define OFS_CRC32INIRESW1_H OFS_CRC32INIRESW1+1\r
+#define CRC32RESB0 CRC32INIRESW0_L\r
+#define CRC32RESB1 CRC32INIRESW0_H\r
+#define CRC32RESB2 CRC32INIRESW1_L\r
+#define CRC32RESB3 CRC32INIRESW1_H\r
+\r
+//#define CRC32RESRL0_O (0x000C) /* CRC32 Result Reverse */\r
+#define OFS_CRC32RESRW1 (0x000C) /* CRC32 Result Reverse */\r
+#define OFS_CRC32RESRW1_L OFS_CRC32RESRW1\r
+#define OFS_CRC32RESRW1_H OFS_CRC32RESRW1+1\r
+#define OFS_CRC32RESRW0 (0x000E) /* CRC32 Result Reverse */\r
+#define OFS_CRC32RESRW0_L OFS_CRC32RESRW0\r
+#define OFS_CRC32RESRW0_H OFS_CRC32RESRW0+1\r
+#define CRC32RESRB3 CRC32RESRW1_L\r
+#define CRC32RESRB2 CRC32RESRW1_H\r
+#define CRC32RESRB1 CRC32RESRW0_L\r
+#define CRC32RESRB0 CRC32RESRW0_H\r
+\r
+//#define CRC16DIL0_O (0x0010) /* CRC16 Data Input */\r
+#define OFS_CRC16DIW0 (0x0010) /* CRC16 Data Input */\r
+#define OFS_CRC16DIW0_L OFS_CRC16DIW0\r
+#define OFS_CRC16DIW0_H OFS_CRC16DIW0+1\r
+#define OFS_CRC16DIW1 (0x0012) /* CRC16 Data Input */\r
+#define OFS_CRC16DIW1_L OFS_CRC16DIW1\r
+#define OFS_CRC16DIW1_H OFS_CRC16DIW1+1\r
+#define CRC16DIB0 CRC16DIW0_L\r
+//#define CRC16DIRBL0_O (0x0014) /* CRC16 Data In Reverse */\r
+#define OFS_CRC16DIRBW1 (0x0014) /* CRC16 Data In Reverse */\r
+#define OFS_CRC16DIRBW1_L OFS_CRC16DIRBW1\r
+#define OFS_CRC16DIRBW1_H OFS_CRC16DIRBW1+1\r
+#define OFS_CRC16DIRBW0 (0x0016) /* CRC16 Data In Reverse */\r
+#define OFS_CRC16DIRBW0_L OFS_CRC16DIRBW0\r
+#define OFS_CRC16DIRBW0_H OFS_CRC16DIRBW0+1\r
+#define CRC16DIRBB0 CRC16DIRBW0_L\r
+\r
+//#define CRC16INIRESL0_O (0x0018) /* CRC16 Init and Result */\r
+#define OFS_CRC16INIRESW0 (0x0018) /* CRC16 Init and Result */\r
+#define OFS_CRC16INIRESW0_L OFS_CRC16INIRESW0\r
+#define OFS_CRC16INIRESW0_H OFS_CRC16INIRESW0+1\r
+#define CRC16INIRESB1 CRC16INIRESW0_H\r
+#define CRC16INIRESB0 CRC16INIRESW0_L\r
+\r
+//#define CRC16RESRL0_O (0x001E) /* CRC16 Result Reverse */\r
+#define OFS_CRC16RESRW0 (0x001E) /* CRC16 Result Reverse */\r
+#define OFS_CRC16RESRW0_L OFS_CRC16RESRW0\r
+#define OFS_CRC16RESRW0_H OFS_CRC16RESRW0+1\r
+#define OFS_CRC16RESRW1 (0x001C) /* CRC16 Result Reverse */\r
+#define OFS_CRC16RESRW1_L OFS_CRC16RESRW1\r
+#define OFS_CRC16RESRW1_H OFS_CRC16RESRW1+1\r
+#define CRC16RESRB1 CRC16RESRW0_L\r
+#define CRC16RESRB0 CRC16RESRW0_H\r
+\r
+#endif\r
+/************************************************************\r
+* CLOCK SYSTEM\r
+************************************************************/\r
+#ifdef __MSP430_HAS_CS__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CSCTL0 (0x0000) /* CS Control Register 0 */\r
+#define OFS_CSCTL0_L OFS_CSCTL0\r
+#define OFS_CSCTL0_H OFS_CSCTL0+1\r
+#define OFS_CSCTL1 (0x0002) /* CS Control Register 1 */\r
+#define OFS_CSCTL1_L OFS_CSCTL1\r
+#define OFS_CSCTL1_H OFS_CSCTL1+1\r
+#define OFS_CSCTL2 (0x0004) /* CS Control Register 2 */\r
+#define OFS_CSCTL2_L OFS_CSCTL2\r
+#define OFS_CSCTL2_H OFS_CSCTL2+1\r
+#define OFS_CSCTL3 (0x0006) /* CS Control Register 3 */\r
+#define OFS_CSCTL3_L OFS_CSCTL3\r
+#define OFS_CSCTL3_H OFS_CSCTL3+1\r
+#define OFS_CSCTL4 (0x0008) /* CS Control Register 4 */\r
+#define OFS_CSCTL4_L OFS_CSCTL4\r
+#define OFS_CSCTL4_H OFS_CSCTL4+1\r
+#define OFS_CSCTL5 (0x000A) /* CS Control Register 5 */\r
+#define OFS_CSCTL5_L OFS_CSCTL5\r
+#define OFS_CSCTL5_H OFS_CSCTL5+1\r
+#define OFS_CSCTL6 (0x000C) /* CS Control Register 6 */\r
+#define OFS_CSCTL6_L OFS_CSCTL6\r
+#define OFS_CSCTL6_H OFS_CSCTL6+1\r
+\r
+/* CSCTL0 Control Bits */\r
+\r
+#define CSKEY (0xA500) /* CS Password */\r
+#define CSKEY_H (0xA5) /* CS Password for high byte access */\r
+\r
+/* CSCTL1 Control Bits */\r
+#define DCOFSEL0 (0x0002) /* DCO frequency select Bit: 0 */\r
+#define DCOFSEL1 (0x0004) /* DCO frequency select Bit: 1 */\r
+#define DCOFSEL2 (0x0008) /* DCO frequency select Bit: 2 */\r
+#define DCORSEL (0x0040) /* DCO range select. */\r
+\r
+/* CSCTL1 Control Bits */\r
+#define DCOFSEL0_L (0x0002) /* DCO frequency select Bit: 0 */\r
+#define DCOFSEL1_L (0x0004) /* DCO frequency select Bit: 1 */\r
+#define DCOFSEL2_L (0x0008) /* DCO frequency select Bit: 2 */\r
+#define DCORSEL_L (0x0040) /* DCO range select. */\r
+\r
+#define DCOFSEL_0 (0x0000) /* DCO frequency select: 0 */\r
+#define DCOFSEL_1 (0x0002) /* DCO frequency select: 1 */\r
+#define DCOFSEL_2 (0x0004) /* DCO frequency select: 2 */\r
+#define DCOFSEL_3 (0x0006) /* DCO frequency select: 3 */\r
+#define DCOFSEL_4 (0x0008) /* DCO frequency select: 4 */\r
+#define DCOFSEL_5 (0x000A) /* DCO frequency select: 5 */\r
+#define DCOFSEL_6 (0x000C) /* DCO frequency select: 6 */\r
+#define DCOFSEL_7 (0x000E) /* DCO frequency select: 7 */\r
+\r
+/* CSCTL2 Control Bits */\r
+#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */\r
+#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */\r
+#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0004) /* RESERVED */\r
+//#define RESERVED (0x0008) /* RESERVED */\r
+#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */\r
+#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */\r
+#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0040) /* RESERVED */\r
+//#define RESERVED (0x0080) /* RESERVED */\r
+#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */\r
+#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */\r
+#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0400) /* RESERVED */\r
+//#define RESERVED (0x0800) /* RESERVED */\r
+//#define RESERVED (0x1000) /* RESERVED */\r
+//#define RESERVED (0x2000) /* RESERVED */\r
+//#define RESERVED (0x4000) /* RESERVED */\r
+//#define RESERVED (0x8000) /* RESERVED */\r
+\r
+/* CSCTL2 Control Bits */\r
+#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */\r
+#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */\r
+#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0004) /* RESERVED */\r
+//#define RESERVED (0x0008) /* RESERVED */\r
+#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */\r
+#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */\r
+#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0040) /* RESERVED */\r
+//#define RESERVED (0x0080) /* RESERVED */\r
+//#define RESERVED (0x0400) /* RESERVED */\r
+//#define RESERVED (0x0800) /* RESERVED */\r
+//#define RESERVED (0x1000) /* RESERVED */\r
+//#define RESERVED (0x2000) /* RESERVED */\r
+//#define RESERVED (0x4000) /* RESERVED */\r
+//#define RESERVED (0x8000) /* RESERVED */\r
+\r
+/* CSCTL2 Control Bits */\r
+//#define RESERVED (0x0004) /* RESERVED */\r
+//#define RESERVED (0x0008) /* RESERVED */\r
+//#define RESERVED (0x0040) /* RESERVED */\r
+//#define RESERVED (0x0080) /* RESERVED */\r
+#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */\r
+#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */\r
+#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0400) /* RESERVED */\r
+//#define RESERVED (0x0800) /* RESERVED */\r
+//#define RESERVED (0x1000) /* RESERVED */\r
+//#define RESERVED (0x2000) /* RESERVED */\r
+//#define RESERVED (0x4000) /* RESERVED */\r
+//#define RESERVED (0x8000) /* RESERVED */\r
+\r
+#define SELM_0 (0x0000) /* MCLK Source Select 0 */\r
+#define SELM_1 (0x0001) /* MCLK Source Select 1 */\r
+#define SELM_2 (0x0002) /* MCLK Source Select 2 */\r
+#define SELM_3 (0x0003) /* MCLK Source Select 3 */\r
+#define SELM_4 (0x0004) /* MCLK Source Select 4 */\r
+#define SELM_5 (0x0005) /* MCLK Source Select 5 */\r
+#define SELM_6 (0x0006) /* MCLK Source Select 6 */\r
+#define SELM_7 (0x0007) /* MCLK Source Select 7 */\r
+#define SELM__LFXTCLK (0x0000) /* MCLK Source Select LFXTCLK */\r
+#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */\r
+#define SELM__LFMODOSC (0x0002) /* MCLK Source Select LFMODOSC */\r
+#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */\r
+#define SELM__MODOSC (0x0004) /* MCLK Source Select MODOSC */\r
+#define SELM__HFXTCLK (0x0005) /* MCLK Source Select HFXTCLK */\r
+\r
+#define SELS_0 (0x0000) /* SMCLK Source Select 0 */\r
+#define SELS_1 (0x0010) /* SMCLK Source Select 1 */\r
+#define SELS_2 (0x0020) /* SMCLK Source Select 2 */\r
+#define SELS_3 (0x0030) /* SMCLK Source Select 3 */\r
+#define SELS_4 (0x0040) /* SMCLK Source Select 4 */\r
+#define SELS_5 (0x0050) /* SMCLK Source Select 5 */\r
+#define SELS_6 (0x0060) /* SMCLK Source Select 6 */\r
+#define SELS_7 (0x0070) /* SMCLK Source Select 7 */\r
+#define SELS__LFXTCLK (0x0000) /* SMCLK Source Select LFXTCLK */\r
+#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */\r
+#define SELS__LFMODOSC (0x0020) /* SMCLK Source Select LFMODOSC */\r
+#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */\r
+#define SELS__MODOSC (0x0040) /* SMCLK Source Select MODOSC */\r
+#define SELS__HFXTCLK (0x0050) /* SMCLK Source Select HFXTCLK */\r
+\r
+#define SELA_0 (0x0000) /* ACLK Source Select 0 */\r
+#define SELA_1 (0x0100) /* ACLK Source Select 1 */\r
+#define SELA_2 (0x0200) /* ACLK Source Select 2 */\r
+#define SELA_3 (0x0300) /* ACLK Source Select 3 */\r
+#define SELA_4 (0x0400) /* ACLK Source Select 4 */\r
+#define SELA_5 (0x0500) /* ACLK Source Select 5 */\r
+#define SELA_6 (0x0600) /* ACLK Source Select 6 */\r
+#define SELA_7 (0x0700) /* ACLK Source Select 7 */\r
+#define SELA__LFXTCLK (0x0000) /* ACLK Source Select LFXTCLK */\r
+#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */\r
+#define SELA__LFMODOSC (0x0200) /* ACLK Source Select LFMODOSC */\r
+\r
+/* CSCTL3 Control Bits */\r
+#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */\r
+#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */\r
+#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0004) /* RESERVED */\r
+//#define RESERVED (0x0008) /* RESERVED */\r
+#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */\r
+#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */\r
+#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0040) /* RESERVED */\r
+//#define RESERVED (0x0080) /* RESERVED */\r
+#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */\r
+#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */\r
+#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */\r
+//#define RESERVED (0x0400) /* RESERVED */\r
+//#define RESERVED (0x0800) /* RESERVED */\r
+//#define RESERVED (0x1000) /* RESERVED */\r
+//#define RESERVED (0x2000) /* RESERVED */\r
+//#define RESERVED (0x4000) /* RESERVED */\r
+//#define RESERVED (0x8000) /* RESERVED */\r
+\r
+/* CSCTL3 Control Bits */\r
+#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */\r
+#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */\r
+#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0004) /* RESERVED */\r
+//#define RESERVED (0x0008) /* RESERVED */\r
+#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */\r
+#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */\r
+#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0040) /* RESERVED */\r
+//#define RESERVED (0x0080) /* RESERVED */\r
+//#define RESERVED (0x0400) /* RESERVED */\r
+//#define RESERVED (0x0800) /* RESERVED */\r
+//#define RESERVED (0x1000) /* RESERVED */\r
+//#define RESERVED (0x2000) /* RESERVED */\r
+//#define RESERVED (0x4000) /* RESERVED */\r
+//#define RESERVED (0x8000) /* RESERVED */\r
+\r
+/* CSCTL3 Control Bits */\r
+//#define RESERVED (0x0004) /* RESERVED */\r
+//#define RESERVED (0x0008) /* RESERVED */\r
+//#define RESERVED (0x0040) /* RESERVED */\r
+//#define RESERVED (0x0080) /* RESERVED */\r
+#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */\r
+#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */\r
+#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */\r
+//#define RESERVED (0x0400) /* RESERVED */\r
+//#define RESERVED (0x0800) /* RESERVED */\r
+//#define RESERVED (0x1000) /* RESERVED */\r
+//#define RESERVED (0x2000) /* RESERVED */\r
+//#define RESERVED (0x4000) /* RESERVED */\r
+//#define RESERVED (0x8000) /* RESERVED */\r
+\r
+#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */\r
+#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */\r
+#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */\r
+#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */\r
+#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */\r
+#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */\r
+#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */\r
+#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */\r
+#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */\r
+#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */\r
+#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */\r
+#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */\r
+\r
+#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */\r
+#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */\r
+#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */\r
+#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */\r
+#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */\r
+#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */\r
+#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */\r
+#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */\r
+#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */\r
+#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */\r
+#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */\r
+#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */\r
+\r
+#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */\r
+#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */\r
+#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */\r
+#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */\r
+#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */\r
+#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */\r
+#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */\r
+#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */\r
+#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */\r
+#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */\r
+#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */\r
+#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define LFXTOFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */\r
+#define SMCLKOFF (0x0002) /* SMCLK Off */\r
+#define VLOOFF (0x0008) /* VLO Off */\r
+#define LFXTBYPASS (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define LFXTAGCOFF (0x0020) /* LFXT automatic gain control off */\r
+#define LFXTDRIVE0 (0x0040) /* LFXT Drive Level mode Bit 0 */\r
+#define LFXTDRIVE1 (0x0080) /* LFXT Drive Level mode Bit 1 */\r
+#define HFXTOFF (0x0100) /* High Frequency Oscillator disable */\r
+#define HFFREQ0 (0x0400) /* HFXT frequency selection Bit 1 */\r
+#define HFFREQ1 (0x0800) /* HFXT frequency selection Bit 0 */\r
+#define HFXTBYPASS (0x1000) /* HFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define HFXTDRIVE0 (0x4000) /* HFXT Drive Level mode Bit 0 */\r
+#define HFXTDRIVE1 (0x8000) /* HFXT Drive Level mode Bit 1 */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define LFXTOFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */\r
+#define SMCLKOFF_L (0x0002) /* SMCLK Off */\r
+#define VLOOFF_L (0x0008) /* VLO Off */\r
+#define LFXTBYPASS_L (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define LFXTAGCOFF_L (0x0020) /* LFXT automatic gain control off */\r
+#define LFXTDRIVE0_L (0x0040) /* LFXT Drive Level mode Bit 0 */\r
+#define LFXTDRIVE1_L (0x0080) /* LFXT Drive Level mode Bit 1 */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define HFXTOFF_H (0x0001) /* High Frequency Oscillator disable */\r
+#define HFFREQ0_H (0x0004) /* HFXT frequency selection Bit 1 */\r
+#define HFFREQ1_H (0x0008) /* HFXT frequency selection Bit 0 */\r
+#define HFXTBYPASS_H (0x0010) /* HFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define HFXTDRIVE0_H (0x0040) /* HFXT Drive Level mode Bit 0 */\r
+#define HFXTDRIVE1_H (0x0080) /* HFXT Drive Level mode Bit 1 */\r
+\r
+#define LFXTDRIVE_0 (0x0000) /* LFXT Drive Level mode: 0 */\r
+#define LFXTDRIVE_1 (0x0040) /* LFXT Drive Level mode: 1 */\r
+#define LFXTDRIVE_2 (0x0080) /* LFXT Drive Level mode: 2 */\r
+#define LFXTDRIVE_3 (0x00C0) /* LFXT Drive Level mode: 3 */\r
+\r
+#define HFFREQ_0 (0x0000) /* HFXT frequency selection: 0 */\r
+#define HFFREQ_1 (0x0400) /* HFXT frequency selection: 1 */\r
+#define HFFREQ_2 (0x0800) /* HFXT frequency selection: 2 */\r
+#define HFFREQ_3 (0x0C00) /* HFXT frequency selection: 3 */\r
+\r
+#define HFXTDRIVE_0 (0x0000) /* HFXT Drive Level mode: 0 */\r
+#define HFXTDRIVE_1 (0x4000) /* HFXT Drive Level mode: 1 */\r
+#define HFXTDRIVE_2 (0x8000) /* HFXT Drive Level mode: 2 */\r
+#define HFXTDRIVE_3 (0xC000) /* HFXT Drive Level mode: 3 */\r
+\r
+/* CSCTL5 Control Bits */\r
+#define LFXTOFFG (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */\r
+#define HFXTOFFG (0x0002) /* HFXT High Frequency Oscillator Fault Flag */\r
+#define ENSTFCNT1 (0x0040) /* Enable start counter for XT1 */\r
+#define ENSTFCNT2 (0x0080) /* Enable start counter for XT2 */\r
+\r
+/* CSCTL5 Control Bits */\r
+#define LFXTOFFG_L (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */\r
+#define HFXTOFFG_L (0x0002) /* HFXT High Frequency Oscillator Fault Flag */\r
+#define ENSTFCNT1_L (0x0040) /* Enable start counter for XT1 */\r
+#define ENSTFCNT2_L (0x0080) /* Enable start counter for XT2 */\r
+\r
+/* CSCTL6 Control Bits */\r
+#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */\r
+#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */\r
+#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */\r
+#define MODCLKREQEN (0x0008) /* MODOSC Clock Request Enable */\r
+\r
+/* CSCTL6 Control Bits */\r
+#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */\r
+#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */\r
+#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */\r
+#define MODCLKREQEN_L (0x0008) /* MODOSC Clock Request Enable */\r
+\r
+#endif\r
+/************************************************************\r
+* DMA_X\r
+************************************************************/\r
+#ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */\r
+\r
+#define OFS_DMACTL0 (0x0000) /* DMA Module Control 0 */\r
+#define OFS_DMACTL0_L OFS_DMACTL0\r
+#define OFS_DMACTL0_H OFS_DMACTL0+1\r
+#define OFS_DMACTL1 (0x0002) /* DMA Module Control 1 */\r
+#define OFS_DMACTL1_L OFS_DMACTL1\r
+#define OFS_DMACTL1_H OFS_DMACTL1+1\r
+#define OFS_DMACTL2 (0x0004) /* DMA Module Control 2 */\r
+#define OFS_DMACTL2_L OFS_DMACTL2\r
+#define OFS_DMACTL2_H OFS_DMACTL2+1\r
+#define OFS_DMACTL3 (0x0006) /* DMA Module Control 3 */\r
+#define OFS_DMACTL3_L OFS_DMACTL3\r
+#define OFS_DMACTL3_H OFS_DMACTL3+1\r
+#define OFS_DMACTL4 (0x0008) /* DMA Module Control 4 */\r
+#define OFS_DMACTL4_L OFS_DMACTL4\r
+#define OFS_DMACTL4_H OFS_DMACTL4+1\r
+#define OFS_DMAIV (0x000E) /* DMA Interrupt Vector Word */\r
+#define OFS_DMAIV_L OFS_DMAIV\r
+#define OFS_DMAIV_H OFS_DMAIV+1\r
+\r
+#define OFS_DMA0CTL (0x0010) /* DMA Channel 0 Control */\r
+#define OFS_DMA0CTL_L OFS_DMA0CTL\r
+#define OFS_DMA0CTL_H OFS_DMA0CTL+1\r
+#define OFS_DMA0SA (0x0012) /* DMA Channel 0 Source Address */\r
+#define OFS_DMA0DA (0x0016) /* DMA Channel 0 Destination Address */\r
+#define OFS_DMA0SZ (0x001A) /* DMA Channel 0 Transfer Size */\r
+\r
+#define OFS_DMA1CTL (0x0020) /* DMA Channel 1 Control */\r
+#define OFS_DMA1CTL_L OFS_DMA1CTL\r
+#define OFS_DMA1CTL_H OFS_DMA1CTL+1\r
+#define OFS_DMA1SA (0x0022) /* DMA Channel 1 Source Address */\r
+#define OFS_DMA1DA (0x0026) /* DMA Channel 1 Destination Address */\r
+#define OFS_DMA1SZ (0x002A) /* DMA Channel 1 Transfer Size */\r
+\r
+#define OFS_DMA2CTL (0x0030) /* DMA Channel 2 Control */\r
+#define OFS_DMA2CTL_L OFS_DMA2CTL\r
+#define OFS_DMA2CTL_H OFS_DMA2CTL+1\r
+#define OFS_DMA2SA (0x0032) /* DMA Channel 2 Source Address */\r
+#define OFS_DMA2DA (0x0036) /* DMA Channel 2 Destination Address */\r
+#define OFS_DMA2SZ (0x003A) /* DMA Channel 2 Transfer Size */\r
+\r
+/* DMACTL0 Control Bits */\r
+#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */\r
+#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */\r
+#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */\r
+#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */\r
+#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */\r
+#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */\r
+#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */\r
+#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */\r
+#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */\r
+#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */\r
+\r
+/* DMACTL0 Control Bits */\r
+#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */\r
+#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */\r
+#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */\r
+#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */\r
+#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */\r
+\r
+/* DMACTL0 Control Bits */\r
+#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */\r
+#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */\r
+#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */\r
+#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */\r
+#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */\r
+\r
+/* DMACTL01 Control Bits */\r
+#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */\r
+#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */\r
+#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */\r
+#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */\r
+#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */\r
+\r
+/* DMACTL01 Control Bits */\r
+#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */\r
+#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */\r
+#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */\r
+#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */\r
+#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */\r
+\r
+/* DMACTL4 Control Bits */\r
+#define ENNMI (0x0001) /* Enable NMI interruption of DMA */\r
+#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */\r
+#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
+\r
+/* DMACTL4 Control Bits */\r
+#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */\r
+#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */\r
+#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
+\r
+/* DMAxCTL Control Bits */\r
+#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */\r
+#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */\r
+#define DMAIE (0x0004) /* DMA interrupt enable */\r
+#define DMAIFG (0x0008) /* DMA interrupt flag */\r
+#define DMAEN (0x0010) /* DMA enable */\r
+#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */\r
+#define DMASRCBYTE (0x0040) /* DMA source byte */\r
+#define DMADSTBYTE (0x0080) /* DMA destination byte */\r
+#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */\r
+#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */\r
+#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */\r
+#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */\r
+#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */\r
+#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */\r
+#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */\r
+\r
+/* DMAxCTL Control Bits */\r
+#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */\r
+#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */\r
+#define DMAIE_L (0x0004) /* DMA interrupt enable */\r
+#define DMAIFG_L (0x0008) /* DMA interrupt flag */\r
+#define DMAEN_L (0x0010) /* DMA enable */\r
+#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */\r
+#define DMASRCBYTE_L (0x0040) /* DMA source byte */\r
+#define DMADSTBYTE_L (0x0080) /* DMA destination byte */\r
+\r
+/* DMAxCTL Control Bits */\r
+#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */\r
+#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */\r
+#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */\r
+#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */\r
+#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */\r
+#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */\r
+#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */\r
+\r
+#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */\r
+#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */\r
+#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */\r
+#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */\r
+\r
+#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */\r
+#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */\r
+#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */\r
+#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */\r
+\r
+#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */\r
+#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */\r
+#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */\r
+#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */\r
+\r
+#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */\r
+#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */\r
+#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */\r
+#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */\r
+#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */\r
+#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */\r
+#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */\r
+#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */\r
+\r
+/* DMAIV Definitions */\r
+#define DMAIV_NONE (0x0000) /* No Interrupt pending */\r
+#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/\r
+#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/\r
+#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/\r
+\r
+#endif\r
+/************************************************************\r
+* EXTENDED SCAN INTERFACE\r
+************************************************************/\r
+#ifdef __MSP430_HAS_ESI__ /* Definition to show that Module is available */\r
+\r
+#define OFS_ESIDEBUG1 (0x0000) /* ESI debug register 1 */\r
+#define OFS_ESIDEBUG1_L OFS_ESIDEBUG1\r
+#define OFS_ESIDEBUG1_H OFS_ESIDEBUG1+1\r
+#define OFS_ESIDEBUG2 (0x0002) /* ESI debug register 2 */\r
+#define OFS_ESIDEBUG2_L OFS_ESIDEBUG2\r
+#define OFS_ESIDEBUG2_H OFS_ESIDEBUG2+1\r
+#define OFS_ESIDEBUG3 (0x0004) /* ESI debug register 3 */\r
+#define OFS_ESIDEBUG3_L OFS_ESIDEBUG3\r
+#define OFS_ESIDEBUG3_H OFS_ESIDEBUG3+1\r
+#define OFS_ESIDEBUG4 (0x0006) /* ESI debug register 4 */\r
+#define OFS_ESIDEBUG4_L OFS_ESIDEBUG4\r
+#define OFS_ESIDEBUG4_H OFS_ESIDEBUG4+1\r
+#define OFS_ESIDEBUG5 (0x0008) /* ESI debug register 5 */\r
+#define OFS_ESIDEBUG5_L OFS_ESIDEBUG5\r
+#define OFS_ESIDEBUG5_H OFS_ESIDEBUG5+1\r
+#define OFS_ESICNT0 (0x0010) /* ESI PSM counter 0 */\r
+#define OFS_ESICNT0_L OFS_ESICNT0\r
+#define OFS_ESICNT0_H OFS_ESICNT0+1\r
+#define OFS_ESICNT1 (0x0012) /* ESI PSM counter 1 */\r
+#define OFS_ESICNT1_L OFS_ESICNT1\r
+#define OFS_ESICNT1_H OFS_ESICNT1+1\r
+#define OFS_ESICNT2 (0x0014) /* ESI PSM counter 2 */\r
+#define OFS_ESICNT2_L OFS_ESICNT2\r
+#define OFS_ESICNT2_H OFS_ESICNT2+1\r
+#define OFS_ESICNT3 (0x0016) /* ESI oscillator counter register */\r
+#define OFS_ESICNT3_L OFS_ESICNT3\r
+#define OFS_ESICNT3_H OFS_ESICNT3+1\r
+#define OFS_ESIIV (0x001A) /* ESI interrupt vector */\r
+#define OFS_ESIIV_L OFS_ESIIV\r
+#define OFS_ESIIV_H OFS_ESIIV+1\r
+#define OFS_ESIINT1 (0x001C) /* ESI interrupt register 1 */\r
+#define OFS_ESIINT1_L OFS_ESIINT1\r
+#define OFS_ESIINT1_H OFS_ESIINT1+1\r
+#define OFS_ESIINT2 (0x001E) /* ESI interrupt register 2 */\r
+#define OFS_ESIINT2_L OFS_ESIINT2\r
+#define OFS_ESIINT2_H OFS_ESIINT2+1\r
+#define OFS_ESIAFE (0x0020) /* ESI AFE control register */\r
+#define OFS_ESIAFE_L OFS_ESIAFE\r
+#define OFS_ESIAFE_H OFS_ESIAFE+1\r
+#define OFS_ESIPPU (0x0022) /* ESI PPU control register */\r
+#define OFS_ESIPPU_L OFS_ESIPPU\r
+#define OFS_ESIPPU_H OFS_ESIPPU+1\r
+#define OFS_ESITSM (0x0024) /* ESI TSM control register */\r
+#define OFS_ESITSM_L OFS_ESITSM\r
+#define OFS_ESITSM_H OFS_ESITSM+1\r
+#define OFS_ESIPSM (0x0026) /* ESI PSM control register */\r
+#define OFS_ESIPSM_L OFS_ESIPSM\r
+#define OFS_ESIPSM_H OFS_ESIPSM+1\r
+#define OFS_ESIOSC (0x0028) /* ESI oscillator control register*/\r
+#define OFS_ESIOSC_L OFS_ESIOSC\r
+#define OFS_ESIOSC_H OFS_ESIOSC+1\r
+#define OFS_ESICTL (0x002A) /* ESI control register */\r
+#define OFS_ESICTL_L OFS_ESICTL\r
+#define OFS_ESICTL_H OFS_ESICTL+1\r
+#define OFS_ESITHR1 (0x002C) /* ESI PSM Counter Threshold 1 register */\r
+#define OFS_ESITHR1_L OFS_ESITHR1\r
+#define OFS_ESITHR1_H OFS_ESITHR1+1\r
+#define OFS_ESITHR2 (0x002E) /* ESI PSM Counter Threshold 2 register */\r
+#define OFS_ESITHR2_L OFS_ESITHR2\r
+#define OFS_ESITHR2_H OFS_ESITHR2+1\r
+#define OFS_ESIDAC1R0 (0x0040) /* ESI DAC1 register 0 */\r
+#define OFS_ESIDAC1R0_L OFS_ESIDAC1R0\r
+#define OFS_ESIDAC1R0_H OFS_ESIDAC1R0+1\r
+#define OFS_ESIDAC1R1 (0x0042) /* ESI DAC1 register 1 */\r
+#define OFS_ESIDAC1R1_L OFS_ESIDAC1R1\r
+#define OFS_ESIDAC1R1_H OFS_ESIDAC1R1+1\r
+#define OFS_ESIDAC1R2 (0x0044) /* ESI DAC1 register 2 */\r
+#define OFS_ESIDAC1R2_L OFS_ESIDAC1R2\r
+#define OFS_ESIDAC1R2_H OFS_ESIDAC1R2+1\r
+#define OFS_ESIDAC1R3 (0x0046) /* ESI DAC1 register 3 */\r
+#define OFS_ESIDAC1R3_L OFS_ESIDAC1R3\r
+#define OFS_ESIDAC1R3_H OFS_ESIDAC1R3+1\r
+#define OFS_ESIDAC1R4 (0x0048) /* ESI DAC1 register 4 */\r
+#define OFS_ESIDAC1R4_L OFS_ESIDAC1R4\r
+#define OFS_ESIDAC1R4_H OFS_ESIDAC1R4+1\r
+#define OFS_ESIDAC1R5 (0x004A) /* ESI DAC1 register 5 */\r
+#define OFS_ESIDAC1R5_L OFS_ESIDAC1R5\r
+#define OFS_ESIDAC1R5_H OFS_ESIDAC1R5+1\r
+#define OFS_ESIDAC1R6 (0x004C) /* ESI DAC1 register 6 */\r
+#define OFS_ESIDAC1R6_L OFS_ESIDAC1R6\r
+#define OFS_ESIDAC1R6_H OFS_ESIDAC1R6+1\r
+#define OFS_ESIDAC1R7 (0x004E) /* ESI DAC1 register 7 */\r
+#define OFS_ESIDAC1R7_L OFS_ESIDAC1R7\r
+#define OFS_ESIDAC1R7_H OFS_ESIDAC1R7+1\r
+#define OFS_ESIDAC2R0 (0x0050) /* ESI DAC2 register 0 */\r
+#define OFS_ESIDAC2R0_L OFS_ESIDAC2R0\r
+#define OFS_ESIDAC2R0_H OFS_ESIDAC2R0+1\r
+#define OFS_ESIDAC2R1 (0x0052) /* ESI DAC2 register 1 */\r
+#define OFS_ESIDAC2R1_L OFS_ESIDAC2R1\r
+#define OFS_ESIDAC2R1_H OFS_ESIDAC2R1+1\r
+#define OFS_ESIDAC2R2 (0x0054) /* ESI DAC2 register 2 */\r
+#define OFS_ESIDAC2R2_L OFS_ESIDAC2R2\r
+#define OFS_ESIDAC2R2_H OFS_ESIDAC2R2+1\r
+#define OFS_ESIDAC2R3 (0x0056) /* ESI DAC2 register 3 */\r
+#define OFS_ESIDAC2R3_L OFS_ESIDAC2R3\r
+#define OFS_ESIDAC2R3_H OFS_ESIDAC2R3+1\r
+#define OFS_ESIDAC2R4 (0x0058) /* ESI DAC2 register 4 */\r
+#define OFS_ESIDAC2R4_L OFS_ESIDAC2R4\r
+#define OFS_ESIDAC2R4_H OFS_ESIDAC2R4+1\r
+#define OFS_ESIDAC2R5 (0x005A) /* ESI DAC2 register 5 */\r
+#define OFS_ESIDAC2R5_L OFS_ESIDAC2R5\r
+#define OFS_ESIDAC2R5_H OFS_ESIDAC2R5+1\r
+#define OFS_ESIDAC2R6 (0x005C) /* ESI DAC2 register 6 */\r
+#define OFS_ESIDAC2R6_L OFS_ESIDAC2R6\r
+#define OFS_ESIDAC2R6_H OFS_ESIDAC2R6+1\r
+#define OFS_ESIDAC2R7 (0x005E) /* ESI DAC2 register 7 */\r
+#define OFS_ESIDAC2R7_L OFS_ESIDAC2R7\r
+#define OFS_ESIDAC2R7_H OFS_ESIDAC2R7+1\r
+#define OFS_ESITSM0 (0x0060) /* ESI TSM 0 */\r
+#define OFS_ESITSM0_L OFS_ESITSM0\r
+#define OFS_ESITSM0_H OFS_ESITSM0+1\r
+#define OFS_ESITSM1 (0x0062) /* ESI TSM 1 */\r
+#define OFS_ESITSM1_L OFS_ESITSM1\r
+#define OFS_ESITSM1_H OFS_ESITSM1+1\r
+#define OFS_ESITSM2 (0x0064) /* ESI TSM 2 */\r
+#define OFS_ESITSM2_L OFS_ESITSM2\r
+#define OFS_ESITSM2_H OFS_ESITSM2+1\r
+#define OFS_ESITSM3 (0x0066) /* ESI TSM 3 */\r
+#define OFS_ESITSM3_L OFS_ESITSM3\r
+#define OFS_ESITSM3_H OFS_ESITSM3+1\r
+#define OFS_ESITSM4 (0x0068) /* ESI TSM 4 */\r
+#define OFS_ESITSM4_L OFS_ESITSM4\r
+#define OFS_ESITSM4_H OFS_ESITSM4+1\r
+#define OFS_ESITSM5 (0x006A) /* ESI TSM 5 */\r
+#define OFS_ESITSM5_L OFS_ESITSM5\r
+#define OFS_ESITSM5_H OFS_ESITSM5+1\r
+#define OFS_ESITSM6 (0x006C) /* ESI TSM 6 */\r
+#define OFS_ESITSM6_L OFS_ESITSM6\r
+#define OFS_ESITSM6_H OFS_ESITSM6+1\r
+#define OFS_ESITSM7 (0x006E) /* ESI TSM 7 */\r
+#define OFS_ESITSM7_L OFS_ESITSM7\r
+#define OFS_ESITSM7_H OFS_ESITSM7+1\r
+#define OFS_ESITSM8 (0x0070) /* ESI TSM 8 */\r
+#define OFS_ESITSM8_L OFS_ESITSM8\r
+#define OFS_ESITSM8_H OFS_ESITSM8+1\r
+#define OFS_ESITSM9 (0x0072) /* ESI TSM 9 */\r
+#define OFS_ESITSM9_L OFS_ESITSM9\r
+#define OFS_ESITSM9_H OFS_ESITSM9+1\r
+#define OFS_ESITSM10 (0x0074) /* ESI TSM 10 */\r
+#define OFS_ESITSM10_L OFS_ESITSM10\r
+#define OFS_ESITSM10_H OFS_ESITSM10+1\r
+#define OFS_ESITSM11 (0x0076) /* ESI TSM 11 */\r
+#define OFS_ESITSM11_L OFS_ESITSM11\r
+#define OFS_ESITSM11_H OFS_ESITSM11+1\r
+#define OFS_ESITSM12 (0x0078) /* ESI TSM 12 */\r
+#define OFS_ESITSM12_L OFS_ESITSM12\r
+#define OFS_ESITSM12_H OFS_ESITSM12+1\r
+#define OFS_ESITSM13 (0x007A) /* ESI TSM 13 */\r
+#define OFS_ESITSM13_L OFS_ESITSM13\r
+#define OFS_ESITSM13_H OFS_ESITSM13+1\r
+#define OFS_ESITSM14 (0x007C) /* ESI TSM 14 */\r
+#define OFS_ESITSM14_L OFS_ESITSM14\r
+#define OFS_ESITSM14_H OFS_ESITSM14+1\r
+#define OFS_ESITSM15 (0x007E) /* ESI TSM 15 */\r
+#define OFS_ESITSM15_L OFS_ESITSM15\r
+#define OFS_ESITSM15_H OFS_ESITSM15+1\r
+#define OFS_ESITSM16 (0x0080) /* ESI TSM 16 */\r
+#define OFS_ESITSM16_L OFS_ESITSM16\r
+#define OFS_ESITSM16_H OFS_ESITSM16+1\r
+#define OFS_ESITSM17 (0x0082) /* ESI TSM 17 */\r
+#define OFS_ESITSM17_L OFS_ESITSM17\r
+#define OFS_ESITSM17_H OFS_ESITSM17+1\r
+#define OFS_ESITSM18 (0x0084) /* ESI TSM 18 */\r
+#define OFS_ESITSM18_L OFS_ESITSM18\r
+#define OFS_ESITSM18_H OFS_ESITSM18+1\r
+#define OFS_ESITSM19 (0x0086) /* ESI TSM 19 */\r
+#define OFS_ESITSM19_L OFS_ESITSM19\r
+#define OFS_ESITSM19_H OFS_ESITSM19+1\r
+#define OFS_ESITSM20 (0x0088) /* ESI TSM 20 */\r
+#define OFS_ESITSM20_L OFS_ESITSM20\r
+#define OFS_ESITSM20_H OFS_ESITSM20+1\r
+#define OFS_ESITSM21 (0x008A) /* ESI TSM 21 */\r
+#define OFS_ESITSM21_L OFS_ESITSM21\r
+#define OFS_ESITSM21_H OFS_ESITSM21+1\r
+#define OFS_ESITSM22 (0x008C) /* ESI TSM 22 */\r
+#define OFS_ESITSM22_L OFS_ESITSM22\r
+#define OFS_ESITSM22_H OFS_ESITSM22+1\r
+#define OFS_ESITSM23 (0x008E) /* ESI TSM 23 */\r
+#define OFS_ESITSM23_L OFS_ESITSM23\r
+#define OFS_ESITSM23_H OFS_ESITSM23+1\r
+#define OFS_ESITSM24 (0x0090) /* ESI TSM 24 */\r
+#define OFS_ESITSM24_L OFS_ESITSM24\r
+#define OFS_ESITSM24_H OFS_ESITSM24+1\r
+#define OFS_ESITSM25 (0x0092) /* ESI TSM 25 */\r
+#define OFS_ESITSM25_L OFS_ESITSM25\r
+#define OFS_ESITSM25_H OFS_ESITSM25+1\r
+#define OFS_ESITSM26 (0x0094) /* ESI TSM 26 */\r
+#define OFS_ESITSM26_L OFS_ESITSM26\r
+#define OFS_ESITSM26_H OFS_ESITSM26+1\r
+#define OFS_ESITSM27 (0x0096) /* ESI TSM 27 */\r
+#define OFS_ESITSM27_L OFS_ESITSM27\r
+#define OFS_ESITSM27_H OFS_ESITSM27+1\r
+#define OFS_ESITSM28 (0x0098) /* ESI TSM 28 */\r
+#define OFS_ESITSM28_L OFS_ESITSM28\r
+#define OFS_ESITSM28_H OFS_ESITSM28+1\r
+#define OFS_ESITSM29 (0x009A) /* ESI TSM 29 */\r
+#define OFS_ESITSM29_L OFS_ESITSM29\r
+#define OFS_ESITSM29_H OFS_ESITSM29+1\r
+#define OFS_ESITSM30 (0x009C) /* ESI TSM 30 */\r
+#define OFS_ESITSM30_L OFS_ESITSM30\r
+#define OFS_ESITSM30_H OFS_ESITSM30+1\r
+#define OFS_ESITSM31 (0x009E) /* ESI TSM 31 */\r
+#define OFS_ESITSM31_L OFS_ESITSM31\r
+#define OFS_ESITSM31_H OFS_ESITSM31+1\r
+\r
+/* ESIIV Control Bits */\r
+\r
+#define ESIIV_NONE (0x0000) /* No ESI Interrupt Pending */\r
+#define ESIIV_ESIIFG1 (0x0002) /* rising edge of the ESISTOP(tsm) */\r
+#define ESIIV_ESIIFG0 (0x0004) /* ESIOUT0 to ESIOUT3 conditions selected by ESIIFGSETx bits */\r
+#define ESIIV_ESIIFG8 (0x0006) /* ESIOUT4 to ESIOUT7 conditions selected by ESIIFGSET2x bits */\r
+#define ESIIV_ESIIFG3 (0x0008) /* ESICNT1 counter conditions selected with the ESITHR1 and ESITHR2 registers */\r
+#define ESIIV_ESIIFG6 (0x000A) /* PSM transitions to a state with a Q7 bit */\r
+#define ESIIV_ESIIFG5 (0x000C) /* PSM transitions to a state with a Q6 bit */\r
+#define ESIIV_ESIIFG4 (0x000E) /* ESICNT2 counter conditions selected with the ESIIS2x bits */\r
+#define ESIIV_ESIIFG7 (0x0010) /* ESICNT0 counter conditions selected with the ESIIS0x bits */\r
+#define ESIIV_ESIIFG2 (0x0012) /* start of a TSM sequence */\r
+\r
+/* ESIINT1 Control Bits */\r
+#define ESIIFGSET22 (0x8000) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET21 (0x4000) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET20 (0x2000) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET12 (0x1000) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET11 (0x0800) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET10 (0x0400) /* ESIIFG0 interrupt flag source */\r
+#define ESIIE8 (0x0100) /* Interrupt enable */\r
+#define ESIIE7 (0x0080) /* Interrupt enable */\r
+#define ESIIE6 (0x0040) /* Interrupt enable */\r
+#define ESIIE5 (0x0020) /* Interrupt enable */\r
+#define ESIIE4 (0x0010) /* Interrupt enable */\r
+#define ESIIE3 (0x0008) /* Interrupt enable */\r
+#define ESIIE2 (0x0004) /* Interrupt enable */\r
+#define ESIIE1 (0x0002) /* Interrupt enable */\r
+#define ESIIE0 (0x0001) /* Interrupt enable */\r
+\r
+/* ESIINT1 Control Bits */\r
+#define ESIIE7_L (0x0080) /* Interrupt enable */\r
+#define ESIIE6_L (0x0040) /* Interrupt enable */\r
+#define ESIIE5_L (0x0020) /* Interrupt enable */\r
+#define ESIIE4_L (0x0010) /* Interrupt enable */\r
+#define ESIIE3_L (0x0008) /* Interrupt enable */\r
+#define ESIIE2_L (0x0004) /* Interrupt enable */\r
+#define ESIIE1_L (0x0002) /* Interrupt enable */\r
+#define ESIIE0_L (0x0001) /* Interrupt enable */\r
+\r
+/* ESIINT1 Control Bits */\r
+#define ESIIFGSET22_H (0x0080) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET21_H (0x0040) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET20_H (0x0020) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET12_H (0x0010) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET11_H (0x0008) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET10_H (0x0004) /* ESIIFG0 interrupt flag source */\r
+#define ESIIE8_H (0x0001) /* Interrupt enable */\r
+\r
+#define ESIIFGSET2_0 (0x0000) /* ESIIFG8 is set when ESIOUT4 is set */\r
+#define ESIIFGSET2_1 (0x2000) /* ESIIFG8 is set when ESIOUT4 is reset */\r
+#define ESIIFGSET2_2 (0x4000) /* ESIIFG8 is set when ESIOUT5 is set */\r
+#define ESIIFGSET2_3 (0x6000) /* ESIIFG8 is set when ESIOUT5 is reset */\r
+#define ESIIFGSET2_4 (0x8000) /* ESIIFG8 is set when ESIOUT6 is set */\r
+#define ESIIFGSET2_5 (0xA000) /* ESIIFG8 is set when ESIOUT6 is reset */\r
+#define ESIIFGSET2_6 (0xC000) /* ESIIFG8 is set when ESIOUT7 is set */\r
+#define ESIIFGSET2_7 (0xE000) /* ESIIFG8 is set when ESIOUT7 is reset */\r
+#define ESIIFGSET1_0 (0x0000) /* ESIIFG0 is set when ESIOUT0 is set */\r
+#define ESIIFGSET1_1 (0x0400) /* ESIIFG0 is set when ESIOUT0 is reset */\r
+#define ESIIFGSET1_2 (0x0800) /* ESIIFG0 is set when ESIOUT1 is set */\r
+#define ESIIFGSET1_3 (0x0C00) /* ESIIFG0 is set when ESIOUT1 is reset */\r
+#define ESIIFGSET1_4 (0x1000) /* ESIIFG0 is set when ESIOUT2 is set */\r
+#define ESIIFGSET1_5 (0x1400) /* ESIIFG0 is set when ESIOUT2 is reset */\r
+#define ESIIFGSET1_6 (0x1800) /* ESIIFG0 is set when ESIOUT3 is set */\r
+#define ESIIFGSET1_7 (0x1C00) /* ESIIFG0 is set when ESIOUT3 is reset */\r
+\r
+/* ESIINT2 Control Bits */\r
+#define ESIIS21 (0x4000) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS20 (0x2000) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS01 (0x0800) /* SIFIFG7 interrupt flag source */\r
+#define ESIIS00 (0x0400) /* SIFIFG7 interrupt flag source */\r
+#define ESIIFG8 (0x0100) /* ESIIFG8 interrupt pending */\r
+#define ESIIFG7 (0x0080) /* ESIIFG7 interrupt pending */\r
+#define ESIIFG6 (0x0040) /* ESIIFG6 interrupt pending */\r
+#define ESIIFG5 (0x0020) /* ESIIFG5 interrupt pending */\r
+#define ESIIFG4 (0x0010) /* ESIIFG4 interrupt pending */\r
+#define ESIIFG3 (0x0008) /* ESIIFG3 interrupt pending */\r
+#define ESIIFG2 (0x0004) /* ESIIFG2 interrupt pending */\r
+#define ESIIFG1 (0x0002) /* ESIIFG1 interrupt pending */\r
+#define ESIIFG0 (0x0001) /* ESIIFG0 interrupt pending */\r
+\r
+/* ESIINT2 Control Bits */\r
+#define ESIIFG7_L (0x0080) /* ESIIFG7 interrupt pending */\r
+#define ESIIFG6_L (0x0040) /* ESIIFG6 interrupt pending */\r
+#define ESIIFG5_L (0x0020) /* ESIIFG5 interrupt pending */\r
+#define ESIIFG4_L (0x0010) /* ESIIFG4 interrupt pending */\r
+#define ESIIFG3_L (0x0008) /* ESIIFG3 interrupt pending */\r
+#define ESIIFG2_L (0x0004) /* ESIIFG2 interrupt pending */\r
+#define ESIIFG1_L (0x0002) /* ESIIFG1 interrupt pending */\r
+#define ESIIFG0_L (0x0001) /* ESIIFG0 interrupt pending */\r
+\r
+/* ESIINT2 Control Bits */\r
+#define ESIIS21_H (0x0040) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS20_H (0x0020) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS01_H (0x0008) /* SIFIFG7 interrupt flag source */\r
+#define ESIIS00_H (0x0004) /* SIFIFG7 interrupt flag source */\r
+#define ESIIFG8_H (0x0001) /* ESIIFG8 interrupt pending */\r
+\r
+#define ESIIS2_0 (0x0000) /* SIFIFG4 interrupt flag source: SIFCNT2 */\r
+#define ESIIS2_1 (0x2000) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 4 */\r
+#define ESIIS2_2 (0x4000) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 256 */\r
+#define ESIIS2_3 (0x6000) /* SIFIFG4 interrupt flag source: SIFCNT2 decrements from 01h to 00h */\r
+#define ESIIS0_0 (0x0000) /* SIFIFG7 interrupt flag source: SIFCNT0 */\r
+#define ESIIS0_1 (0x0400) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 4 */\r
+#define ESIIS0_2 (0x0800) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 256 */\r
+#define ESIIS0_3 (0x0C00) /* SIFIFG7 interrupt flag source: SIFCNT0 increments from FFFFh to 00h */\r
+\r
+/* ESIAFE Control Bits */\r
+#define ESIDAC2EN (0x0800) /* Enable ESIDAC(tsm) control for DAC in AFE2 */\r
+#define ESICA2EN (0x0400) /* Enable ESICA(tsm) control for comparator in AFE2 */\r
+#define ESICA2INV (0x0200) /* Invert AFE2's comparator output */\r
+#define ESICA1INV (0x0100) /* Invert AFE1's comparator output */\r
+#define ESICA2X (0x0080) /* AFE2's comparator input select */\r
+#define ESICA1X (0x0040) /* AFE1's comparator input select */\r
+#define ESICISEL (0x0020) /* Comparator input select for AFE1 only */\r
+#define ESICACI3 (0x0010) /* Comparator input select for AFE1 only */\r
+#define ESIVSS (0x0008) /* Sample-and-hold ESIVSS select */\r
+#define ESIVCC2 (0x0004) /* Mid-voltage generator */\r
+#define ESISH (0x0002) /* Sample-and-hold enable */\r
+#define ESITEN (0x0001) /* Excitation enable */\r
+\r
+/* ESIAFE Control Bits */\r
+#define ESICA2X_L (0x0080) /* AFE2's comparator input select */\r
+#define ESICA1X_L (0x0040) /* AFE1's comparator input select */\r
+#define ESICISEL_L (0x0020) /* Comparator input select for AFE1 only */\r
+#define ESICACI3_L (0x0010) /* Comparator input select for AFE1 only */\r
+#define ESIVSS_L (0x0008) /* Sample-and-hold ESIVSS select */\r
+#define ESIVCC2_L (0x0004) /* Mid-voltage generator */\r
+#define ESISH_L (0x0002) /* Sample-and-hold enable */\r
+#define ESITEN_L (0x0001) /* Excitation enable */\r
+\r
+/* ESIAFE Control Bits */\r
+#define ESIDAC2EN_H (0x0008) /* Enable ESIDAC(tsm) control for DAC in AFE2 */\r
+#define ESICA2EN_H (0x0004) /* Enable ESICA(tsm) control for comparator in AFE2 */\r
+#define ESICA2INV_H (0x0002) /* Invert AFE2's comparator output */\r
+#define ESICA1INV_H (0x0001) /* Invert AFE1's comparator output */\r
+\r
+/* ESIPPU Control Bits */\r
+#define ESITCHOUT1 (0x0200) /* Latched AFE1 comparator output for test channel 1 */\r
+#define ESITCHOUT0 (0x0100) /* Lachted AFE1 comparator output for test channel 0 */\r
+#define ESIOUT7 (0x0080) /* Latched AFE2 comparator output when ESICH3 input is selected */\r
+#define ESIOUT6 (0x0040) /* Latched AFE2 comparator output when ESICH2 input is selected */\r
+#define ESIOUT5 (0x0020) /* Latched AFE2 comparator output when ESICH1 input is selected */\r
+#define ESIOUT4 (0x0010) /* Latched AFE2 comparator output when ESICH0 input is selected */\r
+#define ESIOUT3 (0x0008) /* Latched AFE1 comparator output when ESICH3 input is selected */\r
+#define ESIOUT2 (0x0004) /* Latched AFE1 comparator output when ESICH2 input is selected */\r
+#define ESIOUT1 (0x0002) /* Latched AFE1 comparator output when ESICH1 input is selected */\r
+#define ESIOUT0 (0x0001) /* Latched AFE1 comparator output when ESICH0 input is selected */\r
+\r
+/* ESIPPU Control Bits */\r
+#define ESIOUT7_L (0x0080) /* Latched AFE2 comparator output when ESICH3 input is selected */\r
+#define ESIOUT6_L (0x0040) /* Latched AFE2 comparator output when ESICH2 input is selected */\r
+#define ESIOUT5_L (0x0020) /* Latched AFE2 comparator output when ESICH1 input is selected */\r
+#define ESIOUT4_L (0x0010) /* Latched AFE2 comparator output when ESICH0 input is selected */\r
+#define ESIOUT3_L (0x0008) /* Latched AFE1 comparator output when ESICH3 input is selected */\r
+#define ESIOUT2_L (0x0004) /* Latched AFE1 comparator output when ESICH2 input is selected */\r
+#define ESIOUT1_L (0x0002) /* Latched AFE1 comparator output when ESICH1 input is selected */\r
+#define ESIOUT0_L (0x0001) /* Latched AFE1 comparator output when ESICH0 input is selected */\r
+\r
+/* ESIPPU Control Bits */\r
+#define ESITCHOUT1_H (0x0002) /* Latched AFE1 comparator output for test channel 1 */\r
+#define ESITCHOUT0_H (0x0001) /* Lachted AFE1 comparator output for test channel 0 */\r
+\r
+/* ESITSM Control Bits */\r
+#define ESICLKAZSEL (0x4000) /* Functionality selection of ESITSMx bit5 */\r
+#define ESITSMTRG1 (0x2000) /* TSM start trigger selection */\r
+#define ESITSMTRG0 (0x1000) /* TSM start trigger selection */\r
+#define ESISTART (0x0800) /* TSM software start trigger */\r
+#define ESITSMRP (0x0400) /* TSM repeat modee */\r
+#define ESIDIV3B2 (0x0200) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B1 (0x0100) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B0 (0x0080) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A2 (0x0040) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A1 (0x0020) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A0 (0x0010) /* TSM start trigger ACLK divider */\r
+#define ESIDIV21 (0x0008) /* ACLK divider */\r
+#define ESIDIV20 (0x0004) /* ACLK divider */\r
+#define ESIDIV11 (0x0002) /* TSM SMCLK divider */\r
+#define ESIDIV10 (0x0001) /* TSM SMCLK divider */\r
+\r
+/* ESITSM Control Bits */\r
+#define ESIDIV3B0_L (0x0080) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A2_L (0x0040) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A1_L (0x0020) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A0_L (0x0010) /* TSM start trigger ACLK divider */\r
+#define ESIDIV21_L (0x0008) /* ACLK divider */\r
+#define ESIDIV20_L (0x0004) /* ACLK divider */\r
+#define ESIDIV11_L (0x0002) /* TSM SMCLK divider */\r
+#define ESIDIV10_L (0x0001) /* TSM SMCLK divider */\r
+\r
+/* ESITSM Control Bits */\r
+#define ESICLKAZSEL_H (0x0040) /* Functionality selection of ESITSMx bit5 */\r
+#define ESITSMTRG1_H (0x0020) /* TSM start trigger selection */\r
+#define ESITSMTRG0_H (0x0010) /* TSM start trigger selection */\r
+#define ESISTART_H (0x0008) /* TSM software start trigger */\r
+#define ESITSMRP_H (0x0004) /* TSM repeat modee */\r
+#define ESIDIV3B2_H (0x0002) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B1_H (0x0001) /* TSM start trigger ACLK divider */\r
+\r
+#define ESITSMTRG_0 (0x0000) /* Halt mode */\r
+#define ESITSMTRG_1 (0x1000) /* TSM start trigger ACLK divider */\r
+#define ESITSMTRG_2 (0x2000) /* Software trigger for TSM */\r
+#define ESITSMTRG_3 (0x3000) /* Either the ACLK divider or the ESISTART biT */\r
+#define ESIDIV3B_0 (0x0000) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_1 (0x0080) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_2 (0x0100) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_3 (0x0180) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_4 (0x0200) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_5 (0x0280) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_6 (0x0300) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_7 (0x0380) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_0 (0x0000) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_1 (0x0010) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_2 (0x0020) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_3 (0x0030) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_4 (0x0040) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_5 (0x0050) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_6 (0x0060) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_7 (0x0070) /* TSM start trigger ACLK divider */\r
+#define ESIDIV2_0 (0x0000) /* ACLK divider mode: 0 */\r
+#define ESIDIV2_1 (0x0004) /* ACLK divider mode: 1 */\r
+#define ESIDIV2_2 (0x0008) /* ACLK divider mode: 2 */\r
+#define ESIDIV2_3 (0x000C) /* ACLK divider mode: 3 */\r
+#define ESIDIV2__1 (0x0000) /* ACLK divider = /1 */\r
+#define ESIDIV2__2 (0x0004) /* ACLK divider = /2 */\r
+#define ESIDIV2__4 (0x0008) /* ACLK divider = /4 */\r
+#define ESIDIV2__8 (0x000C) /* ACLK divider = /8 */\r
+#define ESIDIV1_0 (0x0000) /* TSM SMCLK/ESIOSC divider mode: 0 */\r
+#define ESIDIV1_1 (0x0001) /* TSM SMCLK/ESIOSC divider mode: 1 */\r
+#define ESIDIV1_2 (0x0002) /* TSM SMCLK/ESIOSC divider mode: 2 */\r
+#define ESIDIV1_3 (0x0003) /* TSM SMCLK/ESIOSC divider mode: 3 */\r
+#define ESIDIV1__1 (0x0000) /* TSM SMCLK/ESIOSC divider = /1 */\r
+#define ESIDIV1__2 (0x0001) /* TSM SMCLK/ESIOSC divider = /2 */\r
+#define ESIDIV1__4 (0x0002) /* TSM SMCLK/ESIOSC divider = /4 */\r
+#define ESIDIV1__8 (0x0003) /* TSM SMCLK/ESIOSC divider = /8 */\r
+\r
+/* ESIPSM Control Bits */\r
+#define ESICNT2RST (0x8000) /* ESI Counter 2 reset */\r
+#define ESICNT1RST (0x4000) /* ESI Counter 1 reset */\r
+#define ESICNT0RST (0x2000) /* ESI Counter 0 reset */\r
+#define ESITEST4SEL1 (0x0200) /* Output signal selection for SIFTEST4 pin */\r
+#define ESITEST4SEL0 (0x0100) /* Output signal selection for SIFTEST4 pin */\r
+#define ESIV2SEL (0x0080) /* Source Selection for V2 bit*/\r
+#define ESICNT2EN (0x0020) /* ESICNT2 enable (down counter) */\r
+#define ESICNT1EN (0x0010) /* ESICNT1 enable (up/down counter) */\r
+#define ESICNT0EN (0x0008) /* ESICNT0 enable (up counter) */\r
+#define ESIQ7TRG (0x0004) /* Enabling to use Q7 as trigger for a TSM sequence */\r
+#define ESIQ6EN (0x0001) /* Q6 enable */\r
+\r
+/* ESIPSM Control Bits */\r
+#define ESIV2SEL_L (0x0080) /* Source Selection for V2 bit*/\r
+#define ESICNT2EN_L (0x0020) /* ESICNT2 enable (down counter) */\r
+#define ESICNT1EN_L (0x0010) /* ESICNT1 enable (up/down counter) */\r
+#define ESICNT0EN_L (0x0008) /* ESICNT0 enable (up counter) */\r
+#define ESIQ7TRG_L (0x0004) /* Enabling to use Q7 as trigger for a TSM sequence */\r
+#define ESIQ6EN_L (0x0001) /* Q6 enable */\r
+\r
+/* ESIPSM Control Bits */\r
+#define ESICNT2RST_H (0x0080) /* ESI Counter 2 reset */\r
+#define ESICNT1RST_H (0x0040) /* ESI Counter 1 reset */\r
+#define ESICNT0RST_H (0x0020) /* ESI Counter 0 reset */\r
+#define ESITEST4SEL1_H (0x0002) /* Output signal selection for SIFTEST4 pin */\r
+#define ESITEST4SEL0_H (0x0001) /* Output signal selection for SIFTEST4 pin */\r
+\r
+#define ESITEST4SEL_0 (0x0000) /* Q1 signal from PSM table */\r
+#define ESITEST4SEL_1 (0x0100) /* Q2 signal from PSM table */\r
+#define ESITEST4SEL_2 (0x0200) /* TSM clock signal from Timing State Machine */\r
+#define ESITEST4SEL_3 (0x0300) /* AFE1's comparator output signal Comp1Out */\r
+\r
+/* ESIOSC Control Bits */\r
+#define ESICLKFQ5 (0x2000) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ4 (0x1000) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ3 (0x0800) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ2 (0x0400) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ1 (0x0200) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ0 (0x0100) /* Internal oscillator frequency adjust */\r
+#define ESICLKGON (0x0002) /* Internal oscillator control */\r
+#define ESIHFSEL (0x0001) /* Internal oscillator enable */\r
+\r
+/* ESIOSC Control Bits */\r
+#define ESICLKGON_L (0x0002) /* Internal oscillator control */\r
+#define ESIHFSEL_L (0x0001) /* Internal oscillator enable */\r
+\r
+/* ESIOSC Control Bits */\r
+#define ESICLKFQ5_H (0x0020) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ4_H (0x0010) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ3_H (0x0008) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ2_H (0x0004) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ1_H (0x0002) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ0_H (0x0001) /* Internal oscillator frequency adjust */\r
+\r
+/* ESICTL Control Bits */\r
+#define ESIS3SEL2 (0x8000) /* PPUS3 source select */\r
+#define ESIS3SEL1 (0x4000) /* PPUS3 source select */\r
+#define ESIS3SEL0 (0x2000) /* PPUS3 source select */\r
+#define ESIS2SEL2 (0x1000) /* PPUS2 source select */\r
+#define ESIS2SEL1 (0x0800) /* PPUS2 source select */\r
+#define ESIS2SEL0 (0x0400) /* PPUS2 source select */\r
+#define ESIS1SEL2 (0x0200) /* PPUS1 source select */\r
+#define ESIS1SEL1 (0x0100) /* PPUS1 source select */\r
+#define ESIS1SEL0 (0x0080) /* PPUS1 source select */\r
+#define ESITCH11 (0x0040) /* select the comparator input for test channel 1 */\r
+#define ESITCH10 (0x0020) /* select the comparator input for test channel 1 */\r
+#define ESITCH01 (0x0010) /* select the comparator input for test channel 0 */\r
+#define ESITCH00 (0x0008) /* select the comparator input for test channel 0 */\r
+#define ESICS (0x0004) /* Comparator output/Timer_A input selection */\r
+#define ESITESTD (0x0002) /* Test cycle insertion */\r
+#define ESIEN (0x0001) /* Extended Scan interface enable */\r
+\r
+/* ESICTL Control Bits */\r
+#define ESIS1SEL0_L (0x0080) /* PPUS1 source select */\r
+#define ESITCH11_L (0x0040) /* select the comparator input for test channel 1 */\r
+#define ESITCH10_L (0x0020) /* select the comparator input for test channel 1 */\r
+#define ESITCH01_L (0x0010) /* select the comparator input for test channel 0 */\r
+#define ESITCH00_L (0x0008) /* select the comparator input for test channel 0 */\r
+#define ESICS_L (0x0004) /* Comparator output/Timer_A input selection */\r
+#define ESITESTD_L (0x0002) /* Test cycle insertion */\r
+#define ESIEN_L (0x0001) /* Extended Scan interface enable */\r
+\r
+/* ESICTL Control Bits */\r
+#define ESIS3SEL2_H (0x0080) /* PPUS3 source select */\r
+#define ESIS3SEL1_H (0x0040) /* PPUS3 source select */\r
+#define ESIS3SEL0_H (0x0020) /* PPUS3 source select */\r
+#define ESIS2SEL2_H (0x0010) /* PPUS2 source select */\r
+#define ESIS2SEL1_H (0x0008) /* PPUS2 source select */\r
+#define ESIS2SEL0_H (0x0004) /* PPUS2 source select */\r
+#define ESIS1SEL2_H (0x0002) /* PPUS1 source select */\r
+#define ESIS1SEL1_H (0x0001) /* PPUS1 source select */\r
+\r
+#define ESIS3SEL_0 (0x0000) /* ESIOUT0 is the PPUS3 source */\r
+#define ESIS3SEL_1 (0x2000) /* ESIOUT1 is the PPUS3 source */\r
+#define ESIS3SEL_2 (0x4000) /* ESIOUT2 is the PPUS3 source */\r
+#define ESIS3SEL_3 (0x6000) /* ESIOUT3 is the PPUS3 source */\r
+#define ESIS3SEL_4 (0x8000) /* ESIOUT4 is the PPUS3 source */\r
+#define ESIS3SEL_5 (0xA000) /* ESIOUT5 is the PPUS3 source */\r
+#define ESIS3SEL_6 (0xC000) /* ESIOUT6 is the PPUS3 source */\r
+#define ESIS3SEL_7 (0xE000) /* ESIOUT7 is the PPUS3 source */\r
+#define ESIS2SEL_0 (0x0000) /* ESIOUT0 is the PPUS2 source */\r
+#define ESIS2SEL_1 (0x0400) /* ESIOUT1 is the PPUS2 source */\r
+#define ESIS2SEL_2 (0x0800) /* ESIOUT2 is the PPUS2 source */\r
+#define ESIS2SEL_3 (0x0C00) /* ESIOUT3 is the PPUS2 source */\r
+#define ESIS2SEL_4 (0x1000) /* ESIOUT4 is the PPUS2 source */\r
+#define ESIS2SEL_5 (0x1400) /* ESIOUT5 is the PPUS2 source */\r
+#define ESIS2SEL_6 (0x1800) /* ESIOUT6 is the PPUS2 source */\r
+#define ESIS2SEL_7 (0x1C00) /* ESIOUT7 is the PPUS2 source */\r
+#define ESIS1SEL_0 (0x0000) /* ESIOUT0 is the PPUS1 source */\r
+#define ESIS1SEL_1 (0x0080) /* ESIOUT1 is the PPUS1 source */\r
+#define ESIS1SEL_2 (0x0100) /* ESIOUT2 is the PPUS1 source */\r
+#define ESIS1SEL_3 (0x0180) /* ESIOUT3 is the PPUS1 source */\r
+#define ESIS1SEL_4 (0x0200) /* ESIOUT4 is the PPUS1 source */\r
+#define ESIS1SEL_5 (0x0280) /* ESIOUT5 is the PPUS1 source */\r
+#define ESIS1SEL_6 (0x0300) /* ESIOUT6 is the PPUS1 source */\r
+#define ESIS1SEL_7 (0x0380) /* ESIOUT7 is the PPUS1 source */\r
+#define ESITCH1_0 (0x0000) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */\r
+#define ESITCH1_1 (0x0400) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */\r
+#define ESITCH1_2 (0x0800) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */\r
+#define ESITCH1_3 (0x0C00) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */\r
+#define ESITCH0_0 (0x0000) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */\r
+#define ESITCH0_1 (0x0008) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */\r
+#define ESITCH0_2 (0x0010) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */\r
+#define ESITCH0_3 (0x0018) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */\r
+\r
+/* Timing State Machine Control Bits */\r
+#define ESIREPEAT4 (0x8000) /* These bits together with the ESICLK bit configure the duration of this state */\r
+#define ESIREPEAT3 (0x4000) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */\r
+#define ESIREPEAT2 (0x2000) /* */\r
+#define ESIREPEAT1 (0x1000) /* */\r
+#define ESIREPEAT0 (0x0800) /* */\r
+#define ESICLK (0x0400) /* This bit selects the clock source for the TSM */\r
+#define ESISTOP (0x0200) /* This bit indicates the end of the TSM sequence */\r
+#define ESIDAC (0x0100) /* TSM DAC on */\r
+#define ESITESTS1 (0x0080) /* TSM test cycle control */\r
+#define ESIRSON (0x0040) /* Internal output latches enabled */\r
+#define ESICLKON (0x0020) /* High-frequency clock on */\r
+#define ESICA (0x0010) /* TSM comparator on */\r
+#define ESIEX (0x0008) /* Excitation and sample-and-hold */\r
+#define ESILCEN (0x0004) /* LC enable */\r
+#define ESICH1 (0x0002) /* Input channel select */\r
+#define ESICH0 (0x0001) /* Input channel select */\r
+\r
+/* Timing State Machine Control Bits */\r
+#define ESITESTS1_L (0x0080) /* TSM test cycle control */\r
+#define ESIRSON_L (0x0040) /* Internal output latches enabled */\r
+#define ESICLKON_L (0x0020) /* High-frequency clock on */\r
+#define ESICA_L (0x0010) /* TSM comparator on */\r
+#define ESIEX_L (0x0008) /* Excitation and sample-and-hold */\r
+#define ESILCEN_L (0x0004) /* LC enable */\r
+#define ESICH1_L (0x0002) /* Input channel select */\r
+#define ESICH0_L (0x0001) /* Input channel select */\r
+\r
+/* Timing State Machine Control Bits */\r
+#define ESIREPEAT4_H (0x0080) /* These bits together with the ESICLK bit configure the duration of this state */\r
+#define ESIREPEAT3_H (0x0040) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */\r
+#define ESIREPEAT2_H (0x0020) /* */\r
+#define ESIREPEAT1_H (0x0010) /* */\r
+#define ESIREPEAT0_H (0x0008) /* */\r
+#define ESICLK_H (0x0004) /* This bit selects the clock source for the TSM */\r
+#define ESISTOP_H (0x0002) /* This bit indicates the end of the TSM sequence */\r
+#define ESIDAC_H (0x0001) /* TSM DAC on */\r
+\r
+#define ESICAAZ (0x0020) /* Comparator Offset calibration annulation */\r
+\r
+#define ESIREPEAT_0 (0x0000) /* These bits configure the duration of this state */\r
+#define ESIREPEAT_1 (0x0800) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */\r
+#define ESIREPEAT_2 (0x1000)\r
+#define ESIREPEAT_3 (0x1800)\r
+#define ESIREPEAT_4 (0x2000)\r
+#define ESIREPEAT_5 (0x2800)\r
+#define ESIREPEAT_6 (0x3000)\r
+#define ESIREPEAT_7 (0x3800)\r
+#define ESIREPEAT_8 (0x4000)\r
+#define ESIREPEAT_9 (0x4800)\r
+#define ESIREPEAT_10 (0x5000)\r
+#define ESIREPEAT_11 (0x5800)\r
+#define ESIREPEAT_12 (0x6000)\r
+#define ESIREPEAT_13 (0x6800)\r
+#define ESIREPEAT_14 (0x7000)\r
+#define ESIREPEAT_15 (0x7800)\r
+#define ESIREPEAT_16 (0x8000)\r
+#define ESIREPEAT_17 (0x8800)\r
+#define ESIREPEAT_18 (0x9000)\r
+#define ESIREPEAT_19 (0x9800)\r
+#define ESIREPEAT_20 (0xA000)\r
+#define ESIREPEAT_21 (0xA800)\r
+#define ESIREPEAT_22 (0xB000)\r
+#define ESIREPEAT_23 (0xB800)\r
+#define ESIREPEAT_24 (0xC000)\r
+#define ESIREPEAT_25 (0xC800)\r
+#define ESIREPEAT_26 (0xD000)\r
+#define ESIREPEAT_27 (0xD800)\r
+#define ESIREPEAT_28 (0xE000)\r
+#define ESIREPEAT_29 (0xE800)\r
+#define ESIREPEAT_30 (0xF000)\r
+#define ESIREPEAT_31 (0xF800)\r
+#define ESICH_0 (0x0000) /* Input channel select: ESICH0 */\r
+#define ESICH_1 (0x0001) /* Input channel select: ESICH1 */\r
+#define ESICH_2 (0x0002) /* Input channel select: ESICH2 */\r
+#define ESICH_3 (0x0003) /* Input channel select: ESICH3 */\r
+#endif\r
+/************************************************************\r
+* EXTENDED SCAN INTERFACE RAM\r
+************************************************************/\r
+#ifdef __MSP430_HAS_ESI_RAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_ESIRAM0 (0x0000) /* ESI RAM 0 */\r
+#define OFS_ESIRAM1 (0x0001) /* ESI RAM 1 */\r
+#define OFS_ESIRAM2 (0x0002) /* ESI RAM 2 */\r
+#define OFS_ESIRAM3 (0x0003) /* ESI RAM 3 */\r
+#define OFS_ESIRAM4 (0x0004) /* ESI RAM 4 */\r
+#define OFS_ESIRAM5 (0x0005) /* ESI RAM 5 */\r
+#define OFS_ESIRAM6 (0x0006) /* ESI RAM 6 */\r
+#define OFS_ESIRAM7 (0x0007) /* ESI RAM 7 */\r
+#define OFS_ESIRAM8 (0x0008) /* ESI RAM 8 */\r
+#define OFS_ESIRAM9 (0x0009) /* ESI RAM 9 */\r
+#define OFS_ESIRAM10 (0x000A) /* ESI RAM 10 */\r
+#define OFS_ESIRAM11 (0x000B) /* ESI RAM 11 */\r
+#define OFS_ESIRAM12 (0x000C) /* ESI RAM 12 */\r
+#define OFS_ESIRAM13 (0x000D) /* ESI RAM 13 */\r
+#define OFS_ESIRAM14 (0x000E) /* ESI RAM 14 */\r
+#define OFS_ESIRAM15 (0x000F) /* ESI RAM 15 */\r
+#define OFS_ESIRAM16 (0x0010) /* ESI RAM 16 */\r
+#define OFS_ESIRAM17 (0x0011) /* ESI RAM 17 */\r
+#define OFS_ESIRAM18 (0x0012) /* ESI RAM 18 */\r
+#define OFS_ESIRAM19 (0x0013) /* ESI RAM 19 */\r
+#define OFS_ESIRAM20 (0x0014) /* ESI RAM 20 */\r
+#define OFS_ESIRAM21 (0x0015) /* ESI RAM 21 */\r
+#define OFS_ESIRAM22 (0x0016) /* ESI RAM 22 */\r
+#define OFS_ESIRAM23 (0x0017) /* ESI RAM 23 */\r
+#define OFS_ESIRAM24 (0x0018) /* ESI RAM 24 */\r
+#define OFS_ESIRAM25 (0x0019) /* ESI RAM 25 */\r
+#define OFS_ESIRAM26 (0x001A) /* ESI RAM 26 */\r
+#define OFS_ESIRAM27 (0x001B) /* ESI RAM 27 */\r
+#define OFS_ESIRAM28 (0x001C) /* ESI RAM 28 */\r
+#define OFS_ESIRAM29 (0x001D) /* ESI RAM 29 */\r
+#define OFS_ESIRAM30 (0x001E) /* ESI RAM 30 */\r
+#define OFS_ESIRAM31 (0x001F) /* ESI RAM 31 */\r
+#define OFS_ESIRAM32 (0x0020) /* ESI RAM 32 */\r
+#define OFS_ESIRAM33 (0x0021) /* ESI RAM 33 */\r
+#define OFS_ESIRAM34 (0x0022) /* ESI RAM 34 */\r
+#define OFS_ESIRAM35 (0x0023) /* ESI RAM 35 */\r
+#define OFS_ESIRAM36 (0x0024) /* ESI RAM 36 */\r
+#define OFS_ESIRAM37 (0x0025) /* ESI RAM 37 */\r
+#define OFS_ESIRAM38 (0x0026) /* ESI RAM 38 */\r
+#define OFS_ESIRAM39 (0x0027) /* ESI RAM 39 */\r
+#define OFS_ESIRAM40 (0x0028) /* ESI RAM 40 */\r
+#define OFS_ESIRAM41 (0x0029) /* ESI RAM 41 */\r
+#define OFS_ESIRAM42 (0x002A) /* ESI RAM 42 */\r
+#define OFS_ESIRAM43 (0x002B) /* ESI RAM 43 */\r
+#define OFS_ESIRAM44 (0x002C) /* ESI RAM 44 */\r
+#define OFS_ESIRAM45 (0x002D) /* ESI RAM 45 */\r
+#define OFS_ESIRAM46 (0x002E) /* ESI RAM 46 */\r
+#define OFS_ESIRAM47 (0x002F) /* ESI RAM 47 */\r
+#define OFS_ESIRAM48 (0x0030) /* ESI RAM 48 */\r
+#define OFS_ESIRAM49 (0x0031) /* ESI RAM 49 */\r
+#define OFS_ESIRAM50 (0x0032) /* ESI RAM 50 */\r
+#define OFS_ESIRAM51 (0x0033) /* ESI RAM 51 */\r
+#define OFS_ESIRAM52 (0x0034) /* ESI RAM 52 */\r
+#define OFS_ESIRAM53 (0x0035) /* ESI RAM 53 */\r
+#define OFS_ESIRAM54 (0x0036) /* ESI RAM 54 */\r
+#define OFS_ESIRAM55 (0x0037) /* ESI RAM 55 */\r
+#define OFS_ESIRAM56 (0x0038) /* ESI RAM 56 */\r
+#define OFS_ESIRAM57 (0x0039) /* ESI RAM 57 */\r
+#define OFS_ESIRAM58 (0x003A) /* ESI RAM 58 */\r
+#define OFS_ESIRAM59 (0x003B) /* ESI RAM 59 */\r
+#define OFS_ESIRAM60 (0x003C) /* ESI RAM 60 */\r
+#define OFS_ESIRAM61 (0x003D) /* ESI RAM 61 */\r
+#define OFS_ESIRAM62 (0x003E) /* ESI RAM 62 */\r
+#define OFS_ESIRAM63 (0x003F) /* ESI RAM 63 */\r
+#define OFS_ESIRAM64 (0x0040) /* ESI RAM 64 */\r
+#define OFS_ESIRAM65 (0x0041) /* ESI RAM 65 */\r
+#define OFS_ESIRAM66 (0x0042) /* ESI RAM 66 */\r
+#define OFS_ESIRAM67 (0x0043) /* ESI RAM 67 */\r
+#define OFS_ESIRAM68 (0x0044) /* ESI RAM 68 */\r
+#define OFS_ESIRAM69 (0x0045) /* ESI RAM 69 */\r
+#define OFS_ESIRAM70 (0x0046) /* ESI RAM 70 */\r
+#define OFS_ESIRAM71 (0x0047) /* ESI RAM 71 */\r
+#define OFS_ESIRAM72 (0x0048) /* ESI RAM 72 */\r
+#define OFS_ESIRAM73 (0x0049) /* ESI RAM 73 */\r
+#define OFS_ESIRAM74 (0x004A) /* ESI RAM 74 */\r
+#define OFS_ESIRAM75 (0x004B) /* ESI RAM 75 */\r
+#define OFS_ESIRAM76 (0x004C) /* ESI RAM 76 */\r
+#define OFS_ESIRAM77 (0x004D) /* ESI RAM 77 */\r
+#define OFS_ESIRAM78 (0x004E) /* ESI RAM 78 */\r
+#define OFS_ESIRAM79 (0x004F) /* ESI RAM 79 */\r
+#define OFS_ESIRAM80 (0x0050) /* ESI RAM 80 */\r
+#define OFS_ESIRAM81 (0x0051) /* ESI RAM 81 */\r
+#define OFS_ESIRAM82 (0x0052) /* ESI RAM 82 */\r
+#define OFS_ESIRAM83 (0x0053) /* ESI RAM 83 */\r
+#define OFS_ESIRAM84 (0x0054) /* ESI RAM 84 */\r
+#define OFS_ESIRAM85 (0x0055) /* ESI RAM 85 */\r
+#define OFS_ESIRAM86 (0x0056) /* ESI RAM 86 */\r
+#define OFS_ESIRAM87 (0x0057) /* ESI RAM 87 */\r
+#define OFS_ESIRAM88 (0x0058) /* ESI RAM 88 */\r
+#define OFS_ESIRAM89 (0x0059) /* ESI RAM 89 */\r
+#define OFS_ESIRAM90 (0x005A) /* ESI RAM 90 */\r
+#define OFS_ESIRAM91 (0x005B) /* ESI RAM 91 */\r
+#define OFS_ESIRAM92 (0x005C) /* ESI RAM 92 */\r
+#define OFS_ESIRAM93 (0x005D) /* ESI RAM 93 */\r
+#define OFS_ESIRAM94 (0x005E) /* ESI RAM 94 */\r
+#define OFS_ESIRAM95 (0x005F) /* ESI RAM 95 */\r
+#define OFS_ESIRAM96 (0x0060) /* ESI RAM 96 */\r
+#define OFS_ESIRAM97 (0x0061) /* ESI RAM 97 */\r
+#define OFS_ESIRAM98 (0x0062) /* ESI RAM 98 */\r
+#define OFS_ESIRAM99 (0x0063) /* ESI RAM 99 */\r
+#define OFS_ESIRAM100 (0x0064) /* ESI RAM 100 */\r
+#define OFS_ESIRAM101 (0x0065) /* ESI RAM 101 */\r
+#define OFS_ESIRAM102 (0x0066) /* ESI RAM 102 */\r
+#define OFS_ESIRAM103 (0x0067) /* ESI RAM 103 */\r
+#define OFS_ESIRAM104 (0x0068) /* ESI RAM 104 */\r
+#define OFS_ESIRAM105 (0x0069) /* ESI RAM 105 */\r
+#define OFS_ESIRAM106 (0x006A) /* ESI RAM 106 */\r
+#define OFS_ESIRAM107 (0x006B) /* ESI RAM 107 */\r
+#define OFS_ESIRAM108 (0x006C) /* ESI RAM 108 */\r
+#define OFS_ESIRAM109 (0x006D) /* ESI RAM 109 */\r
+#define OFS_ESIRAM110 (0x006E) /* ESI RAM 110 */\r
+#define OFS_ESIRAM111 (0x006F) /* ESI RAM 111 */\r
+#define OFS_ESIRAM112 (0x0070) /* ESI RAM 112 */\r
+#define OFS_ESIRAM113 (0x0071) /* ESI RAM 113 */\r
+#define OFS_ESIRAM114 (0x0072) /* ESI RAM 114 */\r
+#define OFS_ESIRAM115 (0x0073) /* ESI RAM 115 */\r
+#define OFS_ESIRAM116 (0x0074) /* ESI RAM 116 */\r
+#define OFS_ESIRAM117 (0x0075) /* ESI RAM 117 */\r
+#define OFS_ESIRAM118 (0x0076) /* ESI RAM 118 */\r
+#define OFS_ESIRAM119 (0x0077) /* ESI RAM 119 */\r
+#define OFS_ESIRAM120 (0x0078) /* ESI RAM 120 */\r
+#define OFS_ESIRAM121 (0x0079) /* ESI RAM 121 */\r
+#define OFS_ESIRAM122 (0x007A) /* ESI RAM 122 */\r
+#define OFS_ESIRAM123 (0x007B) /* ESI RAM 123 */\r
+#define OFS_ESIRAM124 (0x007C) /* ESI RAM 124 */\r
+#define OFS_ESIRAM125 (0x007D) /* ESI RAM 125 */\r
+#define OFS_ESIRAM126 (0x007E) /* ESI RAM 126 */\r
+#define OFS_ESIRAM127 (0x007F) /* ESI RAM 127 */\r
+#endif\r
+/*************************************************************\r
+* FRAM Memory\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_FRAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_FRCTL0 (0x0000) /* FRAM Controller Control 0 */\r
+#define OFS_FRCTL0_L OFS_FRCTL0\r
+#define OFS_FRCTL0_H OFS_FRCTL0+1\r
+#define OFS_GCCTL0 (0x0004) /* General Control 0 */\r
+#define OFS_GCCTL0_L OFS_GCCTL0\r
+#define OFS_GCCTL0_H OFS_GCCTL0+1\r
+#define OFS_GCCTL1 (0x0006) /* General Control 1 */\r
+#define OFS_GCCTL1_L OFS_GCCTL1\r
+#define OFS_GCCTL1_H OFS_GCCTL1+1\r
+\r
+#define FRCTLPW (0xA500) /* FRAM password for write */\r
+#define FRPW (0x9600) /* FRAM password returned by read */\r
+#define FWPW (0xA500) /* FRAM password for write */\r
+#define FXPW (0x3300) /* for use with XOR instruction */\r
+\r
+/* FRCTL0 Control Bits */\r
+//#define RESERVED (0x0001) /* RESERVED */\r
+//#define RESERVED (0x0002) /* RESERVED */\r
+//#define RESERVED (0x0004) /* RESERVED */\r
+#define NWAITS0 (0x0010) /* FRAM Wait state control Bit: 0 */\r
+#define NWAITS1 (0x0020) /* FRAM Wait state control Bit: 1 */\r
+#define NWAITS2 (0x0040) /* FRAM Wait state control Bit: 2 */\r
+//#define RESERVED (0x0080) /* RESERVED */\r
+\r
+/* FRCTL0 Control Bits */\r
+//#define RESERVED (0x0001) /* RESERVED */\r
+//#define RESERVED (0x0002) /* RESERVED */\r
+//#define RESERVED (0x0004) /* RESERVED */\r
+#define NWAITS0_L (0x0010) /* FRAM Wait state control Bit: 0 */\r
+#define NWAITS1_L (0x0020) /* FRAM Wait state control Bit: 1 */\r
+#define NWAITS2_L (0x0040) /* FRAM Wait state control Bit: 2 */\r
+//#define RESERVED (0x0080) /* RESERVED */\r
+\r
+#define NWAITS_0 (0x0000) /* FRAM Wait state control: 0 */\r
+#define NWAITS_1 (0x0010) /* FRAM Wait state control: 1 */\r
+#define NWAITS_2 (0x0020) /* FRAM Wait state control: 2 */\r
+#define NWAITS_3 (0x0030) /* FRAM Wait state control: 3 */\r
+#define NWAITS_4 (0x0040) /* FRAM Wait state control: 4 */\r
+#define NWAITS_5 (0x0050) /* FRAM Wait state control: 5 */\r
+#define NWAITS_6 (0x0060) /* FRAM Wait state control: 6 */\r
+#define NWAITS_7 (0x0070) /* FRAM Wait state control: 7 */\r
+\r
+/* Legacy Defines */\r
+#define NAUTO (0x0008) /* FRAM Disables the wait state generator (obsolete on Rev.E and later)*/\r
+#define NACCESS0 (0x0010) /* FRAM Wait state Generator Access Time control Bit: 0 */\r
+#define NACCESS1 (0x0020) /* FRAM Wait state Generator Access Time control Bit: 1 */\r
+#define NACCESS2 (0x0040) /* FRAM Wait state Generator Access Time control Bit: 2 */\r
+#define NACCESS_0 (0x0000) /* FRAM Wait state Generator Access Time control: 0 */\r
+#define NACCESS_1 (0x0010) /* FRAM Wait state Generator Access Time control: 1 */\r
+#define NACCESS_2 (0x0020) /* FRAM Wait state Generator Access Time control: 2 */\r
+#define NACCESS_3 (0x0030) /* FRAM Wait state Generator Access Time control: 3 */\r
+#define NACCESS_4 (0x0040) /* FRAM Wait state Generator Access Time control: 4 */\r
+#define NACCESS_5 (0x0050) /* FRAM Wait state Generator Access Time control: 5 */\r
+#define NACCESS_6 (0x0060) /* FRAM Wait state Generator Access Time control: 6 */\r
+#define NACCESS_7 (0x0070) /* FRAM Wait state Generator Access Time control: 7 */\r
+\r
+/* GCCTL0 Control Bits */\r
+//#define RESERVED (0x0001) /* RESERVED */\r
+#define FRLPMPWR (0x0002) /* FRAM Enable FRAM auto power up after LPM */\r
+#define FRPWR (0x0004) /* FRAM Power Control */\r
+#define ACCTEIE (0x0008) /* Enable NMI event if Access time error occurs */\r
+//#define RESERVED (0x0010) /* RESERVED */\r
+#define CBDIE (0x0020) /* Enable NMI event if correctable bit error detected */\r
+#define UBDIE (0x0040) /* Enable NMI event if uncorrectable bit error detected */\r
+#define UBDRSTEN (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */\r
+\r
+/* GCCTL0 Control Bits */\r
+//#define RESERVED (0x0001) /* RESERVED */\r
+#define FRLPMPWR_L (0x0002) /* FRAM Enable FRAM auto power up after LPM */\r
+#define FRPWR_L (0x0004) /* FRAM Power Control */\r
+#define ACCTEIE_L (0x0008) /* Enable NMI event if Access time error occurs */\r
+//#define RESERVED (0x0010) /* RESERVED */\r
+#define CBDIE_L (0x0020) /* Enable NMI event if correctable bit error detected */\r
+#define UBDIE_L (0x0040) /* Enable NMI event if uncorrectable bit error detected */\r
+#define UBDRSTEN_L (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */\r
+\r
+/* GCCTL1 Control Bits */\r
+//#define RESERVED (0x0001) /* RESERVED */\r
+#define CBDIFG (0x0002) /* FRAM correctable bit error flag */\r
+#define UBDIFG (0x0004) /* FRAM uncorrectable bit error flag */\r
+#define ACCTEIFG (0x0008) /* Access time error flag */\r
+\r
+/* GCCTL1 Control Bits */\r
+//#define RESERVED (0x0001) /* RESERVED */\r
+#define CBDIFG_L (0x0002) /* FRAM correctable bit error flag */\r
+#define UBDIFG_L (0x0004) /* FRAM uncorrectable bit error flag */\r
+#define ACCTEIFG_L (0x0008) /* Access time error flag */\r
+\r
+#endif\r
+/************************************************************\r
+* LCD_C\r
+************************************************************/\r
+#ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */\r
+\r
+#define OFS_LCDCCTL0 (0x0000) /* LCD_C Control Register 0 */\r
+#define OFS_LCDCCTL0_L OFS_LCDCCTL0\r
+#define OFS_LCDCCTL0_H OFS_LCDCCTL0+1\r
+#define OFS_LCDCCTL1 (0x0002) /* LCD_C Control Register 1 */\r
+#define OFS_LCDCCTL1_L OFS_LCDCCTL1\r
+#define OFS_LCDCCTL1_H OFS_LCDCCTL1+1\r
+#define OFS_LCDCBLKCTL (0x0004) /* LCD_C blinking control register */\r
+#define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL\r
+#define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1\r
+#define OFS_LCDCMEMCTL (0x0006) /* LCD_C memory control register */\r
+#define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL\r
+#define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1\r
+#define OFS_LCDCVCTL (0x0008) /* LCD_C Voltage Control Register */\r
+#define OFS_LCDCVCTL_L OFS_LCDCVCTL\r
+#define OFS_LCDCVCTL_H OFS_LCDCVCTL+1\r
+#define OFS_LCDCPCTL0 (0x000A) /* LCD_C Port Control Register 0 */\r
+#define OFS_LCDCPCTL0_L OFS_LCDCPCTL0\r
+#define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1\r
+#define OFS_LCDCPCTL1 (0x000C) /* LCD_C Port Control Register 1 */\r
+#define OFS_LCDCPCTL1_L OFS_LCDCPCTL1\r
+#define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1\r
+#define OFS_LCDCPCTL2 (0x000E) /* LCD_C Port Control Register 2 */\r
+#define OFS_LCDCPCTL2_L OFS_LCDCPCTL2\r
+#define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1\r
+#define OFS_LCDCPCTL3 (0x0010) /* LCD_C Port Control Register 3 */\r
+#define OFS_LCDCPCTL3_L OFS_LCDCPCTL3\r
+#define OFS_LCDCPCTL3_H OFS_LCDCPCTL3+1\r
+#define OFS_LCDCCPCTL (0x0012) /* LCD_C Charge Pump Control Register 3 */\r
+#define OFS_LCDCCPCTL_L OFS_LCDCCPCTL\r
+#define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1\r
+#define OFS_LCDCIV (0x001E) /* LCD_C Interrupt Vector Register */\r
+\r
+// LCDCCTL0\r
+#define LCDON (0x0001) /* LCD_C LCD On */\r
+#define LCDLP (0x0002) /* LCD_C Low Power Waveform */\r
+#define LCDSON (0x0004) /* LCD_C LCD Segments On */\r
+#define LCDMX0 (0x0008) /* LCD_C Mux Rate Bit: 0 */\r
+#define LCDMX1 (0x0010) /* LCD_C Mux Rate Bit: 1 */\r
+#define LCDMX2 (0x0020) /* LCD_C Mux Rate Bit: 2 */\r
+//#define RESERVED (0x0040) /* LCD_C RESERVED */\r
+#define LCDSSEL (0x0080) /* LCD_C Clock Select */\r
+#define LCDPRE0 (0x0100) /* LCD_C LCD frequency pre-scaler Bit: 0 */\r
+#define LCDPRE1 (0x0200) /* LCD_C LCD frequency pre-scaler Bit: 1 */\r
+#define LCDPRE2 (0x0400) /* LCD_C LCD frequency pre-scaler Bit: 2 */\r
+#define LCDDIV0 (0x0800) /* LCD_C LCD frequency divider Bit: 0 */\r
+#define LCDDIV1 (0x1000) /* LCD_C LCD frequency divider Bit: 1 */\r
+#define LCDDIV2 (0x2000) /* LCD_C LCD frequency divider Bit: 2 */\r
+#define LCDDIV3 (0x4000) /* LCD_C LCD frequency divider Bit: 3 */\r
+#define LCDDIV4 (0x8000) /* LCD_C LCD frequency divider Bit: 4 */\r
+\r
+// LCDCCTL0\r
+#define LCDON_L (0x0001) /* LCD_C LCD On */\r
+#define LCDLP_L (0x0002) /* LCD_C Low Power Waveform */\r
+#define LCDSON_L (0x0004) /* LCD_C LCD Segments On */\r
+#define LCDMX0_L (0x0008) /* LCD_C Mux Rate Bit: 0 */\r
+#define LCDMX1_L (0x0010) /* LCD_C Mux Rate Bit: 1 */\r
+#define LCDMX2_L (0x0020) /* LCD_C Mux Rate Bit: 2 */\r
+//#define RESERVED (0x0040) /* LCD_C RESERVED */\r
+#define LCDSSEL_L (0x0080) /* LCD_C Clock Select */\r
+\r
+// LCDCCTL0\r
+//#define RESERVED (0x0040) /* LCD_C RESERVED */\r
+#define LCDPRE0_H (0x0001) /* LCD_C LCD frequency pre-scaler Bit: 0 */\r
+#define LCDPRE1_H (0x0002) /* LCD_C LCD frequency pre-scaler Bit: 1 */\r
+#define LCDPRE2_H (0x0004) /* LCD_C LCD frequency pre-scaler Bit: 2 */\r
+#define LCDDIV0_H (0x0008) /* LCD_C LCD frequency divider Bit: 0 */\r
+#define LCDDIV1_H (0x0010) /* LCD_C LCD frequency divider Bit: 1 */\r
+#define LCDDIV2_H (0x0020) /* LCD_C LCD frequency divider Bit: 2 */\r
+#define LCDDIV3_H (0x0040) /* LCD_C LCD frequency divider Bit: 3 */\r
+#define LCDDIV4_H (0x0080) /* LCD_C LCD frequency divider Bit: 4 */\r
+\r
+#define LCDPRE_0 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */\r
+#define LCDPRE_1 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */\r
+#define LCDPRE_2 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */\r
+#define LCDPRE_3 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */\r
+#define LCDPRE_4 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */\r
+#define LCDPRE_5 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */\r
+#define LCDPRE__1 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */\r
+#define LCDPRE__2 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */\r
+#define LCDPRE__4 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */\r
+#define LCDPRE__8 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */\r
+#define LCDPRE__16 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */\r
+#define LCDPRE__32 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */\r
+\r
+#define LCDDIV_0 (0x0000) /* LCD_C LCD frequency divider: /1 */\r
+#define LCDDIV_1 (0x0800) /* LCD_C LCD frequency divider: /2 */\r
+#define LCDDIV_2 (0x1000) /* LCD_C LCD frequency divider: /3 */\r
+#define LCDDIV_3 (0x1800) /* LCD_C LCD frequency divider: /4 */\r
+#define LCDDIV_4 (0x2000) /* LCD_C LCD frequency divider: /5 */\r
+#define LCDDIV_5 (0x2800) /* LCD_C LCD frequency divider: /6 */\r
+#define LCDDIV_6 (0x3000) /* LCD_C LCD frequency divider: /7 */\r
+#define LCDDIV_7 (0x3800) /* LCD_C LCD frequency divider: /8 */\r
+#define LCDDIV_8 (0x4000) /* LCD_C LCD frequency divider: /9 */\r
+#define LCDDIV_9 (0x4800) /* LCD_C LCD frequency divider: /10 */\r
+#define LCDDIV_10 (0x5000) /* LCD_C LCD frequency divider: /11 */\r
+#define LCDDIV_11 (0x5800) /* LCD_C LCD frequency divider: /12 */\r
+#define LCDDIV_12 (0x6000) /* LCD_C LCD frequency divider: /13 */\r
+#define LCDDIV_13 (0x6800) /* LCD_C LCD frequency divider: /14 */\r
+#define LCDDIV_14 (0x7000) /* LCD_C LCD frequency divider: /15 */\r
+#define LCDDIV_15 (0x7800) /* LCD_C LCD frequency divider: /16 */\r
+#define LCDDIV_16 (0x8000) /* LCD_C LCD frequency divider: /17 */\r
+#define LCDDIV_17 (0x8800) /* LCD_C LCD frequency divider: /18 */\r
+#define LCDDIV_18 (0x9000) /* LCD_C LCD frequency divider: /19 */\r
+#define LCDDIV_19 (0x9800) /* LCD_C LCD frequency divider: /20 */\r
+#define LCDDIV_20 (0xA000) /* LCD_C LCD frequency divider: /21 */\r
+#define LCDDIV_21 (0xA800) /* LCD_C LCD frequency divider: /22 */\r
+#define LCDDIV_22 (0xB000) /* LCD_C LCD frequency divider: /23 */\r
+#define LCDDIV_23 (0xB800) /* LCD_C LCD frequency divider: /24 */\r
+#define LCDDIV_24 (0xC000) /* LCD_C LCD frequency divider: /25 */\r
+#define LCDDIV_25 (0xC800) /* LCD_C LCD frequency divider: /26 */\r
+#define LCDDIV_26 (0xD000) /* LCD_C LCD frequency divider: /27 */\r
+#define LCDDIV_27 (0xD800) /* LCD_C LCD frequency divider: /28 */\r
+#define LCDDIV_28 (0xE000) /* LCD_C LCD frequency divider: /29 */\r
+#define LCDDIV_29 (0xE800) /* LCD_C LCD frequency divider: /30 */\r
+#define LCDDIV_30 (0xF000) /* LCD_C LCD frequency divider: /31 */\r
+#define LCDDIV_31 (0xF800) /* LCD_C LCD frequency divider: /32 */\r
+#define LCDDIV__1 (0x0000) /* LCD_C LCD frequency divider: /1 */\r
+#define LCDDIV__2 (0x0800) /* LCD_C LCD frequency divider: /2 */\r
+#define LCDDIV__3 (0x1000) /* LCD_C LCD frequency divider: /3 */\r
+#define LCDDIV__4 (0x1800) /* LCD_C LCD frequency divider: /4 */\r
+#define LCDDIV__5 (0x2000) /* LCD_C LCD frequency divider: /5 */\r
+#define LCDDIV__6 (0x2800) /* LCD_C LCD frequency divider: /6 */\r
+#define LCDDIV__7 (0x3000) /* LCD_C LCD frequency divider: /7 */\r
+#define LCDDIV__8 (0x3800) /* LCD_C LCD frequency divider: /8 */\r
+#define LCDDIV__9 (0x4000) /* LCD_C LCD frequency divider: /9 */\r
+#define LCDDIV__10 (0x4800) /* LCD_C LCD frequency divider: /10 */\r
+#define LCDDIV__11 (0x5000) /* LCD_C LCD frequency divider: /11 */\r
+#define LCDDIV__12 (0x5800) /* LCD_C LCD frequency divider: /12 */\r
+#define LCDDIV__13 (0x6000) /* LCD_C LCD frequency divider: /13 */\r
+#define LCDDIV__14 (0x6800) /* LCD_C LCD frequency divider: /14 */\r
+#define LCDDIV__15 (0x7000) /* LCD_C LCD frequency divider: /15 */\r
+#define LCDDIV__16 (0x7800) /* LCD_C LCD frequency divider: /16 */\r
+#define LCDDIV__17 (0x8000) /* LCD_C LCD frequency divider: /17 */\r
+#define LCDDIV__18 (0x8800) /* LCD_C LCD frequency divider: /18 */\r
+#define LCDDIV__19 (0x9000) /* LCD_C LCD frequency divider: /19 */\r
+#define LCDDIV__20 (0x9800) /* LCD_C LCD frequency divider: /20 */\r
+#define LCDDIV__21 (0xA000) /* LCD_C LCD frequency divider: /21 */\r
+#define LCDDIV__22 (0xA800) /* LCD_C LCD frequency divider: /22 */\r
+#define LCDDIV__23 (0xB000) /* LCD_C LCD frequency divider: /23 */\r
+#define LCDDIV__24 (0xB800) /* LCD_C LCD frequency divider: /24 */\r
+#define LCDDIV__25 (0xC000) /* LCD_C LCD frequency divider: /25 */\r
+#define LCDDIV__26 (0xC800) /* LCD_C LCD frequency divider: /26 */\r
+#define LCDDIV__27 (0xD000) /* LCD_C LCD frequency divider: /27 */\r
+#define LCDDIV__28 (0xD800) /* LCD_C LCD frequency divider: /28 */\r
+#define LCDDIV__29 (0xE000) /* LCD_C LCD frequency divider: /29 */\r
+#define LCDDIV__30 (0xE800) /* LCD_C LCD frequency divider: /30 */\r
+#define LCDDIV__31 (0xF000) /* LCD_C LCD frequency divider: /31 */\r
+#define LCDDIV__32 (0xF800) /* LCD_C LCD frequency divider: /32 */\r
+\r
+/* Display modes coded with Bits 2-4 */\r
+#define LCDSTATIC (LCDSON)\r
+#define LCD2MUX (LCDMX0+LCDSON)\r
+#define LCD3MUX (LCDMX1+LCDSON)\r
+#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)\r
+#define LCD5MUX (LCDMX2+LCDSON)\r
+#define LCD6MUX (LCDMX2+LCDMX0+LCDSON)\r
+#define LCD7MUX (LCDMX2+LCDMX1+LCDSON)\r
+#define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON)\r
+\r
+// LCDCCTL1\r
+#define LCDFRMIFG (0x0001) /* LCD_C LCD frame interrupt flag */\r
+#define LCDBLKOFFIFG (0x0002) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIFG (0x0004) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIFG (0x0008) /* LCD_C No cpacitance connected interrupt flag */\r
+#define LCDFRMIE (0x0100) /* LCD_C LCD frame interrupt enable */\r
+#define LCDBLKOFFIE (0x0200) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIE (0x0400) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIE (0x0800) /* LCD_C No cpacitance connected interrupt enable */\r
+\r
+// LCDCCTL1\r
+#define LCDFRMIFG_L (0x0001) /* LCD_C LCD frame interrupt flag */\r
+#define LCDBLKOFFIFG_L (0x0002) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIFG_L (0x0004) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIFG_L (0x0008) /* LCD_C No cpacitance connected interrupt flag */\r
+\r
+// LCDCCTL1\r
+#define LCDFRMIE_H (0x0001) /* LCD_C LCD frame interrupt enable */\r
+#define LCDBLKOFFIE_H (0x0002) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIE_H (0x0004) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIE_H (0x0008) /* LCD_C No cpacitance connected interrupt enable */\r
+\r
+// LCDCBLKCTL\r
+#define LCDBLKMOD0 (0x0001) /* LCD_C Blinking mode Bit: 0 */\r
+#define LCDBLKMOD1 (0x0002) /* LCD_C Blinking mode Bit: 1 */\r
+#define LCDBLKPRE0 (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */\r
+#define LCDBLKPRE1 (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */\r
+#define LCDBLKPRE2 (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */\r
+#define LCDBLKDIV0 (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */\r
+#define LCDBLKDIV1 (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */\r
+#define LCDBLKDIV2 (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */\r
+\r
+// LCDCBLKCTL\r
+#define LCDBLKMOD0_L (0x0001) /* LCD_C Blinking mode Bit: 0 */\r
+#define LCDBLKMOD1_L (0x0002) /* LCD_C Blinking mode Bit: 1 */\r
+#define LCDBLKPRE0_L (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */\r
+#define LCDBLKPRE1_L (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */\r
+#define LCDBLKPRE2_L (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */\r
+#define LCDBLKDIV0_L (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */\r
+#define LCDBLKDIV1_L (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */\r
+#define LCDBLKDIV2_L (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */\r
+\r
+#define LCDBLKMOD_0 (0x0000) /* LCD_C Blinking mode: Off */\r
+#define LCDBLKMOD_1 (0x0001) /* LCD_C Blinking mode: Individual */\r
+#define LCDBLKMOD_2 (0x0002) /* LCD_C Blinking mode: All */\r
+#define LCDBLKMOD_3 (0x0003) /* LCD_C Blinking mode: Switching */\r
+\r
+// LCDCMEMCTL\r
+#define LCDDISP (0x0001) /* LCD_C LCD memory registers for display */\r
+#define LCDCLRM (0x0002) /* LCD_C Clear LCD memory */\r
+#define LCDCLRBM (0x0004) /* LCD_C Clear LCD blinking memory */\r
+\r
+// LCDCMEMCTL\r
+#define LCDDISP_L (0x0001) /* LCD_C LCD memory registers for display */\r
+#define LCDCLRM_L (0x0002) /* LCD_C Clear LCD memory */\r
+#define LCDCLRBM_L (0x0004) /* LCD_C Clear LCD blinking memory */\r
+\r
+// LCDCVCTL\r
+#define LCD2B (0x0001) /* Selects 1/2 bias. */\r
+#define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */\r
+#define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */\r
+#define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */\r
+#define VLCDEXT (0x0010) /* Select external source for VLCD. */\r
+#define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */\r
+#define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */\r
+#define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */\r
+#define VLCD0 (0x0200) /* VLCD select: 0 */\r
+#define VLCD1 (0x0400) /* VLCD select: 1 */\r
+#define VLCD2 (0x0800) /* VLCD select: 2 */\r
+#define VLCD3 (0x1000) /* VLCD select: 3 */\r
+#define VLCD4 (0x2000) /* VLCD select: 4 */\r
+#define VLCD5 (0x4000) /* VLCD select: 5 */\r
+\r
+// LCDCVCTL\r
+#define LCD2B_L (0x0001) /* Selects 1/2 bias. */\r
+#define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */\r
+#define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */\r
+#define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */\r
+#define VLCDEXT_L (0x0010) /* Select external source for VLCD. */\r
+#define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */\r
+#define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */\r
+#define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */\r
+\r
+// LCDCVCTL\r
+#define VLCD0_H (0x0002) /* VLCD select: 0 */\r
+#define VLCD1_H (0x0004) /* VLCD select: 1 */\r
+#define VLCD2_H (0x0008) /* VLCD select: 2 */\r
+#define VLCD3_H (0x0010) /* VLCD select: 3 */\r
+#define VLCD4_H (0x0020) /* VLCD select: 4 */\r
+#define VLCD5_H (0x0040) /* VLCD select: 5 */\r
+\r
+/* Reference voltage source select for the regulated charge pump */\r
+#define VLCDREF_0 (0x0000) /* Internal */\r
+#define VLCDREF_1 (0x0002) /* External */\r
+#define VLCDREF_2 (0x0004) /* Reserved */\r
+#define VLCDREF_3 (0x0006) /* Reserved */\r
+\r
+/* Charge pump voltage selections */\r
+#define VLCD_0 (0x0000) /* Charge pump disabled */\r
+#define VLCD_1 (0x0200) /* VLCD = 2.60V */\r
+#define VLCD_2 (0x0400) /* VLCD = 2.66V */\r
+#define VLCD_3 (0x0600) /* VLCD = 2.72V */\r
+#define VLCD_4 (0x0800) /* VLCD = 2.78V */\r
+#define VLCD_5 (0x0A00) /* VLCD = 2.84V */\r
+#define VLCD_6 (0x0C00) /* VLCD = 2.90V */\r
+#define VLCD_7 (0x0E00) /* VLCD = 2.96V */\r
+#define VLCD_8 (0x1000) /* VLCD = 3.02V */\r
+#define VLCD_9 (0x1200) /* VLCD = 3.08V */\r
+#define VLCD_10 (0x1400) /* VLCD = 3.14V */\r
+#define VLCD_11 (0x1600) /* VLCD = 3.20V */\r
+#define VLCD_12 (0x1800) /* VLCD = 3.26V */\r
+#define VLCD_13 (0x1A00) /* VLCD = 3.32V */\r
+#define VLCD_14 (0x1C00) /* VLCD = 3.38V */\r
+#define VLCD_15 (0x1E00) /* VLCD = 3.44V */\r
+\r
+#define VLCD_DISABLED (0x0000) /* Charge pump disabled */\r
+#define VLCD_2_60 (0x0200) /* VLCD = 2.60V */\r
+#define VLCD_2_66 (0x0400) /* VLCD = 2.66V */\r
+#define VLCD_2_72 (0x0600) /* VLCD = 2.72V */\r
+#define VLCD_2_78 (0x0800) /* VLCD = 2.78V */\r
+#define VLCD_2_84 (0x0A00) /* VLCD = 2.84V */\r
+#define VLCD_2_90 (0x0C00) /* VLCD = 2.90V */\r
+#define VLCD_2_96 (0x0E00) /* VLCD = 2.96V */\r
+#define VLCD_3_02 (0x1000) /* VLCD = 3.02V */\r
+#define VLCD_3_08 (0x1200) /* VLCD = 3.08V */\r
+#define VLCD_3_14 (0x1400) /* VLCD = 3.14V */\r
+#define VLCD_3_20 (0x1600) /* VLCD = 3.20V */\r
+#define VLCD_3_26 (0x1800) /* VLCD = 3.26V */\r
+#define VLCD_3_32 (0x1A00) /* VLCD = 3.32V */\r
+#define VLCD_3_38 (0x1C00) /* VLCD = 3.38V */\r
+#define VLCD_3_44 (0x1E00) /* VLCD = 3.44V */\r
+\r
+// LCDCPCTL0\r
+#define LCDS0 (0x0001) /* LCD Segment 0 enable. */\r
+#define LCDS1 (0x0002) /* LCD Segment 1 enable. */\r
+#define LCDS2 (0x0004) /* LCD Segment 2 enable. */\r
+#define LCDS3 (0x0008) /* LCD Segment 3 enable. */\r
+#define LCDS4 (0x0010) /* LCD Segment 4 enable. */\r
+#define LCDS5 (0x0020) /* LCD Segment 5 enable. */\r
+#define LCDS6 (0x0040) /* LCD Segment 6 enable. */\r
+#define LCDS7 (0x0080) /* LCD Segment 7 enable. */\r
+#define LCDS8 (0x0100) /* LCD Segment 8 enable. */\r
+#define LCDS9 (0x0200) /* LCD Segment 9 enable. */\r
+#define LCDS10 (0x0400) /* LCD Segment 10 enable. */\r
+#define LCDS11 (0x0800) /* LCD Segment 11 enable. */\r
+#define LCDS12 (0x1000) /* LCD Segment 12 enable. */\r
+#define LCDS13 (0x2000) /* LCD Segment 13 enable. */\r
+#define LCDS14 (0x4000) /* LCD Segment 14 enable. */\r
+#define LCDS15 (0x8000) /* LCD Segment 15 enable. */\r
+\r
+// LCDCPCTL0\r
+#define LCDS0_L (0x0001) /* LCD Segment 0 enable. */\r
+#define LCDS1_L (0x0002) /* LCD Segment 1 enable. */\r
+#define LCDS2_L (0x0004) /* LCD Segment 2 enable. */\r
+#define LCDS3_L (0x0008) /* LCD Segment 3 enable. */\r
+#define LCDS4_L (0x0010) /* LCD Segment 4 enable. */\r
+#define LCDS5_L (0x0020) /* LCD Segment 5 enable. */\r
+#define LCDS6_L (0x0040) /* LCD Segment 6 enable. */\r
+#define LCDS7_L (0x0080) /* LCD Segment 7 enable. */\r
+\r
+// LCDCPCTL0\r
+#define LCDS8_H (0x0001) /* LCD Segment 8 enable. */\r
+#define LCDS9_H (0x0002) /* LCD Segment 9 enable. */\r
+#define LCDS10_H (0x0004) /* LCD Segment 10 enable. */\r
+#define LCDS11_H (0x0008) /* LCD Segment 11 enable. */\r
+#define LCDS12_H (0x0010) /* LCD Segment 12 enable. */\r
+#define LCDS13_H (0x0020) /* LCD Segment 13 enable. */\r
+#define LCDS14_H (0x0040) /* LCD Segment 14 enable. */\r
+#define LCDS15_H (0x0080) /* LCD Segment 15 enable. */\r
+\r
+// LCDCPCTL1\r
+#define LCDS16 (0x0001) /* LCD Segment 16 enable. */\r
+#define LCDS17 (0x0002) /* LCD Segment 17 enable. */\r
+#define LCDS18 (0x0004) /* LCD Segment 18 enable. */\r
+#define LCDS19 (0x0008) /* LCD Segment 19 enable. */\r
+#define LCDS20 (0x0010) /* LCD Segment 20 enable. */\r
+#define LCDS21 (0x0020) /* LCD Segment 21 enable. */\r
+#define LCDS22 (0x0040) /* LCD Segment 22 enable. */\r
+#define LCDS23 (0x0080) /* LCD Segment 23 enable. */\r
+#define LCDS24 (0x0100) /* LCD Segment 24 enable. */\r
+#define LCDS25 (0x0200) /* LCD Segment 25 enable. */\r
+#define LCDS26 (0x0400) /* LCD Segment 26 enable. */\r
+#define LCDS27 (0x0800) /* LCD Segment 27 enable. */\r
+#define LCDS28 (0x1000) /* LCD Segment 28 enable. */\r
+#define LCDS29 (0x2000) /* LCD Segment 29 enable. */\r
+#define LCDS30 (0x4000) /* LCD Segment 30 enable. */\r
+#define LCDS31 (0x8000) /* LCD Segment 31 enable. */\r
+\r
+// LCDCPCTL1\r
+#define LCDS16_L (0x0001) /* LCD Segment 16 enable. */\r
+#define LCDS17_L (0x0002) /* LCD Segment 17 enable. */\r
+#define LCDS18_L (0x0004) /* LCD Segment 18 enable. */\r
+#define LCDS19_L (0x0008) /* LCD Segment 19 enable. */\r
+#define LCDS20_L (0x0010) /* LCD Segment 20 enable. */\r
+#define LCDS21_L (0x0020) /* LCD Segment 21 enable. */\r
+#define LCDS22_L (0x0040) /* LCD Segment 22 enable. */\r
+#define LCDS23_L (0x0080) /* LCD Segment 23 enable. */\r
+\r
+// LCDCPCTL1\r
+#define LCDS24_H (0x0001) /* LCD Segment 24 enable. */\r
+#define LCDS25_H (0x0002) /* LCD Segment 25 enable. */\r
+#define LCDS26_H (0x0004) /* LCD Segment 26 enable. */\r
+#define LCDS27_H (0x0008) /* LCD Segment 27 enable. */\r
+#define LCDS28_H (0x0010) /* LCD Segment 28 enable. */\r
+#define LCDS29_H (0x0020) /* LCD Segment 29 enable. */\r
+#define LCDS30_H (0x0040) /* LCD Segment 30 enable. */\r
+#define LCDS31_H (0x0080) /* LCD Segment 31 enable. */\r
+\r
+// LCDCPCTL2\r
+#define LCDS32 (0x0001) /* LCD Segment 32 enable. */\r
+#define LCDS33 (0x0002) /* LCD Segment 33 enable. */\r
+#define LCDS34 (0x0004) /* LCD Segment 34 enable. */\r
+#define LCDS35 (0x0008) /* LCD Segment 35 enable. */\r
+#define LCDS36 (0x0010) /* LCD Segment 36 enable. */\r
+#define LCDS37 (0x0020) /* LCD Segment 37 enable. */\r
+#define LCDS38 (0x0040) /* LCD Segment 38 enable. */\r
+#define LCDS39 (0x0080) /* LCD Segment 39 enable. */\r
+#define LCDS40 (0x0100) /* LCD Segment 40 enable. */\r
+#define LCDS41 (0x0200) /* LCD Segment 41 enable. */\r
+#define LCDS42 (0x0400) /* LCD Segment 42 enable. */\r
+#define LCDS43 (0x0800) /* LCD Segment 43 enable. */\r
+#define LCDS44 (0x1000) /* LCD Segment 44 enable. */\r
+#define LCDS45 (0x2000) /* LCD Segment 45 enable. */\r
+#define LCDS46 (0x4000) /* LCD Segment 46 enable. */\r
+#define LCDS47 (0x8000) /* LCD Segment 47 enable. */\r
+\r
+// LCDCPCTL2\r
+#define LCDS32_L (0x0001) /* LCD Segment 32 enable. */\r
+#define LCDS33_L (0x0002) /* LCD Segment 33 enable. */\r
+#define LCDS34_L (0x0004) /* LCD Segment 34 enable. */\r
+#define LCDS35_L (0x0008) /* LCD Segment 35 enable. */\r
+#define LCDS36_L (0x0010) /* LCD Segment 36 enable. */\r
+#define LCDS37_L (0x0020) /* LCD Segment 37 enable. */\r
+#define LCDS38_L (0x0040) /* LCD Segment 38 enable. */\r
+#define LCDS39_L (0x0080) /* LCD Segment 39 enable. */\r
+\r
+// LCDCPCTL2\r
+#define LCDS40_H (0x0001) /* LCD Segment 40 enable. */\r
+#define LCDS41_H (0x0002) /* LCD Segment 41 enable. */\r
+#define LCDS42_H (0x0004) /* LCD Segment 42 enable. */\r
+#define LCDS43_H (0x0008) /* LCD Segment 43 enable. */\r
+#define LCDS44_H (0x0010) /* LCD Segment 44 enable. */\r
+#define LCDS45_H (0x0020) /* LCD Segment 45 enable. */\r
+#define LCDS46_H (0x0040) /* LCD Segment 46 enable. */\r
+#define LCDS47_H (0x0080) /* LCD Segment 47 enable. */\r
+\r
+// LCDCPCTL3\r
+#define LCDS48 (0x0001) /* LCD Segment 48 enable. */\r
+#define LCDS49 (0x0002) /* LCD Segment 49 enable. */\r
+#define LCDS50 (0x0004) /* LCD Segment 50 enable. */\r
+#define LCDS51 (0x0008) /* LCD Segment 51 enable. */\r
+#define LCDS52 (0x0010) /* LCD Segment 52 enable. */\r
+#define LCDS53 (0x0020) /* LCD Segment 53 enable. */\r
+\r
+// LCDCPCTL3\r
+#define LCDS48_L (0x0001) /* LCD Segment 48 enable. */\r
+#define LCDS49_L (0x0002) /* LCD Segment 49 enable. */\r
+#define LCDS50_L (0x0004) /* LCD Segment 50 enable. */\r
+#define LCDS51_L (0x0008) /* LCD Segment 51 enable. */\r
+#define LCDS52_L (0x0010) /* LCD Segment 52 enable. */\r
+#define LCDS53_L (0x0020) /* LCD Segment 53 enable. */\r
+\r
+// LCDCCPCTL\r
+#define LCDCPDIS0 (0x0001) /* LCD charge pump disable */\r
+#define LCDCPDIS1 (0x0002) /* LCD charge pump disable */\r
+#define LCDCPDIS2 (0x0004) /* LCD charge pump disable */\r
+#define LCDCPDIS3 (0x0008) /* LCD charge pump disable */\r
+#define LCDCPDIS4 (0x0010) /* LCD charge pump disable */\r
+#define LCDCPDIS5 (0x0020) /* LCD charge pump disable */\r
+#define LCDCPDIS6 (0x0040) /* LCD charge pump disable */\r
+#define LCDCPDIS7 (0x0080) /* LCD charge pump disable */\r
+#define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */\r
+\r
+// LCDCCPCTL\r
+#define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */\r
+#define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */\r
+#define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */\r
+#define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */\r
+#define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */\r
+#define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */\r
+#define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */\r
+#define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */\r
+\r
+// LCDCCPCTL\r
+#define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */\r
+\r
+#define OFS_LCDM1 (0x0020) /* LCD Memory 1 */\r
+#define LCDMEM_ LCDM1 /* LCD Memory */\r
+#ifdef __ASM_HEADER__\r
+#define LCDMEM LCDM1 /* LCD Memory (for assembler) */\r
+#else\r
+#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */\r
+#endif\r
+#define OFS_LCDM2 (0x0021) /* LCD Memory 2 */\r
+#define OFS_LCDM3 (0x0022) /* LCD Memory 3 */\r
+#define OFS_LCDM4 (0x0023) /* LCD Memory 4 */\r
+#define OFS_LCDM5 (0x0024) /* LCD Memory 5 */\r
+#define OFS_LCDM6 (0x0025) /* LCD Memory 6 */\r
+#define OFS_LCDM7 (0x0026) /* LCD Memory 7 */\r
+#define OFS_LCDM8 (0x0027) /* LCD Memory 8 */\r
+#define OFS_LCDM9 (0x0028) /* LCD Memory 9 */\r
+#define OFS_LCDM10 (0x0029) /* LCD Memory 10 */\r
+#define OFS_LCDM11 (0x002A) /* LCD Memory 11 */\r
+#define OFS_LCDM12 (0x002B) /* LCD Memory 12 */\r
+#define OFS_LCDM13 (0x002C) /* LCD Memory 13 */\r
+#define OFS_LCDM14 (0x002D) /* LCD Memory 14 */\r
+#define OFS_LCDM15 (0x002E) /* LCD Memory 15 */\r
+#define OFS_LCDM16 (0x002F) /* LCD Memory 16 */\r
+#define OFS_LCDM17 (0x0030) /* LCD Memory 17 */\r
+#define OFS_LCDM18 (0x0031) /* LCD Memory 18 */\r
+#define OFS_LCDM19 (0x0032) /* LCD Memory 19 */\r
+#define OFS_LCDM20 (0x0033) /* LCD Memory 20 */\r
+#define OFS_LCDM21 (0x0034) /* LCD Memory 21 */\r
+#define OFS_LCDM22 (0x0035) /* LCD Memory 22 */\r
+#define OFS_LCDM23 (0x0036) /* LCD Memory 23 */\r
+#define OFS_LCDM24 (0x0037) /* LCD Memory 24 */\r
+#define OFS_LCDM25 (0x0038) /* LCD Memory 25 */\r
+#define OFS_LCDM26 (0x0039) /* LCD Memory 26 */\r
+#define OFS_LCDM27 (0x003A) /* LCD Memory 27 */\r
+#define OFS_LCDM28 (0x003B) /* LCD Memory 28 */\r
+#define OFS_LCDM29 (0x003C) /* LCD Memory 29 */\r
+#define OFS_LCDM30 (0x003D) /* LCD Memory 30 */\r
+#define OFS_LCDM31 (0x003E) /* LCD Memory 31 */\r
+#define OFS_LCDM32 (0x003F) /* LCD Memory 32 */\r
+#define OFS_LCDM33 (0x0040) /* LCD Memory 33 */\r
+#define OFS_LCDM34 (0x0041) /* LCD Memory 34 */\r
+#define OFS_LCDM35 (0x0042) /* LCD Memory 35 */\r
+#define OFS_LCDM36 (0x0043) /* LCD Memory 36 */\r
+#define OFS_LCDM37 (0x0044) /* LCD Memory 37 */\r
+#define OFS_LCDM38 (0x0045) /* LCD Memory 38 */\r
+#define OFS_LCDM39 (0x0046) /* LCD Memory 39 */\r
+#define OFS_LCDM40 (0x0047) /* LCD Memory 40 */\r
+\r
+#define OFS_LCDBM1 (0x0040) /* LCD Blinking Memory 1 */\r
+#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */\r
+#ifdef __ASM_HEADER__\r
+#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */\r
+#else\r
+#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */\r
+#endif\r
+#define OFS_LCDBM2 (0x0041) /* LCD Blinking Memory 2 */\r
+#define OFS_LCDBM3 (0x0042) /* LCD Blinking Memory 3 */\r
+#define OFS_LCDBM4 (0x0043) /* LCD Blinking Memory 4 */\r
+#define OFS_LCDBM5 (0x0044) /* LCD Blinking Memory 5 */\r
+#define OFS_LCDBM6 (0x0045) /* LCD Blinking Memory 6 */\r
+#define OFS_LCDBM7 (0x0046) /* LCD Blinking Memory 7 */\r
+#define OFS_LCDBM8 (0x0047) /* LCD Blinking Memory 8 */\r
+#define OFS_LCDBM9 (0x0048) /* LCD Blinking Memory 9 */\r
+#define OFS_LCDBM10 (0x0049) /* LCD Blinking Memory 10 */\r
+#define OFS_LCDBM11 (0x004A) /* LCD Blinking Memory 11 */\r
+#define OFS_LCDBM12 (0x004B) /* LCD Blinking Memory 12 */\r
+#define OFS_LCDBM13 (0x004C) /* LCD Blinking Memory 13 */\r
+#define OFS_LCDBM14 (0x004D) /* LCD Blinking Memory 14 */\r
+#define OFS_LCDBM15 (0x004E) /* LCD Blinking Memory 15 */\r
+#define OFS_LCDBM16 (0x004F) /* LCD Blinking Memory 16 */\r
+#define OFS_LCDBM17 (0x0050) /* LCD Blinking Memory 17 */\r
+#define OFS_LCDBM18 (0x0051) /* LCD Blinking Memory 18 */\r
+#define OFS_LCDBM19 (0x0052) /* LCD Blinking Memory 19 */\r
+#define OFS_LCDBM20 (0x0053) /* LCD Blinking Memory 20 */\r
+\r
+/* LCDCIV Definitions */\r
+#define LCDCIV_NONE (0x0000) /* No Interrupt pending */\r
+#define LCDCIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */\r
+#define LCDCIV_LCDCLKOFFIFG (0x0004) /* Blink, segments off */\r
+#define LCDCIV_LCDCLKONIFG (0x0006) /* Blink, segments on */\r
+#define LCDCIV_LCDFRMIFG (0x0008) /* Frame interrupt */\r
+\r
+#endif\r
+/************************************************************\r
+* Memory Protection Unit\r
+************************************************************/\r
+#ifdef __MSP430_HAS_MPU__ /* Definition to show that Module is available */\r
+\r
+#define OFS_MPUCTL0 (0x0000) /* MPU Control Register 0 */\r
+#define OFS_MPUCTL0_L OFS_MPUCTL0\r
+#define OFS_MPUCTL0_H OFS_MPUCTL0+1\r
+#define OFS_MPUCTL1 (0x0002) /* MPU Control Register 1 */\r
+#define OFS_MPUCTL1_L OFS_MPUCTL1\r
+#define OFS_MPUCTL1_H OFS_MPUCTL1+1\r
+#define OFS_MPUSEGB2 (0x0004) /* MPU Segmentation Border 2 Register */\r
+#define OFS_MPUSEGB2_L OFS_MPUSEGB2\r
+#define OFS_MPUSEGB2_H OFS_MPUSEGB2+1\r
+#define OFS_MPUSEGB1 (0x0006) /* MPU Segmentation Border 1 Register */\r
+#define OFS_MPUSEGB1_L OFS_MPUSEGB1\r
+#define OFS_MPUSEGB1_H OFS_MPUSEGB1+1\r
+#define OFS_MPUSAM (0x0008) /* MPU Access Management Register */\r
+#define OFS_MPUSAM_L OFS_MPUSAM\r
+#define OFS_MPUSAM_H OFS_MPUSAM+1\r
+#define OFS_MPUIPC0 (0x000A) /* MPU IP Control 0 Register */\r
+#define OFS_MPUIPC0_L OFS_MPUIPC0\r
+#define OFS_MPUIPC0_H OFS_MPUIPC0+1\r
+#define OFS_MPUIPSEGB2 (0x000C) /* MPU IP Segment Border 2 Register */\r
+#define OFS_MPUIPSEGB2_L OFS_MPUIPSEGB2\r
+#define OFS_MPUIPSEGB2_H OFS_MPUIPSEGB2+1\r
+#define OFS_MPUIPSEGB1 (0x000E) /* MPU IP Segment Border 1 Register */\r
+#define OFS_MPUIPSEGB1_L OFS_MPUIPSEGB1\r
+#define OFS_MPUIPSEGB1_H OFS_MPUIPSEGB1+1\r
+\r
+/* MPUCTL0 Control Bits */\r
+#define MPUENA (0x0001) /* MPU Enable */\r
+#define MPULOCK (0x0002) /* MPU Lock */\r
+#define MPUSEGIE (0x0010) /* MPU Enable NMI on Segment violation */\r
+\r
+/* MPUCTL0 Control Bits */\r
+#define MPUENA_L (0x0001) /* MPU Enable */\r
+#define MPULOCK_L (0x0002) /* MPU Lock */\r
+#define MPUSEGIE_L (0x0010) /* MPU Enable NMI on Segment violation */\r
+\r
+#define MPUPW (0xA500) /* MPU Access Password */\r
+#define MPUPW_H (0xA5) /* MPU Access Password */\r
+\r
+/* MPUCTL1 Control Bits */\r
+#define MPUSEG1IFG (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */\r
+#define MPUSEG2IFG (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */\r
+#define MPUSEG3IFG (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */\r
+#define MPUSEGIIFG (0x0008) /* MPU Info Memory Segment violation interupt flag */\r
+#define MPUSEGIPIFG (0x0010) /* MPU IP Memory Segment violation interupt flag */\r
+\r
+/* MPUCTL1 Control Bits */\r
+#define MPUSEG1IFG_L (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */\r
+#define MPUSEG2IFG_L (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */\r
+#define MPUSEG3IFG_L (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */\r
+#define MPUSEGIIFG_L (0x0008) /* MPU Info Memory Segment violation interupt flag */\r
+#define MPUSEGIPIFG_L (0x0010) /* MPU IP Memory Segment violation interupt flag */\r
+\r
+/* MPUSEGB2 Control Bits */\r
+\r
+/* MPUSEGB2 Control Bits */\r
+\r
+/* MPUSEGB2 Control Bits */\r
+\r
+/* MPUSEGB1 Control Bits */\r
+\r
+/* MPUSEGB1 Control Bits */\r
+\r
+/* MPUSEGB1 Control Bits */\r
+\r
+/* MPUSAM Control Bits */\r
+#define MPUSEG1RE (0x0001) /* MPU Main memory Segment 1 Read enable */\r
+#define MPUSEG1WE (0x0002) /* MPU Main memory Segment 1 Write enable */\r
+#define MPUSEG1XE (0x0004) /* MPU Main memory Segment 1 Execute enable */\r
+#define MPUSEG1VS (0x0008) /* MPU Main memory Segment 1 Violation select */\r
+#define MPUSEG2RE (0x0010) /* MPU Main memory Segment 2 Read enable */\r
+#define MPUSEG2WE (0x0020) /* MPU Main memory Segment 2 Write enable */\r
+#define MPUSEG2XE (0x0040) /* MPU Main memory Segment 2 Execute enable */\r
+#define MPUSEG2VS (0x0080) /* MPU Main memory Segment 2 Violation select */\r
+#define MPUSEG3RE (0x0100) /* MPU Main memory Segment 3 Read enable */\r
+#define MPUSEG3WE (0x0200) /* MPU Main memory Segment 3 Write enable */\r
+#define MPUSEG3XE (0x0400) /* MPU Main memory Segment 3 Execute enable */\r
+#define MPUSEG3VS (0x0800) /* MPU Main memory Segment 3 Violation select */\r
+#define MPUSEGIRE (0x1000) /* MPU Info memory Segment Read enable */\r
+#define MPUSEGIWE (0x2000) /* MPU Info memory Segment Write enable */\r
+#define MPUSEGIXE (0x4000) /* MPU Info memory Segment Execute enable */\r
+#define MPUSEGIVS (0x8000) /* MPU Info memory Segment Violation select */\r
+\r
+/* MPUSAM Control Bits */\r
+#define MPUSEG1RE_L (0x0001) /* MPU Main memory Segment 1 Read enable */\r
+#define MPUSEG1WE_L (0x0002) /* MPU Main memory Segment 1 Write enable */\r
+#define MPUSEG1XE_L (0x0004) /* MPU Main memory Segment 1 Execute enable */\r
+#define MPUSEG1VS_L (0x0008) /* MPU Main memory Segment 1 Violation select */\r
+#define MPUSEG2RE_L (0x0010) /* MPU Main memory Segment 2 Read enable */\r
+#define MPUSEG2WE_L (0x0020) /* MPU Main memory Segment 2 Write enable */\r
+#define MPUSEG2XE_L (0x0040) /* MPU Main memory Segment 2 Execute enable */\r
+#define MPUSEG2VS_L (0x0080) /* MPU Main memory Segment 2 Violation select */\r
+\r
+/* MPUSAM Control Bits */\r
+#define MPUSEG3RE_H (0x0001) /* MPU Main memory Segment 3 Read enable */\r
+#define MPUSEG3WE_H (0x0002) /* MPU Main memory Segment 3 Write enable */\r
+#define MPUSEG3XE_H (0x0004) /* MPU Main memory Segment 3 Execute enable */\r
+#define MPUSEG3VS_H (0x0008) /* MPU Main memory Segment 3 Violation select */\r
+#define MPUSEGIRE_H (0x0010) /* MPU Info memory Segment Read enable */\r
+#define MPUSEGIWE_H (0x0020) /* MPU Info memory Segment Write enable */\r
+#define MPUSEGIXE_H (0x0040) /* MPU Info memory Segment Execute enable */\r
+#define MPUSEGIVS_H (0x0080) /* MPU Info memory Segment Violation select */\r
+\r
+/* MPUIPC0 Control Bits */\r
+#define MPUIPVS (0x0020) /* MPU MPU IP protection segment Violation Select */\r
+#define MPUIPENA (0x0040) /* MPU MPU IP Protection Enable */\r
+#define MPUIPLOCK (0x0080) /* MPU IP Protection Lock */\r
+\r
+/* MPUIPC0 Control Bits */\r
+#define MPUIPVS_L (0x0020) /* MPU MPU IP protection segment Violation Select */\r
+#define MPUIPENA_L (0x0040) /* MPU MPU IP Protection Enable */\r
+#define MPUIPLOCK_L (0x0080) /* MPU IP Protection Lock */\r
+\r
+/* MPUIPSEGB2 Control Bits */\r
+\r
+/* MPUIPSEGB2 Control Bits */\r
+\r
+/* MPUIPSEGB2 Control Bits */\r
+\r
+/* MPUIPSEGB1 Control Bits */\r
+\r
+/* MPUIPSEGB1 Control Bits */\r
+\r
+/* MPUIPSEGB1 Control Bits */\r
+\r
+#endif\r
+/************************************************************\r
+* HARDWARE MULTIPLIER 32Bit\r
+************************************************************/\r
+#ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */\r
+\r
+#define OFS_MPY (0x0000) /* Multiply Unsigned/Operand 1 */\r
+#define OFS_MPY_L OFS_MPY\r
+#define OFS_MPY_H OFS_MPY+1\r
+#define OFS_MPYS (0x0002) /* Multiply Signed/Operand 1 */\r
+#define OFS_MPYS_L OFS_MPYS\r
+#define OFS_MPYS_H OFS_MPYS+1\r
+#define OFS_MAC (0x0004) /* Multiply Unsigned and Accumulate/Operand 1 */\r
+#define OFS_MAC_L OFS_MAC\r
+#define OFS_MAC_H OFS_MAC+1\r
+#define OFS_MACS (0x0006) /* Multiply Signed and Accumulate/Operand 1 */\r
+#define OFS_MACS_L OFS_MACS\r
+#define OFS_MACS_H OFS_MACS+1\r
+#define OFS_OP2 (0x0008) /* Operand 2 */\r
+#define OFS_OP2_L OFS_OP2\r
+#define OFS_OP2_H OFS_OP2+1\r
+#define OFS_RESLO (0x000A) /* Result Low Word */\r
+#define OFS_RESLO_L OFS_RESLO\r
+#define OFS_RESLO_H OFS_RESLO+1\r
+#define OFS_RESHI (0x000C) /* Result High Word */\r
+#define OFS_RESHI_L OFS_RESHI\r
+#define OFS_RESHI_H OFS_RESHI+1\r
+#define OFS_SUMEXT (0x000E) /* Sum Extend */\r
+#define OFS_SUMEXT_L OFS_SUMEXT\r
+#define OFS_SUMEXT_H OFS_SUMEXT+1\r
+#define OFS_MPY32CTL0 (0x002C)\r
+#define OFS_MPY32CTL0_L OFS_MPY32CTL0\r
+#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1\r
+\r
+#define OFS_MPY32L (0x0010) /* 32-bit operand 1 - multiply - low word */\r
+#define OFS_MPY32L_L OFS_MPY32L\r
+#define OFS_MPY32L_H OFS_MPY32L+1\r
+#define OFS_MPY32H (0x0012) /* 32-bit operand 1 - multiply - high word */\r
+#define OFS_MPY32H_L OFS_MPY32H\r
+#define OFS_MPY32H_H OFS_MPY32H+1\r
+#define OFS_MPYS32L (0x0014) /* 32-bit operand 1 - signed multiply - low word */\r
+#define OFS_MPYS32L_L OFS_MPYS32L\r
+#define OFS_MPYS32L_H OFS_MPYS32L+1\r
+#define OFS_MPYS32H (0x0016) /* 32-bit operand 1 - signed multiply - high word */\r
+#define OFS_MPYS32H_L OFS_MPYS32H\r
+#define OFS_MPYS32H_H OFS_MPYS32H+1\r
+#define OFS_MAC32L (0x0018) /* 32-bit operand 1 - multiply accumulate - low word */\r
+#define OFS_MAC32L_L OFS_MAC32L\r
+#define OFS_MAC32L_H OFS_MAC32L+1\r
+#define OFS_MAC32H (0x001A) /* 32-bit operand 1 - multiply accumulate - high word */\r
+#define OFS_MAC32H_L OFS_MAC32H\r
+#define OFS_MAC32H_H OFS_MAC32H+1\r
+#define OFS_MACS32L (0x001C) /* 32-bit operand 1 - signed multiply accumulate - low word */\r
+#define OFS_MACS32L_L OFS_MACS32L\r
+#define OFS_MACS32L_H OFS_MACS32L+1\r
+#define OFS_MACS32H (0x001E) /* 32-bit operand 1 - signed multiply accumulate - high word */\r
+#define OFS_MACS32H_L OFS_MACS32H\r
+#define OFS_MACS32H_H OFS_MACS32H+1\r
+#define OFS_OP2L (0x0020) /* 32-bit operand 2 - low word */\r
+#define OFS_OP2L_L OFS_OP2L\r
+#define OFS_OP2L_H OFS_OP2L+1\r
+#define OFS_OP2H (0x0022) /* 32-bit operand 2 - high word */\r
+#define OFS_OP2H_L OFS_OP2H\r
+#define OFS_OP2H_H OFS_OP2H+1\r
+#define OFS_RES0 (0x0024) /* 32x32-bit result 0 - least significant word */\r
+#define OFS_RES0_L OFS_RES0\r
+#define OFS_RES0_H OFS_RES0+1\r
+#define OFS_RES1 (0x0026) /* 32x32-bit result 1 */\r
+#define OFS_RES1_L OFS_RES1\r
+#define OFS_RES1_H OFS_RES1+1\r
+#define OFS_RES2 (0x0028) /* 32x32-bit result 2 */\r
+#define OFS_RES2_L OFS_RES2\r
+#define OFS_RES2_H OFS_RES2+1\r
+#define OFS_RES3 (0x002A) /* 32x32-bit result 3 - most significant word */\r
+#define OFS_RES3_L OFS_RES3\r
+#define OFS_RES3_H OFS_RES3+1\r
+#define OFS_SUMEXT (0x000E)\r
+#define OFS_SUMEXT_L OFS_SUMEXT\r
+#define OFS_SUMEXT_H OFS_SUMEXT+1\r
+#define OFS_MPY32CTL0 (0x002C) /* MPY32 Control Register 0 */\r
+#define OFS_MPY32CTL0_L OFS_MPY32CTL0\r
+#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1\r
+\r
+#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */\r
+#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */\r
+#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */\r
+#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */\r
+#define OP2_B OP2_L /* Operand 2 (Byte Access) */\r
+#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */\r
+#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */\r
+#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */\r
+#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */\r
+#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */\r
+#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */\r
+#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */\r
+#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */\r
+#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */\r
+#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+#define MPYC (0x0001) /* Carry of the multiplier */\r
+//#define RESERVED (0x0002) /* Reserved */\r
+#define MPYFRAC (0x0004) /* Fractional mode */\r
+#define MPYSAT (0x0008) /* Saturation mode */\r
+#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */\r
+#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */\r
+#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */\r
+#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */\r
+#define MPYDLYWRTEN (0x0100) /* Delayed write enable */\r
+#define MPYDLY32 (0x0200) /* Delayed write mode */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+#define MPYC_L (0x0001) /* Carry of the multiplier */\r
+//#define RESERVED (0x0002) /* Reserved */\r
+#define MPYFRAC_L (0x0004) /* Fractional mode */\r
+#define MPYSAT_L (0x0008) /* Saturation mode */\r
+#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */\r
+#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */\r
+#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */\r
+#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+//#define RESERVED (0x0002) /* Reserved */\r
+#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */\r
+#define MPYDLY32_H (0x0002) /* Delayed write mode */\r
+\r
+#define MPYM_0 (0x0000) /* Multiplier mode: MPY */\r
+#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */\r
+#define MPYM_2 (0x0020) /* Multiplier mode: MAC */\r
+#define MPYM_3 (0x0030) /* Multiplier mode: MACS */\r
+#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */\r
+#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */\r
+#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */\r
+#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */\r
+\r
+#endif\r
+/************************************************************\r
+* PMM - Power Management System for FRAM\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PMM_FRAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PMMCTL0 (0x0000) /* PMM Control 0 */\r
+#define OFS_PMMCTL0_L OFS_PMMCTL0\r
+#define OFS_PMMCTL0_H OFS_PMMCTL0+1\r
+#define OFS_PMMCTL1 (0x0002) /* PMM Control 1 */\r
+#define OFS_PMMIFG (0x000A) /* PMM Interrupt Flag */\r
+#define OFS_PMMIFG_L OFS_PMMIFG\r
+#define OFS_PMMIFG_H OFS_PMMIFG+1\r
+#define OFS_PM5CTL0 (0x0010) /* PMM Power Mode 5 Control Register 0 */\r
+#define OFS_PM5CTL0_L OFS_PM5CTL0\r
+#define OFS_PM5CTL0_H OFS_PM5CTL0+1\r
+\r
+#define PMMPW (0xA500) /* PMM Register Write Password */\r
+#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */\r
+\r
+/* PMMCTL0 Control Bits */\r
+#define PMMSWBOR (0x0004) /* PMM Software BOR */\r
+#define PMMSWPOR (0x0008) /* PMM Software POR */\r
+#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */\r
+#define SVSHE (0x0040) /* SVS high side enable */\r
+#define PMMLPRST (0x0080) /* PMM Low-Power Reset Enable */\r
+\r
+/* PMMCTL0 Control Bits */\r
+#define PMMSWBOR_L (0x0004) /* PMM Software BOR */\r
+#define PMMSWPOR_L (0x0008) /* PMM Software POR */\r
+#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */\r
+#define SVSHE_L (0x0040) /* SVS high side enable */\r
+#define PMMLPRST_L (0x0080) /* PMM Low-Power Reset Enable */\r
+\r
+/* PMMCTL1 Control Bits */\r
+#define PMMLPSVEN (0x0002) /* PMM Low-Power Supervision Enable */\r
+#define PMMLPRNG0 (0x0004) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 0 */\r
+#define PMMLPRNG1 (0x0008) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 1 */\r
+#define PMMAMRNG0 (0x0010) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 0 */\r
+#define PMMAMRNG1 (0x0020) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 1 */\r
+#define PMMAMRNG2 (0x0040) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 2 */\r
+#define PMMAMRNG3 (0x0080) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 3 */\r
+#define PMMCTL1KEY (0xCC00) /* PMM PMMCTL1 Register Write Password */\r
+\r
+/* PMMIFG Control Bits */\r
+#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */\r
+#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */\r
+#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */\r
+#define SVSHIFG (0x2000) /* SVS low side interrupt flag */\r
+#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */\r
+\r
+/* PMMIFG Control Bits */\r
+#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */\r
+#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */\r
+#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */\r
+#define SVSHIFG_H (0x0020) /* SVS low side interrupt flag */\r
+#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */\r
+\r
+/* PM5CTL0 Power Mode 5 Control Bits */\r
+#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */\r
+\r
+/* PM5CTL0 Power Mode 5 Control Bits */\r
+#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */\r
+\r
+\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port1/2 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PAIN (0x0000) /* Port A Input */\r
+#define OFS_PAIN_L OFS_PAIN\r
+#define OFS_PAIN_H OFS_PAIN+1\r
+#define OFS_PAOUT (0x0002) /* Port A Output */\r
+#define OFS_PAOUT_L OFS_PAOUT\r
+#define OFS_PAOUT_H OFS_PAOUT+1\r
+#define OFS_PADIR (0x0004) /* Port A Direction */\r
+#define OFS_PADIR_L OFS_PADIR\r
+#define OFS_PADIR_H OFS_PADIR+1\r
+#define OFS_PAREN (0x0006) /* Port A Resistor Enable */\r
+#define OFS_PAREN_L OFS_PAREN\r
+#define OFS_PAREN_H OFS_PAREN+1\r
+#define OFS_PASEL0 (0x000A) /* Port A Selection 0 */\r
+#define OFS_PASEL0_L OFS_PASEL0\r
+#define OFS_PASEL0_H OFS_PASEL0+1\r
+#define OFS_PASEL1 (0x000C) /* Port A Selection 1 */\r
+#define OFS_PASEL1_L OFS_PASEL1\r
+#define OFS_PASEL1_H OFS_PASEL1+1\r
+#define OFS_PASELC (0x0016) /* Port A Complement Selection */\r
+#define OFS_PASELC_L OFS_PASELC\r
+#define OFS_PASELC_H OFS_PASELC+1\r
+#define OFS_PAIES (0x0018) /* Port A Interrupt Edge Select */\r
+#define OFS_PAIES_L OFS_PAIES\r
+#define OFS_PAIES_H OFS_PAIES+1\r
+#define OFS_PAIE (0x001A) /* Port A Interrupt Enable */\r
+#define OFS_PAIE_L OFS_PAIE\r
+#define OFS_PAIE_H OFS_PAIE+1\r
+#define OFS_PAIFG (0x001C) /* Port A Interrupt Flag */\r
+#define OFS_PAIFG_L OFS_PAIFG\r
+#define OFS_PAIFG_H OFS_PAIFG+1\r
+\r
+\r
+#define OFS_P1IN (0x0000)\r
+#define OFS_P1OUT (0x0002)\r
+#define OFS_P1DIR (0x0004)\r
+#define OFS_P1REN (0x0006)\r
+#define OFS_P1SEL0 (0x000A)\r
+#define OFS_P1SEL1 (0x000C)\r
+#define OFS_P1SELC (0x0016)\r
+#define OFS_P1IV (0x000E) /* Port 1 Interrupt Vector Word */\r
+#define OFS_P1IES (0x0018)\r
+#define OFS_P1IE (0x001A)\r
+#define OFS_P1IFG (0x001C)\r
+#define OFS_P2IN (0x0001)\r
+#define OFS_P2OUT (0x0003)\r
+#define OFS_P2DIR (0x0005)\r
+#define OFS_P2REN (0x0007)\r
+#define OFS_P2SEL0 (0x000B)\r
+#define OFS_P2SEL1 (0x000D)\r
+#define OFS_P2SELC (0x0017)\r
+#define OFS_P2IV (0x001E) /* Port 2 Interrupt Vector Word */\r
+#define OFS_P2IES (0x0019)\r
+#define OFS_P2IE (0x001B)\r
+#define OFS_P2IFG (0x001d)\r
+#define P1IN (PAIN_L) /* Port 1 Input */\r
+#define P1OUT (PAOUT_L) /* Port 1 Output */\r
+#define P1DIR (PADIR_L) /* Port 1 Direction */\r
+#define P1REN (PAREN_L) /* Port 1 Resistor Enable */\r
+#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */\r
+#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */\r
+#define P1SELC (PASELC_L) /* Port 1 Complement Selection */\r
+#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */\r
+#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */\r
+#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */\r
+\r
+//Definitions for P1IV\r
+#define P1IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */\r
+#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */\r
+#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */\r
+#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */\r
+#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */\r
+#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */\r
+#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */\r
+#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */\r
+\r
+#define P2IN (PAIN_H) /* Port 2 Input */\r
+#define P2OUT (PAOUT_H) /* Port 2 Output */\r
+#define P2DIR (PADIR_H) /* Port 2 Direction */\r
+#define P2REN (PAREN_H) /* Port 2 Resistor Enable */\r
+#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */\r
+#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */\r
+#define P2SELC (PASELC_H) /* Port 2 Complement Selection */\r
+#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */\r
+#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */\r
+#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */\r
+\r
+//Definitions for P2IV\r
+#define P2IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */\r
+#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */\r
+#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */\r
+#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */\r
+#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */\r
+#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */\r
+#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */\r
+#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port3/4 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PBIN (0x0000) /* Port B Input */\r
+#define OFS_PBIN_L OFS_PBIN\r
+#define OFS_PBIN_H OFS_PBIN+1\r
+#define OFS_PBOUT (0x0002) /* Port B Output */\r
+#define OFS_PBOUT_L OFS_PBOUT\r
+#define OFS_PBOUT_H OFS_PBOUT+1\r
+#define OFS_PBDIR (0x0004) /* Port B Direction */\r
+#define OFS_PBDIR_L OFS_PBDIR\r
+#define OFS_PBDIR_H OFS_PBDIR+1\r
+#define OFS_PBREN (0x0006) /* Port B Resistor Enable */\r
+#define OFS_PBREN_L OFS_PBREN\r
+#define OFS_PBREN_H OFS_PBREN+1\r
+#define OFS_PBSEL0 (0x000A) /* Port B Selection 0 */\r
+#define OFS_PBSEL0_L OFS_PBSEL0\r
+#define OFS_PBSEL0_H OFS_PBSEL0+1\r
+#define OFS_PBSEL1 (0x000C) /* Port B Selection 1 */\r
+#define OFS_PBSEL1_L OFS_PBSEL1\r
+#define OFS_PBSEL1_H OFS_PBSEL1+1\r
+#define OFS_PBSELC (0x0016) /* Port B Complement Selection */\r
+#define OFS_PBSELC_L OFS_PBSELC\r
+#define OFS_PBSELC_H OFS_PBSELC+1\r
+#define OFS_PBIES (0x0018) /* Port B Interrupt Edge Select */\r
+#define OFS_PBIES_L OFS_PBIES\r
+#define OFS_PBIES_H OFS_PBIES+1\r
+#define OFS_PBIE (0x001A) /* Port B Interrupt Enable */\r
+#define OFS_PBIE_L OFS_PBIE\r
+#define OFS_PBIE_H OFS_PBIE+1\r
+#define OFS_PBIFG (0x001C) /* Port B Interrupt Flag */\r
+#define OFS_PBIFG_L OFS_PBIFG\r
+#define OFS_PBIFG_H OFS_PBIFG+1\r
+\r
+\r
+#define OFS_P3IN (0x0000)\r
+#define OFS_P3OUT (0x0002)\r
+#define OFS_P3DIR (0x0004)\r
+#define OFS_P3REN (0x0006)\r
+#define OFS_P3SEL0 (0x000A)\r
+#define OFS_P3SEL1 (0x000C)\r
+#define OFS_P3SELC (0x0016)\r
+#define OFS_P3IV (0x000E) /* Port 3 Interrupt Vector Word */\r
+#define OFS_P3IES (0x0018)\r
+#define OFS_P3IE (0x001A)\r
+#define OFS_P3IFG (0x001C)\r
+#define OFS_P4IN (0x0001)\r
+#define OFS_P4OUT (0x0003)\r
+#define OFS_P4DIR (0x0005)\r
+#define OFS_P4REN (0x0007)\r
+#define OFS_P4SEL0 (0x000B)\r
+#define OFS_P4SEL1 (0x000D)\r
+#define OFS_P4SELC (0x0017)\r
+#define OFS_P4IV (0x001E) /* Port 4 Interrupt Vector Word */\r
+#define OFS_P4IES (0x0019)\r
+#define OFS_P4IE (0x001B)\r
+#define OFS_P4IFG (0x001d)\r
+#define P3IN (PBIN_L) /* Port 3 Input */\r
+#define P3OUT (PBOUT_L) /* Port 3 Output */\r
+#define P3DIR (PBDIR_L) /* Port 3 Direction */\r
+#define P3REN (PBREN_L) /* Port 3 Resistor Enable */\r
+#define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */\r
+#define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */\r
+#define P3SELC (PBSELC_L) /* Port 3 Complement Selection */\r
+#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */\r
+#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */\r
+#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */\r
+\r
+//Definitions for P3IV\r
+#define P3IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P3IV_P3IFG0 (0x0002) /* P3IV P3IFG.0 */\r
+#define P3IV_P3IFG1 (0x0004) /* P3IV P3IFG.1 */\r
+#define P3IV_P3IFG2 (0x0006) /* P3IV P3IFG.2 */\r
+#define P3IV_P3IFG3 (0x0008) /* P3IV P3IFG.3 */\r
+#define P3IV_P3IFG4 (0x000A) /* P3IV P3IFG.4 */\r
+#define P3IV_P3IFG5 (0x000C) /* P3IV P3IFG.5 */\r
+#define P3IV_P3IFG6 (0x000E) /* P3IV P3IFG.6 */\r
+#define P3IV_P3IFG7 (0x0010) /* P3IV P3IFG.7 */\r
+\r
+#define P4IN (PBIN_H) /* Port 4 Input */\r
+#define P4OUT (PBOUT_H) /* Port 4 Output */\r
+#define P4DIR (PBDIR_H) /* Port 4 Direction */\r
+#define P4REN (PBREN_H) /* Port 4 Resistor Enable */\r
+#define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */\r
+#define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */\r
+#define P4SELC (PBSELC_H) /* Port 4 Complement Selection */\r
+#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */\r
+#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */\r
+#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */\r
+\r
+//Definitions for P4IV\r
+#define P4IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P4IV_P4IFG0 (0x0002) /* P4IV P4IFG.0 */\r
+#define P4IV_P4IFG1 (0x0004) /* P4IV P4IFG.1 */\r
+#define P4IV_P4IFG2 (0x0006) /* P4IV P4IFG.2 */\r
+#define P4IV_P4IFG3 (0x0008) /* P4IV P4IFG.3 */\r
+#define P4IV_P4IFG4 (0x000A) /* P4IV P4IFG.4 */\r
+#define P4IV_P4IFG5 (0x000C) /* P4IV P4IFG.5 */\r
+#define P4IV_P4IFG6 (0x000E) /* P4IV P4IFG.6 */\r
+#define P4IV_P4IFG7 (0x0010) /* P4IV P4IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port5/6 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PCIN (0x0000) /* Port C Input */\r
+#define OFS_PCIN_L OFS_PCIN\r
+#define OFS_PCIN_H OFS_PCIN+1\r
+#define OFS_PCOUT (0x0002) /* Port C Output */\r
+#define OFS_PCOUT_L OFS_PCOUT\r
+#define OFS_PCOUT_H OFS_PCOUT+1\r
+#define OFS_PCDIR (0x0004) /* Port C Direction */\r
+#define OFS_PCDIR_L OFS_PCDIR\r
+#define OFS_PCDIR_H OFS_PCDIR+1\r
+#define OFS_PCREN (0x0006) /* Port C Resistor Enable */\r
+#define OFS_PCREN_L OFS_PCREN\r
+#define OFS_PCREN_H OFS_PCREN+1\r
+#define OFS_PCSEL0 (0x000A) /* Port C Selection 0 */\r
+#define OFS_PCSEL0_L OFS_PCSEL0\r
+#define OFS_PCSEL0_H OFS_PCSEL0+1\r
+#define OFS_PCSEL1 (0x000C) /* Port C Selection 1 */\r
+#define OFS_PCSEL1_L OFS_PCSEL1\r
+#define OFS_PCSEL1_H OFS_PCSEL1+1\r
+#define OFS_PCSELC (0x0016) /* Port C Complement Selection */\r
+#define OFS_PCSELC_L OFS_PCSELC\r
+#define OFS_PCSELC_H OFS_PCSELC+1\r
+#define OFS_PCIES (0x0018) /* Port C Interrupt Edge Select */\r
+#define OFS_PCIES_L OFS_PCIES\r
+#define OFS_PCIES_H OFS_PCIES+1\r
+#define OFS_PCIE (0x001A) /* Port C Interrupt Enable */\r
+#define OFS_PCIE_L OFS_PCIE\r
+#define OFS_PCIE_H OFS_PCIE+1\r
+#define OFS_PCIFG (0x001C) /* Port C Interrupt Flag */\r
+#define OFS_PCIFG_L OFS_PCIFG\r
+#define OFS_PCIFG_H OFS_PCIFG+1\r
+\r
+\r
+#define OFS_P5IN (0x0000)\r
+#define OFS_P5OUT (0x0002)\r
+#define OFS_P5DIR (0x0004)\r
+#define OFS_P5REN (0x0006)\r
+#define OFS_P5SEL0 (0x000A)\r
+#define OFS_P5SEL1 (0x000C)\r
+#define OFS_P5SELC (0x0016)\r
+#define OFS_P5IV (0x000E) /* Port 5 Interrupt Vector Word */\r
+#define OFS_P5IES (0x0018)\r
+#define OFS_P5IE (0x001A)\r
+#define OFS_P5IFG (0x001C)\r
+#define OFS_P6IN (0x0001)\r
+#define OFS_P6OUT (0x0003)\r
+#define OFS_P6DIR (0x0005)\r
+#define OFS_P6REN (0x0007)\r
+#define OFS_P6SEL0 (0x000B)\r
+#define OFS_P6SEL1 (0x000D)\r
+#define OFS_P6SELC (0x0017)\r
+#define OFS_P6IV (0x001E) /* Port 6 Interrupt Vector Word */\r
+#define OFS_P6IES (0x0019)\r
+#define OFS_P6IE (0x001B)\r
+#define OFS_P6IFG (0x001d)\r
+#define P5IN (PCIN_L) /* Port 5 Input */\r
+#define P5OUT (PCOUT_L) /* Port 5 Output */\r
+#define P5DIR (PCDIR_L) /* Port 5 Direction */\r
+#define P5REN (PCREN_L) /* Port 5 Resistor Enable */\r
+#define P5SEL0 (PCSEL0_L) /* Port 5 Selection 0 */\r
+#define P5SEL1 (PCSEL1_L) /* Port 5 Selection 1 */\r
+#define P5SELC (PCSELC_L) /* Port 5 Complement Selection */\r
+#define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */\r
+#define P5IE (PCIE_L) /* Port 5 Interrupt Enable */\r
+#define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */\r
+\r
+//Definitions for P5IV\r
+#define P5IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P5IV_P5IFG0 (0x0002) /* P5IV P5IFG.0 */\r
+#define P5IV_P5IFG1 (0x0004) /* P5IV P5IFG.1 */\r
+#define P5IV_P5IFG2 (0x0006) /* P5IV P5IFG.2 */\r
+#define P5IV_P5IFG3 (0x0008) /* P5IV P5IFG.3 */\r
+#define P5IV_P5IFG4 (0x000A) /* P5IV P5IFG.4 */\r
+#define P5IV_P5IFG5 (0x000C) /* P5IV P5IFG.5 */\r
+#define P5IV_P5IFG6 (0x000E) /* P5IV P5IFG.6 */\r
+#define P5IV_P5IFG7 (0x0010) /* P5IV P5IFG.7 */\r
+\r
+#define P6IN (PCIN_H) /* Port 6 Input */\r
+#define P6OUT (PCOUT_H) /* Port 6 Output */\r
+#define P6DIR (PCDIR_H) /* Port 6 Direction */\r
+#define P6REN (PCREN_H) /* Port 6 Resistor Enable */\r
+#define P6SEL0 (PCSEL0_H) /* Port 6 Selection 0 */\r
+#define P6SEL1 (PCSEL1_H) /* Port 6 Selection 1 */\r
+#define P6SELC (PCSELC_H) /* Port 6 Complement Selection */\r
+#define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */\r
+#define P6IE (PCIE_H) /* Port 6 Interrupt Enable */\r
+#define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */\r
+\r
+//Definitions for P6IV\r
+#define P6IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P6IV_P6IFG0 (0x0002) /* P6IV P6IFG.0 */\r
+#define P6IV_P6IFG1 (0x0004) /* P6IV P6IFG.1 */\r
+#define P6IV_P6IFG2 (0x0006) /* P6IV P6IFG.2 */\r
+#define P6IV_P6IFG3 (0x0008) /* P6IV P6IFG.3 */\r
+#define P6IV_P6IFG4 (0x000A) /* P6IV P6IFG.4 */\r
+#define P6IV_P6IFG5 (0x000C) /* P6IV P6IFG.5 */\r
+#define P6IV_P6IFG6 (0x000E) /* P6IV P6IFG.6 */\r
+#define P6IV_P6IFG7 (0x0010) /* P6IV P6IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port7/8 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PDIN (0x0000) /* Port D Input */\r
+#define OFS_PDIN_L OFS_PDIN\r
+#define OFS_PDIN_H OFS_PDIN+1\r
+#define OFS_PDOUT (0x0002) /* Port D Output */\r
+#define OFS_PDOUT_L OFS_PDOUT\r
+#define OFS_PDOUT_H OFS_PDOUT+1\r
+#define OFS_PDDIR (0x0004) /* Port D Direction */\r
+#define OFS_PDDIR_L OFS_PDDIR\r
+#define OFS_PDDIR_H OFS_PDDIR+1\r
+#define OFS_PDREN (0x0006) /* Port D Resistor Enable */\r
+#define OFS_PDREN_L OFS_PDREN\r
+#define OFS_PDREN_H OFS_PDREN+1\r
+#define OFS_PDSEL0 (0x000A) /* Port D Selection 0 */\r
+#define OFS_PDSEL0_L OFS_PDSEL0\r
+#define OFS_PDSEL0_H OFS_PDSEL0+1\r
+#define OFS_PDSEL1 (0x000C) /* Port D Selection 1 */\r
+#define OFS_PDSEL1_L OFS_PDSEL1\r
+#define OFS_PDSEL1_H OFS_PDSEL1+1\r
+#define OFS_PDSELC (0x0016) /* Port D Complement Selection */\r
+#define OFS_PDSELC_L OFS_PDSELC\r
+#define OFS_PDSELC_H OFS_PDSELC+1\r
+#define OFS_PDIES (0x0018) /* Port D Interrupt Edge Select */\r
+#define OFS_PDIES_L OFS_PDIES\r
+#define OFS_PDIES_H OFS_PDIES+1\r
+#define OFS_PDIE (0x001A) /* Port D Interrupt Enable */\r
+#define OFS_PDIE_L OFS_PDIE\r
+#define OFS_PDIE_H OFS_PDIE+1\r
+#define OFS_PDIFG (0x001C) /* Port D Interrupt Flag */\r
+#define OFS_PDIFG_L OFS_PDIFG\r
+#define OFS_PDIFG_H OFS_PDIFG+1\r
+\r
+\r
+#define OFS_P7IN (0x0000)\r
+#define OFS_P7OUT (0x0002)\r
+#define OFS_P7DIR (0x0004)\r
+#define OFS_P7REN (0x0006)\r
+#define OFS_P7SEL0 (0x000A)\r
+#define OFS_P7SEL1 (0x000C)\r
+#define OFS_P7SELC (0x0016)\r
+#define OFS_P7IV (0x000E) /* Port 7 Interrupt Vector Word */\r
+#define OFS_P7IES (0x0018)\r
+#define OFS_P7IE (0x001A)\r
+#define OFS_P7IFG (0x001C)\r
+#define OFS_P8IN (0x0001)\r
+#define OFS_P8OUT (0x0003)\r
+#define OFS_P8DIR (0x0005)\r
+#define OFS_P8REN (0x0007)\r
+#define OFS_P8SEL0 (0x000B)\r
+#define OFS_P8SEL1 (0x000D)\r
+#define OFS_P8SELC (0x0017)\r
+#define OFS_P8IV (0x001E) /* Port 8 Interrupt Vector Word */\r
+#define OFS_P8IES (0x0019)\r
+#define OFS_P8IE (0x001B)\r
+#define OFS_P8IFG (0x001d)\r
+#define P7IN (PDIN_L) /* Port 7 Input */\r
+#define P7OUT (PDOUT_L) /* Port 7 Output */\r
+#define P7DIR (PDDIR_L) /* Port 7 Direction */\r
+#define P7REN (PDREN_L) /* Port 7 Resistor Enable */\r
+#define P7SEL0 (PDSEL0_L) /* Port 7 Selection 0 */\r
+#define P7SEL1 (PDSEL1_L) /* Port 7 Selection 1 */\r
+#define P7SELC (PDSELC_L) /* Port 7 Complement Selection */\r
+#define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */\r
+#define P7IE (PDIE_L) /* Port 7 Interrupt Enable */\r
+#define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */\r
+\r
+//Definitions for P7IV\r
+#define P7IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P7IV_P7IFG0 (0x0002) /* P7IV P7IFG.0 */\r
+#define P7IV_P7IFG1 (0x0004) /* P7IV P7IFG.1 */\r
+#define P7IV_P7IFG2 (0x0006) /* P7IV P7IFG.2 */\r
+#define P7IV_P7IFG3 (0x0008) /* P7IV P7IFG.3 */\r
+#define P7IV_P7IFG4 (0x000A) /* P7IV P7IFG.4 */\r
+#define P7IV_P7IFG5 (0x000C) /* P7IV P7IFG.5 */\r
+#define P7IV_P7IFG6 (0x000E) /* P7IV P7IFG.6 */\r
+#define P7IV_P7IFG7 (0x0010) /* P7IV P7IFG.7 */\r
+\r
+#define P8IN (PDIN_H) /* Port 8 Input */\r
+#define P8OUT (PDOUT_H) /* Port 8 Output */\r
+#define P8DIR (PDDIR_H) /* Port 8 Direction */\r
+#define P8REN (PDREN_H) /* Port 8 Resistor Enable */\r
+#define P8SEL0 (PDSEL0_H) /* Port 8 Selection 0 */\r
+#define P8SEL1 (PDSEL1_H) /* Port 8 Selection 1 */\r
+#define P8SELC (PDSELC_H) /* Port 8 Complement Selection */\r
+#define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */\r
+#define P8IE (PDIE_H) /* Port 8 Interrupt Enable */\r
+#define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */\r
+\r
+//Definitions for P8IV\r
+#define P8IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P8IV_P8IFG0 (0x0002) /* P8IV P8IFG.0 */\r
+#define P8IV_P8IFG1 (0x0004) /* P8IV P8IFG.1 */\r
+#define P8IV_P8IFG2 (0x0006) /* P8IV P8IFG.2 */\r
+#define P8IV_P8IFG3 (0x0008) /* P8IV P8IFG.3 */\r
+#define P8IV_P8IFG4 (0x000A) /* P8IV P8IFG.4 */\r
+#define P8IV_P8IFG5 (0x000C) /* P8IV P8IFG.5 */\r
+#define P8IV_P8IFG6 (0x000E) /* P8IV P8IFG.6 */\r
+#define P8IV_P8IFG7 (0x0010) /* P8IV P8IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port9/10 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PEIN (0x0000) /* Port E Input */\r
+#define OFS_PEIN_L OFS_PEIN\r
+#define OFS_PEIN_H OFS_PEIN+1\r
+#define OFS_PEOUT (0x0002) /* Port E Output */\r
+#define OFS_PEOUT_L OFS_PEOUT\r
+#define OFS_PEOUT_H OFS_PEOUT+1\r
+#define OFS_PEDIR (0x0004) /* Port E Direction */\r
+#define OFS_PEDIR_L OFS_PEDIR\r
+#define OFS_PEDIR_H OFS_PEDIR+1\r
+#define OFS_PEREN (0x0006) /* Port E Resistor Enable */\r
+#define OFS_PEREN_L OFS_PEREN\r
+#define OFS_PEREN_H OFS_PEREN+1\r
+#define OFS_PESEL0 (0x000A) /* Port E Selection 0 */\r
+#define OFS_PESEL0_L OFS_PESEL0\r
+#define OFS_PESEL0_H OFS_PESEL0+1\r
+#define OFS_PESEL1 (0x000C) /* Port E Selection 1 */\r
+#define OFS_PESEL1_L OFS_PESEL1\r
+#define OFS_PESEL1_H OFS_PESEL1+1\r
+#define OFS_PESELC (0x0016) /* Port E Complement Selection */\r
+#define OFS_PESELC_L OFS_PESELC\r
+#define OFS_PESELC_H OFS_PESELC+1\r
+#define OFS_PEIES (0x0018) /* Port E Interrupt Edge Select */\r
+#define OFS_PEIES_L OFS_PEIES\r
+#define OFS_PEIES_H OFS_PEIES+1\r
+#define OFS_PEIE (0x001A) /* Port E Interrupt Enable */\r
+#define OFS_PEIE_L OFS_PEIE\r
+#define OFS_PEIE_H OFS_PEIE+1\r
+#define OFS_PEIFG (0x001C) /* Port E Interrupt Flag */\r
+#define OFS_PEIFG_L OFS_PEIFG\r
+#define OFS_PEIFG_H OFS_PEIFG+1\r
+\r
+\r
+#define OFS_P9IN (0x0000)\r
+#define OFS_P9OUT (0x0002)\r
+#define OFS_P9DIR (0x0004)\r
+#define OFS_P9REN (0x0006)\r
+#define OFS_P9SEL0 (0x000A)\r
+#define OFS_P9SEL1 (0x000C)\r
+#define OFS_P9SELC (0x0016)\r
+#define OFS_P9IV (0x000E) /* Port 9 Interrupt Vector Word */\r
+#define OFS_P9IES (0x0018)\r
+#define OFS_P9IE (0x001A)\r
+#define OFS_P9IFG (0x001C)\r
+#define OFS_P10IN (0x0001)\r
+#define OFS_P10OUT (0x0003)\r
+#define OFS_P10DIR (0x0005)\r
+#define OFS_P10REN (0x0007)\r
+#define OFS_P10SEL0 (0x000B)\r
+#define OFS_P10SEL1 (0x000D)\r
+#define OFS_P10SELC (0x0017)\r
+#define OFS_P10IV (0x001E) /* Port 10 Interrupt Vector Word */\r
+#define OFS_P10IES (0x0019)\r
+#define OFS_P10IE (0x001B)\r
+#define OFS_P10IFG (0x001d)\r
+#define P9IN (PEIN_L) /* Port 9 Input */\r
+#define P9OUT (PEOUT_L) /* Port 9 Output */\r
+#define P9DIR (PEDIR_L) /* Port 9 Direction */\r
+#define P9REN (PEREN_L) /* Port 9 Resistor Enable */\r
+#define P9SEL0 (PESEL0_L) /* Port 9 Selection 0 */\r
+#define P9SEL1 (PESEL1_L) /* Port 9 Selection 1 */\r
+#define P9SELC (PESELC_L) /* Port 9 Complement Selection */\r
+#define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */\r
+#define P9IE (PEIE_L) /* Port 9 Interrupt Enable */\r
+#define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */\r
+\r
+//Definitions for P9IV\r
+#define P9IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P9IV_P9IFG0 (0x0002) /* P9IV P9IFG.0 */\r
+#define P9IV_P9IFG1 (0x0004) /* P9IV P9IFG.1 */\r
+#define P9IV_P9IFG2 (0x0006) /* P9IV P9IFG.2 */\r
+#define P9IV_P9IFG3 (0x0008) /* P9IV P9IFG.3 */\r
+#define P9IV_P9IFG4 (0x000A) /* P9IV P9IFG.4 */\r
+#define P9IV_P9IFG5 (0x000C) /* P9IV P9IFG.5 */\r
+#define P9IV_P9IFG6 (0x000E) /* P9IV P9IFG.6 */\r
+#define P9IV_P9IFG7 (0x0010) /* P9IV P9IFG.7 */\r
+\r
+#define P10IN (PEIN_H) /* Port 10 Input */\r
+#define P10OUT (PEOUT_H) /* Port 10 Output */\r
+#define P10DIR (PEDIR_H) /* Port 10 Direction */\r
+#define P10REN (PEREN_H) /* Port 10 Resistor Enable */\r
+#define P10SEL0 (PESEL0_H) /* Port 10 Selection 0 */\r
+#define P10SEL1 (PESEL1_H) /* Port 10 Selection 1 */\r
+#define P10SELC (PESELC_H) /* Port 10 Complement Selection */\r
+#define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */\r
+#define P10IE (PEIE_H) /* Port 10 Interrupt Enable */\r
+#define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */\r
+\r
+//Definitions for P10IV\r
+#define P10IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P10IV_P10IFG0 (0x0002) /* P10IV P10IFG.0 */\r
+#define P10IV_P10IFG1 (0x0004) /* P10IV P10IFG.1 */\r
+#define P10IV_P10IFG2 (0x0006) /* P10IV P10IFG.2 */\r
+#define P10IV_P10IFG3 (0x0008) /* P10IV P10IFG.3 */\r
+#define P10IV_P10IFG4 (0x000A) /* P10IV P10IFG.4 */\r
+#define P10IV_P10IFG5 (0x000C) /* P10IV P10IFG.5 */\r
+#define P10IV_P10IFG6 (0x000E) /* P10IV P10IFG.6 */\r
+#define P10IV_P10IFG7 (0x0010) /* P10IV P10IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port11 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PFIN (0x0000) /* Port F Input */\r
+#define OFS_PFIN_L OFS_PFIN\r
+#define OFS_PFIN_H OFS_PFIN+1\r
+#define OFS_PFOUT (0x0002) /* Port F Output */\r
+#define OFS_PFOUT_L OFS_PFOUT\r
+#define OFS_PFOUT_H OFS_PFOUT+1\r
+#define OFS_PFDIR (0x0004) /* Port F Direction */\r
+#define OFS_PFDIR_L OFS_PFDIR\r
+#define OFS_PFDIR_H OFS_PFDIR+1\r
+#define OFS_PFREN (0x0006) /* Port F Resistor Enable */\r
+#define OFS_PFREN_L OFS_PFREN\r
+#define OFS_PFREN_H OFS_PFREN+1\r
+#define OFS_PFSEL0 (0x000A) /* Port F Selection 0 */\r
+#define OFS_PFSEL0_L OFS_PFSEL0\r
+#define OFS_PFSEL0_H OFS_PFSEL0+1\r
+#define OFS_PFSEL1 (0x000C) /* Port F Selection 1 */\r
+#define OFS_PFSEL1_L OFS_PFSEL1\r
+#define OFS_PFSEL1_H OFS_PFSEL1+1\r
+#define OFS_PFSELC (0x0016) /* Port F Complement Selection */\r
+#define OFS_PFSELC_L OFS_PFSELC\r
+#define OFS_PFSELC_H OFS_PFSELC+1\r
+#define OFS_PFIES (0x0018) /* Port F Interrupt Edge Select */\r
+#define OFS_PFIES_L OFS_PFIES\r
+#define OFS_PFIES_H OFS_PFIES+1\r
+#define OFS_PFIE (0x001A) /* Port F Interrupt Enable */\r
+#define OFS_PFIE_L OFS_PFIE\r
+#define OFS_PFIE_H OFS_PFIE+1\r
+#define OFS_PFIFG (0x001C) /* Port F Interrupt Flag */\r
+#define OFS_PFIFG_L OFS_PFIFG\r
+#define OFS_PFIFG_H OFS_PFIFG+1\r
+\r
+\r
+#define OFS_P11IN (0x0000)\r
+#define OFS_P11OUT (0x0002)\r
+#define OFS_P11DIR (0x0004)\r
+#define OFS_P11REN (0x0006)\r
+#define OFS_P11SEL0 (0x000A)\r
+#define OFS_P11SEL1 (0x000C)\r
+#define OFS_P11SELC (0x0016)\r
+#define OFS_P11IV (0x000E) /* Port 11 Interrupt Vector Word */\r
+#define OFS_P11IES (0x0018)\r
+#define OFS_P11IE (0x001A)\r
+#define OFS_P11IFG (0x001C)\r
+#define P11IN (PFIN_L) /* Port 11 Input */\r
+#define P11OUT (PFOUT_L) /* Port 11 Output */\r
+#define P11DIR (PFDIR_L) /* Port 11 Direction */\r
+#define P11REN (PFREN_L) /* Port 11 Resistor Enable */\r
+#define P11SEL0 (PFSEL0_L) /* Port 11 Selection0 */\r
+#define P11SEL1 (PFSEL1_L) /* Port 11 Selection1 */\r
+#define OFS_P11SELC (0x0017)\r
+\r
+#define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */\r
+#define P11IE (PFIE_L) /* Port 11 Interrupt Enable */\r
+#define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */\r
+\r
+//Definitions for P11IV\r
+#define P11IV_NONE (0x0000) /* No Interrupt pending */\r
+#define P11IV_P11IFG0 (0x0002) /* P11IV P11IFG.0 */\r
+#define P11IV_P11IFG1 (0x0004) /* P11IV P11IFG.1 */\r
+#define P11IV_P11IFG2 (0x0006) /* P11IV P11IFG.2 */\r
+#define P11IV_P11IFG3 (0x0008) /* P11IV P11IFG.3 */\r
+#define P11IV_P11IFG4 (0x000A) /* P11IV P11IFG.4 */\r
+#define P11IV_P11IFG5 (0x000C) /* P11IV P11IFG.5 */\r
+#define P11IV_P11IFG6 (0x000E) /* P11IV P11IFG.6 */\r
+#define P11IV_P11IFG7 (0x0010) /* P11IV P11IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O PortJ Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PJIN (0x0000) /* Port J Input */\r
+#define OFS_PJIN_L OFS_PJIN\r
+#define OFS_PJIN_H OFS_PJIN+1\r
+#define OFS_PJOUT (0x0002) /* Port J Output */\r
+#define OFS_PJOUT_L OFS_PJOUT\r
+#define OFS_PJOUT_H OFS_PJOUT+1\r
+#define OFS_PJDIR (0x0004) /* Port J Direction */\r
+#define OFS_PJDIR_L OFS_PJDIR\r
+#define OFS_PJDIR_H OFS_PJDIR+1\r
+#define OFS_PJREN (0x0006) /* Port J Resistor Enable */\r
+#define OFS_PJREN_L OFS_PJREN\r
+#define OFS_PJREN_H OFS_PJREN+1\r
+#define OFS_PJSEL0 (0x000A) /* Port J Selection 0 */\r
+#define OFS_PJSEL0_L OFS_PJSEL0\r
+#define OFS_PJSEL0_H OFS_PJSEL0+1\r
+#define OFS_PJSEL1 (0x000C) /* Port J Selection 1 */\r
+#define OFS_PJSEL1_L OFS_PJSEL1\r
+#define OFS_PJSEL1_H OFS_PJSEL1+1\r
+#define OFS_PJSELC (0x0016) /* Port J Complement Selection */\r
+#define OFS_PJSELC_L OFS_PJSELC\r
+#define OFS_PJSELC_H OFS_PJSELC+1\r
+\r
+#endif\r
+/*************************************************************\r
+* RAM Control Module for FRAM\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_RC_FRAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_RCCTL0 (0x0000) /* Ram Controller Control Register */\r
+#define OFS_RCCTL0_L OFS_RCCTL0\r
+#define OFS_RCCTL0_H OFS_RCCTL0+1\r
+\r
+/* RCCTL0 Control Bits */\r
+#define RCRS0OFF0 (0x0001) /* RAM Controller RAM Sector 0 Off Bit: 0 */\r
+#define RCRS0OFF1 (0x0002) /* RAM Controller RAM Sector 0 Off Bit: 1 */\r
+#define RCRS4OFF0 (0x0100) /* RAM Controller RAM Sector 4 Off Bit: 0 */\r
+#define RCRS4OFF1 (0x0200) /* RAM Controller RAM Sector 4 Off Bit: 1 */\r
+#define RCRS5OFF0 (0x0400) /* RAM Controller RAM Sector 5 Off Bit: 0 */\r
+#define RCRS5OFF1 (0x0800) /* RAM Controller RAM Sector 5 Off Bit: 1 */\r
+#define RCRS6OFF0 (0x1000) /* RAM Controller RAM Sector 6 Off Bit: 0 */\r
+#define RCRS6OFF1 (0x2000) /* RAM Controller RAM Sector 6 Off Bit: 1 */\r
+#define RCRS7OFF0 (0x4000) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */\r
+#define RCRS7OFF1 (0x8000) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */\r
+\r
+/* RCCTL0 Control Bits */\r
+#define RCRS0OFF0_L (0x0001) /* RAM Controller RAM Sector 0 Off Bit: 0 */\r
+#define RCRS0OFF1_L (0x0002) /* RAM Controller RAM Sector 0 Off Bit: 1 */\r
+\r
+/* RCCTL0 Control Bits */\r
+#define RCRS4OFF0_H (0x0001) /* RAM Controller RAM Sector 4 Off Bit: 0 */\r
+#define RCRS4OFF1_H (0x0002) /* RAM Controller RAM Sector 4 Off Bit: 1 */\r
+#define RCRS5OFF0_H (0x0004) /* RAM Controller RAM Sector 5 Off Bit: 0 */\r
+#define RCRS5OFF1_H (0x0008) /* RAM Controller RAM Sector 5 Off Bit: 1 */\r
+#define RCRS6OFF0_H (0x0010) /* RAM Controller RAM Sector 6 Off Bit: 0 */\r
+#define RCRS6OFF1_H (0x0020) /* RAM Controller RAM Sector 6 Off Bit: 1 */\r
+#define RCRS7OFF0_H (0x0040) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */\r
+#define RCRS7OFF1_H (0x0080) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */\r
+\r
+#define RCKEY (0x5A00)\r
+\r
+#define RCRS0OFF_0 (0x0000) /* RAM Controller RAM Sector 0 Off : 0 */\r
+#define RCRS0OFF_1 (0x0001) /* RAM Controller RAM Sector 0 Off : 1 */\r
+#define RCRS0OFF_2 (0x0002) /* RAM Controller RAM Sector 0 Off : 2 */\r
+#define RCRS0OFF_3 (0x0003) /* RAM Controller RAM Sector 0 Off : 3 */\r
+#define RCRS4OFF_0 (0x0000) /* RAM Controller RAM Sector 4 Off : 0 */\r
+#define RCRS4OFF_2 (0x0100) /* RAM Controller RAM Sector 4 Off : 1 */\r
+#define RCRS4OFF_3 (0x0200) /* RAM Controller RAM Sector 4 Off : 2 */\r
+#define RCRS4OFF_4 (0x0300) /* RAM Controller RAM Sector 4 Off : 3 */\r
+#define RCRS5OFF_0 (0x0000) /* RAM Controller RAM Sector 5 Off : 0 */\r
+#define RCRS5OFF_1 (0x0400) /* RAM Controller RAM Sector 5 Off : 1 */\r
+#define RCRS5OFF_2 (0x0800) /* RAM Controller RAM Sector 5 Off : 2 */\r
+#define RCRS5OFF_3 (0x0C00) /* RAM Controller RAM Sector 5 Off : 3 */\r
+#define RCRS6OFF_0 (0x0000) /* RAM Controller RAM Sector 6 Off : 0 */\r
+#define RCRS6OFF_1 (0x0100) /* RAM Controller RAM Sector 6 Off : 1 */\r
+#define RCRS6OFF_2 (0x0200) /* RAM Controller RAM Sector 6 Off : 2 */\r
+#define RCRS6OFF_3 (0x0300) /* RAM Controller RAM Sector 6 Off : 3 */\r
+#define RCRS7OFF_0 (0x0000) /* RAM Controller RAM Sector 7 Off : 0 */\r
+#define RCRS7OFF_1 (0x4000) /* RAM Controller RAM Sector 7 Off : 1 */\r
+#define RCRS7OFF_2 (0x8000) /* RAM Controller RAM Sector 7 Off : 2*/\r
+#define RCRS7OFF_3 (0xC000) /* RAM Controller RAM Sector 7 Off : 3*/\r
+\r
+#endif\r
+/************************************************************\r
+* Shared Reference\r
+************************************************************/\r
+#ifdef __MSP430_HAS_REF_A__ /* Definition to show that Module is available */\r
+\r
+#define OFS_REFCTL0 (0x0000) /* REF Shared Reference control register 0 */\r
+#define OFS_REFCTL0_L OFS_REFCTL0\r
+#define OFS_REFCTL0_H OFS_REFCTL0+1\r
+\r
+/* REFCTL0 Control Bits */\r
+#define REFON (0x0001) /* REF Reference On */\r
+#define REFOUT (0x0002) /* REF Reference output Buffer On */\r
+//#define RESERVED (0x0004) /* Reserved */\r
+#define REFTCOFF (0x0008) /* REF Temp.Sensor off */\r
+#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */\r
+#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */\r
+#define REFGENOT (0x0040) /* REF Reference generator one-time trigger */\r
+#define REFBGOT (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */\r
+#define REFGENACT (0x0100) /* REF Reference generator active */\r
+#define REFBGACT (0x0200) /* REF Reference bandgap active */\r
+#define REFGENBUSY (0x0400) /* REF Reference generator busy */\r
+#define BGMODE (0x0800) /* REF Bandgap mode */\r
+#define REFGENRDY (0x1000) /* REF Reference generator ready */\r
+#define REFBGRDY (0x2000) /* REF Reference bandgap ready */\r
+//#define RESERVED (0x4000) /* Reserved */\r
+//#define RESERVED (0x8000) /* Reserved */\r
+\r
+/* REFCTL0 Control Bits */\r
+#define REFON_L (0x0001) /* REF Reference On */\r
+#define REFOUT_L (0x0002) /* REF Reference output Buffer On */\r
+//#define RESERVED (0x0004) /* Reserved */\r
+#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */\r
+#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */\r
+#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */\r
+#define REFGENOT_L (0x0040) /* REF Reference generator one-time trigger */\r
+#define REFBGOT_L (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */\r
+//#define RESERVED (0x4000) /* Reserved */\r
+//#define RESERVED (0x8000) /* Reserved */\r
+\r
+/* REFCTL0 Control Bits */\r
+//#define RESERVED (0x0004) /* Reserved */\r
+#define REFGENACT_H (0x0001) /* REF Reference generator active */\r
+#define REFBGACT_H (0x0002) /* REF Reference bandgap active */\r
+#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */\r
+#define BGMODE_H (0x0008) /* REF Bandgap mode */\r
+#define REFGENRDY_H (0x0010) /* REF Reference generator ready */\r
+#define REFBGRDY_H (0x0020) /* REF Reference bandgap ready */\r
+//#define RESERVED (0x4000) /* Reserved */\r
+//#define RESERVED (0x8000) /* Reserved */\r
+\r
+#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.2V */\r
+#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */\r
+#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */\r
+#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */\r
+\r
+#endif\r
+/************************************************************\r
+* Real Time Clock\r
+************************************************************/\r
+#ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */\r
+\r
+#define OFS_RTCCTL01 (0x0000) /* Real Timer Control 0/1 */\r
+#define OFS_RTCCTL01_L OFS_RTCCTL01\r
+#define OFS_RTCCTL01_H OFS_RTCCTL01+1\r
+#define OFS_RTCCTL23 (0x0002) /* Real Timer Control 2/3 */\r
+#define OFS_RTCCTL23_L OFS_RTCCTL23\r
+#define OFS_RTCCTL23_H OFS_RTCCTL23+1\r
+#define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */\r
+#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
+#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
+#define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */\r
+#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
+#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
+#define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */\r
+#define OFS_RTCPS_L OFS_RTCPS\r
+#define OFS_RTCPS_H OFS_RTCPS+1\r
+#define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */\r
+#define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */\r
+#define OFS_RTCTIM0_L OFS_RTCTIM0\r
+#define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
+#define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */\r
+#define OFS_RTCTIM1_L OFS_RTCTIM1\r
+#define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
+#define OFS_RTCDATE (0x0014) /* Real Time Clock Date */\r
+#define OFS_RTCDATE_L OFS_RTCDATE\r
+#define OFS_RTCDATE_H OFS_RTCDATE+1\r
+#define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */\r
+#define OFS_RTCYEAR_L OFS_RTCYEAR\r
+#define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
+#define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */\r
+#define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
+#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
+#define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */\r
+#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
+#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
+#define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */\r
+#define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */\r
+#define OFS_RTCSEC (0x0010)\r
+#define OFS_RTCMIN (0x0011)\r
+#define OFS_RTCHOUR (0x0012)\r
+#define OFS_RTCDOW (0x0013)\r
+#define OFS_RTCDAY (0x0014)\r
+#define OFS_RTCMON (0x0015)\r
+#define OFS_RTCAMIN (0x0018)\r
+#define OFS_RTCAHOUR (0x0019)\r
+#define OFS_RTCADOW (0x001A)\r
+#define OFS_RTCADAY (0x001B)\r
+\r
+#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */\r
+#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */\r
+#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */\r
+#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */\r
+#define RTCNT12 RTCTIM0\r
+#define RTCNT34 RTCTIM1\r
+#define RTCNT1 RTCTIM0_L\r
+#define RTCNT2 RTCTIM0_H\r
+#define RTCNT3 RTCTIM1_L\r
+#define RTCNT4 RTCTIM1_H\r
+#define RTCSEC RTCTIM0_L\r
+#define RTCMIN RTCTIM0_H\r
+#define RTCHOUR RTCTIM1_L\r
+#define RTCDOW RTCTIM1_H\r
+#define RTCDAY RTCDATE_L\r
+#define RTCMON RTCDATE_H\r
+#define RTCYEARL RTCYEAR_L\r
+#define RTCYEARH RTCYEAR_H\r
+#define RT0PS RTCPS_L\r
+#define RT1PS RTCPS_H\r
+#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
+#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
+#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
+#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
+\r
+/* RTCCTL01 Control Bits */\r
+#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD (0x4000) /* RTC Hold */\r
+//#define RESERVED (0x2000) /* RESERVED */\r
+#define RTCRDY (0x1000) /* RTC Ready */\r
+//#define RESERVED (0x0800) /* RESERVED */\r
+//#define RESERVED (0x0400) /* RESERVED */\r
+#define RTCTEV1 (0x0200) /* RTC Time Event 1 */\r
+#define RTCTEV0 (0x0100) /* RTC Time Event 0 */\r
+#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */\r
+\r
+/* RTCCTL01 Control Bits */\r
+//#define RESERVED (0x2000) /* RESERVED */\r
+//#define RESERVED (0x0800) /* RESERVED */\r
+//#define RESERVED (0x0400) /* RESERVED */\r
+#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */\r
+\r
+/* RTCCTL01 Control Bits */\r
+#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD_H (0x0040) /* RTC Hold */\r
+//#define RESERVED (0x2000) /* RESERVED */\r
+#define RTCRDY_H (0x0010) /* RTC Ready */\r
+//#define RESERVED (0x0800) /* RESERVED */\r
+//#define RESERVED (0x0400) /* RESERVED */\r
+#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */\r
+#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */\r
+\r
+#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */\r
+#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */\r
+#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */\r
+#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */\r
+\r
+/* RTCCTL23 Control Bits */\r
+#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */\r
+#define RTCCALS (0x0080) /* RTC Calibration Sign */\r
+//#define Reserved (0x0040)\r
+#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */\r
+#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */\r
+#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */\r
+#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */\r
+#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */\r
+#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */\r
+\r
+/* RTCCTL23 Control Bits */\r
+#define RTCCALS_L (0x0080) /* RTC Calibration Sign */\r
+//#define Reserved (0x0040)\r
+#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */\r
+#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */\r
+#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */\r
+#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */\r
+#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */\r
+#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */\r
+\r
+/* RTCCTL23 Control Bits */\r
+#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */\r
+//#define Reserved (0x0040)\r
+\r
+#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */\r
+#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */\r
+#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */\r
+#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */\r
+\r
+#define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
+#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
+#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
+#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
+#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
+#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
+#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
+#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
+\r
+#define RT0IP__2 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
+#define RT0IP__4 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
+#define RT0IP__8 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
+#define RT0IP__16 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
+#define RT0IP__32 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
+#define RT0IP__64 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
+#define RT0IP__128 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
+#define RT0IP__256 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
+#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
+#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
+#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
+#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
+#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
+#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
+#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
+\r
+#define RT1IP__2 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
+#define RT1IP__4 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
+#define RT1IP__8 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
+#define RT1IP__16 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
+#define RT1IP__32 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
+#define RT1IP__64 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
+#define RT1IP__128 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
+#define RT1IP__256 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
+\r
+/* RTC Definitions */\r
+#define RTCIV_NONE (0x0000) /* No Interrupt pending */\r
+#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */\r
+#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */\r
+#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */\r
+#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */\r
+#define RTCIV_RTCOFIFG (0x000C) /* RTC Oscillator fault */\r
+\r
+/* Legacy Definitions */\r
+#define RTC_NONE (0x0000) /* No Interrupt pending */\r
+#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */\r
+#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */\r
+#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */\r
+#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */\r
+#define RTC_RTCOFIFG (0x000C) /* RTC Oscillator fault */\r
+\r
+#endif\r
+/************************************************************\r
+* Real Time Clock\r
+************************************************************/\r
+#ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */\r
+\r
+#define OFS_RTCCTL0 (0x0000) /* Real Timer Clock Control 0/Key */\r
+#define OFS_RTCCTL0_L OFS_RTCCTL0\r
+#define OFS_RTCCTL0_H OFS_RTCCTL0+1\r
+#define OFS_RTCCTL13 (0x0002) /* Real Timer Clock Control 1/3 */\r
+#define OFS_RTCCTL13_L OFS_RTCCTL13\r
+#define OFS_RTCCTL13_H OFS_RTCCTL13+1\r
+#define RTCCTL1 RTCCTL13_L\r
+#define RTCCTL3 RTCCTL13_H\r
+#define OFS_RTCOCAL (0x0004) /* Real Timer Clock Offset Calibartion */\r
+#define OFS_RTCOCAL_L OFS_RTCOCAL\r
+#define OFS_RTCOCAL_H OFS_RTCOCAL+1\r
+#define OFS_RTCTCMP (0x0006) /* Real Timer Temperature Compensation */\r
+#define OFS_RTCTCMP_L OFS_RTCTCMP\r
+#define OFS_RTCTCMP_H OFS_RTCTCMP+1\r
+#define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */\r
+#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
+#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
+#define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */\r
+#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
+#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
+#define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */\r
+#define OFS_RTCPS_L OFS_RTCPS\r
+#define OFS_RTCPS_H OFS_RTCPS+1\r
+#define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */\r
+#define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */\r
+#define OFS_RTCTIM0_L OFS_RTCTIM0\r
+#define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
+#define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */\r
+#define OFS_RTCTIM1_L OFS_RTCTIM1\r
+#define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
+#define OFS_RTCDATE (0x0014) /* Real Time Clock Date */\r
+#define OFS_RTCDATE_L OFS_RTCDATE\r
+#define OFS_RTCDATE_H OFS_RTCDATE+1\r
+#define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */\r
+#define OFS_RTCYEAR_L OFS_RTCYEAR\r
+#define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
+#define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */\r
+#define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
+#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
+#define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */\r
+#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
+#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
+#define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */\r
+#define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */\r
+#define OFS_RTCSEC (0x0010)\r
+#define OFS_RTCMIN (0x0011)\r
+#define OFS_RTCHOUR (0x0012)\r
+#define OFS_RTCDOW (0x0013)\r
+#define OFS_RTCDAY (0x0014)\r
+#define OFS_RTCMON (0x0015)\r
+#define OFS_RTCAMIN (0x0018)\r
+#define OFS_RTCAHOUR (0x0019)\r
+#define OFS_RTCADOW (0x001A)\r
+#define OFS_RTCADAY (0x001B)\r
+\r
+#define RTCSEC RTCTIM0_L\r
+#define RTCMIN RTCTIM0_H\r
+#define RTCHOUR RTCTIM1_L\r
+#define RTCDOW RTCTIM1_H\r
+#define RTCDAY RTCDATE_L\r
+#define RTCMON RTCDATE_H\r
+#define RTCYEARL RTCYEAR_L\r
+#define RT0PS RTCPS_L\r
+#define RT1PS RTCPS_H\r
+#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
+#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
+#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
+#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
+\r
+/* RTCCTL0 Control Bits */\r
+#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */\r
+\r
+/* RTCCTL0 Control Bits */\r
+#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */\r
+\r
+#define RTCKEY (0xA500) /* RTC Key for RTC write access */\r
+#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */\r
+\r
+/* RTCCTL13 Control Bits */\r
+#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */\r
+#define RTCBCD (0x0080) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD (0x0040) /* RTC Hold */\r
+#define RTCMODE (0x0020) /* RTC Mode 0:Counter / 1: Calendar */\r
+#define RTCRDY (0x0010) /* RTC Ready */\r
+#define RTCSSEL1 (0x0008) /* RTC Source Select 1 */\r
+#define RTCSSEL0 (0x0004) /* RTC Source Select 0 */\r
+#define RTCTEV1 (0x0002) /* RTC Time Event 1 */\r
+#define RTCTEV0 (0x0001) /* RTC Time Event 0 */\r
+\r
+/* RTCCTL13 Control Bits */\r
+#define RTCBCD_L (0x0080) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD_L (0x0040) /* RTC Hold */\r
+#define RTCMODE_L (0x0020) /* RTC Mode 0:Counter / 1: Calendar */\r
+#define RTCRDY_L (0x0010) /* RTC Ready */\r
+#define RTCSSEL1_L (0x0008) /* RTC Source Select 1 */\r
+#define RTCSSEL0_L (0x0004) /* RTC Source Select 0 */\r
+#define RTCTEV1_L (0x0002) /* RTC Time Event 1 */\r
+#define RTCTEV0_L (0x0001) /* RTC Time Event 0 */\r
+\r
+/* RTCCTL13 Control Bits */\r
+#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */\r
+\r
+#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */\r
+#define RTCSSEL_1 (0x0004) /* RTC Source Select SMCLK */\r
+#define RTCSSEL_2 (0x0008) /* RTC Source Select RT1PS */\r
+#define RTCSSEL_3 (0x000C) /* RTC Source Select RT1PS */\r
+#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */\r
+#define RTCSSEL__SMCLK (0x0004) /* RTC Source Select SMCLK */\r
+#define RTCSSEL__RT1PS (0x0008) /* RTC Source Select RT1PS */\r
+\r
+#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV_1 (0x0001) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV_2 (0x0002) /* RTC Time Event: 2 (12:00 changed) */\r
+#define RTCTEV_3 (0x0003) /* RTC Time Event: 3 (00:00 changed) */\r
+#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV__HOUR (0x0001) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV__0000 (0x0002) /* RTC Time Event: 2 (00:00 changed) */\r
+#define RTCTEV__1200 (0x0003) /* RTC Time Event: 3 (12:00 changed) */\r
+\r
+#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */\r
+#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */\r
+#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */\r
+#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */\r
+\r
+/* RTCOCAL Control Bits */\r
+#define RTCOCALS (0x8000) /* RTC Offset Calibration Sign */\r
+#define RTCOCAL7 (0x0080) /* RTC Offset Calibration Bit 7 */\r
+#define RTCOCAL6 (0x0040) /* RTC Offset Calibration Bit 6 */\r
+#define RTCOCAL5 (0x0020) /* RTC Offset Calibration Bit 5 */\r
+#define RTCOCAL4 (0x0010) /* RTC Offset Calibration Bit 4 */\r
+#define RTCOCAL3 (0x0008) /* RTC Offset Calibration Bit 3 */\r
+#define RTCOCAL2 (0x0004) /* RTC Offset Calibration Bit 2 */\r
+#define RTCOCAL1 (0x0002) /* RTC Offset Calibration Bit 1 */\r
+#define RTCOCAL0 (0x0001) /* RTC Offset Calibration Bit 0 */\r
+\r
+/* RTCOCAL Control Bits */\r
+#define RTCOCAL7_L (0x0080) /* RTC Offset Calibration Bit 7 */\r
+#define RTCOCAL6_L (0x0040) /* RTC Offset Calibration Bit 6 */\r
+#define RTCOCAL5_L (0x0020) /* RTC Offset Calibration Bit 5 */\r
+#define RTCOCAL4_L (0x0010) /* RTC Offset Calibration Bit 4 */\r
+#define RTCOCAL3_L (0x0008) /* RTC Offset Calibration Bit 3 */\r
+#define RTCOCAL2_L (0x0004) /* RTC Offset Calibration Bit 2 */\r
+#define RTCOCAL1_L (0x0002) /* RTC Offset Calibration Bit 1 */\r
+#define RTCOCAL0_L (0x0001) /* RTC Offset Calibration Bit 0 */\r
+\r
+/* RTCOCAL Control Bits */\r
+#define RTCOCALS_H (0x0080) /* RTC Offset Calibration Sign */\r
+\r
+/* RTCTCMP Control Bits */\r
+#define RTCTCMPS (0x8000) /* RTC Temperature Compensation Sign */\r
+#define RTCTCRDY (0x4000) /* RTC Temperature compensation ready */\r
+#define RTCTCOK (0x2000) /* RTC Temperature compensation write OK */\r
+#define RTCTCMP7 (0x0080) /* RTC Temperature Compensation Bit 7 */\r
+#define RTCTCMP6 (0x0040) /* RTC Temperature Compensation Bit 6 */\r
+#define RTCTCMP5 (0x0020) /* RTC Temperature Compensation Bit 5 */\r
+#define RTCTCMP4 (0x0010) /* RTC Temperature Compensation Bit 4 */\r
+#define RTCTCMP3 (0x0008) /* RTC Temperature Compensation Bit 3 */\r
+#define RTCTCMP2 (0x0004) /* RTC Temperature Compensation Bit 2 */\r
+#define RTCTCMP1 (0x0002) /* RTC Temperature Compensation Bit 1 */\r
+#define RTCTCMP0 (0x0001) /* RTC Temperature Compensation Bit 0 */\r
+\r
+/* RTCTCMP Control Bits */\r
+#define RTCTCMP7_L (0x0080) /* RTC Temperature Compensation Bit 7 */\r
+#define RTCTCMP6_L (0x0040) /* RTC Temperature Compensation Bit 6 */\r
+#define RTCTCMP5_L (0x0020) /* RTC Temperature Compensation Bit 5 */\r
+#define RTCTCMP4_L (0x0010) /* RTC Temperature Compensation Bit 4 */\r
+#define RTCTCMP3_L (0x0008) /* RTC Temperature Compensation Bit 3 */\r
+#define RTCTCMP2_L (0x0004) /* RTC Temperature Compensation Bit 2 */\r
+#define RTCTCMP1_L (0x0002) /* RTC Temperature Compensation Bit 1 */\r
+#define RTCTCMP0_L (0x0001) /* RTC Temperature Compensation Bit 0 */\r
+\r
+/* RTCTCMP Control Bits */\r
+#define RTCTCMPS_H (0x0080) /* RTC Temperature Compensation Sign */\r
+#define RTCTCRDY_H (0x0040) /* RTC Temperature compensation ready */\r
+#define RTCTCOK_H (0x0020) /* RTC Temperature compensation write OK */\r
+\r
+#define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x8000)\r
+//#define Reserved (0x4000)\r
+#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
+#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
+#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400)\r
+//#define Reserved (0x0200)\r
+#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x8000)\r
+//#define Reserved (0x4000)\r
+//#define Reserved (0x0400)\r
+//#define Reserved (0x0200)\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x8000)\r
+//#define Reserved (0x4000)\r
+#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
+#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
+#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400)\r
+//#define Reserved (0x0200)\r
+#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+\r
+#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
+#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
+#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
+#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
+#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
+#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
+#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
+#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
+#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
+#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
+#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
+#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400)\r
+//#define Reserved (0x0200)\r
+#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+//#define Reserved (0x0400)\r
+//#define Reserved (0x0200)\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
+#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
+#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
+#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
+#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400)\r
+//#define Reserved (0x0200)\r
+#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */\r
+//#define Reserved (0x0080)\r
+//#define Reserved (0x0040)\r
+//#define Reserved (0x0020)\r
+\r
+#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
+#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
+#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
+#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
+#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
+#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
+#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
+#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
+\r
+/* RTC Definitions */\r
+#define RTCIV_NONE (0x0000) /* No Interrupt pending */\r
+#define RTCIV_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */\r
+#define RTCIV_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */\r
+#define RTCIV_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */\r
+#define RTCIV_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */\r
+#define RTCIV_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTCIV_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */\r
+\r
+/* Legacy Definitions */\r
+#define RTC_NONE (0x0000) /* No Interrupt pending */\r
+#define RTC_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */\r
+#define RTC_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */\r
+#define RTC_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */\r
+#define RTC_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */\r
+#define RTC_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTC_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */\r
+\r
+#endif\r
+/************************************************************\r
+* SFR - Special Function Register Module\r
+************************************************************/\r
+#ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */\r
+\r
+#define OFS_SFRIE1 (0x0000) /* Interrupt Enable 1 */\r
+#define OFS_SFRIE1_L OFS_SFRIE1\r
+#define OFS_SFRIE1_H OFS_SFRIE1+1\r
+\r
+/* SFRIE1 Control Bits */\r
+#define WDTIE (0x0001) /* WDT Interrupt Enable */\r
+#define OFIE (0x0002) /* Osc Fault Enable */\r
+//#define Reserved (0x0004)\r
+#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */\r
+#define NMIIE (0x0010) /* NMI Interrupt Enable */\r
+#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */\r
+#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */\r
+\r
+#define WDTIE_L (0x0001) /* WDT Interrupt Enable */\r
+#define OFIE_L (0x0002) /* Osc Fault Enable */\r
+//#define Reserved (0x0004)\r
+#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */\r
+#define NMIIE_L (0x0010) /* NMI Interrupt Enable */\r
+#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */\r
+#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */\r
+\r
+#define OFS_SFRIFG1 (0x0002) /* Interrupt Flag 1 */\r
+#define OFS_SFRIFG1_L OFS_SFRIFG1\r
+#define OFS_SFRIFG1_H OFS_SFRIFG1+1\r
+/* SFRIFG1 Control Bits */\r
+#define WDTIFG (0x0001) /* WDT Interrupt Flag */\r
+#define OFIFG (0x0002) /* Osc Fault Flag */\r
+//#define Reserved (0x0004)\r
+#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */\r
+#define NMIIFG (0x0010) /* NMI Interrupt Flag */\r
+//#define Reserved (0x0020)\r
+#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */\r
+#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */\r
+\r
+#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */\r
+#define OFIFG_L (0x0002) /* Osc Fault Flag */\r
+//#define Reserved (0x0004)\r
+#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */\r
+#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */\r
+//#define Reserved (0x0020)\r
+#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */\r
+#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */\r
+\r
+#define OFS_SFRRPCR (0x0004) /* RESET Pin Control Register */\r
+#define OFS_SFRRPCR_L OFS_SFRRPCR\r
+#define OFS_SFRRPCR_H OFS_SFRRPCR+1\r
+/* SFRRPCR Control Bits */\r
+#define SYSNMI (0x0001) /* NMI select */\r
+#define SYSNMIIES (0x0002) /* NMI edge select */\r
+#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */\r
+#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */\r
+\r
+#define SYSNMI_L (0x0001) /* NMI select */\r
+#define SYSNMIIES_L (0x0002) /* NMI edge select */\r
+#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */\r
+#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */\r
+\r
+#endif\r
+/************************************************************\r
+* SYS - System Module\r
+************************************************************/\r
+#ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */\r
+\r
+#define OFS_SYSCTL (0x0000) /* System control */\r
+#define OFS_SYSCTL_L OFS_SYSCTL\r
+#define OFS_SYSCTL_H OFS_SYSCTL+1\r
+#define OFS_SYSBSLC (0x0002) /* Boot strap configuration area */\r
+#define OFS_SYSBSLC_L OFS_SYSBSLC\r
+#define OFS_SYSBSLC_H OFS_SYSBSLC+1\r
+#define OFS_SYSJMBC (0x0006) /* JTAG mailbox control */\r
+#define OFS_SYSJMBC_L OFS_SYSJMBC\r
+#define OFS_SYSJMBC_H OFS_SYSJMBC+1\r
+#define OFS_SYSJMBI0 (0x0008) /* JTAG mailbox input 0 */\r
+#define OFS_SYSJMBI0_L OFS_SYSJMBI0\r
+#define OFS_SYSJMBI0_H OFS_SYSJMBI0+1\r
+#define OFS_SYSJMBI1 (0x000A) /* JTAG mailbox input 1 */\r
+#define OFS_SYSJMBI1_L OFS_SYSJMBI1\r
+#define OFS_SYSJMBI1_H OFS_SYSJMBI1+1\r
+#define OFS_SYSJMBO0 (0x000C) /* JTAG mailbox output 0 */\r
+#define OFS_SYSJMBO0_L OFS_SYSJMBO0\r
+#define OFS_SYSJMBO0_H OFS_SYSJMBO0+1\r
+#define OFS_SYSJMBO1 (0x000E) /* JTAG mailbox output 1 */\r
+#define OFS_SYSJMBO1_L OFS_SYSJMBO1\r
+#define OFS_SYSJMBO1_H OFS_SYSJMBO1+1\r
+\r
+#define OFS_SYSBERRIV (0x0018) /* Bus Error vector generator */\r
+#define OFS_SYSBERRIV_L OFS_SYSBERRIV\r
+#define OFS_SYSBERRIV_H OFS_SYSBERRIV+1\r
+#define OFS_SYSUNIV (0x001A) /* User NMI vector generator */\r
+#define OFS_SYSUNIV_L OFS_SYSUNIV\r
+#define OFS_SYSUNIV_H OFS_SYSUNIV+1\r
+#define OFS_SYSSNIV (0x001C) /* System NMI vector generator */\r
+#define OFS_SYSSNIV_L OFS_SYSSNIV\r
+#define OFS_SYSSNIV_H OFS_SYSSNIV+1\r
+#define OFS_SYSRSTIV (0x001E) /* Reset vector generator */\r
+#define OFS_SYSRSTIV_L OFS_SYSRSTIV\r
+#define OFS_SYSRSTIV_H OFS_SYSRSTIV+1\r
+\r
+/* SYSCTL Control Bits */\r
+#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */\r
+//#define RESERVED (0x0002) /* SYS - Reserved */\r
+#define SYSPMMPE (0x0004) /* SYS - PMM access protect */\r
+//#define RESERVED (0x0008) /* SYS - Reserved */\r
+#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */\r
+#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */\r
+//#define RESERVED (0x0040) /* SYS - Reserved */\r
+//#define RESERVED (0x0080) /* SYS - Reserved */\r
+//#define RESERVED (0x0100) /* SYS - Reserved */\r
+//#define RESERVED (0x0200) /* SYS - Reserved */\r
+//#define RESERVED (0x0400) /* SYS - Reserved */\r
+//#define RESERVED (0x0800) /* SYS - Reserved */\r
+//#define RESERVED (0x1000) /* SYS - Reserved */\r
+//#define RESERVED (0x2000) /* SYS - Reserved */\r
+//#define RESERVED (0x4000) /* SYS - Reserved */\r
+//#define RESERVED (0x8000) /* SYS - Reserved */\r
+\r
+/* SYSCTL Control Bits */\r
+#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */\r
+//#define RESERVED (0x0002) /* SYS - Reserved */\r
+#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */\r
+//#define RESERVED (0x0008) /* SYS - Reserved */\r
+#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */\r
+#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */\r
+//#define RESERVED (0x0040) /* SYS - Reserved */\r
+//#define RESERVED (0x0080) /* SYS - Reserved */\r
+//#define RESERVED (0x0100) /* SYS - Reserved */\r
+//#define RESERVED (0x0200) /* SYS - Reserved */\r
+//#define RESERVED (0x0400) /* SYS - Reserved */\r
+//#define RESERVED (0x0800) /* SYS - Reserved */\r
+//#define RESERVED (0x1000) /* SYS - Reserved */\r
+//#define RESERVED (0x2000) /* SYS - Reserved */\r
+//#define RESERVED (0x4000) /* SYS - Reserved */\r
+//#define RESERVED (0x8000) /* SYS - Reserved */\r
+\r
+/* SYSBSLC Control Bits */\r
+#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */\r
+#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */\r
+#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */\r
+//#define RESERVED (0x0008) /* SYS - Reserved */\r
+//#define RESERVED (0x0010) /* SYS - Reserved */\r
+//#define RESERVED (0x0020) /* SYS - Reserved */\r
+//#define RESERVED (0x0040) /* SYS - Reserved */\r
+//#define RESERVED (0x0080) /* SYS - Reserved */\r
+//#define RESERVED (0x0100) /* SYS - Reserved */\r
+//#define RESERVED (0x0200) /* SYS - Reserved */\r
+//#define RESERVED (0x0400) /* SYS - Reserved */\r
+//#define RESERVED (0x0800) /* SYS - Reserved */\r
+//#define RESERVED (0x1000) /* SYS - Reserved */\r
+//#define RESERVED (0x2000) /* SYS - Reserved */\r
+#define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */\r
+#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */\r
+\r
+/* SYSBSLC Control Bits */\r
+#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */\r
+#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */\r
+#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */\r
+//#define RESERVED (0x0008) /* SYS - Reserved */\r
+//#define RESERVED (0x0010) /* SYS - Reserved */\r
+//#define RESERVED (0x0020) /* SYS - Reserved */\r
+//#define RESERVED (0x0040) /* SYS - Reserved */\r
+//#define RESERVED (0x0080) /* SYS - Reserved */\r
+//#define RESERVED (0x0100) /* SYS - Reserved */\r
+//#define RESERVED (0x0200) /* SYS - Reserved */\r
+//#define RESERVED (0x0400) /* SYS - Reserved */\r
+//#define RESERVED (0x0800) /* SYS - Reserved */\r
+//#define RESERVED (0x1000) /* SYS - Reserved */\r
+//#define RESERVED (0x2000) /* SYS - Reserved */\r
+\r
+/* SYSBSLC Control Bits */\r
+//#define RESERVED (0x0008) /* SYS - Reserved */\r
+//#define RESERVED (0x0010) /* SYS - Reserved */\r
+//#define RESERVED (0x0020) /* SYS - Reserved */\r
+//#define RESERVED (0x0040) /* SYS - Reserved */\r
+//#define RESERVED (0x0080) /* SYS - Reserved */\r
+//#define RESERVED (0x0100) /* SYS - Reserved */\r
+//#define RESERVED (0x0200) /* SYS - Reserved */\r
+//#define RESERVED (0x0400) /* SYS - Reserved */\r
+//#define RESERVED (0x0800) /* SYS - Reserved */\r
+//#define RESERVED (0x1000) /* SYS - Reserved */\r
+//#define RESERVED (0x2000) /* SYS - Reserved */\r
+#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */\r
+#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */\r
+\r
+/* SYSJMBC Control Bits */\r
+#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */\r
+#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */\r
+#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */\r
+#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */\r
+#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */\r
+//#define RESERVED (0x0020) /* SYS - Reserved */\r
+#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */\r
+#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */\r
+//#define RESERVED (0x0100) /* SYS - Reserved */\r
+//#define RESERVED (0x0200) /* SYS - Reserved */\r
+//#define RESERVED (0x0400) /* SYS - Reserved */\r
+//#define RESERVED (0x0800) /* SYS - Reserved */\r
+//#define RESERVED (0x1000) /* SYS - Reserved */\r
+//#define RESERVED (0x2000) /* SYS - Reserved */\r
+//#define RESERVED (0x4000) /* SYS - Reserved */\r
+//#define RESERVED (0x8000) /* SYS - Reserved */\r
+\r
+/* SYSJMBC Control Bits */\r
+#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */\r
+#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */\r
+#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */\r
+#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */\r
+#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */\r
+//#define RESERVED (0x0020) /* SYS - Reserved */\r
+#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */\r
+#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */\r
+//#define RESERVED (0x0100) /* SYS - Reserved */\r
+//#define RESERVED (0x0200) /* SYS - Reserved */\r
+//#define RESERVED (0x0400) /* SYS - Reserved */\r
+//#define RESERVED (0x0800) /* SYS - Reserved */\r
+//#define RESERVED (0x1000) /* SYS - Reserved */\r
+//#define RESERVED (0x2000) /* SYS - Reserved */\r
+//#define RESERVED (0x4000) /* SYS - Reserved */\r
+//#define RESERVED (0x8000) /* SYS - Reserved */\r
+\r
+\r
+#endif\r
+/************************************************************\r
+* Timerx_A7\r
+************************************************************/\r
+#ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */\r
+\r
+#define OFS_TAxCTL (0x0000) /* Timerx_A7 Control */\r
+#define OFS_TAxCCTL0 (0x0002) /* Timerx_A7 Capture/Compare Control 0 */\r
+#define OFS_TAxCCTL1 (0x0004) /* Timerx_A7 Capture/Compare Control 1 */\r
+#define OFS_TAxCCTL2 (0x0006) /* Timerx_A7 Capture/Compare Control 2 */\r
+#define OFS_TAxCCTL3 (0x0008) /* Timerx_A7 Capture/Compare Control 3 */\r
+#define OFS_TAxCCTL4 (0x000A) /* Timerx_A7 Capture/Compare Control 4 */\r
+#define OFS_TAxCCTL5 (0x000C) /* Timerx_A7 Capture/Compare Control 5 */\r
+#define OFS_TAxCCTL6 (0x000E) /* Timerx_A7 Capture/Compare Control 6 */\r
+#define OFS_TAxR (0x0010) /* Timerx_A7 */\r
+#define OFS_TAxCCR0 (0x0012) /* Timerx_A7 Capture/Compare 0 */\r
+#define OFS_TAxCCR1 (0x0014) /* Timerx_A7 Capture/Compare 1 */\r
+#define OFS_TAxCCR2 (0x0016) /* Timerx_A7 Capture/Compare 2 */\r
+#define OFS_TAxCCR3 (0x0018) /* Timerx_A7 Capture/Compare 3 */\r
+#define OFS_TAxCCR4 (0x001A) /* Timerx_A7 Capture/Compare 4 */\r
+#define OFS_TAxCCR5 (0x001C) /* Timerx_A7 Capture/Compare 5 */\r
+#define OFS_TAxCCR6 (0x001E) /* Timerx_A7 Capture/Compare 6 */\r
+#define OFS_TAxIV (0x002E) /* Timerx_A7 Interrupt Vector Word */\r
+#define OFS_TAxEX0 (0x0020) /* Timerx_A7 Expansion Register 0 */\r
+\r
+/* Bits are already defined within the Timer0_Ax */\r
+\r
+/* TAxIV Definitions */\r
+#define TAxIV_NONE (0x0000) /* No Interrupt pending */\r
+#define TAxIV_TACCR1 (0x0002) /* TAxCCR1_CCIFG */\r
+#define TAxIV_TACCR2 (0x0004) /* TAxCCR2_CCIFG */\r
+#define TAxIV_TACCR3 (0x0006) /* TAxCCR3_CCIFG */\r
+#define TAxIV_TACCR4 (0x0008) /* TAxCCR4_CCIFG */\r
+#define TAxIV_TACCR5 (0x000A) /* TAxCCR5_CCIFG */\r
+#define TAxIV_TACCR6 (0x000C) /* TAxCCR6_CCIFG */\r
+#define TAxIV_TAIFG (0x000E) /* TAxIFG */\r
+\r
+/* Legacy Defines */\r
+#define TAxIV_TAxCCR1 (0x0002) /* TAxCCR1_CCIFG */\r
+#define TAxIV_TAxCCR2 (0x0004) /* TAxCCR2_CCIFG */\r
+#define TAxIV_TAxCCR3 (0x0006) /* TAxCCR3_CCIFG */\r
+#define TAxIV_TAxCCR4 (0x0008) /* TAxCCR4_CCIFG */\r
+#define TAxIV_TAxCCR5 (0x000A) /* TAxCCR5_CCIFG */\r
+#define TAxIV_TAxCCR6 (0x000C) /* TAxCCR6_CCIFG */\r
+#define TAxIV_TAxIFG (0x000E) /* TAxIFG */\r
+\r
+/* TAxCTL Control Bits */\r
+#define TASSEL1 (0x0200) /* Timer A clock source select 1 */\r
+#define TASSEL0 (0x0100) /* Timer A clock source select 0 */\r
+#define ID1 (0x0080) /* Timer A clock input divider 1 */\r
+#define ID0 (0x0040) /* Timer A clock input divider 0 */\r
+#define MC1 (0x0020) /* Timer A mode control 1 */\r
+#define MC0 (0x0010) /* Timer A mode control 0 */\r
+#define TACLR (0x0004) /* Timer A counter clear */\r
+#define TAIE (0x0002) /* Timer A counter interrupt enable */\r
+#define TAIFG (0x0001) /* Timer A counter interrupt flag */\r
+\r
+#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */\r
+#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */\r
+#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */\r
+#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */\r
+#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */\r
+#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */\r
+#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */\r
+#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */\r
+#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */\r
+#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */\r
+#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */\r
+#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */\r
+#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */\r
+#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */\r
+#define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */\r
+#define MC__CONTINOUS (2*0x10u) /* Legacy define */\r
+#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */\r
+#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */\r
+#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */\r
+#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */\r
+#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */\r
+#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */\r
+#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */\r
+#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */\r
+#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */\r
+\r
+/* TAxCCTLx Control Bits */\r
+#define CM1 (0x8000) /* Capture mode 1 */\r
+#define CM0 (0x4000) /* Capture mode 0 */\r
+#define CCIS1 (0x2000) /* Capture input select 1 */\r
+#define CCIS0 (0x1000) /* Capture input select 0 */\r
+#define SCS (0x0800) /* Capture sychronize */\r
+#define SCCI (0x0400) /* Latched capture signal (read) */\r
+#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */\r
+#define OUTMOD2 (0x0080) /* Output mode 2 */\r
+#define OUTMOD1 (0x0040) /* Output mode 1 */\r
+#define OUTMOD0 (0x0020) /* Output mode 0 */\r
+#define CCIE (0x0010) /* Capture/compare interrupt enable */\r
+#define CCI (0x0008) /* Capture input signal (read) */\r
+#define OUT (0x0004) /* PWM Output signal if output mode 0 */\r
+#define COV (0x0002) /* Capture/compare overflow flag */\r
+#define CCIFG (0x0001) /* Capture/compare interrupt flag */\r
+\r
+#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */\r
+#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */\r
+#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */\r
+#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */\r
+#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */\r
+#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */\r
+#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */\r
+#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */\r
+#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */\r
+#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */\r
+#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */\r
+#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */\r
+#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */\r
+#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */\r
+#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */\r
+#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */\r
+\r
+/* TAxEX0 Control Bits */\r
+#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */\r
+#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */\r
+#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */\r
+\r
+#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */\r
+#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */\r
+#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */\r
+#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */\r
+#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */\r
+#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */\r
+#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */\r
+#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */\r
+\r
+#endif\r
+/************************************************************\r
+* Timerx_B7\r
+************************************************************/\r
+#ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */\r
+\r
+#define OFS_TBxCTL (0x0000) /* Timerx_B7 Control */\r
+#define OFS_TBxCCTL0 (0x0002) /* Timerx_B7 Capture/Compare Control 0 */\r
+#define OFS_TBxCCTL1 (0x0004) /* Timerx_B7 Capture/Compare Control 1 */\r
+#define OFS_TBxCCTL2 (0x0006) /* Timerx_B7 Capture/Compare Control 2 */\r
+#define OFS_TBxCCTL3 (0x0008) /* Timerx_B7 Capture/Compare Control 3 */\r
+#define OFS_TBxCCTL4 (0x000A) /* Timerx_B7 Capture/Compare Control 4 */\r
+#define OFS_TBxCCTL5 (0x000C) /* Timerx_B7 Capture/Compare Control 5 */\r
+#define OFS_TBxCCTL6 (0x000E) /* Timerx_B7 Capture/Compare Control 6 */\r
+#define OFS_TBxR (0x0010) /* Timerx_B7 */\r
+#define OFS_TBxCCR0 (0x0012) /* Timerx_B7 Capture/Compare 0 */\r
+#define OFS_TBxCCR1 (0x0014) /* Timerx_B7 Capture/Compare 1 */\r
+#define OFS_TBxCCR2 (0x0016) /* Timerx_B7 Capture/Compare 2 */\r
+#define OFS_TBxCCR3 (0x0018) /* Timerx_B7 Capture/Compare 3 */\r
+#define OFS_TBxCCR4 (0x001A) /* Timerx_B7 Capture/Compare 4 */\r
+#define OFS_TBxCCR5 (0x001C) /* Timerx_B7 Capture/Compare 5 */\r
+#define OFS_TBxCCR6 (0x001E) /* Timerx_B7 Capture/Compare 6 */\r
+#define OFS_TBxIV (0x002E) /* Timerx_B7 Interrupt Vector Word */\r
+#define OFS_TBxEX0 (0x0020) /* Timerx_B7 Expansion Register 0 */\r
+\r
+/* Bits are already defined within the Timer0_Ax */\r
+\r
+/* TBxIV Definitions */\r
+#define TBxIV_NONE (0x0000) /* No Interrupt pending */\r
+#define TBxIV_TBCCR1 (0x0002) /* TBxCCR1_CCIFG */\r
+#define TBxIV_TBCCR2 (0x0004) /* TBxCCR2_CCIFG */\r
+#define TBxIV_TBCCR3 (0x0006) /* TBxCCR3_CCIFG */\r
+#define TBxIV_TBCCR4 (0x0008) /* TBxCCR4_CCIFG */\r
+#define TBxIV_TBCCR5 (0x000A) /* TBxCCR5_CCIFG */\r
+#define TBxIV_TBCCR6 (0x000C) /* TBxCCR6_CCIFG */\r
+#define TBxIV_TBIFG (0x000E) /* TBxIFG */\r
+\r
+/* Legacy Defines */\r
+#define TBxIV_TBxCCR1 (0x0002) /* TBxCCR1_CCIFG */\r
+#define TBxIV_TBxCCR2 (0x0004) /* TBxCCR2_CCIFG */\r
+#define TBxIV_TBxCCR3 (0x0006) /* TBxCCR3_CCIFG */\r
+#define TBxIV_TBxCCR4 (0x0008) /* TBxCCR4_CCIFG */\r
+#define TBxIV_TBxCCR5 (0x000A) /* TBxCCR5_CCIFG */\r
+#define TBxIV_TBxCCR6 (0x000C) /* TBxCCR6_CCIFG */\r
+#define TBxIV_TBxIFG (0x000E) /* TBxIFG */\r
+\r
+/* TBxCTL Control Bits */\r
+#define TBCLGRP1 (0x4000) /* Timer_B7 Compare latch load group 1 */\r
+#define TBCLGRP0 (0x2000) /* Timer_B7 Compare latch load group 0 */\r
+#define CNTL1 (0x1000) /* Counter lenght 1 */\r
+#define CNTL0 (0x0800) /* Counter lenght 0 */\r
+#define TBSSEL1 (0x0200) /* Clock source 1 */\r
+#define TBSSEL0 (0x0100) /* Clock source 0 */\r
+#define TBCLR (0x0004) /* Timer_B7 counter clear */\r
+#define TBIE (0x0002) /* Timer_B7 interrupt enable */\r
+#define TBIFG (0x0001) /* Timer_B7 interrupt flag */\r
+\r
+#define SHR1 (0x4000) /* Timer_B7 Compare latch load group 1 */\r
+#define SHR0 (0x2000) /* Timer_B7 Compare latch load group 0 */\r
+\r
+#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */\r
+#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */\r
+#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */\r
+#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */\r
+#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */\r
+#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */\r
+#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */\r
+#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */\r
+#define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */\r
+#define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
+#define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/\r
+#define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */\r
+#define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */\r
+#define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
+#define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/\r
+#define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */\r
+#define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */\r
+#define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */\r
+#define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */\r
+#define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */\r
+#define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */\r
+#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */\r
+#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */\r
+#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */\r
+#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */\r
+\r
+/* Additional Timer B Control Register bits are defined in Timer A */\r
+/* TBxCCTLx Control Bits */\r
+#define CLLD1 (0x0400) /* Compare latch load source 1 */\r
+#define CLLD0 (0x0200) /* Compare latch load source 0 */\r
+\r
+#define SLSHR1 (0x0400) /* Compare latch load source 1 */\r
+#define SLSHR0 (0x0200) /* Compare latch load source 0 */\r
+\r
+#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
+#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */\r
+#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
+#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */\r
+\r
+#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
+#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */\r
+#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
+#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */\r
+\r
+/* TBxEX0 Control Bits */\r
+#define TBIDEX0 (0x0001) /* Timer_B7 Input divider expansion Bit: 0 */\r
+#define TBIDEX1 (0x0002) /* Timer_B7 Input divider expansion Bit: 1 */\r
+#define TBIDEX2 (0x0004) /* Timer_B7 Input divider expansion Bit: 2 */\r
+\r
+#define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */\r
+#define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */\r
+#define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */\r
+#define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */\r
+#define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */\r
+#define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */\r
+#define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */\r
+#define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */\r
+#define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */\r
+#define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */\r
+#define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */\r
+#define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */\r
+#define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */\r
+#define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */\r
+#define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */\r
+#define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */\r
+\r
+\r
+#define ID1 (0x0080) /* Timer B clock input divider 1 */\r
+#define ID0 (0x0040) /* Timer B clock input divider 0 */\r
+#define MC1 (0x0020) /* Timer B mode control 1 */\r
+#define MC0 (0x0010) /* Timer B mode control 0 */\r
+#define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */\r
+#define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */\r
+#define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */\r
+#define MC__CONTINOUS (2*0x10u) /* Legacy define */\r
+#define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */\r
+#define CM1 (0x8000) /* Capture mode 1 */\r
+#define CM0 (0x4000) /* Capture mode 0 */\r
+#define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */\r
+#define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */\r
+#define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */\r
+#define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */\r
+#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */\r
+#define CCIE (0x0010) /* Capture/compare interrupt enable */\r
+#define CCIFG (0x0001) /* Capture/compare interrupt flag */\r
+#define CCIS_0 (0*0x1000u)\r
+#define CCIS_1 (1*0x1000u)\r
+#define CCIS_2 (2*0x1000u)\r
+#define CCIS_3 (3*0x1000u)\r
+#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */\r
+#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */\r
+#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */\r
+#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */\r
+#define OUT (0x0004) /* PWM Output signal if output mode 0 */\r
+#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */\r
+#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */\r
+#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */\r
+#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */\r
+#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */\r
+#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */\r
+#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */\r
+#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */\r
+#define SCCI (0x0400) /* Latched capture signal (read) */\r
+#define SCS (0x0800) /* Capture sychronize */\r
+#define CCI (0x0008) /* Capture input signal (read) */\r
+#define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */\r
+#define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */\r
+#define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */\r
+#define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */\r
+#define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */\r
+#define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */\r
+#define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */\r
+#define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */\r
+\r
+#endif\r
+/************************************************************\r
+* USCI Ax\r
+************************************************************/\r
+#ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */\r
+\r
+#define OFS_UCAxCTLW0 (0x0000) /* USCI Ax Control Word Register 0 */\r
+#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0\r
+#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1\r
+#define OFS_UCAxCTL0 (0x0001)\r
+#define OFS_UCAxCTL1 (0x0000)\r
+#define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */\r
+#define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */\r
+#define OFS_UCAxCTLW1 (0x0002) /* USCI Ax Control Word Register 1 */\r
+#define OFS_UCAxCTLW1_L OFS_UCAxCTLW1\r
+#define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1\r
+#define OFS_UCAxBRW (0x0006) /* USCI Ax Baud Word Rate 0 */\r
+#define OFS_UCAxBRW_L OFS_UCAxBRW\r
+#define OFS_UCAxBRW_H OFS_UCAxBRW+1\r
+#define OFS_UCAxBR0 (0x0006)\r
+#define OFS_UCAxBR1 (0x0007)\r
+#define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */\r
+#define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */\r
+#define OFS_UCAxMCTLW (0x0008) /* USCI Ax Modulation Control */\r
+#define OFS_UCAxMCTLW_L OFS_UCAxMCTLW\r
+#define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1\r
+#define OFS_UCAxSTATW (0x000A) /* USCI Ax Status Register */\r
+#define OFS_UCAxRXBUF (0x000C) /* USCI Ax Receive Buffer */\r
+#define OFS_UCAxRXBUF_L OFS_UCAxRXBUF\r
+#define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1\r
+#define OFS_UCAxTXBUF (0x000E) /* USCI Ax Transmit Buffer */\r
+#define OFS_UCAxTXBUF_L OFS_UCAxTXBUF\r
+#define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1\r
+#define OFS_UCAxABCTL (0x0010) /* USCI Ax LIN Control */\r
+#define OFS_UCAxIRCTL (0x0012) /* USCI Ax IrDA Transmit Control */\r
+#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL\r
+#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1\r
+#define OFS_UCAxIRTCTL (0x0012)\r
+#define OFS_UCAxIRRCTL (0x0013)\r
+#define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */\r
+#define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */\r
+#define OFS_UCAxIE (0x001A) /* USCI Ax Interrupt Enable Register */\r
+#define OFS_UCAxIE_L OFS_UCAxIE\r
+#define OFS_UCAxIE_H OFS_UCAxIE+1\r
+#define OFS_UCAxIFG (0x001C) /* USCI Ax Interrupt Flags Register */\r
+#define OFS_UCAxIFG_L OFS_UCAxIFG\r
+#define OFS_UCAxIFG_H OFS_UCAxIFG+1\r
+#define OFS_UCAxIE__UART (0x001A)\r
+#define OFS_UCAxIE__UART_L OFS_UCAxIE__UART\r
+#define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1\r
+#define OFS_UCAxIFG__UART (0x001C)\r
+#define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART\r
+#define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1\r
+#define OFS_UCAxIV (0x001E) /* USCI Ax Interrupt Vector Register */\r
+\r
+#define OFS_UCAxCTLW0__SPI (0x0000)\r
+#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI\r
+#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1\r
+#define OFS_UCAxCTL0__SPI (0x0001)\r
+#define OFS_UCAxCTL1__SPI (0x0000)\r
+#define OFS_UCAxBRW__SPI (0x0006)\r
+#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI\r
+#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1\r
+#define OFS_UCAxBR0__SPI (0x0006)\r
+#define OFS_UCAxBR1__SPI (0x0007)\r
+#define OFS_UCAxSTATW__SPI (0x000A)\r
+#define OFS_UCAxRXBUF__SPI (0x000C)\r
+#define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI\r
+#define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1\r
+#define OFS_UCAxTXBUF__SPI (0x000E)\r
+#define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI\r
+#define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1\r
+#define OFS_UCAxIE__SPI (0x001A)\r
+#define OFS_UCAxIFG__SPI (0x001C)\r
+#define OFS_UCAxIV__SPI (0x001E)\r
+\r
+#endif\r
+/************************************************************\r
+* USCI Bx\r
+************************************************************/\r
+#ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */\r
+\r
+#define OFS_UCBxCTLW0__SPI (0x0000)\r
+#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI\r
+#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1\r
+#define OFS_UCBxCTL0__SPI (0x0001)\r
+#define OFS_UCBxCTL1__SPI (0x0000)\r
+#define OFS_UCBxBRW__SPI (0x0006)\r
+#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI\r
+#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1\r
+#define OFS_UCBxBR0__SPI (0x0006)\r
+#define OFS_UCBxBR1__SPI (0x0007)\r
+#define OFS_UCBxSTATW__SPI (0x0008)\r
+#define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI\r
+#define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1\r
+#define OFS_UCBxRXBUF__SPI (0x000C)\r
+#define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI\r
+#define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1\r
+#define OFS_UCBxTXBUF__SPI (0x000E)\r
+#define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI\r
+#define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1\r
+#define OFS_UCBxIE__SPI (0x002A)\r
+#define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI\r
+#define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1\r
+#define OFS_UCBxIFG__SPI (0x002C)\r
+#define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI\r
+#define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1\r
+#define OFS_UCBxIV__SPI (0x002E)\r
+\r
+#define OFS_UCBxCTLW0 (0x0000) /* USCI Bx Control Word Register 0 */\r
+#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0\r
+#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1\r
+#define OFS_UCBxCTL0 (0x0001)\r
+#define OFS_UCBxCTL1 (0x0000)\r
+#define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */\r
+#define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */\r
+#define OFS_UCBxCTLW1 (0x0002) /* USCI Bx Control Word Register 1 */\r
+#define OFS_UCBxCTLW1_L OFS_UCBxCTLW1\r
+#define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1\r
+#define OFS_UCBxBRW (0x0006) /* USCI Bx Baud Word Rate 0 */\r
+#define OFS_UCBxBRW_L OFS_UCBxBRW\r
+#define OFS_UCBxBRW_H OFS_UCBxBRW+1\r
+#define OFS_UCBxBR0 (0x0006)\r
+#define OFS_UCBxBR1 (0x0007)\r
+#define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */\r
+#define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */\r
+#define OFS_UCBxSTATW (0x0008) /* USCI Bx Status Word Register */\r
+#define OFS_UCBxSTATW_L OFS_UCBxSTATW\r
+#define OFS_UCBxSTATW_H OFS_UCBxSTATW+1\r
+#define OFS_UCBxSTATW__I2C (0x0008)\r
+#define OFS_UCBxSTAT__I2C (0x0008)\r
+#define OFS_UCBxBCNT__I2C (0x0009)\r
+#define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */\r
+#define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */\r
+#define OFS_UCBxTBCNT (0x000A) /* USCI Bx Byte Counter Threshold Register */\r
+#define OFS_UCBxTBCNT_L OFS_UCBxTBCNT\r
+#define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1\r
+#define OFS_UCBxRXBUF (0x000C) /* USCI Bx Receive Buffer */\r
+#define OFS_UCBxRXBUF_L OFS_UCBxRXBUF\r
+#define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1\r
+#define OFS_UCBxTXBUF (0x000E) /* USCI Bx Transmit Buffer */\r
+#define OFS_UCBxTXBUF_L OFS_UCBxTXBUF\r
+#define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1\r
+#define OFS_UCBxI2COA0 (0x0014) /* USCI Bx I2C Own Address 0 */\r
+#define OFS_UCBxI2COA0_L OFS_UCBxI2COA0\r
+#define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1\r
+#define OFS_UCBxI2COA1 (0x0016) /* USCI Bx I2C Own Address 1 */\r
+#define OFS_UCBxI2COA1_L OFS_UCBxI2COA1\r
+#define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1\r
+#define OFS_UCBxI2COA2 (0x0018) /* USCI Bx I2C Own Address 2 */\r
+#define OFS_UCBxI2COA2_L OFS_UCBxI2COA2\r
+#define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1\r
+#define OFS_UCBxI2COA3 (0x001A) /* USCI Bx I2C Own Address 3 */\r
+#define OFS_UCBxI2COA3_L OFS_UCBxI2COA3\r
+#define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1\r
+#define OFS_UCBxADDRX (0x001C) /* USCI Bx Received Address Register */\r
+#define OFS_UCBxADDRX_L OFS_UCBxADDRX\r
+#define OFS_UCBxADDRX_H OFS_UCBxADDRX+1\r
+#define OFS_UCBxADDMASK (0x001E) /* USCI Bx Address Mask Register */\r
+#define OFS_UCBxADDMASK_L OFS_UCBxADDMASK\r
+#define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1\r
+#define OFS_UCBxI2CSA (0x0020) /* USCI Bx I2C Slave Address */\r
+#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA\r
+#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1\r
+#define OFS_UCBxIE (0x002A) /* USCI Bx Interrupt Enable Register */\r
+#define OFS_UCBxIE_L OFS_UCBxIE\r
+#define OFS_UCBxIE_H OFS_UCBxIE+1\r
+#define OFS_UCBxIFG (0x002C) /* USCI Bx Interrupt Flags Register */\r
+#define OFS_UCBxIFG_L OFS_UCBxIFG\r
+#define OFS_UCBxIFG_H OFS_UCBxIFG+1\r
+#define OFS_UCBxIE__I2C (0x002A)\r
+#define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C\r
+#define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1\r
+#define OFS_UCBxIFG__I2C (0x002C)\r
+#define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C\r
+#define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1\r
+#define OFS_UCBxIV (0x002E) /* USCI Bx Interrupt Vector Register */\r
+\r
+#endif\r
+#if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__))\r
+\r
+// UCAxCTLW0 UART-Mode Control Bits\r
+#define UCPEN (0x8000) /* Async. Mode: Parity enable */\r
+#define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */\r
+#define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */\r
+#define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */\r
+#define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */\r
+#define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */\r
+#define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */\r
+#define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */\r
+#define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */\r
+#define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */\r
+#define UCRXEIE (0x0020) /* RX Error interrupt enable */\r
+#define UCBRKIE (0x0010) /* Break interrupt enable */\r
+#define UCDORM (0x0008) /* Dormant (Sleep) Mode */\r
+#define UCTXADDR (0x0004) /* Send next Data as Address */\r
+#define UCTXBRK (0x0002) /* Send next Data as Break */\r
+#define UCSWRST (0x0001) /* USCI Software Reset */\r
+\r
+// UCAxCTLW0 UART-Mode Control Bits\r
+#define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */\r
+#define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */\r
+#define UCRXEIE_L (0x0020) /* RX Error interrupt enable */\r
+#define UCBRKIE_L (0x0010) /* Break interrupt enable */\r
+#define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */\r
+#define UCTXADDR_L (0x0004) /* Send next Data as Address */\r
+#define UCTXBRK_L (0x0002) /* Send next Data as Break */\r
+#define UCSWRST_L (0x0001) /* USCI Software Reset */\r
+\r
+// UCAxCTLW0 UART-Mode Control Bits\r
+#define UCPEN_H (0x0080) /* Async. Mode: Parity enable */\r
+#define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */\r
+#define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */\r
+#define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */\r
+#define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */\r
+#define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */\r
+#define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */\r
+#define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */\r
+\r
+// UCxxCTLW0 SPI-Mode Control Bits\r
+#define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */\r
+#define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */\r
+#define UCMST (0x0800) /* Sync. Mode: Master Select */\r
+//#define res (0x0020) /* reserved */\r
+//#define res (0x0010) /* reserved */\r
+//#define res (0x0008) /* reserved */\r
+//#define res (0x0004) /* reserved */\r
+#define UCSTEM (0x0002) /* USCI STE Mode */\r
+\r
+// UCBxCTLW0 I2C-Mode Control Bits\r
+#define UCA10 (0x8000) /* 10-bit Address Mode */\r
+#define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */\r
+#define UCMM (0x2000) /* Multi-Master Environment */\r
+//#define res (0x1000) /* reserved */\r
+//#define res (0x0100) /* reserved */\r
+#define UCTXACK (0x0020) /* Transmit ACK */\r
+#define UCTR (0x0010) /* Transmit/Receive Select/Flag */\r
+#define UCTXNACK (0x0008) /* Transmit NACK */\r
+#define UCTXSTP (0x0004) /* Transmit STOP */\r
+#define UCTXSTT (0x0002) /* Transmit START */\r
+\r
+// UCBxCTLW0 I2C-Mode Control Bits\r
+//#define res (0x1000) /* reserved */\r
+//#define res (0x0100) /* reserved */\r
+#define UCTXACK_L (0x0020) /* Transmit ACK */\r
+#define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */\r
+#define UCTXNACK_L (0x0008) /* Transmit NACK */\r
+#define UCTXSTP_L (0x0004) /* Transmit STOP */\r
+#define UCTXSTT_L (0x0002) /* Transmit START */\r
+\r
+// UCBxCTLW0 I2C-Mode Control Bits\r
+#define UCA10_H (0x0080) /* 10-bit Address Mode */\r
+#define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */\r
+#define UCMM_H (0x0020) /* Multi-Master Environment */\r
+//#define res (0x1000) /* reserved */\r
+//#define res (0x0100) /* reserved */\r
+\r
+#define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */\r
+#define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */\r
+#define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */\r
+#define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */\r
+\r
+#define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */\r
+#define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */\r
+#define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */\r
+#define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */\r
+#define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */\r
+#define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */\r
+#define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */\r
+\r
+// UCAxCTLW1 UART-Mode Control Bits\r
+#define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */\r
+#define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */\r
+\r
+// UCAxCTLW1 UART-Mode Control Bits\r
+#define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */\r
+#define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */\r
+\r
+// UCBxCTLW1 I2C-Mode Control Bits\r
+#define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */\r
+#define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */\r
+#define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */\r
+#define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */\r
+#define UCSWACK (0x0010) /* USCI Software controlled ACK */\r
+#define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */\r
+#define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */\r
+#define UCGLIT1 (0x0002) /* USCI Deglitch time Bit: 1 */\r
+#define UCGLIT0 (0x0001) /* USCI Deglitch time Bit: 0 */\r
+\r
+// UCBxCTLW1 I2C-Mode Control Bits\r
+#define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */\r
+#define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */\r
+#define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */\r
+#define UCSWACK_L (0x0010) /* USCI Software controlled ACK */\r
+#define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */\r
+#define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */\r
+#define UCGLIT1_L (0x0002) /* USCI Deglitch time Bit: 1 */\r
+#define UCGLIT0_L (0x0001) /* USCI Deglitch time Bit: 0 */\r
+\r
+// UCBxCTLW1 I2C-Mode Control Bits\r
+#define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */\r
+\r
+#define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */\r
+#define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */\r
+#define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */\r
+#define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */\r
+\r
+#define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */\r
+#define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */\r
+#define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */\r
+#define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */\r
+\r
+#define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */\r
+#define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */\r
+#define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */\r
+#define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */\r
+\r
+/* UCAxMCTLW Control Bits */\r
+#define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */\r
+#define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */\r
+#define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */\r
+#define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */\r
+#define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */\r
+#define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */\r
+#define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */\r
+#define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */\r
+#define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */\r
+#define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */\r
+#define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */\r
+#define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */\r
+#define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */\r
+\r
+/* UCAxMCTLW Control Bits */\r
+#define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */\r
+#define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */\r
+#define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */\r
+#define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */\r
+#define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */\r
+\r
+/* UCAxMCTLW Control Bits */\r
+#define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */\r
+#define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */\r
+#define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */\r
+#define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */\r
+#define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */\r
+#define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */\r
+#define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */\r
+#define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */\r
+\r
+#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */\r
+#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */\r
+#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */\r
+#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */\r
+#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */\r
+#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */\r
+#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */\r
+#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */\r
+#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */\r
+#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */\r
+#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */\r
+#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */\r
+#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */\r
+#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */\r
+#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */\r
+#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */\r
+\r
+/* UCAxSTATW Control Bits */\r
+#define UCLISTEN (0x0080) /* USCI Listen mode */\r
+#define UCFE (0x0040) /* USCI Frame Error Flag */\r
+#define UCOE (0x0020) /* USCI Overrun Error Flag */\r
+#define UCPE (0x0010) /* USCI Parity Error Flag */\r
+#define UCBRK (0x0008) /* USCI Break received */\r
+#define UCRXERR (0x0004) /* USCI RX Error Flag */\r
+#define UCADDR (0x0002) /* USCI Address received Flag */\r
+#define UCBUSY (0x0001) /* USCI Busy Flag */\r
+#define UCIDLE (0x0002) /* USCI Idle line detected Flag */\r
+\r
+/* UCBxSTATW I2C Control Bits */\r
+#define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */\r
+#define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */\r
+#define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */\r
+#define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */\r
+#define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */\r
+#define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */\r
+#define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */\r
+#define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */\r
+#define UCSCLLOW (0x0040) /* SCL low */\r
+#define UCGC (0x0020) /* General Call address received Flag */\r
+#define UCBBUSY (0x0010) /* Bus Busy Flag */\r
+\r
+/* UCBxTBCNT I2C Control Bits */\r
+#define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */\r
+#define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */\r
+#define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */\r
+#define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */\r
+#define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */\r
+#define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */\r
+#define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */\r
+#define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */\r
+\r
+/* UCAxIRCTL Control Bits */\r
+#define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */\r
+#define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */\r
+#define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */\r
+#define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */\r
+#define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */\r
+#define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */\r
+#define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */\r
+#define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */\r
+#define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */\r
+#define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */\r
+#define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */\r
+#define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */\r
+#define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */\r
+#define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */\r
+#define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */\r
+#define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */\r
+\r
+/* UCAxIRCTL Control Bits */\r
+#define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */\r
+#define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */\r
+#define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */\r
+#define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */\r
+#define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */\r
+#define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */\r
+#define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */\r
+#define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */\r
+\r
+/* UCAxIRCTL Control Bits */\r
+#define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */\r
+#define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */\r
+#define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */\r
+#define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */\r
+#define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */\r
+#define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */\r
+#define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */\r
+#define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */\r
+\r
+/* UCAxABCTL Control Bits */\r
+//#define res (0x80) /* reserved */\r
+//#define res (0x40) /* reserved */\r
+#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */\r
+#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */\r
+#define UCSTOE (0x08) /* Sync-Field Timeout error */\r
+#define UCBTOE (0x04) /* Break Timeout error */\r
+//#define res (0x02) /* reserved */\r
+#define UCABDEN (0x01) /* Auto Baud Rate detect enable */\r
+\r
+/* UCBxI2COA0 Control Bits */\r
+#define UCGCEN (0x8000) /* I2C General Call enable */\r
+#define UCOAEN (0x0400) /* I2C Own Address enable */\r
+#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */\r
+#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */\r
+#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */\r
+#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */\r
+#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */\r
+#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */\r
+#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */\r
+#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */\r
+#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */\r
+#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COA0 Control Bits */\r
+#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */\r
+#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */\r
+#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */\r
+#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */\r
+#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */\r
+#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */\r
+#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */\r
+#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COA0 Control Bits */\r
+#define UCGCEN_H (0x0080) /* I2C General Call enable */\r
+#define UCOAEN_H (0x0004) /* I2C Own Address enable */\r
+#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */\r
+#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */\r
+\r
+/* UCBxI2COAx Control Bits */\r
+#define UCOAEN (0x0400) /* I2C Own Address enable */\r
+#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */\r
+#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */\r
+#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */\r
+#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */\r
+#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */\r
+#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */\r
+#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */\r
+#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */\r
+#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */\r
+#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COAx Control Bits */\r
+#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */\r
+#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */\r
+#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */\r
+#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */\r
+#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */\r
+#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */\r
+#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */\r
+#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COAx Control Bits */\r
+#define UCOAEN_H (0x0004) /* I2C Own Address enable */\r
+#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */\r
+#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */\r
+\r
+/* UCBxADDRX Control Bits */\r
+#define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */\r
+#define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */\r
+#define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */\r
+#define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */\r
+#define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */\r
+#define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */\r
+#define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */\r
+#define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */\r
+#define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */\r
+#define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */\r
+\r
+/* UCBxADDRX Control Bits */\r
+#define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */\r
+#define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */\r
+#define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */\r
+#define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */\r
+#define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */\r
+#define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */\r
+#define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */\r
+#define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */\r
+\r
+/* UCBxADDRX Control Bits */\r
+#define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */\r
+#define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */\r
+\r
+/* UCBxADDMASK Control Bits */\r
+#define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */\r
+#define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */\r
+#define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */\r
+#define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */\r
+#define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */\r
+#define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */\r
+#define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */\r
+#define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */\r
+#define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */\r
+#define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */\r
+\r
+/* UCBxADDMASK Control Bits */\r
+#define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */\r
+#define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */\r
+#define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */\r
+#define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */\r
+#define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */\r
+#define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */\r
+#define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */\r
+#define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */\r
+\r
+/* UCBxADDMASK Control Bits */\r
+#define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */\r
+#define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */\r
+\r
+/* UCBxI2CSA Control Bits */\r
+#define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */\r
+#define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */\r
+#define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */\r
+#define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */\r
+#define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */\r
+#define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */\r
+#define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */\r
+#define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */\r
+#define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */\r
+#define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */\r
+\r
+/* UCBxI2CSA Control Bits */\r
+#define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */\r
+#define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */\r
+#define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */\r
+#define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */\r
+#define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */\r
+#define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */\r
+#define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */\r
+#define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */\r
+\r
+/* UCBxI2CSA Control Bits */\r
+#define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */\r
+#define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */\r
+\r
+/* UCAxIE UART Control Bits */\r
+#define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */\r
+#define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */\r
+#define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */\r
+#define UCRXIE (0x0001) /* UART Receive Interrupt Enable */\r
+\r
+/* UCAxIE/UCBxIE SPI Control Bits */\r
+\r
+/* UCBxIE I2C Control Bits */\r
+#define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */\r
+#define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */\r
+#define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */\r
+#define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */\r
+#define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */\r
+#define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */\r
+#define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */\r
+#define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */\r
+#define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */\r
+#define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */\r
+#define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */\r
+#define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */\r
+#define UCSTTIE (0x0004) /* I2C START Condition interrupt enable */\r
+#define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */\r
+#define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */\r
+\r
+/* UCAxIFG UART Control Bits */\r
+#define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */\r
+#define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */\r
+#define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */\r
+#define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */\r
+\r
+/* UCAxIFG/UCBxIFG SPI Control Bits */\r
+#define UCTXIFG (0x0002) /* SPI Transmit Interrupt Flag */\r
+#define UCRXIFG (0x0001) /* SPI Receive Interrupt Flag */\r
+\r
+/* UCBxIFG Control Bits */\r
+#define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */\r
+#define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */\r
+#define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */\r
+#define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */\r
+#define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */\r
+#define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */\r
+#define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */\r
+#define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */\r
+#define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */\r
+#define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */\r
+#define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */\r
+#define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */\r
+#define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */\r
+#define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */\r
+#define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */\r
+\r
+/* USCI UART Definitions */\r
+#define USCI_NONE (0x0000) /* No Interrupt pending */\r
+#define USCI_UART_UCRXIFG (0x0002) /* USCI UCRXIFG */\r
+#define USCI_UART_UCTXIFG (0x0004) /* USCI UCTXIFG */\r
+#define USCI_UART_UCSTTIFG (0x0006) /* USCI UCSTTIFG */\r
+#define USCI_UART_UCTXCPTIFG (0x0008) /* USCI UCTXCPTIFG */\r
+\r
+/* USCI SPI Definitions */\r
+#define USCI_SPI_UCRXIFG (0x0002) /* USCI UCRXIFG */\r
+#define USCI_SPI_UCTXIFG (0x0004) /* USCI UCTXIFG */\r
+\r
+/* USCI I2C Definitions */\r
+#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */\r
+#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */\r
+#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/\r
+#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/\r
+#define USCI_I2C_UCRXIFG3 (0x000A) /* USCI I2C Mode: UCRXIFG3 */\r
+#define USCI_I2C_UCTXIFG3 (0x000C) /* USCI I2C Mode: UCTXIFG3 */\r
+#define USCI_I2C_UCRXIFG2 (0x000E) /* USCI I2C Mode: UCRXIFG2 */\r
+#define USCI_I2C_UCTXIFG2 (0x0010) /* USCI I2C Mode: UCTXIFG2 */\r
+#define USCI_I2C_UCRXIFG1 (0x0012) /* USCI I2C Mode: UCRXIFG1 */\r
+#define USCI_I2C_UCTXIFG1 (0x0014) /* USCI I2C Mode: UCTXIFG1 */\r
+#define USCI_I2C_UCRXIFG0 (0x0016) /* USCI I2C Mode: UCRXIFG0 */\r
+#define USCI_I2C_UCTXIFG0 (0x0018) /* USCI I2C Mode: UCTXIFG0 */\r
+#define USCI_I2C_UCBCNTIFG (0x001A) /* USCI I2C Mode: UCBCNTIFG */\r
+#define USCI_I2C_UCCLTOIFG (0x001C) /* USCI I2C Mode: UCCLTOIFG */\r
+#define USCI_I2C_UCBIT9IFG (0x001E) /* USCI I2C Mode: UCBIT9IFG */\r
+\r
+#endif\r
+/************************************************************\r
+* WATCHDOG TIMER A\r
+************************************************************/\r
+#ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */\r
+\r
+#define OFS_WDTCTL (0x000C) /* Watchdog Timer Control */\r
+#define OFS_WDTCTL_L OFS_WDTCTL\r
+#define OFS_WDTCTL_H OFS_WDTCTL+1\r
+/* The bit names have been prefixed with "WDT" */\r
+/* WDTCTL Control Bits */\r
+#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */\r
+#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */\r
+#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */\r
+#define WDTCNTCL (0x0008) /* WDT - Timer Clear */\r
+#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */\r
+#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */\r
+#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */\r
+#define WDTHOLD (0x0080) /* WDT - Timer hold */\r
+\r
+/* WDTCTL Control Bits */\r
+#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */\r
+#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */\r
+#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */\r
+#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */\r
+#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */\r
+#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */\r
+#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */\r
+#define WDTHOLD_L (0x0080) /* WDT - Timer hold */\r
+\r
+#define WDTPW (0x5A00)\r
+\r
+#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */\r
+#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */\r
+#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */\r
+#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */\r
+#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */\r
+#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */\r
+#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */\r
+#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */\r
+#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */\r
+#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */\r
+#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */\r
+#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */\r
+#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */\r
+#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */\r
+#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */\r
+#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */\r
+\r
+#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */\r
+#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */\r
+#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */\r
+#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */\r
+#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */\r
+#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */\r
+#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */\r
+\r
+/* WDT-interval times [1ms] coded with Bits 0-2 */\r
+/* WDT is clocked by fSMCLK (assumed 1MHz) */\r
+#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */\r
+#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */\r
+#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */\r
+#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */\r
+/* WDT is clocked by fACLK (assumed 32KHz) */\r
+#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */\r
+#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */\r
+#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */\r
+#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */\r
+/* Watchdog mode -> reset after expired time */\r
+/* WDT is clocked by fSMCLK (assumed 1MHz) */\r
+#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */\r
+#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */\r
+#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */\r
+#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */\r
+/* WDT is clocked by fACLK (assumed 32KHz) */\r
+#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */\r
+#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */\r
+#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */\r
+#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */\r
+\r
+#endif\r
+\r
+/************************************************************\r
+* TLV Descriptors\r
+************************************************************/\r
+#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */\r
+#define TLV_BASE __MSP430_BASEADDRESS_TLV__\r
+\r
+#define TLV_START (0x1A08) /* Start Address of the TLV structure */\r
+#define TLV_END (0x1AFF) /* End Address of the TLV structure */\r
+\r
+#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */\r
+#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */\r
+#define TLV_Reserved3 (0x03) /* Future usage */\r
+#define TLV_Reserved4 (0x04) /* Future usage */\r
+#define TLV_BLANK (0x05) /* Blank descriptor */\r
+#define TLV_Reserved6 (0x06) /* Future usage */\r
+#define TLV_Reserved7 (0x07) /* Serial Number */\r
+#define TLV_DIERECORD (0x08) /* Die Record */\r
+#define TLV_ADCCAL (0x11) /* ADC12 calibration */\r
+#define TLV_ADC12CAL (0x11) /* ADC12 calibration */\r
+#define TLV_REFCAL (0x12) /* REF calibration */\r
+#define TLV_ADC10CAL (0x13) /* ADC10 calibration */\r
+#define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */\r
+#define TLV_TAGEXT (0xFE) /* Tag extender */\r
+#define TLV_TAGEND (0xFF) /* Tag End of Table */\r
+\r
+/************************************************************\r
+* Interrupt Vectors (offset from 0xFF80)\r
+************************************************************/\r
+\r
+#pragma diag_suppress 1107\r
+#define VECTOR_NAME(name) name##_ptr\r
+#define EMIT_PRAGMA(x) _Pragma(#x)\r
+#define CREATE_VECTOR(name) void * const VECTOR_NAME(name) = (void *)(long)&name\r
+#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))\r
+#define PLACE_INTERRUPT(func) EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))\r
+#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \\r
+ PLACE_VECTOR(VECTOR_NAME(func), offset) \\r
+ PLACE_INTERRUPT(func)\r
+\r
+\r
+/************************************************************\r
+* End of Modules\r
+************************************************************/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* extern "C" */\r
+\r
+#endif /* #ifndef __msp430FR5XX_FR6XXGENERIC */\r
+\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+/********************************************************************\r
+*\r
+* Standard register and bit definitions for the Texas Instruments\r
+* MSP430 microcontroller.\r
+*\r
+* This file supports assembler and C development for\r
+* MSP430FR5XX_FR6XXGENERIC device.\r
+*\r
+* Texas Instruments, Version 1.0\r
+*\r
+* Rev. 1.0, Setup\r
+*\r
+*\r
+********************************************************************/\r
+\r
+#ifndef __msp430FR5XX_FR6XXGENERIC\r
+#define __msp430FR5XX_FR6XXGENERIC\r
+\r
+//#define __MSP430_HEADER_VERSION__ 1125\r
+\r
+#ifdef __IAR_SYSTEMS_ICC__\r
+#ifndef _SYSTEM_BUILD\r
+#pragma system_include\r
+#endif\r
+#endif\r
+\r
+#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */\r
+#error msp430fr5xx_6xxgeneric.h file for use with ICC430/A430 only\r
+#endif\r
+\r
+\r
+#ifdef __IAR_SYSTEMS_ICC__\r
+#include "in430.h"\r
+#pragma language=extended\r
+\r
+#define DEFC(name, address) __no_init volatile unsigned char name @ address;\r
+#define DEFW(name, address) __no_init volatile unsigned short name @ address;\r
+\r
+#define DEFCW(name, address) __no_init union \\r
+{ \\r
+ struct \\r
+ { \\r
+ volatile unsigned char name##_L; \\r
+ volatile unsigned char name##_H; \\r
+ }; \\r
+ volatile unsigned short name; \\r
+} @ address;\r
+\r
+#define READ_ONLY_DEFCW(name, address) __no_init union \\r
+{ \\r
+ struct \\r
+ { \\r
+ volatile READ_ONLY unsigned char name##_L; \\r
+ volatile READ_ONLY unsigned char name##_H; \\r
+ }; \\r
+ volatile READ_ONLY unsigned short name; \\r
+} @ address;\r
+\r
+\r
+#if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__\r
+#define __ACCESS_20BIT_REG__ void __data20 * volatile\r
+#else\r
+#define __ACCESS_20BIT_REG__ volatile unsigned short /* only short access from C is allowed in small memory model */\r
+#endif\r
+\r
+#define DEFA(name, address) __no_init union \\r
+{ \\r
+ struct \\r
+ { \\r
+ volatile unsigned char name##_L; \\r
+ volatile unsigned char name##_H; \\r
+ }; \\r
+ struct \\r
+ { \\r
+ volatile unsigned short name##L; \\r
+ volatile unsigned short name##H; \\r
+ }; \\r
+ __ACCESS_20BIT_REG__ name; \\r
+} @ address;\r
+\r
+#endif /* __IAR_SYSTEMS_ICC__ */\r
+\r
+\r
+#ifdef __IAR_SYSTEMS_ASM__\r
+#define DEFC(name, address) sfrb name = address;\r
+#define DEFW(name, address) sfrw name = address;\r
+\r
+#define DEFCW(name, address) sfrbw name, name##_L, name##_H, address;\r
+sfrbw macro name, name_L, name_H, address;\r
+sfrb name_L = address;\r
+sfrb name_H = address+1;\r
+sfrw name = address;\r
+ endm\r
+\r
+#define READ_ONLY_DEFCW(name, address) const_sfrbw name, name##_L, name##_H, address;\r
+const_sfrbw macro name, name_L, name_H, address;\r
+const sfrb name_L = address;\r
+const sfrb name_H = address+1;\r
+const sfrw name = address;\r
+ endm\r
+\r
+#define DEFA(name, address) sfrba name, name##L, name##H, name##_L, name##_H, address;\r
+sfrba macro name, nameL, nameH, name_L, name_H, address;\r
+sfrb name_L = address;\r
+sfrb name_H = address+1;\r
+sfrw nameL = address;\r
+sfrw nameH = address+2;\r
+sfrl name = address;\r
+ endm\r
+\r
+#endif /* __IAR_SYSTEMS_ASM__*/\r
+\r
+#ifdef __cplusplus\r
+#define READ_ONLY\r
+#else\r
+#define READ_ONLY const\r
+#endif\r
+\r
+/************************************************************\r
+* STANDARD BITS\r
+************************************************************/\r
+\r
+#define BIT0 (0x0001u)\r
+#define BIT1 (0x0002u)\r
+#define BIT2 (0x0004u)\r
+#define BIT3 (0x0008u)\r
+#define BIT4 (0x0010u)\r
+#define BIT5 (0x0020u)\r
+#define BIT6 (0x0040u)\r
+#define BIT7 (0x0080u)\r
+#define BIT8 (0x0100u)\r
+#define BIT9 (0x0200u)\r
+#define BITA (0x0400u)\r
+#define BITB (0x0800u)\r
+#define BITC (0x1000u)\r
+#define BITD (0x2000u)\r
+#define BITE (0x4000u)\r
+#define BITF (0x8000u)\r
+\r
+/************************************************************\r
+* STATUS REGISTER BITS\r
+************************************************************/\r
+\r
+#define C (0x0001u)\r
+#define Z (0x0002u)\r
+#define N (0x0004u)\r
+#define V (0x0100u)\r
+#define GIE (0x0008u)\r
+#define CPUOFF (0x0010u)\r
+#define OSCOFF (0x0020u)\r
+#define SCG0 (0x0040u)\r
+#define SCG1 (0x0080u)\r
+\r
+/* Low Power Modes coded with Bits 4-7 in SR */\r
+\r
+#ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */\r
+#define LPM0 (CPUOFF)\r
+#define LPM1 (SCG0+CPUOFF)\r
+#define LPM2 (SCG1+CPUOFF)\r
+#define LPM3 (SCG1+SCG0+CPUOFF)\r
+#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)\r
+/* End #defines for assembler */\r
+\r
+#else /* Begin #defines for C */\r
+#define LPM0_bits (CPUOFF)\r
+#define LPM1_bits (SCG0+CPUOFF)\r
+#define LPM2_bits (SCG1+CPUOFF)\r
+#define LPM3_bits (SCG1+SCG0+CPUOFF)\r
+#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)\r
+\r
+#include "in430.h"\r
+\r
+#if __MSP430_HEADER_VERSION__ < 1107\r
+#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */\r
+#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */\r
+#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */\r
+#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */\r
+#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */\r
+#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */\r
+#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */\r
+#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */\r
+#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */\r
+#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */\r
+#else\r
+#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */\r
+#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */\r
+#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */\r
+#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */\r
+#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */\r
+#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */\r
+#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */\r
+#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */\r
+#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */\r
+#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */\r
+#endif\r
+#endif /* End #defines for C */\r
+\r
+/************************************************************\r
+* CPU\r
+************************************************************/\r
+#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */\r
+\r
+#if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \\r
+ || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \\r
+ || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \\r
+ || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__)\r
+ #define __MSP430_HAS_TxA7__\r
+#endif\r
+#if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \\r
+ || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__)\r
+ #define __MSP430_HAS_TxB7__\r
+#endif\r
+#if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \\r
+ || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__)\r
+ #define __MSP430_HAS_TxD7__\r
+#endif\r
+#if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__)\r
+ #define __MSP430_HAS_USCI_Ax__\r
+#endif\r
+#if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__)\r
+ #define __MSP430_HAS_USCI_Bx__\r
+#endif\r
+#if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__)\r
+ #define __MSP430_HAS_EUSCI_Ax__\r
+#endif\r
+#if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__)\r
+ #define __MSP430_HAS_EUSCI_Bx__\r
+#endif\r
+#ifdef __MSP430_HAS_EUSCI_B0__\r
+ #define __MSP430_HAS_EUSCI_Bx__\r
+#endif\r
+\r
+/************************************************************\r
+* ADC12_B\r
+************************************************************/\r
+#ifdef __MSP430_HAS_ADC12_B__ /* Definition to show that Module is available */\r
+\r
+#define OFS_ADC12CTL0 (0x0000u) /* ADC12 B Control 0 */\r
+#define OFS_ADC12CTL0_L OFS_ADC12CTL0\r
+#define OFS_ADC12CTL0_H OFS_ADC12CTL0+1\r
+#define OFS_ADC12CTL1 (0x0002u) /* ADC12 B Control 1 */\r
+#define OFS_ADC12CTL1_L OFS_ADC12CTL1\r
+#define OFS_ADC12CTL1_H OFS_ADC12CTL1+1\r
+#define OFS_ADC12CTL2 (0x0004u) /* ADC12 B Control 2 */\r
+#define OFS_ADC12CTL2_L OFS_ADC12CTL2\r
+#define OFS_ADC12CTL2_H OFS_ADC12CTL2+1\r
+#define OFS_ADC12CTL3 (0x0006u) /* ADC12 B Control 3 */\r
+#define OFS_ADC12CTL3_L OFS_ADC12CTL3\r
+#define OFS_ADC12CTL3_H OFS_ADC12CTL3+1\r
+#define OFS_ADC12LO (0x0008u) /* ADC12 B Window Comparator High Threshold */\r
+#define OFS_ADC12LO_L OFS_ADC12LO\r
+#define OFS_ADC12LO_H OFS_ADC12LO+1\r
+#define OFS_ADC12HI (0x000Au) /* ADC12 B Window Comparator High Threshold */\r
+#define OFS_ADC12HI_L OFS_ADC12HI\r
+#define OFS_ADC12HI_H OFS_ADC12HI+1\r
+#define OFS_ADC12IFGR0 (0x000Cu) /* ADC12 B Interrupt Flag 0 */\r
+#define OFS_ADC12IFGR0_L OFS_ADC12IFGR0\r
+#define OFS_ADC12IFGR0_H OFS_ADC12IFGR0+1\r
+#define OFS_ADC12IFGR1 (0x000Eu) /* ADC12 B Interrupt Flag 1 */\r
+#define OFS_ADC12IFGR1_L OFS_ADC12IFGR1\r
+#define OFS_ADC12IFGR1_H OFS_ADC12IFGR1+1\r
+#define OFS_ADC12IFGR2 (0x0010u) /* ADC12 B Interrupt Flag 2 */\r
+#define OFS_ADC12IFGR2_L OFS_ADC12IFGR2\r
+#define OFS_ADC12IFGR2_H OFS_ADC12IFGR2+1\r
+#define OFS_ADC12IER0 (0x0012u) /* ADC12 B Interrupt Enable 0 */\r
+#define OFS_ADC12IER0_L OFS_ADC12IER0\r
+#define OFS_ADC12IER0_H OFS_ADC12IER0+1\r
+#define OFS_ADC12IER1 (0x0014u) /* ADC12 B Interrupt Enable 1 */\r
+#define OFS_ADC12IER1_L OFS_ADC12IER1\r
+#define OFS_ADC12IER1_H OFS_ADC12IER1+1\r
+#define OFS_ADC12IER2 (0x0016u) /* ADC12 B Interrupt Enable 2 */\r
+#define OFS_ADC12IER2_L OFS_ADC12IER2\r
+#define OFS_ADC12IER2_H OFS_ADC12IER2+1\r
+#define OFS_ADC12IV (0x0018u) /* ADC12 B Interrupt Vector Word */\r
+#define OFS_ADC12IV_L OFS_ADC12IV\r
+#define OFS_ADC12IV_H OFS_ADC12IV+1\r
+\r
+#define OFS_ADC12MCTL0 (0x0020u) /* ADC12 Memory Control 0 */\r
+#define OFS_ADC12MCTL0_L OFS_ADC12MCTL0\r
+#define OFS_ADC12MCTL0_H OFS_ADC12MCTL0+1\r
+#define OFS_ADC12MCTL1 (0x0022u) /* ADC12 Memory Control 1 */\r
+#define OFS_ADC12MCTL1_L OFS_ADC12MCTL1\r
+#define OFS_ADC12MCTL1_H OFS_ADC12MCTL1+1\r
+#define OFS_ADC12MCTL2 (0x0024u) /* ADC12 Memory Control 2 */\r
+#define OFS_ADC12MCTL2_L OFS_ADC12MCTL2\r
+#define OFS_ADC12MCTL2_H OFS_ADC12MCTL2+1\r
+#define OFS_ADC12MCTL3 (0x0026u) /* ADC12 Memory Control 3 */\r
+#define OFS_ADC12MCTL3_L OFS_ADC12MCTL3\r
+#define OFS_ADC12MCTL3_H OFS_ADC12MCTL3+1\r
+#define OFS_ADC12MCTL4 (0x0028u) /* ADC12 Memory Control 4 */\r
+#define OFS_ADC12MCTL4_L OFS_ADC12MCTL4\r
+#define OFS_ADC12MCTL4_H OFS_ADC12MCTL4+1\r
+#define OFS_ADC12MCTL5 (0x002Au) /* ADC12 Memory Control 5 */\r
+#define OFS_ADC12MCTL5_L OFS_ADC12MCTL5\r
+#define OFS_ADC12MCTL5_H OFS_ADC12MCTL5+1\r
+#define OFS_ADC12MCTL6 (0x002Cu) /* ADC12 Memory Control 6 */\r
+#define OFS_ADC12MCTL6_L OFS_ADC12MCTL6\r
+#define OFS_ADC12MCTL6_H OFS_ADC12MCTL6+1\r
+#define OFS_ADC12MCTL7 (0x002Eu) /* ADC12 Memory Control 7 */\r
+#define OFS_ADC12MCTL7_L OFS_ADC12MCTL7\r
+#define OFS_ADC12MCTL7_H OFS_ADC12MCTL7+1\r
+#define OFS_ADC12MCTL8 (0x0030u) /* ADC12 Memory Control 8 */\r
+#define OFS_ADC12MCTL8_L OFS_ADC12MCTL8\r
+#define OFS_ADC12MCTL8_H OFS_ADC12MCTL8+1\r
+#define OFS_ADC12MCTL9 (0x0032u) /* ADC12 Memory Control 9 */\r
+#define OFS_ADC12MCTL9_L OFS_ADC12MCTL9\r
+#define OFS_ADC12MCTL9_H OFS_ADC12MCTL9+1\r
+#define OFS_ADC12MCTL10 (0x0034u) /* ADC12 Memory Control 10 */\r
+#define OFS_ADC12MCTL10_L OFS_ADC12MCTL10\r
+#define OFS_ADC12MCTL10_H OFS_ADC12MCTL10+1\r
+#define OFS_ADC12MCTL11 (0x0036u) /* ADC12 Memory Control 11 */\r
+#define OFS_ADC12MCTL11_L OFS_ADC12MCTL11\r
+#define OFS_ADC12MCTL11_H OFS_ADC12MCTL11+1\r
+#define OFS_ADC12MCTL12 (0x0038u) /* ADC12 Memory Control 12 */\r
+#define OFS_ADC12MCTL12_L OFS_ADC12MCTL12\r
+#define OFS_ADC12MCTL12_H OFS_ADC12MCTL12+1\r
+#define OFS_ADC12MCTL13 (0x003Au) /* ADC12 Memory Control 13 */\r
+#define OFS_ADC12MCTL13_L OFS_ADC12MCTL13\r
+#define OFS_ADC12MCTL13_H OFS_ADC12MCTL13+1\r
+#define OFS_ADC12MCTL14 (0x003Cu) /* ADC12 Memory Control 14 */\r
+#define OFS_ADC12MCTL14_L OFS_ADC12MCTL14\r
+#define OFS_ADC12MCTL14_H OFS_ADC12MCTL14+1\r
+#define OFS_ADC12MCTL15 (0x003Eu) /* ADC12 Memory Control 15 */\r
+#define OFS_ADC12MCTL15_L OFS_ADC12MCTL15\r
+#define OFS_ADC12MCTL15_H OFS_ADC12MCTL15+1\r
+#define OFS_ADC12MCTL16 (0x0040u) /* ADC12 Memory Control 16 */\r
+#define OFS_ADC12MCTL16_L OFS_ADC12MCTL16\r
+#define OFS_ADC12MCTL16_H OFS_ADC12MCTL16+1\r
+#define OFS_ADC12MCTL17 (0x0042u) /* ADC12 Memory Control 17 */\r
+#define OFS_ADC12MCTL17_L OFS_ADC12MCTL17\r
+#define OFS_ADC12MCTL17_H OFS_ADC12MCTL17+1\r
+#define OFS_ADC12MCTL18 (0x0044u) /* ADC12 Memory Control 18 */\r
+#define OFS_ADC12MCTL18_L OFS_ADC12MCTL18\r
+#define OFS_ADC12MCTL18_H OFS_ADC12MCTL18+1\r
+#define OFS_ADC12MCTL19 (0x0046u) /* ADC12 Memory Control 19 */\r
+#define OFS_ADC12MCTL19_L OFS_ADC12MCTL19\r
+#define OFS_ADC12MCTL19_H OFS_ADC12MCTL19+1\r
+#define OFS_ADC12MCTL20 (0x0048u) /* ADC12 Memory Control 20 */\r
+#define OFS_ADC12MCTL20_L OFS_ADC12MCTL20\r
+#define OFS_ADC12MCTL20_H OFS_ADC12MCTL20+1\r
+#define OFS_ADC12MCTL21 (0x004Au) /* ADC12 Memory Control 21 */\r
+#define OFS_ADC12MCTL21_L OFS_ADC12MCTL21\r
+#define OFS_ADC12MCTL21_H OFS_ADC12MCTL21+1\r
+#define OFS_ADC12MCTL22 (0x004Cu) /* ADC12 Memory Control 22 */\r
+#define OFS_ADC12MCTL22_L OFS_ADC12MCTL22\r
+#define OFS_ADC12MCTL22_H OFS_ADC12MCTL22+1\r
+#define OFS_ADC12MCTL23 (0x004Eu) /* ADC12 Memory Control 23 */\r
+#define OFS_ADC12MCTL23_L OFS_ADC12MCTL23\r
+#define OFS_ADC12MCTL23_H OFS_ADC12MCTL23+1\r
+#define OFS_ADC12MCTL24 (0x0050u) /* ADC12 Memory Control 24 */\r
+#define OFS_ADC12MCTL24_L OFS_ADC12MCTL24\r
+#define OFS_ADC12MCTL24_H OFS_ADC12MCTL24+1\r
+#define OFS_ADC12MCTL25 (0x0052u) /* ADC12 Memory Control 25 */\r
+#define OFS_ADC12MCTL25_L OFS_ADC12MCTL25\r
+#define OFS_ADC12MCTL25_H OFS_ADC12MCTL25+1\r
+#define OFS_ADC12MCTL26 (0x0054u) /* ADC12 Memory Control 26 */\r
+#define OFS_ADC12MCTL26_L OFS_ADC12MCTL26\r
+#define OFS_ADC12MCTL26_H OFS_ADC12MCTL26+1\r
+#define OFS_ADC12MCTL27 (0x0056u) /* ADC12 Memory Control 27 */\r
+#define OFS_ADC12MCTL27_L OFS_ADC12MCTL27\r
+#define OFS_ADC12MCTL27_H OFS_ADC12MCTL27+1\r
+#define OFS_ADC12MCTL28 (0x0058u) /* ADC12 Memory Control 28 */\r
+#define OFS_ADC12MCTL28_L OFS_ADC12MCTL28\r
+#define OFS_ADC12MCTL28_H OFS_ADC12MCTL28+1\r
+#define OFS_ADC12MCTL29 (0x005Au) /* ADC12 Memory Control 29 */\r
+#define OFS_ADC12MCTL29_L OFS_ADC12MCTL29\r
+#define OFS_ADC12MCTL29_H OFS_ADC12MCTL29+1\r
+#define OFS_ADC12MCTL30 (0x005Cu) /* ADC12 Memory Control 30 */\r
+#define OFS_ADC12MCTL30_L OFS_ADC12MCTL30\r
+#define OFS_ADC12MCTL30_H OFS_ADC12MCTL30+1\r
+#define OFS_ADC12MCTL31 (0x005Eu) /* ADC12 Memory Control 31 */\r
+#define OFS_ADC12MCTL31_L OFS_ADC12MCTL31\r
+#define OFS_ADC12MCTL31_H OFS_ADC12MCTL31+1\r
+#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */\r
+#ifndef __IAR_SYSTEMS_ICC__\r
+#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */\r
+#else\r
+#define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */\r
+#endif\r
+\r
+#define OFS_ADC12MEM0 (0x0060u) /* ADC12 Conversion Memory 0 */\r
+#define OFS_ADC12MEM0_L OFS_ADC12MEM0\r
+#define OFS_ADC12MEM0_H OFS_ADC12MEM0+1\r
+#define OFS_ADC12MEM1 (0x0062u) /* ADC12 Conversion Memory 1 */\r
+#define OFS_ADC12MEM1_L OFS_ADC12MEM1\r
+#define OFS_ADC12MEM1_H OFS_ADC12MEM1+1\r
+#define OFS_ADC12MEM2 (0x0064u) /* ADC12 Conversion Memory 2 */\r
+#define OFS_ADC12MEM2_L OFS_ADC12MEM2\r
+#define OFS_ADC12MEM2_H OFS_ADC12MEM2+1\r
+#define OFS_ADC12MEM3 (0x0066u) /* ADC12 Conversion Memory 3 */\r
+#define OFS_ADC12MEM3_L OFS_ADC12MEM3\r
+#define OFS_ADC12MEM3_H OFS_ADC12MEM3+1\r
+#define OFS_ADC12MEM4 (0x0068u) /* ADC12 Conversion Memory 4 */\r
+#define OFS_ADC12MEM4_L OFS_ADC12MEM4\r
+#define OFS_ADC12MEM4_H OFS_ADC12MEM4+1\r
+#define OFS_ADC12MEM5 (0x006Au) /* ADC12 Conversion Memory 5 */\r
+#define OFS_ADC12MEM5_L OFS_ADC12MEM5\r
+#define OFS_ADC12MEM5_H OFS_ADC12MEM5+1\r
+#define OFS_ADC12MEM6 (0x006Cu) /* ADC12 Conversion Memory 6 */\r
+#define OFS_ADC12MEM6_L OFS_ADC12MEM6\r
+#define OFS_ADC12MEM6_H OFS_ADC12MEM6+1\r
+#define OFS_ADC12MEM7 (0x006Eu) /* ADC12 Conversion Memory 7 */\r
+#define OFS_ADC12MEM7_L OFS_ADC12MEM7\r
+#define OFS_ADC12MEM7_H OFS_ADC12MEM7+1\r
+#define OFS_ADC12MEM8 (0x0070u) /* ADC12 Conversion Memory 8 */\r
+#define OFS_ADC12MEM8_L OFS_ADC12MEM8\r
+#define OFS_ADC12MEM8_H OFS_ADC12MEM8+1\r
+#define OFS_ADC12MEM9 (0x0072u) /* ADC12 Conversion Memory 9 */\r
+#define OFS_ADC12MEM9_L OFS_ADC12MEM9\r
+#define OFS_ADC12MEM9_H OFS_ADC12MEM9+1\r
+#define OFS_ADC12MEM10 (0x0074u) /* ADC12 Conversion Memory 10 */\r
+#define OFS_ADC12MEM10_L OFS_ADC12MEM10\r
+#define OFS_ADC12MEM10_H OFS_ADC12MEM10+1\r
+#define OFS_ADC12MEM11 (0x0076u) /* ADC12 Conversion Memory 11 */\r
+#define OFS_ADC12MEM11_L OFS_ADC12MEM11\r
+#define OFS_ADC12MEM11_H OFS_ADC12MEM11+1\r
+#define OFS_ADC12MEM12 (0x0078u) /* ADC12 Conversion Memory 12 */\r
+#define OFS_ADC12MEM12_L OFS_ADC12MEM12\r
+#define OFS_ADC12MEM12_H OFS_ADC12MEM12+1\r
+#define OFS_ADC12MEM13 (0x007Au) /* ADC12 Conversion Memory 13 */\r
+#define OFS_ADC12MEM13_L OFS_ADC12MEM13\r
+#define OFS_ADC12MEM13_H OFS_ADC12MEM13+1\r
+#define OFS_ADC12MEM14 (0x007Cu) /* ADC12 Conversion Memory 14 */\r
+#define OFS_ADC12MEM14_L OFS_ADC12MEM14\r
+#define OFS_ADC12MEM14_H OFS_ADC12MEM14+1\r
+#define OFS_ADC12MEM15 (0x007Eu) /* ADC12 Conversion Memory 15 */\r
+#define OFS_ADC12MEM15_L OFS_ADC12MEM15\r
+#define OFS_ADC12MEM15_H OFS_ADC12MEM15+1\r
+#define OFS_ADC12MEM16 (0x0080u) /* ADC12 Conversion Memory 16 */\r
+#define OFS_ADC12MEM16_L OFS_ADC12MEM16\r
+#define OFS_ADC12MEM16_H OFS_ADC12MEM16+1\r
+#define OFS_ADC12MEM17 (0x0082u) /* ADC12 Conversion Memory 17 */\r
+#define OFS_ADC12MEM17_L OFS_ADC12MEM17\r
+#define OFS_ADC12MEM17_H OFS_ADC12MEM17+1\r
+#define OFS_ADC12MEM18 (0x0084u) /* ADC12 Conversion Memory 18 */\r
+#define OFS_ADC12MEM18_L OFS_ADC12MEM18\r
+#define OFS_ADC12MEM18_H OFS_ADC12MEM18+1\r
+#define OFS_ADC12MEM19 (0x0086u) /* ADC12 Conversion Memory 19 */\r
+#define OFS_ADC12MEM19_L OFS_ADC12MEM19\r
+#define OFS_ADC12MEM19_H OFS_ADC12MEM19+1\r
+#define OFS_ADC12MEM20 (0x0088u) /* ADC12 Conversion Memory 20 */\r
+#define OFS_ADC12MEM20_L OFS_ADC12MEM20\r
+#define OFS_ADC12MEM20_H OFS_ADC12MEM20+1\r
+#define OFS_ADC12MEM21 (0x008Au) /* ADC12 Conversion Memory 21 */\r
+#define OFS_ADC12MEM21_L OFS_ADC12MEM21\r
+#define OFS_ADC12MEM21_H OFS_ADC12MEM21+1\r
+#define OFS_ADC12MEM22 (0x008Cu) /* ADC12 Conversion Memory 22 */\r
+#define OFS_ADC12MEM22_L OFS_ADC12MEM22\r
+#define OFS_ADC12MEM22_H OFS_ADC12MEM22+1\r
+#define OFS_ADC12MEM23 (0x008Eu) /* ADC12 Conversion Memory 23 */\r
+#define OFS_ADC12MEM23_L OFS_ADC12MEM23\r
+#define OFS_ADC12MEM23_H OFS_ADC12MEM23+1\r
+#define OFS_ADC12MEM24 (0x0090u) /* ADC12 Conversion Memory 24 */\r
+#define OFS_ADC12MEM24_L OFS_ADC12MEM24\r
+#define OFS_ADC12MEM24_H OFS_ADC12MEM24+1\r
+#define OFS_ADC12MEM25 (0x0092u) /* ADC12 Conversion Memory 25 */\r
+#define OFS_ADC12MEM25_L OFS_ADC12MEM25\r
+#define OFS_ADC12MEM25_H OFS_ADC12MEM25+1\r
+#define OFS_ADC12MEM26 (0x0094u) /* ADC12 Conversion Memory 26 */\r
+#define OFS_ADC12MEM26_L OFS_ADC12MEM26\r
+#define OFS_ADC12MEM26_H OFS_ADC12MEM26+1\r
+#define OFS_ADC12MEM27 (0x0096u) /* ADC12 Conversion Memory 27 */\r
+#define OFS_ADC12MEM27_L OFS_ADC12MEM27\r
+#define OFS_ADC12MEM27_H OFS_ADC12MEM27+1\r
+#define OFS_ADC12MEM28 (0x0098u) /* ADC12 Conversion Memory 28 */\r
+#define OFS_ADC12MEM28_L OFS_ADC12MEM28\r
+#define OFS_ADC12MEM28_H OFS_ADC12MEM28+1\r
+#define OFS_ADC12MEM29 (0x009Au) /* ADC12 Conversion Memory 29 */\r
+#define OFS_ADC12MEM29_L OFS_ADC12MEM29\r
+#define OFS_ADC12MEM29_H OFS_ADC12MEM29+1\r
+#define OFS_ADC12MEM30 (0x009Cu) /* ADC12 Conversion Memory 30 */\r
+#define OFS_ADC12MEM30_L OFS_ADC12MEM30\r
+#define OFS_ADC12MEM30_H OFS_ADC12MEM30+1\r
+#define OFS_ADC12MEM31 (0x009Eu) /* ADC12 Conversion Memory 31 */\r
+#define OFS_ADC12MEM31_L OFS_ADC12MEM31\r
+#define OFS_ADC12MEM31_H OFS_ADC12MEM31+1\r
+#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */\r
+#ifndef __IAR_SYSTEMS_ICC__\r
+#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */\r
+#else\r
+#define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */\r
+#endif\r
+\r
+/* ADC12CTL0 Control Bits */\r
+#define ADC12SC (0x0001u) /* ADC12 Start Conversion */\r
+#define ADC12ENC (0x0002u) /* ADC12 Enable Conversion */\r
+#define ADC12ON (0x0010u) /* ADC12 On/enable */\r
+#define ADC12MSC (0x0080u) /* ADC12 Multiple SampleConversion */\r
+#define ADC12SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
+#define ADC12SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
+#define ADC12SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
+#define ADC12SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
+#define ADC12SHT10 (0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
+#define ADC12SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
+#define ADC12SHT12 (0x4000u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
+#define ADC12SHT13 (0x8000u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
+\r
+/* ADC12CTL0 Control Bits */\r
+#define ADC12SC_L (0x0001u) /* ADC12 Start Conversion */\r
+#define ADC12ENC_L (0x0002u) /* ADC12 Enable Conversion */\r
+#define ADC12ON_L (0x0010u) /* ADC12 On/enable */\r
+#define ADC12MSC_L (0x0080u) /* ADC12 Multiple SampleConversion */\r
+\r
+/* ADC12CTL0 Control Bits */\r
+#define ADC12SHT00_H (0x0001u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
+#define ADC12SHT01_H (0x0002u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
+#define ADC12SHT02_H (0x0004u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
+#define ADC12SHT03_H (0x0008u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
+#define ADC12SHT10_H (0x0010u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
+#define ADC12SHT11_H (0x0020u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
+#define ADC12SHT12_H (0x0040u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
+#define ADC12SHT13_H (0x0080u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
+\r
+#define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
+#define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
+#define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
+#define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
+#define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */\r
+#define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */\r
+#define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */\r
+#define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */\r
+#define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */\r
+#define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */\r
+#define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */\r
+#define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */\r
+#define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */\r
+#define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */\r
+#define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */\r
+#define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */\r
+\r
+#define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
+#define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
+#define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
+#define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
+#define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */\r
+#define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */\r
+#define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */\r
+#define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */\r
+#define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */\r
+#define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */\r
+#define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */\r
+#define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */\r
+#define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */\r
+#define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */\r
+#define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */\r
+#define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */\r
+\r
+/* ADC12CTL1 Control Bits */\r
+#define ADC12BUSY (0x0001u) /* ADC12 Busy */\r
+#define ADC12CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */\r
+#define ADC12CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */\r
+#define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select Bit: 0 */\r
+#define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select Bit: 1 */\r
+#define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */\r
+#define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */\r
+#define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */\r
+#define ADC12ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */\r
+#define ADC12SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */\r
+#define ADC12SHS0 (0x0400u) /* ADC12 Sample/Hold Source Bit: 0 */\r
+#define ADC12SHS1 (0x0800u) /* ADC12 Sample/Hold Source Bit: 1 */\r
+#define ADC12SHS2 (0x1000u) /* ADC12 Sample/Hold Source Bit: 2 */\r
+#define ADC12PDIV0 (0x2000u) /* ADC12 Predivider Bit: 0 */\r
+#define ADC12PDIV1 (0x4000u) /* ADC12 Predivider Bit: 1 */\r
+\r
+/* ADC12CTL1 Control Bits */\r
+#define ADC12BUSY_L (0x0001u) /* ADC12 Busy */\r
+#define ADC12CONSEQ0_L (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */\r
+#define ADC12CONSEQ1_L (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */\r
+#define ADC12SSEL0_L (0x0008u) /* ADC12 Clock Source Select Bit: 0 */\r
+#define ADC12SSEL1_L (0x0010u) /* ADC12 Clock Source Select Bit: 1 */\r
+#define ADC12DIV0_L (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */\r
+#define ADC12DIV1_L (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */\r
+#define ADC12DIV2_L (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */\r
+\r
+/* ADC12CTL1 Control Bits */\r
+#define ADC12ISSH_H (0x0001u) /* ADC12 Invert Sample Hold Signal */\r
+#define ADC12SHP_H (0x0002u) /* ADC12 Sample/Hold Pulse Mode */\r
+#define ADC12SHS0_H (0x0004u) /* ADC12 Sample/Hold Source Bit: 0 */\r
+#define ADC12SHS1_H (0x0008u) /* ADC12 Sample/Hold Source Bit: 1 */\r
+#define ADC12SHS2_H (0x0010u) /* ADC12 Sample/Hold Source Bit: 2 */\r
+#define ADC12PDIV0_H (0x0020u) /* ADC12 Predivider Bit: 0 */\r
+#define ADC12PDIV1_H (0x0040u) /* ADC12 Predivider Bit: 1 */\r
+\r
+#define ADC12CONSEQ_0 (0*0x0002u) /* ADC12 Conversion Sequence Select: 0 */\r
+#define ADC12CONSEQ_1 (1*0x0002u) /* ADC12 Conversion Sequence Select: 1 */\r
+#define ADC12CONSEQ_2 (2*0x0002u) /* ADC12 Conversion Sequence Select: 2 */\r
+#define ADC12CONSEQ_3 (3*0x0002u) /* ADC12 Conversion Sequence Select: 3 */\r
+\r
+#define ADC12SSEL_0 (0*0x0008u) /* ADC12 Clock Source Select: 0 */\r
+#define ADC12SSEL_1 (1*0x0008u) /* ADC12 Clock Source Select: 1 */\r
+#define ADC12SSEL_2 (2*0x0008u) /* ADC12 Clock Source Select: 2 */\r
+#define ADC12SSEL_3 (3*0x0008u) /* ADC12 Clock Source Select: 3 */\r
+\r
+#define ADC12DIV_0 (0*0x0020u) /* ADC12 Clock Divider Select: 0 */\r
+#define ADC12DIV_1 (1*0x0020u) /* ADC12 Clock Divider Select: 1 */\r
+#define ADC12DIV_2 (2*0x0020u) /* ADC12 Clock Divider Select: 2 */\r
+#define ADC12DIV_3 (3*0x0020u) /* ADC12 Clock Divider Select: 3 */\r
+#define ADC12DIV_4 (4*0x0020u) /* ADC12 Clock Divider Select: 4 */\r
+#define ADC12DIV_5 (5*0x0020u) /* ADC12 Clock Divider Select: 5 */\r
+#define ADC12DIV_6 (6*0x0020u) /* ADC12 Clock Divider Select: 6 */\r
+#define ADC12DIV_7 (7*0x0020u) /* ADC12 Clock Divider Select: 7 */\r
+\r
+#define ADC12SHS_0 (0*0x0400u) /* ADC12 Sample/Hold Source: 0 */\r
+#define ADC12SHS_1 (1*0x0400u) /* ADC12 Sample/Hold Source: 1 */\r
+#define ADC12SHS_2 (2*0x0400u) /* ADC12 Sample/Hold Source: 2 */\r
+#define ADC12SHS_3 (3*0x0400u) /* ADC12 Sample/Hold Source: 3 */\r
+#define ADC12SHS_4 (4*0x0400u) /* ADC12 Sample/Hold Source: 4 */\r
+#define ADC12SHS_5 (5*0x0400u) /* ADC12 Sample/Hold Source: 5 */\r
+#define ADC12SHS_6 (6*0x0400u) /* ADC12 Sample/Hold Source: 6 */\r
+#define ADC12SHS_7 (7*0x0400u) /* ADC12 Sample/Hold Source: 7 */\r
+\r
+#define ADC12PDIV_0 (0*0x2000u) /* ADC12 Clock predivider Select 0 */\r
+#define ADC12PDIV_1 (1*0x2000u) /* ADC12 Clock predivider Select 1 */\r
+#define ADC12PDIV_2 (2*0x2000u) /* ADC12 Clock predivider Select 2 */\r
+#define ADC12PDIV_3 (3*0x2000u) /* ADC12 Clock predivider Select 3 */\r
+#define ADC12PDIV__1 (0*0x2000u) /* ADC12 Clock predivider Select: /1 */\r
+#define ADC12PDIV__4 (1*0x2000u) /* ADC12 Clock predivider Select: /4 */\r
+#define ADC12PDIV__32 (2*0x2000u) /* ADC12 Clock predivider Select: /32 */\r
+#define ADC12PDIV__64 (3*0x2000u) /* ADC12 Clock predivider Select: /64 */\r
+\r
+/* ADC12CTL2 Control Bits */\r
+#define ADC12PWRMD (0x0001u) /* ADC12 Power Mode */\r
+#define ADC12DF (0x0008u) /* ADC12 Data Format */\r
+#define ADC12RES0 (0x0010u) /* ADC12 Resolution Bit: 0 */\r
+#define ADC12RES1 (0x0020u) /* ADC12 Resolution Bit: 1 */\r
+\r
+/* ADC12CTL2 Control Bits */\r
+#define ADC12PWRMD_L (0x0001u) /* ADC12 Power Mode */\r
+#define ADC12DF_L (0x0008u) /* ADC12 Data Format */\r
+#define ADC12RES0_L (0x0010u) /* ADC12 Resolution Bit: 0 */\r
+#define ADC12RES1_L (0x0020u) /* ADC12 Resolution Bit: 1 */\r
+\r
+#define ADC12RES_0 (0x0000u) /* ADC12+ Resolution : 8 Bit */\r
+#define ADC12RES_1 (0x0010u) /* ADC12+ Resolution : 10 Bit */\r
+#define ADC12RES_2 (0x0020u) /* ADC12+ Resolution : 12 Bit */\r
+#define ADC12RES_3 (0x0030u) /* ADC12+ Resolution : reserved */\r
+\r
+#define ADC12RES__8BIT (0x0000u) /* ADC12+ Resolution : 8 Bit */\r
+#define ADC12RES__10BIT (0x0010u) /* ADC12+ Resolution : 10 Bit */\r
+#define ADC12RES__12BIT (0x0020u) /* ADC12+ Resolution : 12 Bit */\r
+\r
+/* ADC12CTL3 Control Bits */\r
+#define ADC12CSTARTADD0 (0x0001u) /* ADC12 Conversion Start Address Bit: 0 */\r
+#define ADC12CSTARTADD1 (0x0002u) /* ADC12 Conversion Start Address Bit: 1 */\r
+#define ADC12CSTARTADD2 (0x0004u) /* ADC12 Conversion Start Address Bit: 2 */\r
+#define ADC12CSTARTADD3 (0x0008u) /* ADC12 Conversion Start Address Bit: 3 */\r
+#define ADC12CSTARTADD4 (0x0010u) /* ADC12 Conversion Start Address Bit: 4 */\r
+#define ADC12BATMAP (0x0040u) /* ADC12 Internal AVCC/2 select */\r
+#define ADC12TCMAP (0x0080u) /* ADC12 Internal TempSensor select */\r
+#define ADC12ICH0MAP (0x0100u) /* ADC12 Internal Channel 0 select */\r
+#define ADC12ICH1MAP (0x0200u) /* ADC12 Internal Channel 1 select */\r
+#define ADC12ICH2MAP (0x0400u) /* ADC12 Internal Channel 2 select */\r
+#define ADC12ICH3MAP (0x0800u) /* ADC12 Internal Channel 3 select */\r
+\r
+/* ADC12CTL3 Control Bits */\r
+#define ADC12CSTARTADD0_L (0x0001u) /* ADC12 Conversion Start Address Bit: 0 */\r
+#define ADC12CSTARTADD1_L (0x0002u) /* ADC12 Conversion Start Address Bit: 1 */\r
+#define ADC12CSTARTADD2_L (0x0004u) /* ADC12 Conversion Start Address Bit: 2 */\r
+#define ADC12CSTARTADD3_L (0x0008u) /* ADC12 Conversion Start Address Bit: 3 */\r
+#define ADC12CSTARTADD4_L (0x0010u) /* ADC12 Conversion Start Address Bit: 4 */\r
+#define ADC12BATMAP_L (0x0040u) /* ADC12 Internal AVCC/2 select */\r
+#define ADC12TCMAP_L (0x0080u) /* ADC12 Internal TempSensor select */\r
+\r
+/* ADC12CTL3 Control Bits */\r
+#define ADC12ICH0MAP_H (0x0001u) /* ADC12 Internal Channel 0 select */\r
+#define ADC12ICH1MAP_H (0x0002u) /* ADC12 Internal Channel 1 select */\r
+#define ADC12ICH2MAP_H (0x0004u) /* ADC12 Internal Channel 2 select */\r
+#define ADC12ICH3MAP_H (0x0008u) /* ADC12 Internal Channel 3 select */\r
+\r
+#define ADC12CSTARTADD_0 ( 0*0x0001u) /* ADC12 Conversion Start Address: 0 */\r
+#define ADC12CSTARTADD_1 ( 1*0x0001u) /* ADC12 Conversion Start Address: 1 */\r
+#define ADC12CSTARTADD_2 ( 2*0x0001u) /* ADC12 Conversion Start Address: 2 */\r
+#define ADC12CSTARTADD_3 ( 3*0x0001u) /* ADC12 Conversion Start Address: 3 */\r
+#define ADC12CSTARTADD_4 ( 4*0x0001u) /* ADC12 Conversion Start Address: 4 */\r
+#define ADC12CSTARTADD_5 ( 5*0x0001u) /* ADC12 Conversion Start Address: 5 */\r
+#define ADC12CSTARTADD_6 ( 6*0x0001u) /* ADC12 Conversion Start Address: 6 */\r
+#define ADC12CSTARTADD_7 ( 7*0x0001u) /* ADC12 Conversion Start Address: 7 */\r
+#define ADC12CSTARTADD_8 ( 8*0x0001u) /* ADC12 Conversion Start Address: 8 */\r
+#define ADC12CSTARTADD_9 ( 9*0x0001u) /* ADC12 Conversion Start Address: 9 */\r
+#define ADC12CSTARTADD_10 (10*0x0001u) /* ADC12 Conversion Start Address: 10 */\r
+#define ADC12CSTARTADD_11 (11*0x0001u) /* ADC12 Conversion Start Address: 11 */\r
+#define ADC12CSTARTADD_12 (12*0x0001u) /* ADC12 Conversion Start Address: 12 */\r
+#define ADC12CSTARTADD_13 (13*0x0001u) /* ADC12 Conversion Start Address: 13 */\r
+#define ADC12CSTARTADD_14 (14*0x0001u) /* ADC12 Conversion Start Address: 14 */\r
+#define ADC12CSTARTADD_15 (15*0x0001u) /* ADC12 Conversion Start Address: 15 */\r
+#define ADC12CSTARTADD_16 (16*0x0001u) /* ADC12 Conversion Start Address: 16 */\r
+#define ADC12CSTARTADD_17 (17*0x0001u) /* ADC12 Conversion Start Address: 17 */\r
+#define ADC12CSTARTADD_18 (18*0x0001u) /* ADC12 Conversion Start Address: 18 */\r
+#define ADC12CSTARTADD_19 (19*0x0001u) /* ADC12 Conversion Start Address: 19 */\r
+#define ADC12CSTARTADD_20 (20*0x0001u) /* ADC12 Conversion Start Address: 20 */\r
+#define ADC12CSTARTADD_21 (21*0x0001u) /* ADC12 Conversion Start Address: 21 */\r
+#define ADC12CSTARTADD_22 (22*0x0001u) /* ADC12 Conversion Start Address: 22 */\r
+#define ADC12CSTARTADD_23 (23*0x0001u) /* ADC12 Conversion Start Address: 23 */\r
+#define ADC12CSTARTADD_24 (24*0x0001u) /* ADC12 Conversion Start Address: 24 */\r
+#define ADC12CSTARTADD_25 (25*0x0001u) /* ADC12 Conversion Start Address: 25 */\r
+#define ADC12CSTARTADD_26 (26*0x0001u) /* ADC12 Conversion Start Address: 26 */\r
+#define ADC12CSTARTADD_27 (27*0x0001u) /* ADC12 Conversion Start Address: 27 */\r
+#define ADC12CSTARTADD_28 (28*0x0001u) /* ADC12 Conversion Start Address: 28 */\r
+#define ADC12CSTARTADD_29 (29*0x0001u) /* ADC12 Conversion Start Address: 29 */\r
+#define ADC12CSTARTADD_30 (30*0x0001u) /* ADC12 Conversion Start Address: 30 */\r
+#define ADC12CSTARTADD_31 (31*0x0001u) /* ADC12 Conversion Start Address: 31 */\r
+\r
+/* ADC12MCTLx Control Bits */\r
+#define ADC12INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */\r
+#define ADC12INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */\r
+#define ADC12INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */\r
+#define ADC12INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */\r
+#define ADC12INCH4 (0x0010u) /* ADC12 Input Channel Select Bit 4 */\r
+#define ADC12EOS (0x0080u) /* ADC12 End of Sequence */\r
+#define ADC12VRSEL0 (0x0100u) /* ADC12 VR Select Bit 0 */\r
+#define ADC12VRSEL1 (0x0200u) /* ADC12 VR Select Bit 1 */\r
+#define ADC12VRSEL2 (0x0400u) /* ADC12 VR Select Bit 2 */\r
+#define ADC12VRSEL3 (0x0800u) /* ADC12 VR Select Bit 3 */\r
+#define ADC12DIF (0x2000u) /* ADC12 Differential mode (only for even Registers) */\r
+#define ADC12WINC (0x4000u) /* ADC12 Comparator window enable */\r
+\r
+/* ADC12MCTLx Control Bits */\r
+#define ADC12INCH0_L (0x0001u) /* ADC12 Input Channel Select Bit 0 */\r
+#define ADC12INCH1_L (0x0002u) /* ADC12 Input Channel Select Bit 1 */\r
+#define ADC12INCH2_L (0x0004u) /* ADC12 Input Channel Select Bit 2 */\r
+#define ADC12INCH3_L (0x0008u) /* ADC12 Input Channel Select Bit 3 */\r
+#define ADC12INCH4_L (0x0010u) /* ADC12 Input Channel Select Bit 4 */\r
+#define ADC12EOS_L (0x0080u) /* ADC12 End of Sequence */\r
+\r
+/* ADC12MCTLx Control Bits */\r
+#define ADC12VRSEL0_H (0x0001u) /* ADC12 VR Select Bit 0 */\r
+#define ADC12VRSEL1_H (0x0002u) /* ADC12 VR Select Bit 1 */\r
+#define ADC12VRSEL2_H (0x0004u) /* ADC12 VR Select Bit 2 */\r
+#define ADC12VRSEL3_H (0x0008u) /* ADC12 VR Select Bit 3 */\r
+#define ADC12DIF_H (0x0020u) /* ADC12 Differential mode (only for even Registers) */\r
+#define ADC12WINC_H (0x0040u) /* ADC12 Comparator window enable */\r
+\r
+#define ADC12INCH_0 (0x0000u) /* ADC12 Input Channel 0 */\r
+#define ADC12INCH_1 (0x0001u) /* ADC12 Input Channel 1 */\r
+#define ADC12INCH_2 (0x0002u) /* ADC12 Input Channel 2 */\r
+#define ADC12INCH_3 (0x0003u) /* ADC12 Input Channel 3 */\r
+#define ADC12INCH_4 (0x0004u) /* ADC12 Input Channel 4 */\r
+#define ADC12INCH_5 (0x0005u) /* ADC12 Input Channel 5 */\r
+#define ADC12INCH_6 (0x0006u) /* ADC12 Input Channel 6 */\r
+#define ADC12INCH_7 (0x0007u) /* ADC12 Input Channel 7 */\r
+#define ADC12INCH_8 (0x0008u) /* ADC12 Input Channel 8 */\r
+#define ADC12INCH_9 (0x0009u) /* ADC12 Input Channel 9 */\r
+#define ADC12INCH_10 (0x000Au) /* ADC12 Input Channel 10 */\r
+#define ADC12INCH_11 (0x000Bu) /* ADC12 Input Channel 11 */\r
+#define ADC12INCH_12 (0x000Cu) /* ADC12 Input Channel 12 */\r
+#define ADC12INCH_13 (0x000Du) /* ADC12 Input Channel 13 */\r
+#define ADC12INCH_14 (0x000Eu) /* ADC12 Input Channel 14 */\r
+#define ADC12INCH_15 (0x000Fu) /* ADC12 Input Channel 15 */\r
+#define ADC12INCH_16 (0x0010u) /* ADC12 Input Channel 16 */\r
+#define ADC12INCH_17 (0x0011u) /* ADC12 Input Channel 17 */\r
+#define ADC12INCH_18 (0x0012u) /* ADC12 Input Channel 18 */\r
+#define ADC12INCH_19 (0x0013u) /* ADC12 Input Channel 19 */\r
+#define ADC12INCH_20 (0x0014u) /* ADC12 Input Channel 20 */\r
+#define ADC12INCH_21 (0x0015u) /* ADC12 Input Channel 21 */\r
+#define ADC12INCH_22 (0x0016u) /* ADC12 Input Channel 22 */\r
+#define ADC12INCH_23 (0x0017u) /* ADC12 Input Channel 23 */\r
+#define ADC12INCH_24 (0x0018u) /* ADC12 Input Channel 24 */\r
+#define ADC12INCH_25 (0x0019u) /* ADC12 Input Channel 25 */\r
+#define ADC12INCH_26 (0x001Au) /* ADC12 Input Channel 26 */\r
+#define ADC12INCH_27 (0x001Bu) /* ADC12 Input Channel 27 */\r
+#define ADC12INCH_28 (0x001Cu) /* ADC12 Input Channel 28 */\r
+#define ADC12INCH_29 (0x001Du) /* ADC12 Input Channel 29 */\r
+#define ADC12INCH_30 (0x001Eu) /* ADC12 Input Channel 30 */\r
+#define ADC12INCH_31 (0x001Fu) /* ADC12 Input Channel 31 */\r
+\r
+#define ADC12VRSEL_0 (0*0x100u) /* ADC12 Select Reference 0 */\r
+#define ADC12VRSEL_1 (1*0x100u) /* ADC12 Select Reference 1 */\r
+#define ADC12VRSEL_2 (2*0x100u) /* ADC12 Select Reference 2 */\r
+#define ADC12VRSEL_3 (3*0x100u) /* ADC12 Select Reference 3 */\r
+#define ADC12VRSEL_4 (4*0x100u) /* ADC12 Select Reference 4 */\r
+#define ADC12VRSEL_5 (5*0x100u) /* ADC12 Select Reference 5 */\r
+#define ADC12VRSEL_6 (6*0x100u) /* ADC12 Select Reference 6 */\r
+#define ADC12VRSEL_7 (7*0x100u) /* ADC12 Select Reference 7 */\r
+#define ADC12VRSEL_8 (8*0x100u) /* ADC12 Select Reference 8 */\r
+#define ADC12VRSEL_9 (9*0x100u) /* ADC12 Select Reference 9 */\r
+#define ADC12VRSEL_10 (10*0x100u) /* ADC12 Select Reference 10 */\r
+#define ADC12VRSEL_11 (11*0x100u) /* ADC12 Select Reference 11 */\r
+#define ADC12VRSEL_12 (12*0x100u) /* ADC12 Select Reference 12 */\r
+#define ADC12VRSEL_13 (13*0x100u) /* ADC12 Select Reference 13 */\r
+#define ADC12VRSEL_14 (14*0x100u) /* ADC12 Select Reference 14 */\r
+#define ADC12VRSEL_15 (15*0x100u) /* ADC12 Select Reference 15 */\r
+\r
+/* ADC12HI Control Bits */\r
+\r
+/* ADC12LO Control Bits */\r
+\r
+/* ADC12IER0 Control Bits */\r
+#define ADC12IE0 (0x0001u) /* ADC12 Memory 0 Interrupt Enable */\r
+#define ADC12IE1 (0x0002u) /* ADC12 Memory 1 Interrupt Enable */\r
+#define ADC12IE2 (0x0004u) /* ADC12 Memory 2 Interrupt Enable */\r
+#define ADC12IE3 (0x0008u) /* ADC12 Memory 3 Interrupt Enable */\r
+#define ADC12IE4 (0x0010u) /* ADC12 Memory 4 Interrupt Enable */\r
+#define ADC12IE5 (0x0020u) /* ADC12 Memory 5 Interrupt Enable */\r
+#define ADC12IE6 (0x0040u) /* ADC12 Memory 6 Interrupt Enable */\r
+#define ADC12IE7 (0x0080u) /* ADC12 Memory 7 Interrupt Enable */\r
+#define ADC12IE8 (0x0100u) /* ADC12 Memory 8 Interrupt Enable */\r
+#define ADC12IE9 (0x0200u) /* ADC12 Memory 9 Interrupt Enable */\r
+#define ADC12IE10 (0x0400u) /* ADC12 Memory 10 Interrupt Enable */\r
+#define ADC12IE11 (0x0800u) /* ADC12 Memory 11 Interrupt Enable */\r
+#define ADC12IE12 (0x1000u) /* ADC12 Memory 12 Interrupt Enable */\r
+#define ADC12IE13 (0x2000u) /* ADC12 Memory 13 Interrupt Enable */\r
+#define ADC12IE14 (0x4000u) /* ADC12 Memory 14 Interrupt Enable */\r
+#define ADC12IE15 (0x8000u) /* ADC12 Memory 15 Interrupt Enable */\r
+\r
+/* ADC12IER0 Control Bits */\r
+#define ADC12IE0_L (0x0001u) /* ADC12 Memory 0 Interrupt Enable */\r
+#define ADC12IE1_L (0x0002u) /* ADC12 Memory 1 Interrupt Enable */\r
+#define ADC12IE2_L (0x0004u) /* ADC12 Memory 2 Interrupt Enable */\r
+#define ADC12IE3_L (0x0008u) /* ADC12 Memory 3 Interrupt Enable */\r
+#define ADC12IE4_L (0x0010u) /* ADC12 Memory 4 Interrupt Enable */\r
+#define ADC12IE5_L (0x0020u) /* ADC12 Memory 5 Interrupt Enable */\r
+#define ADC12IE6_L (0x0040u) /* ADC12 Memory 6 Interrupt Enable */\r
+#define ADC12IE7_L (0x0080u) /* ADC12 Memory 7 Interrupt Enable */\r
+\r
+/* ADC12IER0 Control Bits */\r
+#define ADC12IE8_H (0x0001u) /* ADC12 Memory 8 Interrupt Enable */\r
+#define ADC12IE9_H (0x0002u) /* ADC12 Memory 9 Interrupt Enable */\r
+#define ADC12IE10_H (0x0004u) /* ADC12 Memory 10 Interrupt Enable */\r
+#define ADC12IE11_H (0x0008u) /* ADC12 Memory 11 Interrupt Enable */\r
+#define ADC12IE12_H (0x0010u) /* ADC12 Memory 12 Interrupt Enable */\r
+#define ADC12IE13_H (0x0020u) /* ADC12 Memory 13 Interrupt Enable */\r
+#define ADC12IE14_H (0x0040u) /* ADC12 Memory 14 Interrupt Enable */\r
+#define ADC12IE15_H (0x0080u) /* ADC12 Memory 15 Interrupt Enable */\r
+\r
+/* ADC12IER1 Control Bits */\r
+#define ADC12IE16 (0x0001u) /* ADC12 Memory 16 Interrupt Enable */\r
+#define ADC12IE17 (0x0002u) /* ADC12 Memory 17 Interrupt Enable */\r
+#define ADC12IE18 (0x0004u) /* ADC12 Memory 18 Interrupt Enable */\r
+#define ADC12IE19 (0x0008u) /* ADC12 Memory 19 Interrupt Enable */\r
+#define ADC12IE20 (0x0010u) /* ADC12 Memory 20 Interrupt Enable */\r
+#define ADC12IE21 (0x0020u) /* ADC12 Memory 21 Interrupt Enable */\r
+#define ADC12IE22 (0x0040u) /* ADC12 Memory 22 Interrupt Enable */\r
+#define ADC12IE23 (0x0080u) /* ADC12 Memory 23 Interrupt Enable */\r
+#define ADC12IE24 (0x0100u) /* ADC12 Memory 24 Interrupt Enable */\r
+#define ADC12IE25 (0x0200u) /* ADC12 Memory 25 Interrupt Enable */\r
+#define ADC12IE26 (0x0400u) /* ADC12 Memory 26 Interrupt Enable */\r
+#define ADC12IE27 (0x0800u) /* ADC12 Memory 27 Interrupt Enable */\r
+#define ADC12IE28 (0x1000u) /* ADC12 Memory 28 Interrupt Enable */\r
+#define ADC12IE29 (0x2000u) /* ADC12 Memory 29 Interrupt Enable */\r
+#define ADC12IE30 (0x4000u) /* ADC12 Memory 30 Interrupt Enable */\r
+#define ADC12IE31 (0x8000u) /* ADC12 Memory 31 Interrupt Enable */\r
+\r
+/* ADC12IER1 Control Bits */\r
+#define ADC12IE16_L (0x0001u) /* ADC12 Memory 16 Interrupt Enable */\r
+#define ADC12IE17_L (0x0002u) /* ADC12 Memory 17 Interrupt Enable */\r
+#define ADC12IE18_L (0x0004u) /* ADC12 Memory 18 Interrupt Enable */\r
+#define ADC12IE19_L (0x0008u) /* ADC12 Memory 19 Interrupt Enable */\r
+#define ADC12IE20_L (0x0010u) /* ADC12 Memory 20 Interrupt Enable */\r
+#define ADC12IE21_L (0x0020u) /* ADC12 Memory 21 Interrupt Enable */\r
+#define ADC12IE22_L (0x0040u) /* ADC12 Memory 22 Interrupt Enable */\r
+#define ADC12IE23_L (0x0080u) /* ADC12 Memory 23 Interrupt Enable */\r
+\r
+/* ADC12IER1 Control Bits */\r
+#define ADC12IE24_H (0x0001u) /* ADC12 Memory 24 Interrupt Enable */\r
+#define ADC12IE25_H (0x0002u) /* ADC12 Memory 25 Interrupt Enable */\r
+#define ADC12IE26_H (0x0004u) /* ADC12 Memory 26 Interrupt Enable */\r
+#define ADC12IE27_H (0x0008u) /* ADC12 Memory 27 Interrupt Enable */\r
+#define ADC12IE28_H (0x0010u) /* ADC12 Memory 28 Interrupt Enable */\r
+#define ADC12IE29_H (0x0020u) /* ADC12 Memory 29 Interrupt Enable */\r
+#define ADC12IE30_H (0x0040u) /* ADC12 Memory 30 Interrupt Enable */\r
+#define ADC12IE31_H (0x0080u) /* ADC12 Memory 31 Interrupt Enable */\r
+\r
+/* ADC12IER2 Control Bits */\r
+#define ADC12INIE (0x0002u) /* ADC12 Interrupt enable for the inside of window of the Window comparator */\r
+#define ADC12LOIE (0x0004u) /* ADC12 Interrupt enable for lower threshold of the Window comparator */\r
+#define ADC12HIIE (0x0008u) /* ADC12 Interrupt enable for upper threshold of the Window comparator */\r
+#define ADC12OVIE (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt enable */\r
+#define ADC12TOVIE (0x0020u) /* ADC12 Timer Overflow interrupt enable */\r
+#define ADC12RDYIE (0x0040u) /* ADC12 local buffered reference ready interrupt enable */\r
+\r
+/* ADC12IER2 Control Bits */\r
+#define ADC12INIE_L (0x0002u) /* ADC12 Interrupt enable for the inside of window of the Window comparator */\r
+#define ADC12LOIE_L (0x0004u) /* ADC12 Interrupt enable for lower threshold of the Window comparator */\r
+#define ADC12HIIE_L (0x0008u) /* ADC12 Interrupt enable for upper threshold of the Window comparator */\r
+#define ADC12OVIE_L (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt enable */\r
+#define ADC12TOVIE_L (0x0020u) /* ADC12 Timer Overflow interrupt enable */\r
+#define ADC12RDYIE_L (0x0040u) /* ADC12 local buffered reference ready interrupt enable */\r
+\r
+/* ADC12IFGR0 Control Bits */\r
+#define ADC12IFG0 (0x0001u) /* ADC12 Memory 0 Interrupt Flag */\r
+#define ADC12IFG1 (0x0002u) /* ADC12 Memory 1 Interrupt Flag */\r
+#define ADC12IFG2 (0x0004u) /* ADC12 Memory 2 Interrupt Flag */\r
+#define ADC12IFG3 (0x0008u) /* ADC12 Memory 3 Interrupt Flag */\r
+#define ADC12IFG4 (0x0010u) /* ADC12 Memory 4 Interrupt Flag */\r
+#define ADC12IFG5 (0x0020u) /* ADC12 Memory 5 Interrupt Flag */\r
+#define ADC12IFG6 (0x0040u) /* ADC12 Memory 6 Interrupt Flag */\r
+#define ADC12IFG7 (0x0080u) /* ADC12 Memory 7 Interrupt Flag */\r
+#define ADC12IFG8 (0x0100u) /* ADC12 Memory 8 Interrupt Flag */\r
+#define ADC12IFG9 (0x0200u) /* ADC12 Memory 9 Interrupt Flag */\r
+#define ADC12IFG10 (0x0400u) /* ADC12 Memory 10 Interrupt Flag */\r
+#define ADC12IFG11 (0x0800u) /* ADC12 Memory 11 Interrupt Flag */\r
+#define ADC12IFG12 (0x1000u) /* ADC12 Memory 12 Interrupt Flag */\r
+#define ADC12IFG13 (0x2000u) /* ADC12 Memory 13 Interrupt Flag */\r
+#define ADC12IFG14 (0x4000u) /* ADC12 Memory 14 Interrupt Flag */\r
+#define ADC12IFG15 (0x8000u) /* ADC12 Memory 15 Interrupt Flag */\r
+\r
+/* ADC12IFGR0 Control Bits */\r
+#define ADC12IFG0_L (0x0001u) /* ADC12 Memory 0 Interrupt Flag */\r
+#define ADC12IFG1_L (0x0002u) /* ADC12 Memory 1 Interrupt Flag */\r
+#define ADC12IFG2_L (0x0004u) /* ADC12 Memory 2 Interrupt Flag */\r
+#define ADC12IFG3_L (0x0008u) /* ADC12 Memory 3 Interrupt Flag */\r
+#define ADC12IFG4_L (0x0010u) /* ADC12 Memory 4 Interrupt Flag */\r
+#define ADC12IFG5_L (0x0020u) /* ADC12 Memory 5 Interrupt Flag */\r
+#define ADC12IFG6_L (0x0040u) /* ADC12 Memory 6 Interrupt Flag */\r
+#define ADC12IFG7_L (0x0080u) /* ADC12 Memory 7 Interrupt Flag */\r
+\r
+/* ADC12IFGR0 Control Bits */\r
+#define ADC12IFG8_H (0x0001u) /* ADC12 Memory 8 Interrupt Flag */\r
+#define ADC12IFG9_H (0x0002u) /* ADC12 Memory 9 Interrupt Flag */\r
+#define ADC12IFG10_H (0x0004u) /* ADC12 Memory 10 Interrupt Flag */\r
+#define ADC12IFG11_H (0x0008u) /* ADC12 Memory 11 Interrupt Flag */\r
+#define ADC12IFG12_H (0x0010u) /* ADC12 Memory 12 Interrupt Flag */\r
+#define ADC12IFG13_H (0x0020u) /* ADC12 Memory 13 Interrupt Flag */\r
+#define ADC12IFG14_H (0x0040u) /* ADC12 Memory 14 Interrupt Flag */\r
+#define ADC12IFG15_H (0x0080u) /* ADC12 Memory 15 Interrupt Flag */\r
+\r
+/* ADC12IFGR1 Control Bits */\r
+#define ADC12IFG16 (0x0001u) /* ADC12 Memory 16 Interrupt Flag */\r
+#define ADC12IFG17 (0x0002u) /* ADC12 Memory 17 Interrupt Flag */\r
+#define ADC12IFG18 (0x0004u) /* ADC12 Memory 18 Interrupt Flag */\r
+#define ADC12IFG19 (0x0008u) /* ADC12 Memory 19 Interrupt Flag */\r
+#define ADC12IFG20 (0x0010u) /* ADC12 Memory 20 Interrupt Flag */\r
+#define ADC12IFG21 (0x0020u) /* ADC12 Memory 21 Interrupt Flag */\r
+#define ADC12IFG22 (0x0040u) /* ADC12 Memory 22 Interrupt Flag */\r
+#define ADC12IFG23 (0x0080u) /* ADC12 Memory 23 Interrupt Flag */\r
+#define ADC12IFG24 (0x0100u) /* ADC12 Memory 24 Interrupt Flag */\r
+#define ADC12IFG25 (0x0200u) /* ADC12 Memory 25 Interrupt Flag */\r
+#define ADC12IFG26 (0x0400u) /* ADC12 Memory 26 Interrupt Flag */\r
+#define ADC12IFG27 (0x0800u) /* ADC12 Memory 27 Interrupt Flag */\r
+#define ADC12IFG28 (0x1000u) /* ADC12 Memory 28 Interrupt Flag */\r
+#define ADC12IFG29 (0x2000u) /* ADC12 Memory 29 Interrupt Flag */\r
+#define ADC12IFG30 (0x4000u) /* ADC12 Memory 30 Interrupt Flag */\r
+#define ADC12IFG31 (0x8000u) /* ADC12 Memory 31 Interrupt Flag */\r
+\r
+/* ADC12IFGR1 Control Bits */\r
+#define ADC12IFG16_L (0x0001u) /* ADC12 Memory 16 Interrupt Flag */\r
+#define ADC12IFG17_L (0x0002u) /* ADC12 Memory 17 Interrupt Flag */\r
+#define ADC12IFG18_L (0x0004u) /* ADC12 Memory 18 Interrupt Flag */\r
+#define ADC12IFG19_L (0x0008u) /* ADC12 Memory 19 Interrupt Flag */\r
+#define ADC12IFG20_L (0x0010u) /* ADC12 Memory 20 Interrupt Flag */\r
+#define ADC12IFG21_L (0x0020u) /* ADC12 Memory 21 Interrupt Flag */\r
+#define ADC12IFG22_L (0x0040u) /* ADC12 Memory 22 Interrupt Flag */\r
+#define ADC12IFG23_L (0x0080u) /* ADC12 Memory 23 Interrupt Flag */\r
+\r
+/* ADC12IFGR1 Control Bits */\r
+#define ADC12IFG24_H (0x0001u) /* ADC12 Memory 24 Interrupt Flag */\r
+#define ADC12IFG25_H (0x0002u) /* ADC12 Memory 25 Interrupt Flag */\r
+#define ADC12IFG26_H (0x0004u) /* ADC12 Memory 26 Interrupt Flag */\r
+#define ADC12IFG27_H (0x0008u) /* ADC12 Memory 27 Interrupt Flag */\r
+#define ADC12IFG28_H (0x0010u) /* ADC12 Memory 28 Interrupt Flag */\r
+#define ADC12IFG29_H (0x0020u) /* ADC12 Memory 29 Interrupt Flag */\r
+#define ADC12IFG30_H (0x0040u) /* ADC12 Memory 30 Interrupt Flag */\r
+#define ADC12IFG31_H (0x0080u) /* ADC12 Memory 31 Interrupt Flag */\r
+\r
+/* ADC12IFGR2 Control Bits */\r
+#define ADC12INIFG (0x0002u) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */\r
+#define ADC12LOIFG (0x0004u) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */\r
+#define ADC12HIIFG (0x0008u) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */\r
+#define ADC12OVIFG (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt Flag */\r
+#define ADC12TOVIFG (0x0020u) /* ADC12 Timer Overflow interrupt Flag */\r
+#define ADC12RDYIFG (0x0040u) /* ADC12 local buffered reference ready interrupt Flag */\r
+\r
+/* ADC12IFGR2 Control Bits */\r
+#define ADC12INIFG_L (0x0002u) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */\r
+#define ADC12LOIFG_L (0x0004u) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */\r
+#define ADC12HIIFG_L (0x0008u) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */\r
+#define ADC12OVIFG_L (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt Flag */\r
+#define ADC12TOVIFG_L (0x0020u) /* ADC12 Timer Overflow interrupt Flag */\r
+#define ADC12RDYIFG_L (0x0040u) /* ADC12 local buffered reference ready interrupt Flag */\r
+\r
+/* ADC12IV Definitions */\r
+#define ADC12IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */\r
+#define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */\r
+#define ADC12IV_ADC12HIIFG (0x0006u) /* ADC12HIIFG */\r
+#define ADC12IV_ADC12LOIFG (0x0008u) /* ADC12LOIFG */\r
+#define ADC12IV_ADC12INIFG (0x000Au) /* ADC12INIFG */\r
+#define ADC12IV_ADC12IFG0 (0x000Cu) /* ADC12IFG0 */\r
+#define ADC12IV_ADC12IFG1 (0x000Eu) /* ADC12IFG1 */\r
+#define ADC12IV_ADC12IFG2 (0x0010u) /* ADC12IFG2 */\r
+#define ADC12IV_ADC12IFG3 (0x0012u) /* ADC12IFG3 */\r
+#define ADC12IV_ADC12IFG4 (0x0014u) /* ADC12IFG4 */\r
+#define ADC12IV_ADC12IFG5 (0x0016u) /* ADC12IFG5 */\r
+#define ADC12IV_ADC12IFG6 (0x0018u) /* ADC12IFG6 */\r
+#define ADC12IV_ADC12IFG7 (0x001Au) /* ADC12IFG7 */\r
+#define ADC12IV_ADC12IFG8 (0x001Cu) /* ADC12IFG8 */\r
+#define ADC12IV_ADC12IFG9 (0x001Eu) /* ADC12IFG9 */\r
+#define ADC12IV_ADC12IFG10 (0x0020u) /* ADC12IFG10 */\r
+#define ADC12IV_ADC12IFG11 (0x0022u) /* ADC12IFG11 */\r
+#define ADC12IV_ADC12IFG12 (0x0024u) /* ADC12IFG12 */\r
+#define ADC12IV_ADC12IFG13 (0x0026u) /* ADC12IFG13 */\r
+#define ADC12IV_ADC12IFG14 (0x0028u) /* ADC12IFG14 */\r
+#define ADC12IV_ADC12IFG15 (0x002Au) /* ADC12IFG15 */\r
+#define ADC12IV_ADC12IFG16 (0x002Cu) /* ADC12IFG16 */\r
+#define ADC12IV_ADC12IFG17 (0x002Eu) /* ADC12IFG17 */\r
+#define ADC12IV_ADC12IFG18 (0x0030u) /* ADC12IFG18 */\r
+#define ADC12IV_ADC12IFG19 (0x0032u) /* ADC12IFG19 */\r
+#define ADC12IV_ADC12IFG20 (0x0034u) /* ADC12IFG20 */\r
+#define ADC12IV_ADC12IFG21 (0x0036u) /* ADC12IFG21 */\r
+#define ADC12IV_ADC12IFG22 (0x0038u) /* ADC12IFG22 */\r
+#define ADC12IV_ADC12IFG23 (0x003Au) /* ADC12IFG23 */\r
+#define ADC12IV_ADC12IFG24 (0x003Cu) /* ADC12IFG24 */\r
+#define ADC12IV_ADC12IFG25 (0x003Eu) /* ADC12IFG25 */\r
+#define ADC12IV_ADC12IFG26 (0x0040u) /* ADC12IFG26 */\r
+#define ADC12IV_ADC12IFG27 (0x0042u) /* ADC12IFG27 */\r
+#define ADC12IV_ADC12IFG28 (0x0044u) /* ADC12IFG28 */\r
+#define ADC12IV_ADC12IFG29 (0x0046u) /* ADC12IFG29 */\r
+#define ADC12IV_ADC12IFG30 (0x0048u) /* ADC12IFG30 */\r
+#define ADC12IV_ADC12IFG31 (0x004Au) /* ADC12IFG31 */\r
+#define ADC12IV_ADC12RDYIFG (0x004Cu) /* ADC12RDYIFG */\r
+\r
+\r
+#endif\r
+/************************************************************\r
+* AES256 Accelerator\r
+************************************************************/\r
+#ifdef __MSP430_HAS_AES256__ /* Definition to show that Module is available */\r
+\r
+#define OFS_AESACTL0 (0x0000u) /* AES accelerator control register 0 */\r
+#define OFS_AESACTL0_L OFS_AESACTL0\r
+#define OFS_AESACTL0_H OFS_AESACTL0+1\r
+#define OFS_AESACTL1 (0x0002u) /* AES accelerator control register 1 */\r
+#define OFS_AESACTL1_L OFS_AESACTL1\r
+#define OFS_AESACTL1_H OFS_AESACTL1+1\r
+#define OFS_AESASTAT (0x0004u) /* AES accelerator status register */\r
+#define OFS_AESASTAT_L OFS_AESASTAT\r
+#define OFS_AESASTAT_H OFS_AESASTAT+1\r
+#define OFS_AESAKEY (0x0006u) /* AES accelerator key register */\r
+#define OFS_AESAKEY_L OFS_AESAKEY\r
+#define OFS_AESAKEY_H OFS_AESAKEY+1\r
+#define OFS_AESADIN (0x0008u) /* AES accelerator data in register */\r
+#define OFS_AESADIN_L OFS_AESADIN\r
+#define OFS_AESADIN_H OFS_AESADIN+1\r
+#define OFS_AESADOUT (0x000Au) /* AES accelerator data out register */\r
+#define OFS_AESADOUT_L OFS_AESADOUT\r
+#define OFS_AESADOUT_H OFS_AESADOUT+1\r
+#define OFS_AESAXDIN (0x000Cu) /* AES accelerator XORed data in register */\r
+#define OFS_AESAXDIN_L OFS_AESAXDIN\r
+#define OFS_AESAXDIN_H OFS_AESAXDIN+1\r
+#define OFS_AESAXIN (0x000Eu) /* AES accelerator XORed data in register (no trigger) */\r
+#define OFS_AESAXIN_L OFS_AESAXIN\r
+#define OFS_AESAXIN_H OFS_AESAXIN+1\r
+\r
+/* AESACTL0 Control Bits */\r
+#define AESOP0 (0x0001u) /* AES Operation Bit: 0 */\r
+#define AESOP1 (0x0002u) /* AES Operation Bit: 1 */\r
+#define AESKL0 (0x0004u) /* AES Key length Bit: 0 */\r
+#define AESKL1 (0x0008u) /* AES Key length Bit: 1 */\r
+#define AESTRIG (0x0010u) /* AES Trigger Select */\r
+#define AESCM0 (0x0020u) /* AES Cipher mode select Bit: 0 */\r
+#define AESCM1 (0x0040u) /* AES Cipher mode select Bit: 1 */\r
+#define AESSWRST (0x0080u) /* AES Software Reset */\r
+#define AESRDYIFG (0x0100u) /* AES ready interrupt flag */\r
+#define AESERRFG (0x0800u) /* AES Error Flag */\r
+#define AESRDYIE (0x1000u) /* AES ready interrupt enable*/\r
+#define AESCMEN (0x8000u) /* AES DMA cipher mode enable*/\r
+\r
+/* AESACTL0 Control Bits */\r
+#define AESOP0_L (0x0001u) /* AES Operation Bit: 0 */\r
+#define AESOP1_L (0x0002u) /* AES Operation Bit: 1 */\r
+#define AESKL0_L (0x0004u) /* AES Key length Bit: 0 */\r
+#define AESKL1_L (0x0008u) /* AES Key length Bit: 1 */\r
+#define AESTRIG_L (0x0010u) /* AES Trigger Select */\r
+#define AESCM0_L (0x0020u) /* AES Cipher mode select Bit: 0 */\r
+#define AESCM1_L (0x0040u) /* AES Cipher mode select Bit: 1 */\r
+#define AESSWRST_L (0x0080u) /* AES Software Reset */\r
+\r
+/* AESACTL0 Control Bits */\r
+#define AESRDYIFG_H (0x0001u) /* AES ready interrupt flag */\r
+#define AESERRFG_H (0x0008u) /* AES Error Flag */\r
+#define AESRDYIE_H (0x0010u) /* AES ready interrupt enable*/\r
+#define AESCMEN_H (0x0080u) /* AES DMA cipher mode enable*/\r
+\r
+#define AESOP_0 (0x0000u) /* AES Operation: Encrypt */\r
+#define AESOP_1 (0x0001u) /* AES Operation: Decrypt (same Key) */\r
+#define AESOP_2 (0x0002u) /* AES Operation: Decrypt (frist round Key) */\r
+#define AESOP_3 (0x0003u) /* AES Operation: Generate first round Key */\r
+\r
+#define AESKL_0 (0x0000u) /* AES Key length: AES128 */\r
+#define AESKL_1 (0x0004u) /* AES Key length: AES192 */\r
+#define AESKL_2 (0x0008u) /* AES Key length: AES256 */\r
+#define AESKL__128 (0x0000u) /* AES Key length: AES128 */\r
+#define AESKL__192 (0x0004u) /* AES Key length: AES192 */\r
+#define AESKL__256 (0x0008u) /* AES Key length: AES256 */\r
+\r
+#define AESCM_0 (0x0000u) /* AES Cipher mode select: ECB */\r
+#define AESCM_1 (0x0020u) /* AES Cipher mode select: CBC */\r
+#define AESCM_2 (0x0040u) /* AES Cipher mode select: OFB */\r
+#define AESCM_3 (0x0060u) /* AES Cipher mode select: CFB */\r
+#define AESCM__ECB (0x0000u) /* AES Cipher mode select: ECB */\r
+#define AESCM__CBC (0x0020u) /* AES Cipher mode select: CBC */\r
+#define AESCM__OFB (0x0040u) /* AES Cipher mode select: OFB */\r
+#define AESCM__CFB (0x0060u) /* AES Cipher mode select: CFB */\r
+\r
+/* AESACTL1 Control Bits */\r
+#define AESBLKCNT0 (0x0001u) /* AES Cipher Block Counter Bit: 0 */\r
+#define AESBLKCNT1 (0x0002u) /* AES Cipher Block Counter Bit: 1 */\r
+#define AESBLKCNT2 (0x0004u) /* AES Cipher Block Counter Bit: 2 */\r
+#define AESBLKCNT3 (0x0008u) /* AES Cipher Block Counter Bit: 3 */\r
+#define AESBLKCNT4 (0x0010u) /* AES Cipher Block Counter Bit: 4 */\r
+#define AESBLKCNT5 (0x0020u) /* AES Cipher Block Counter Bit: 5 */\r
+#define AESBLKCNT6 (0x0040u) /* AES Cipher Block Counter Bit: 6 */\r
+#define AESBLKCNT7 (0x0080u) /* AES Cipher Block Counter Bit: 7 */\r
+\r
+/* AESACTL1 Control Bits */\r
+#define AESBLKCNT0_L (0x0001u) /* AES Cipher Block Counter Bit: 0 */\r
+#define AESBLKCNT1_L (0x0002u) /* AES Cipher Block Counter Bit: 1 */\r
+#define AESBLKCNT2_L (0x0004u) /* AES Cipher Block Counter Bit: 2 */\r
+#define AESBLKCNT3_L (0x0008u) /* AES Cipher Block Counter Bit: 3 */\r
+#define AESBLKCNT4_L (0x0010u) /* AES Cipher Block Counter Bit: 4 */\r
+#define AESBLKCNT5_L (0x0020u) /* AES Cipher Block Counter Bit: 5 */\r
+#define AESBLKCNT6_L (0x0040u) /* AES Cipher Block Counter Bit: 6 */\r
+#define AESBLKCNT7_L (0x0080u) /* AES Cipher Block Counter Bit: 7 */\r
+\r
+/* AESASTAT Control Bits */\r
+#define AESBUSY (0x0001u) /* AES Busy */\r
+#define AESKEYWR (0x0002u) /* AES All 16 bytes written to AESAKEY */\r
+#define AESDINWR (0x0004u) /* AES All 16 bytes written to AESADIN */\r
+#define AESDOUTRD (0x0008u) /* AES All 16 bytes read from AESADOUT */\r
+#define AESKEYCNT0 (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */\r
+#define AESKEYCNT1 (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */\r
+#define AESKEYCNT2 (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */\r
+#define AESKEYCNT3 (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */\r
+#define AESDINCNT0 (0x0100u) /* AES Bytes written via AESADIN Bit: 0 */\r
+#define AESDINCNT1 (0x0200u) /* AES Bytes written via AESADIN Bit: 1 */\r
+#define AESDINCNT2 (0x0400u) /* AES Bytes written via AESADIN Bit: 2 */\r
+#define AESDINCNT3 (0x0800u) /* AES Bytes written via AESADIN Bit: 3 */\r
+#define AESDOUTCNT0 (0x1000u) /* AES Bytes read via AESADOUT Bit: 0 */\r
+#define AESDOUTCNT1 (0x2000u) /* AES Bytes read via AESADOUT Bit: 1 */\r
+#define AESDOUTCNT2 (0x4000u) /* AES Bytes read via AESADOUT Bit: 2 */\r
+#define AESDOUTCNT3 (0x8000u) /* AES Bytes read via AESADOUT Bit: 3 */\r
+\r
+/* AESASTAT Control Bits */\r
+#define AESBUSY_L (0x0001u) /* AES Busy */\r
+#define AESKEYWR_L (0x0002u) /* AES All 16 bytes written to AESAKEY */\r
+#define AESDINWR_L (0x0004u) /* AES All 16 bytes written to AESADIN */\r
+#define AESDOUTRD_L (0x0008u) /* AES All 16 bytes read from AESADOUT */\r
+#define AESKEYCNT0_L (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */\r
+#define AESKEYCNT1_L (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */\r
+#define AESKEYCNT2_L (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */\r
+#define AESKEYCNT3_L (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */\r
+\r
+/* AESASTAT Control Bits */\r
+#define AESDINCNT0_H (0x0001u) /* AES Bytes written via AESADIN Bit: 0 */\r
+#define AESDINCNT1_H (0x0002u) /* AES Bytes written via AESADIN Bit: 1 */\r
+#define AESDINCNT2_H (0x0004u) /* AES Bytes written via AESADIN Bit: 2 */\r
+#define AESDINCNT3_H (0x0008u) /* AES Bytes written via AESADIN Bit: 3 */\r
+#define AESDOUTCNT0_H (0x0010u) /* AES Bytes read via AESADOUT Bit: 0 */\r
+#define AESDOUTCNT1_H (0x0020u) /* AES Bytes read via AESADOUT Bit: 1 */\r
+#define AESDOUTCNT2_H (0x0040u) /* AES Bytes read via AESADOUT Bit: 2 */\r
+#define AESDOUTCNT3_H (0x0080u) /* AES Bytes read via AESADOUT Bit: 3 */\r
+\r
+#endif\r
+/************************************************************\r
+* Capacitive_Touch_IO 0\r
+************************************************************/\r
+#ifdef __MSP430_HAS_CAP_TOUCH_IO_0__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CAPTIO0CTL (0x000Eu) /* Capacitive_Touch_IO 0 control register */\r
+#define OFS_CAPTIO0CTL_L OFS_CAPTIO0CTL\r
+#define OFS_CAPTIO0CTL_H OFS_CAPTIO0CTL+1\r
+\r
+#define CAPSIO0CTL CAPTIO0CTL /* legacy define */\r
+\r
+/* CAPTIOxCTL Control Bits */\r
+#define CAPTIOPISEL0 (0x0002u) /* CapTouchIO Pin Select Bit: 0 */\r
+#define CAPTIOPISEL1 (0x0004u) /* CapTouchIO Pin Select Bit: 1 */\r
+#define CAPTIOPISEL2 (0x0008u) /* CapTouchIO Pin Select Bit: 2 */\r
+#define CAPTIOPOSEL0 (0x0010u) /* CapTouchIO Port Select Bit: 0 */\r
+#define CAPTIOPOSEL1 (0x0020u) /* CapTouchIO Port Select Bit: 1 */\r
+#define CAPTIOPOSEL2 (0x0040u) /* CapTouchIO Port Select Bit: 2 */\r
+#define CAPTIOPOSEL3 (0x0080u) /* CapTouchIO Port Select Bit: 3 */\r
+#define CAPTIOEN (0x0100u) /* CapTouchIO Enable */\r
+#define CAPTIO (0x0200u) /* CapTouchIO state */\r
+\r
+/* CAPTIOxCTL Control Bits */\r
+#define CAPTIOPISEL0_L (0x0002u) /* CapTouchIO Pin Select Bit: 0 */\r
+#define CAPTIOPISEL1_L (0x0004u) /* CapTouchIO Pin Select Bit: 1 */\r
+#define CAPTIOPISEL2_L (0x0008u) /* CapTouchIO Pin Select Bit: 2 */\r
+#define CAPTIOPOSEL0_L (0x0010u) /* CapTouchIO Port Select Bit: 0 */\r
+#define CAPTIOPOSEL1_L (0x0020u) /* CapTouchIO Port Select Bit: 1 */\r
+#define CAPTIOPOSEL2_L (0x0040u) /* CapTouchIO Port Select Bit: 2 */\r
+#define CAPTIOPOSEL3_L (0x0080u) /* CapTouchIO Port Select Bit: 3 */\r
+\r
+/* CAPTIOxCTL Control Bits */\r
+#define CAPTIOEN_H (0x0001u) /* CapTouchIO Enable */\r
+#define CAPTIO_H (0x0002u) /* CapTouchIO state */\r
+\r
+/* Legacy defines */\r
+#define CAPSIOPISEL0 (0x0002u) /* CapTouchIO Pin Select Bit: 0 */\r
+#define CAPSIOPISEL1 (0x0004u) /* CapTouchIO Pin Select Bit: 1 */\r
+#define CAPSIOPISEL2 (0x0008u) /* CapTouchIO Pin Select Bit: 2 */\r
+#define CAPSIOPOSEL0 (0x0010u) /* CapTouchIO Port Select Bit: 0 */\r
+#define CAPSIOPOSEL1 (0x0020u) /* CapTouchIO Port Select Bit: 1 */\r
+#define CAPSIOPOSEL2 (0x0040u) /* CapTouchIO Port Select Bit: 2 */\r
+#define CAPSIOPOSEL3 (0x0080u) /* CapTouchIO Port Select Bit: 3 */\r
+#define CAPSIOEN (0x0100u) /* CapTouchIO Enable */\r
+#define CAPSIO (0x0200u) /* CapTouchIO state */\r
+\r
+#endif\r
+/************************************************************\r
+* Capacitive_Touch_IO 1\r
+************************************************************/\r
+#ifdef __MSP430_HAS_CAP_TOUCH_IO_1__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CAPTIO1CTL (0x000Eu) /* Capacitive_Touch_IO 1 control register */\r
+#define OFS_CAPTIO1CTL_L OFS_CAPTIO1CTL\r
+#define OFS_CAPTIO1CTL_H OFS_CAPTIO1CTL+1\r
+\r
+#define CAPSIO1CTL CAPTIO1CTL /* legacy define */\r
+\r
+#endif\r
+/************************************************************\r
+* Comparator E\r
+************************************************************/\r
+#ifdef __MSP430_HAS_COMP_E__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CECTL0 (0x0000u) /* Comparator E Control Register 0 */\r
+#define OFS_CECTL0_L OFS_CECTL0\r
+#define OFS_CECTL0_H OFS_CECTL0+1\r
+#define OFS_CECTL1 (0x0002u) /* Comparator E Control Register 1 */\r
+#define OFS_CECTL1_L OFS_CECTL1\r
+#define OFS_CECTL1_H OFS_CECTL1+1\r
+#define OFS_CECTL2 (0x0004u) /* Comparator E Control Register 2 */\r
+#define OFS_CECTL2_L OFS_CECTL2\r
+#define OFS_CECTL2_H OFS_CECTL2+1\r
+#define OFS_CECTL3 (0x0006u) /* Comparator E Control Register 3 */\r
+#define OFS_CECTL3_L OFS_CECTL3\r
+#define OFS_CECTL3_H OFS_CECTL3+1\r
+#define OFS_CEINT (0x000Cu) /* Comparator E Interrupt Register */\r
+#define OFS_CEINT_L OFS_CEINT\r
+#define OFS_CEINT_H OFS_CEINT+1\r
+#define OFS_CEIV (0x000Eu) /* Comparator E Interrupt Vector Word */\r
+#define OFS_CEIV_L OFS_CEIV\r
+#define OFS_CEIV_H OFS_CEIV+1\r
+\r
+/* CECTL0 Control Bits */\r
+#define CEIPSEL0 (0x0001u) /* Comp. E Pos. Channel Input Select 0 */\r
+#define CEIPSEL1 (0x0002u) /* Comp. E Pos. Channel Input Select 1 */\r
+#define CEIPSEL2 (0x0004u) /* Comp. E Pos. Channel Input Select 2 */\r
+#define CEIPSEL3 (0x0008u) /* Comp. E Pos. Channel Input Select 3 */\r
+//#define RESERVED (0x0010u) /* Comp. E */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+#define CEIPEN (0x0080u) /* Comp. E Pos. Channel Input Enable */\r
+#define CEIMSEL0 (0x0100u) /* Comp. E Neg. Channel Input Select 0 */\r
+#define CEIMSEL1 (0x0200u) /* Comp. E Neg. Channel Input Select 1 */\r
+#define CEIMSEL2 (0x0400u) /* Comp. E Neg. Channel Input Select 2 */\r
+#define CEIMSEL3 (0x0800u) /* Comp. E Neg. Channel Input Select 3 */\r
+//#define RESERVED (0x1000u) /* Comp. E */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+#define CEIMEN (0x8000u) /* Comp. E Neg. Channel Input Enable */\r
+\r
+/* CECTL0 Control Bits */\r
+#define CEIPSEL0_L (0x0001u) /* Comp. E Pos. Channel Input Select 0 */\r
+#define CEIPSEL1_L (0x0002u) /* Comp. E Pos. Channel Input Select 1 */\r
+#define CEIPSEL2_L (0x0004u) /* Comp. E Pos. Channel Input Select 2 */\r
+#define CEIPSEL3_L (0x0008u) /* Comp. E Pos. Channel Input Select 3 */\r
+//#define RESERVED (0x0010u) /* Comp. E */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+#define CEIPEN_L (0x0080u) /* Comp. E Pos. Channel Input Enable */\r
+//#define RESERVED (0x1000u) /* Comp. E */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+\r
+/* CECTL0 Control Bits */\r
+//#define RESERVED (0x0010u) /* Comp. E */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+#define CEIMSEL0_H (0x0001u) /* Comp. E Neg. Channel Input Select 0 */\r
+#define CEIMSEL1_H (0x0002u) /* Comp. E Neg. Channel Input Select 1 */\r
+#define CEIMSEL2_H (0x0004u) /* Comp. E Neg. Channel Input Select 2 */\r
+#define CEIMSEL3_H (0x0008u) /* Comp. E Neg. Channel Input Select 3 */\r
+//#define RESERVED (0x1000u) /* Comp. E */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+#define CEIMEN_H (0x0080u) /* Comp. E Neg. Channel Input Enable */\r
+\r
+#define CEIPSEL_0 (0x0000u) /* Comp. E V+ terminal Input Select: Channel 0 */\r
+#define CEIPSEL_1 (0x0001u) /* Comp. E V+ terminal Input Select: Channel 1 */\r
+#define CEIPSEL_2 (0x0002u) /* Comp. E V+ terminal Input Select: Channel 2 */\r
+#define CEIPSEL_3 (0x0003u) /* Comp. E V+ terminal Input Select: Channel 3 */\r
+#define CEIPSEL_4 (0x0004u) /* Comp. E V+ terminal Input Select: Channel 4 */\r
+#define CEIPSEL_5 (0x0005u) /* Comp. E V+ terminal Input Select: Channel 5 */\r
+#define CEIPSEL_6 (0x0006u) /* Comp. E V+ terminal Input Select: Channel 6 */\r
+#define CEIPSEL_7 (0x0007u) /* Comp. E V+ terminal Input Select: Channel 7 */\r
+#define CEIPSEL_8 (0x0008u) /* Comp. E V+ terminal Input Select: Channel 8 */\r
+#define CEIPSEL_9 (0x0009u) /* Comp. E V+ terminal Input Select: Channel 9 */\r
+#define CEIPSEL_10 (0x000Au) /* Comp. E V+ terminal Input Select: Channel 10 */\r
+#define CEIPSEL_11 (0x000Bu) /* Comp. E V+ terminal Input Select: Channel 11 */\r
+#define CEIPSEL_12 (0x000Cu) /* Comp. E V+ terminal Input Select: Channel 12 */\r
+#define CEIPSEL_13 (0x000Du) /* Comp. E V+ terminal Input Select: Channel 13 */\r
+#define CEIPSEL_14 (0x000Eu) /* Comp. E V+ terminal Input Select: Channel 14 */\r
+#define CEIPSEL_15 (0x000Fu) /* Comp. E V+ terminal Input Select: Channel 15 */\r
+\r
+#define CEIMSEL_0 (0x0000u) /* Comp. E V- Terminal Input Select: Channel 0 */\r
+#define CEIMSEL_1 (0x0100u) /* Comp. E V- Terminal Input Select: Channel 1 */\r
+#define CEIMSEL_2 (0x0200u) /* Comp. E V- Terminal Input Select: Channel 2 */\r
+#define CEIMSEL_3 (0x0300u) /* Comp. E V- Terminal Input Select: Channel 3 */\r
+#define CEIMSEL_4 (0x0400u) /* Comp. E V- Terminal Input Select: Channel 4 */\r
+#define CEIMSEL_5 (0x0500u) /* Comp. E V- Terminal Input Select: Channel 5 */\r
+#define CEIMSEL_6 (0x0600u) /* Comp. E V- Terminal Input Select: Channel 6 */\r
+#define CEIMSEL_7 (0x0700u) /* Comp. E V- Terminal Input Select: Channel 7 */\r
+#define CEIMSEL_8 (0x0800u) /* Comp. E V- terminal Input Select: Channel 8 */\r
+#define CEIMSEL_9 (0x0900u) /* Comp. E V- terminal Input Select: Channel 9 */\r
+#define CEIMSEL_10 (0x0A00u) /* Comp. E V- terminal Input Select: Channel 10 */\r
+#define CEIMSEL_11 (0x0B00u) /* Comp. E V- terminal Input Select: Channel 11 */\r
+#define CEIMSEL_12 (0x0C00u) /* Comp. E V- terminal Input Select: Channel 12 */\r
+#define CEIMSEL_13 (0x0D00u) /* Comp. E V- terminal Input Select: Channel 13 */\r
+#define CEIMSEL_14 (0x0E00u) /* Comp. E V- terminal Input Select: Channel 14 */\r
+#define CEIMSEL_15 (0x0F00u) /* Comp. E V- terminal Input Select: Channel 15 */\r
+\r
+/* CECTL1 Control Bits */\r
+#define CEOUT (0x0001u) /* Comp. E Output */\r
+#define CEOUTPOL (0x0002u) /* Comp. E Output Polarity */\r
+#define CEF (0x0004u) /* Comp. E Enable Output Filter */\r
+#define CEIES (0x0008u) /* Comp. E Interrupt Edge Select */\r
+#define CESHORT (0x0010u) /* Comp. E Input Short */\r
+#define CEEX (0x0020u) /* Comp. E Exchange Inputs */\r
+#define CEFDLY0 (0x0040u) /* Comp. E Filter delay Bit 0 */\r
+#define CEFDLY1 (0x0080u) /* Comp. E Filter delay Bit 1 */\r
+#define CEPWRMD0 (0x0100u) /* Comp. E Power mode Bit 0 */\r
+#define CEPWRMD1 (0x0200u) /* Comp. E Power mode Bit 1 */\r
+#define CEON (0x0400u) /* Comp. E enable */\r
+#define CEMRVL (0x0800u) /* Comp. E CEMRV Level */\r
+#define CEMRVS (0x1000u) /* Comp. E Output selects between VREF0 or VREF1*/\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CECTL1 Control Bits */\r
+#define CEOUT_L (0x0001u) /* Comp. E Output */\r
+#define CEOUTPOL_L (0x0002u) /* Comp. E Output Polarity */\r
+#define CEF_L (0x0004u) /* Comp. E Enable Output Filter */\r
+#define CEIES_L (0x0008u) /* Comp. E Interrupt Edge Select */\r
+#define CESHORT_L (0x0010u) /* Comp. E Input Short */\r
+#define CEEX_L (0x0020u) /* Comp. E Exchange Inputs */\r
+#define CEFDLY0_L (0x0040u) /* Comp. E Filter delay Bit 0 */\r
+#define CEFDLY1_L (0x0080u) /* Comp. E Filter delay Bit 1 */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CECTL1 Control Bits */\r
+#define CEPWRMD0_H (0x0001u) /* Comp. E Power mode Bit 0 */\r
+#define CEPWRMD1_H (0x0002u) /* Comp. E Power mode Bit 1 */\r
+#define CEON_H (0x0004u) /* Comp. E enable */\r
+#define CEMRVL_H (0x0008u) /* Comp. E CEMRV Level */\r
+#define CEMRVS_H (0x0010u) /* Comp. E Output selects between VREF0 or VREF1*/\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+#define CEPWRMD_0 (0x0000u) /* Comp. E Power mode 0 */\r
+#define CEPWRMD_1 (0x0100u) /* Comp. E Power mode 1 */\r
+#define CEPWRMD_2 (0x0200u) /* Comp. E Power mode 2 */\r
+#define CEPWRMD_3 (0x0300u) /* Comp. E Power mode 3*/\r
+\r
+#define CEFDLY_0 (0x0000u) /* Comp. E Filter delay 0 : 450ns */\r
+#define CEFDLY_1 (0x0040u) /* Comp. E Filter delay 1 : 900ns */\r
+#define CEFDLY_2 (0x0080u) /* Comp. E Filter delay 2 : 1800ns */\r
+#define CEFDLY_3 (0x00C0u) /* Comp. E Filter delay 3 : 3600ns */\r
+\r
+/* CECTL2 Control Bits */\r
+#define CEREF00 (0x0001u) /* Comp. E Reference 0 Resistor Select Bit : 0 */\r
+#define CEREF01 (0x0002u) /* Comp. E Reference 0 Resistor Select Bit : 1 */\r
+#define CEREF02 (0x0004u) /* Comp. E Reference 0 Resistor Select Bit : 2 */\r
+#define CEREF03 (0x0008u) /* Comp. E Reference 0 Resistor Select Bit : 3 */\r
+#define CEREF04 (0x0010u) /* Comp. E Reference 0 Resistor Select Bit : 4 */\r
+#define CERSEL (0x0020u) /* Comp. E Reference select */\r
+#define CERS0 (0x0040u) /* Comp. E Reference Source Bit : 0 */\r
+#define CERS1 (0x0080u) /* Comp. E Reference Source Bit : 1 */\r
+#define CEREF10 (0x0100u) /* Comp. E Reference 1 Resistor Select Bit : 0 */\r
+#define CEREF11 (0x0200u) /* Comp. E Reference 1 Resistor Select Bit : 1 */\r
+#define CEREF12 (0x0400u) /* Comp. E Reference 1 Resistor Select Bit : 2 */\r
+#define CEREF13 (0x0800u) /* Comp. E Reference 1 Resistor Select Bit : 3 */\r
+#define CEREF14 (0x1000u) /* Comp. E Reference 1 Resistor Select Bit : 4 */\r
+#define CEREFL0 (0x2000u) /* Comp. E Reference voltage level Bit : 0 */\r
+#define CEREFL1 (0x4000u) /* Comp. E Reference voltage level Bit : 1 */\r
+#define CEREFACC (0x8000u) /* Comp. E Reference Accuracy */\r
+\r
+/* CECTL2 Control Bits */\r
+#define CEREF00_L (0x0001u) /* Comp. E Reference 0 Resistor Select Bit : 0 */\r
+#define CEREF01_L (0x0002u) /* Comp. E Reference 0 Resistor Select Bit : 1 */\r
+#define CEREF02_L (0x0004u) /* Comp. E Reference 0 Resistor Select Bit : 2 */\r
+#define CEREF03_L (0x0008u) /* Comp. E Reference 0 Resistor Select Bit : 3 */\r
+#define CEREF04_L (0x0010u) /* Comp. E Reference 0 Resistor Select Bit : 4 */\r
+#define CERSEL_L (0x0020u) /* Comp. E Reference select */\r
+#define CERS0_L (0x0040u) /* Comp. E Reference Source Bit : 0 */\r
+#define CERS1_L (0x0080u) /* Comp. E Reference Source Bit : 1 */\r
+\r
+/* CECTL2 Control Bits */\r
+#define CEREF10_H (0x0001u) /* Comp. E Reference 1 Resistor Select Bit : 0 */\r
+#define CEREF11_H (0x0002u) /* Comp. E Reference 1 Resistor Select Bit : 1 */\r
+#define CEREF12_H (0x0004u) /* Comp. E Reference 1 Resistor Select Bit : 2 */\r
+#define CEREF13_H (0x0008u) /* Comp. E Reference 1 Resistor Select Bit : 3 */\r
+#define CEREF14_H (0x0010u) /* Comp. E Reference 1 Resistor Select Bit : 4 */\r
+#define CEREFL0_H (0x0020u) /* Comp. E Reference voltage level Bit : 0 */\r
+#define CEREFL1_H (0x0040u) /* Comp. E Reference voltage level Bit : 1 */\r
+#define CEREFACC_H (0x0080u) /* Comp. E Reference Accuracy */\r
+\r
+#define CEREF0_0 (0x0000u) /* Comp. E Int. Ref.0 Select 0 : 1/32 */\r
+#define CEREF0_1 (0x0001u) /* Comp. E Int. Ref.0 Select 1 : 2/32 */\r
+#define CEREF0_2 (0x0002u) /* Comp. E Int. Ref.0 Select 2 : 3/32 */\r
+#define CEREF0_3 (0x0003u) /* Comp. E Int. Ref.0 Select 3 : 4/32 */\r
+#define CEREF0_4 (0x0004u) /* Comp. E Int. Ref.0 Select 4 : 5/32 */\r
+#define CEREF0_5 (0x0005u) /* Comp. E Int. Ref.0 Select 5 : 6/32 */\r
+#define CEREF0_6 (0x0006u) /* Comp. E Int. Ref.0 Select 6 : 7/32 */\r
+#define CEREF0_7 (0x0007u) /* Comp. E Int. Ref.0 Select 7 : 8/32 */\r
+#define CEREF0_8 (0x0008u) /* Comp. E Int. Ref.0 Select 0 : 9/32 */\r
+#define CEREF0_9 (0x0009u) /* Comp. E Int. Ref.0 Select 1 : 10/32 */\r
+#define CEREF0_10 (0x000Au) /* Comp. E Int. Ref.0 Select 2 : 11/32 */\r
+#define CEREF0_11 (0x000Bu) /* Comp. E Int. Ref.0 Select 3 : 12/32 */\r
+#define CEREF0_12 (0x000Cu) /* Comp. E Int. Ref.0 Select 4 : 13/32 */\r
+#define CEREF0_13 (0x000Du) /* Comp. E Int. Ref.0 Select 5 : 14/32 */\r
+#define CEREF0_14 (0x000Eu) /* Comp. E Int. Ref.0 Select 6 : 15/32 */\r
+#define CEREF0_15 (0x000Fu) /* Comp. E Int. Ref.0 Select 7 : 16/32 */\r
+#define CEREF0_16 (0x0010u) /* Comp. E Int. Ref.0 Select 0 : 17/32 */\r
+#define CEREF0_17 (0x0011u) /* Comp. E Int. Ref.0 Select 1 : 18/32 */\r
+#define CEREF0_18 (0x0012u) /* Comp. E Int. Ref.0 Select 2 : 19/32 */\r
+#define CEREF0_19 (0x0013u) /* Comp. E Int. Ref.0 Select 3 : 20/32 */\r
+#define CEREF0_20 (0x0014u) /* Comp. E Int. Ref.0 Select 4 : 21/32 */\r
+#define CEREF0_21 (0x0015u) /* Comp. E Int. Ref.0 Select 5 : 22/32 */\r
+#define CEREF0_22 (0x0016u) /* Comp. E Int. Ref.0 Select 6 : 23/32 */\r
+#define CEREF0_23 (0x0017u) /* Comp. E Int. Ref.0 Select 7 : 24/32 */\r
+#define CEREF0_24 (0x0018u) /* Comp. E Int. Ref.0 Select 0 : 25/32 */\r
+#define CEREF0_25 (0x0019u) /* Comp. E Int. Ref.0 Select 1 : 26/32 */\r
+#define CEREF0_26 (0x001Au) /* Comp. E Int. Ref.0 Select 2 : 27/32 */\r
+#define CEREF0_27 (0x001Bu) /* Comp. E Int. Ref.0 Select 3 : 28/32 */\r
+#define CEREF0_28 (0x001Cu) /* Comp. E Int. Ref.0 Select 4 : 29/32 */\r
+#define CEREF0_29 (0x001Du) /* Comp. E Int. Ref.0 Select 5 : 30/32 */\r
+#define CEREF0_30 (0x001Eu) /* Comp. E Int. Ref.0 Select 6 : 31/32 */\r
+#define CEREF0_31 (0x001Fu) /* Comp. E Int. Ref.0 Select 7 : 32/32 */\r
+\r
+#define CERS_0 (0x0000u) /* Comp. E Reference Source 0 : Off */\r
+#define CERS_1 (0x0040u) /* Comp. E Reference Source 1 : Vcc */\r
+#define CERS_2 (0x0080u) /* Comp. E Reference Source 2 : Shared Ref. */\r
+#define CERS_3 (0x00C0u) /* Comp. E Reference Source 3 : Shared Ref. / Off */\r
+\r
+#define CEREF1_0 (0x0000u) /* Comp. E Int. Ref.1 Select 0 : 1/32 */\r
+#define CEREF1_1 (0x0100u) /* Comp. E Int. Ref.1 Select 1 : 2/32 */\r
+#define CEREF1_2 (0x0200u) /* Comp. E Int. Ref.1 Select 2 : 3/32 */\r
+#define CEREF1_3 (0x0300u) /* Comp. E Int. Ref.1 Select 3 : 4/32 */\r
+#define CEREF1_4 (0x0400u) /* Comp. E Int. Ref.1 Select 4 : 5/32 */\r
+#define CEREF1_5 (0x0500u) /* Comp. E Int. Ref.1 Select 5 : 6/32 */\r
+#define CEREF1_6 (0x0600u) /* Comp. E Int. Ref.1 Select 6 : 7/32 */\r
+#define CEREF1_7 (0x0700u) /* Comp. E Int. Ref.1 Select 7 : 8/32 */\r
+#define CEREF1_8 (0x0800u) /* Comp. E Int. Ref.1 Select 0 : 9/32 */\r
+#define CEREF1_9 (0x0900u) /* Comp. E Int. Ref.1 Select 1 : 10/32 */\r
+#define CEREF1_10 (0x0A00u) /* Comp. E Int. Ref.1 Select 2 : 11/32 */\r
+#define CEREF1_11 (0x0B00u) /* Comp. E Int. Ref.1 Select 3 : 12/32 */\r
+#define CEREF1_12 (0x0C00u) /* Comp. E Int. Ref.1 Select 4 : 13/32 */\r
+#define CEREF1_13 (0x0D00u) /* Comp. E Int. Ref.1 Select 5 : 14/32 */\r
+#define CEREF1_14 (0x0E00u) /* Comp. E Int. Ref.1 Select 6 : 15/32 */\r
+#define CEREF1_15 (0x0F00u) /* Comp. E Int. Ref.1 Select 7 : 16/32 */\r
+#define CEREF1_16 (0x1000u) /* Comp. E Int. Ref.1 Select 0 : 17/32 */\r
+#define CEREF1_17 (0x1100u) /* Comp. E Int. Ref.1 Select 1 : 18/32 */\r
+#define CEREF1_18 (0x1200u) /* Comp. E Int. Ref.1 Select 2 : 19/32 */\r
+#define CEREF1_19 (0x1300u) /* Comp. E Int. Ref.1 Select 3 : 20/32 */\r
+#define CEREF1_20 (0x1400u) /* Comp. E Int. Ref.1 Select 4 : 21/32 */\r
+#define CEREF1_21 (0x1500u) /* Comp. E Int. Ref.1 Select 5 : 22/32 */\r
+#define CEREF1_22 (0x1600u) /* Comp. E Int. Ref.1 Select 6 : 23/32 */\r
+#define CEREF1_23 (0x1700u) /* Comp. E Int. Ref.1 Select 7 : 24/32 */\r
+#define CEREF1_24 (0x1800u) /* Comp. E Int. Ref.1 Select 0 : 25/32 */\r
+#define CEREF1_25 (0x1900u) /* Comp. E Int. Ref.1 Select 1 : 26/32 */\r
+#define CEREF1_26 (0x1A00u) /* Comp. E Int. Ref.1 Select 2 : 27/32 */\r
+#define CEREF1_27 (0x1B00u) /* Comp. E Int. Ref.1 Select 3 : 28/32 */\r
+#define CEREF1_28 (0x1C00u) /* Comp. E Int. Ref.1 Select 4 : 29/32 */\r
+#define CEREF1_29 (0x1D00u) /* Comp. E Int. Ref.1 Select 5 : 30/32 */\r
+#define CEREF1_30 (0x1E00u) /* Comp. E Int. Ref.1 Select 6 : 31/32 */\r
+#define CEREF1_31 (0x1F00u) /* Comp. E Int. Ref.1 Select 7 : 32/32 */\r
+\r
+#define CEREFL_0 (0x0000u) /* Comp. E Reference voltage level 0 : None */\r
+#define CEREFL_1 (0x2000u) /* Comp. E Reference voltage level 1 : 1.2V */\r
+#define CEREFL_2 (0x4000u) /* Comp. E Reference voltage level 2 : 2.0V */\r
+#define CEREFL_3 (0x6000u) /* Comp. E Reference voltage level 3 : 2.5V */\r
+\r
+#define CEPD0 (0x0001u) /* Comp. E Disable Input Buffer of Port Register .0 */\r
+#define CEPD1 (0x0002u) /* Comp. E Disable Input Buffer of Port Register .1 */\r
+#define CEPD2 (0x0004u) /* Comp. E Disable Input Buffer of Port Register .2 */\r
+#define CEPD3 (0x0008u) /* Comp. E Disable Input Buffer of Port Register .3 */\r
+#define CEPD4 (0x0010u) /* Comp. E Disable Input Buffer of Port Register .4 */\r
+#define CEPD5 (0x0020u) /* Comp. E Disable Input Buffer of Port Register .5 */\r
+#define CEPD6 (0x0040u) /* Comp. E Disable Input Buffer of Port Register .6 */\r
+#define CEPD7 (0x0080u) /* Comp. E Disable Input Buffer of Port Register .7 */\r
+#define CEPD8 (0x0100u) /* Comp. E Disable Input Buffer of Port Register .8 */\r
+#define CEPD9 (0x0200u) /* Comp. E Disable Input Buffer of Port Register .9 */\r
+#define CEPD10 (0x0400u) /* Comp. E Disable Input Buffer of Port Register .10 */\r
+#define CEPD11 (0x0800u) /* Comp. E Disable Input Buffer of Port Register .11 */\r
+#define CEPD12 (0x1000u) /* Comp. E Disable Input Buffer of Port Register .12 */\r
+#define CEPD13 (0x2000u) /* Comp. E Disable Input Buffer of Port Register .13 */\r
+#define CEPD14 (0x4000u) /* Comp. E Disable Input Buffer of Port Register .14 */\r
+#define CEPD15 (0x8000u) /* Comp. E Disable Input Buffer of Port Register .15 */\r
+\r
+#define CEPD0_L (0x0001u) /* Comp. E Disable Input Buffer of Port Register .0 */\r
+#define CEPD1_L (0x0002u) /* Comp. E Disable Input Buffer of Port Register .1 */\r
+#define CEPD2_L (0x0004u) /* Comp. E Disable Input Buffer of Port Register .2 */\r
+#define CEPD3_L (0x0008u) /* Comp. E Disable Input Buffer of Port Register .3 */\r
+#define CEPD4_L (0x0010u) /* Comp. E Disable Input Buffer of Port Register .4 */\r
+#define CEPD5_L (0x0020u) /* Comp. E Disable Input Buffer of Port Register .5 */\r
+#define CEPD6_L (0x0040u) /* Comp. E Disable Input Buffer of Port Register .6 */\r
+#define CEPD7_L (0x0080u) /* Comp. E Disable Input Buffer of Port Register .7 */\r
+\r
+#define CEPD8_H (0x0001u) /* Comp. E Disable Input Buffer of Port Register .8 */\r
+#define CEPD9_H (0x0002u) /* Comp. E Disable Input Buffer of Port Register .9 */\r
+#define CEPD10_H (0x0004u) /* Comp. E Disable Input Buffer of Port Register .10 */\r
+#define CEPD11_H (0x0008u) /* Comp. E Disable Input Buffer of Port Register .11 */\r
+#define CEPD12_H (0x0010u) /* Comp. E Disable Input Buffer of Port Register .12 */\r
+#define CEPD13_H (0x0020u) /* Comp. E Disable Input Buffer of Port Register .13 */\r
+#define CEPD14_H (0x0040u) /* Comp. E Disable Input Buffer of Port Register .14 */\r
+#define CEPD15_H (0x0080u) /* Comp. E Disable Input Buffer of Port Register .15 */\r
+\r
+/* CEINT Control Bits */\r
+#define CEIFG (0x0001u) /* Comp. E Interrupt Flag */\r
+#define CEIIFG (0x0002u) /* Comp. E Interrupt Flag Inverted Polarity */\r
+//#define RESERVED (0x0004u) /* Comp. E */\r
+//#define RESERVED (0x0008u) /* Comp. E */\r
+#define CERDYIFG (0x0010u) /* Comp. E Comparator_E ready interrupt flag */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+//#define RESERVED (0x0080u) /* Comp. E */\r
+#define CEIE (0x0100u) /* Comp. E Interrupt Enable */\r
+#define CEIIE (0x0200u) /* Comp. E Interrupt Enable Inverted Polarity */\r
+//#define RESERVED (0x0400u) /* Comp. E */\r
+//#define RESERVED (0x0800u) /* Comp. E */\r
+#define CERDYIE (0x1000u) /* Comp. E Comparator_E ready interrupt enable */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CEINT Control Bits */\r
+#define CEIFG_L (0x0001u) /* Comp. E Interrupt Flag */\r
+#define CEIIFG_L (0x0002u) /* Comp. E Interrupt Flag Inverted Polarity */\r
+//#define RESERVED (0x0004u) /* Comp. E */\r
+//#define RESERVED (0x0008u) /* Comp. E */\r
+#define CERDYIFG_L (0x0010u) /* Comp. E Comparator_E ready interrupt flag */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+//#define RESERVED (0x0080u) /* Comp. E */\r
+//#define RESERVED (0x0400u) /* Comp. E */\r
+//#define RESERVED (0x0800u) /* Comp. E */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CEINT Control Bits */\r
+//#define RESERVED (0x0004u) /* Comp. E */\r
+//#define RESERVED (0x0008u) /* Comp. E */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+//#define RESERVED (0x0080u) /* Comp. E */\r
+#define CEIE_H (0x0001u) /* Comp. E Interrupt Enable */\r
+#define CEIIE_H (0x0002u) /* Comp. E Interrupt Enable Inverted Polarity */\r
+//#define RESERVED (0x0400u) /* Comp. E */\r
+//#define RESERVED (0x0800u) /* Comp. E */\r
+#define CERDYIE_H (0x0010u) /* Comp. E Comparator_E ready interrupt enable */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CEIV Definitions */\r
+#define CEIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define CEIV_CEIFG (0x0002u) /* CEIFG */\r
+#define CEIV_CEIIFG (0x0004u) /* CEIIFG */\r
+#define CEIV_CERDYIFG (0x000Au) /* CERDYIFG */\r
+\r
+#endif\r
+/*************************************************************\r
+* CRC Module\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CRCDI (0x0000u) /* CRC Data In Register */\r
+#define OFS_CRCDI_L OFS_CRCDI\r
+#define OFS_CRCDI_H OFS_CRCDI+1\r
+#define OFS_CRCDIRB (0x0002u) /* CRC data in reverse byte Register */\r
+#define OFS_CRCDIRB_L OFS_CRCDIRB\r
+#define OFS_CRCDIRB_H OFS_CRCDIRB+1\r
+#define OFS_CRCINIRES (0x0004u) /* CRC Initialisation Register and Result Register */\r
+#define OFS_CRCINIRES_L OFS_CRCINIRES\r
+#define OFS_CRCINIRES_H OFS_CRCINIRES+1\r
+#define OFS_CRCRESR (0x0006u) /* CRC reverse result Register */\r
+#define OFS_CRCRESR_L OFS_CRCRESR\r
+#define OFS_CRCRESR_H OFS_CRCRESR+1\r
+\r
+#endif\r
+/*************************************************************\r
+* CRC Module\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_CRC32__ /* Definition to show that Module is available */\r
+\r
+\r
+//#define CRC32DIL0_O (0x0000u) /* CRC32 Data In */\r
+#define OFS_CRC32DIW0 (0x0000u) /* CRC32 Data In */\r
+#define OFS_CRC32DIW0_L OFS_CRC32DIW0\r
+#define OFS_CRC32DIW0_H OFS_CRC32DIW0+1\r
+#define OFS_CRC32DIW1 (0x0002u) /* CRC32 Data In */\r
+#define OFS_CRC32DIW1_L OFS_CRC32DIW1\r
+#define OFS_CRC32DIW1_H OFS_CRC32DIW1+1\r
+#define CRC32DIB0 CRC32DIW0_L\r
+\r
+//#define CRC32DIRBL0_O (0x0004u) /* CRC32 Data In Reversed Bit */\r
+#define OFS_CRC32DIRBW1 (0x0004u) /* CRC32 Data In Reversed Bit */\r
+#define OFS_CRC32DIRBW1_L OFS_CRC32DIRBW1\r
+#define OFS_CRC32DIRBW1_H OFS_CRC32DIRBW1+1\r
+#define OFS_CRC32DIRBW0 (0x0006u) /* CRC32 Data In Reversed Bit */\r
+#define OFS_CRC32DIRBW0_L OFS_CRC32DIRBW0\r
+#define OFS_CRC32DIRBW0_H OFS_CRC32DIRBW0+1\r
+#define CRC32DIRBB0 CRC32DIRBW0_H\r
+\r
+//#define CRC32INIRESL0_O (0x0008u) /* CRC32 Initialization and Result */\r
+#define OFS_CRC32INIRESW0 (0x0008u) /* CRC32 Initialization and Result */\r
+#define OFS_CRC32INIRESW0_L OFS_CRC32INIRESW0\r
+#define OFS_CRC32INIRESW0_H OFS_CRC32INIRESW0+1\r
+#define OFS_CRC32INIRESW1 (0x000Au) /* CRC32 Initialization and Result */\r
+#define OFS_CRC32INIRESW1_L OFS_CRC32INIRESW1\r
+#define OFS_CRC32INIRESW1_H OFS_CRC32INIRESW1+1\r
+#define CRC32RESB0 CRC32INIRESW0_L\r
+#define CRC32RESB1 CRC32INIRESW0_H\r
+#define CRC32RESB2 CRC32INIRESW1_L\r
+#define CRC32RESB3 CRC32INIRESW1_H\r
+\r
+//#define CRC32RESRL0_O (0x000Cu) /* CRC32 Result Reverse */\r
+#define OFS_CRC32RESRW1 (0x000Cu) /* CRC32 Result Reverse */\r
+#define OFS_CRC32RESRW1_L OFS_CRC32RESRW1\r
+#define OFS_CRC32RESRW1_H OFS_CRC32RESRW1+1\r
+#define OFS_CRC32RESRW0 (0x000Eu) /* CRC32 Result Reverse */\r
+#define OFS_CRC32RESRW0_L OFS_CRC32RESRW0\r
+#define OFS_CRC32RESRW0_H OFS_CRC32RESRW0+1\r
+#define CRC32RESRB3 CRC32RESRW1_L\r
+#define CRC32RESRB2 CRC32RESRW1_H\r
+#define CRC32RESRB1 CRC32RESRW0_L\r
+#define CRC32RESRB0 CRC32RESRW0_H\r
+\r
+//#define CRC16DIL0_O (0x0010u) /* CRC16 Data Input */\r
+#define OFS_CRC16DIW0 (0x0010u) /* CRC16 Data Input */\r
+#define OFS_CRC16DIW0_L OFS_CRC16DIW0\r
+#define OFS_CRC16DIW0_H OFS_CRC16DIW0+1\r
+#define OFS_CRC16DIW1 (0x0012u) /* CRC16 Data Input */\r
+#define OFS_CRC16DIW1_L OFS_CRC16DIW1\r
+#define OFS_CRC16DIW1_H OFS_CRC16DIW1+1\r
+#define CRC16DIB0 CRC16DIW0_L\r
+//#define CRC16DIRBL0_O (0x0014u) /* CRC16 Data In Reverse */\r
+#define OFS_CRC16DIRBW1 (0x0014u) /* CRC16 Data In Reverse */\r
+#define OFS_CRC16DIRBW1_L OFS_CRC16DIRBW1\r
+#define OFS_CRC16DIRBW1_H OFS_CRC16DIRBW1+1\r
+#define OFS_CRC16DIRBW0 (0x0016u) /* CRC16 Data In Reverse */\r
+#define OFS_CRC16DIRBW0_L OFS_CRC16DIRBW0\r
+#define OFS_CRC16DIRBW0_H OFS_CRC16DIRBW0+1\r
+#define CRC16DIRBB0 CRC16DIRBW0_L\r
+\r
+//#define CRC16INIRESL0_O (0x0018u) /* CRC16 Init and Result */\r
+#define OFS_CRC16INIRESW0 (0x0018u) /* CRC16 Init and Result */\r
+#define OFS_CRC16INIRESW0_L OFS_CRC16INIRESW0\r
+#define OFS_CRC16INIRESW0_H OFS_CRC16INIRESW0+1\r
+#define CRC16INIRESB1 CRC16INIRESW0_H\r
+#define CRC16INIRESB0 CRC16INIRESW0_L\r
+\r
+//#define CRC16RESRL0_O (0x001Eu) /* CRC16 Result Reverse */\r
+#define OFS_CRC16RESRW0 (0x001Eu) /* CRC16 Result Reverse */\r
+#define OFS_CRC16RESRW0_L OFS_CRC16RESRW0\r
+#define OFS_CRC16RESRW0_H OFS_CRC16RESRW0+1\r
+#define OFS_CRC16RESRW1 (0x001Cu) /* CRC16 Result Reverse */\r
+#define OFS_CRC16RESRW1_L OFS_CRC16RESRW1\r
+#define OFS_CRC16RESRW1_H OFS_CRC16RESRW1+1\r
+#define CRC16RESRB1 CRC16RESRW0_L\r
+#define CRC16RESRB0 CRC16RESRW0_H\r
+\r
+#endif\r
+/************************************************************\r
+* CLOCK SYSTEM\r
+************************************************************/\r
+#ifdef __MSP430_HAS_CS__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CSCTL0 (0x0000u) /* CS Control Register 0 */\r
+#define OFS_CSCTL0_L OFS_CSCTL0\r
+#define OFS_CSCTL0_H OFS_CSCTL0+1\r
+#define OFS_CSCTL1 (0x0002u) /* CS Control Register 1 */\r
+#define OFS_CSCTL1_L OFS_CSCTL1\r
+#define OFS_CSCTL1_H OFS_CSCTL1+1\r
+#define OFS_CSCTL2 (0x0004u) /* CS Control Register 2 */\r
+#define OFS_CSCTL2_L OFS_CSCTL2\r
+#define OFS_CSCTL2_H OFS_CSCTL2+1\r
+#define OFS_CSCTL3 (0x0006u) /* CS Control Register 3 */\r
+#define OFS_CSCTL3_L OFS_CSCTL3\r
+#define OFS_CSCTL3_H OFS_CSCTL3+1\r
+#define OFS_CSCTL4 (0x0008u) /* CS Control Register 4 */\r
+#define OFS_CSCTL4_L OFS_CSCTL4\r
+#define OFS_CSCTL4_H OFS_CSCTL4+1\r
+#define OFS_CSCTL5 (0x000Au) /* CS Control Register 5 */\r
+#define OFS_CSCTL5_L OFS_CSCTL5\r
+#define OFS_CSCTL5_H OFS_CSCTL5+1\r
+#define OFS_CSCTL6 (0x000Cu) /* CS Control Register 6 */\r
+#define OFS_CSCTL6_L OFS_CSCTL6\r
+#define OFS_CSCTL6_H OFS_CSCTL6+1\r
+\r
+/* CSCTL0 Control Bits */\r
+\r
+#define CSKEY (0xA500u) /* CS Password */\r
+#define CSKEY_H (0xA5) /* CS Password for high byte access */\r
+\r
+/* CSCTL1 Control Bits */\r
+#define DCOFSEL0 (0x0002u) /* DCO frequency select Bit: 0 */\r
+#define DCOFSEL1 (0x0004u) /* DCO frequency select Bit: 1 */\r
+#define DCOFSEL2 (0x0008u) /* DCO frequency select Bit: 2 */\r
+#define DCORSEL (0x0040u) /* DCO range select. */\r
+\r
+/* CSCTL1 Control Bits */\r
+#define DCOFSEL0_L (0x0002u) /* DCO frequency select Bit: 0 */\r
+#define DCOFSEL1_L (0x0004u) /* DCO frequency select Bit: 1 */\r
+#define DCOFSEL2_L (0x0008u) /* DCO frequency select Bit: 2 */\r
+#define DCORSEL_L (0x0040u) /* DCO range select. */\r
+\r
+#define DCOFSEL_0 (0x0000u) /* DCO frequency select: 0 */\r
+#define DCOFSEL_1 (0x0002u) /* DCO frequency select: 1 */\r
+#define DCOFSEL_2 (0x0004u) /* DCO frequency select: 2 */\r
+#define DCOFSEL_3 (0x0006u) /* DCO frequency select: 3 */\r
+#define DCOFSEL_4 (0x0008u) /* DCO frequency select: 4 */\r
+#define DCOFSEL_5 (0x000Au) /* DCO frequency select: 5 */\r
+#define DCOFSEL_6 (0x000Cu) /* DCO frequency select: 6 */\r
+#define DCOFSEL_7 (0x000Eu) /* DCO frequency select: 7 */\r
+\r
+/* CSCTL2 Control Bits */\r
+#define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */\r
+#define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */\r
+#define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+#define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */\r
+#define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */\r
+#define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+#define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */\r
+#define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */\r
+#define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+/* CSCTL2 Control Bits */\r
+#define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */\r
+#define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */\r
+#define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+#define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */\r
+#define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */\r
+#define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+/* CSCTL2 Control Bits */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+#define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */\r
+#define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */\r
+#define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+#define SELM_0 (0x0000u) /* MCLK Source Select 0 */\r
+#define SELM_1 (0x0001u) /* MCLK Source Select 1 */\r
+#define SELM_2 (0x0002u) /* MCLK Source Select 2 */\r
+#define SELM_3 (0x0003u) /* MCLK Source Select 3 */\r
+#define SELM_4 (0x0004u) /* MCLK Source Select 4 */\r
+#define SELM_5 (0x0005u) /* MCLK Source Select 5 */\r
+#define SELM_6 (0x0006u) /* MCLK Source Select 6 */\r
+#define SELM_7 (0x0007u) /* MCLK Source Select 7 */\r
+#define SELM__LFXTCLK (0x0000u) /* MCLK Source Select LFXTCLK */\r
+#define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */\r
+#define SELM__LFMODOSC (0x0002u) /* MCLK Source Select LFMODOSC */\r
+#define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */\r
+#define SELM__MODOSC (0x0004u) /* MCLK Source Select MODOSC */\r
+#define SELM__HFXTCLK (0x0005u) /* MCLK Source Select HFXTCLK */\r
+\r
+#define SELS_0 (0x0000u) /* SMCLK Source Select 0 */\r
+#define SELS_1 (0x0010u) /* SMCLK Source Select 1 */\r
+#define SELS_2 (0x0020u) /* SMCLK Source Select 2 */\r
+#define SELS_3 (0x0030u) /* SMCLK Source Select 3 */\r
+#define SELS_4 (0x0040u) /* SMCLK Source Select 4 */\r
+#define SELS_5 (0x0050u) /* SMCLK Source Select 5 */\r
+#define SELS_6 (0x0060u) /* SMCLK Source Select 6 */\r
+#define SELS_7 (0x0070u) /* SMCLK Source Select 7 */\r
+#define SELS__LFXTCLK (0x0000u) /* SMCLK Source Select LFXTCLK */\r
+#define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */\r
+#define SELS__LFMODOSC (0x0020u) /* SMCLK Source Select LFMODOSC */\r
+#define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */\r
+#define SELS__MODOSC (0x0040u) /* SMCLK Source Select MODOSC */\r
+#define SELS__HFXTCLK (0x0050u) /* SMCLK Source Select HFXTCLK */\r
+\r
+#define SELA_0 (0x0000u) /* ACLK Source Select 0 */\r
+#define SELA_1 (0x0100u) /* ACLK Source Select 1 */\r
+#define SELA_2 (0x0200u) /* ACLK Source Select 2 */\r
+#define SELA_3 (0x0300u) /* ACLK Source Select 3 */\r
+#define SELA_4 (0x0400u) /* ACLK Source Select 4 */\r
+#define SELA_5 (0x0500u) /* ACLK Source Select 5 */\r
+#define SELA_6 (0x0600u) /* ACLK Source Select 6 */\r
+#define SELA_7 (0x0700u) /* ACLK Source Select 7 */\r
+#define SELA__LFXTCLK (0x0000u) /* ACLK Source Select LFXTCLK */\r
+#define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */\r
+#define SELA__LFMODOSC (0x0200u) /* ACLK Source Select LFMODOSC */\r
+\r
+/* CSCTL3 Control Bits */\r
+#define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */\r
+#define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */\r
+#define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+#define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */\r
+#define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */\r
+#define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+#define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */\r
+#define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */\r
+#define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+/* CSCTL3 Control Bits */\r
+#define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */\r
+#define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */\r
+#define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+#define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */\r
+#define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */\r
+#define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+/* CSCTL3 Control Bits */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+#define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */\r
+#define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */\r
+#define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+#define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */\r
+#define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */\r
+#define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */\r
+#define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */\r
+#define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */\r
+#define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */\r
+#define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */\r
+#define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */\r
+#define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */\r
+#define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */\r
+#define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */\r
+#define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */\r
+\r
+#define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */\r
+#define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */\r
+#define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */\r
+#define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */\r
+#define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */\r
+#define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */\r
+#define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */\r
+#define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */\r
+#define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */\r
+#define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */\r
+#define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */\r
+#define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */\r
+\r
+#define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */\r
+#define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */\r
+#define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */\r
+#define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */\r
+#define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */\r
+#define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */\r
+#define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */\r
+#define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */\r
+#define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */\r
+#define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */\r
+#define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */\r
+#define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define LFXTOFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */\r
+#define SMCLKOFF (0x0002u) /* SMCLK Off */\r
+#define VLOOFF (0x0008u) /* VLO Off */\r
+#define LFXTBYPASS (0x0010u) /* LFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define LFXTAGCOFF (0x0020u) /* LFXT automatic gain control off */\r
+#define LFXTDRIVE0 (0x0040u) /* LFXT Drive Level mode Bit 0 */\r
+#define LFXTDRIVE1 (0x0080u) /* LFXT Drive Level mode Bit 1 */\r
+#define HFXTOFF (0x0100u) /* High Frequency Oscillator disable */\r
+#define HFFREQ0 (0x0400u) /* HFXT frequency selection Bit 1 */\r
+#define HFFREQ1 (0x0800u) /* HFXT frequency selection Bit 0 */\r
+#define HFXTBYPASS (0x1000u) /* HFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define HFXTDRIVE0 (0x4000u) /* HFXT Drive Level mode Bit 0 */\r
+#define HFXTDRIVE1 (0x8000u) /* HFXT Drive Level mode Bit 1 */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define LFXTOFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */\r
+#define SMCLKOFF_L (0x0002u) /* SMCLK Off */\r
+#define VLOOFF_L (0x0008u) /* VLO Off */\r
+#define LFXTBYPASS_L (0x0010u) /* LFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define LFXTAGCOFF_L (0x0020u) /* LFXT automatic gain control off */\r
+#define LFXTDRIVE0_L (0x0040u) /* LFXT Drive Level mode Bit 0 */\r
+#define LFXTDRIVE1_L (0x0080u) /* LFXT Drive Level mode Bit 1 */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define HFXTOFF_H (0x0001u) /* High Frequency Oscillator disable */\r
+#define HFFREQ0_H (0x0004u) /* HFXT frequency selection Bit 1 */\r
+#define HFFREQ1_H (0x0008u) /* HFXT frequency selection Bit 0 */\r
+#define HFXTBYPASS_H (0x0010u) /* HFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define HFXTDRIVE0_H (0x0040u) /* HFXT Drive Level mode Bit 0 */\r
+#define HFXTDRIVE1_H (0x0080u) /* HFXT Drive Level mode Bit 1 */\r
+\r
+#define LFXTDRIVE_0 (0x0000u) /* LFXT Drive Level mode: 0 */\r
+#define LFXTDRIVE_1 (0x0040u) /* LFXT Drive Level mode: 1 */\r
+#define LFXTDRIVE_2 (0x0080u) /* LFXT Drive Level mode: 2 */\r
+#define LFXTDRIVE_3 (0x00C0u) /* LFXT Drive Level mode: 3 */\r
+\r
+#define HFFREQ_0 (0x0000u) /* HFXT frequency selection: 0 */\r
+#define HFFREQ_1 (0x0400u) /* HFXT frequency selection: 1 */\r
+#define HFFREQ_2 (0x0800u) /* HFXT frequency selection: 2 */\r
+#define HFFREQ_3 (0x0C00u) /* HFXT frequency selection: 3 */\r
+\r
+#define HFXTDRIVE_0 (0x0000u) /* HFXT Drive Level mode: 0 */\r
+#define HFXTDRIVE_1 (0x4000u) /* HFXT Drive Level mode: 1 */\r
+#define HFXTDRIVE_2 (0x8000u) /* HFXT Drive Level mode: 2 */\r
+#define HFXTDRIVE_3 (0xC000u) /* HFXT Drive Level mode: 3 */\r
+\r
+/* CSCTL5 Control Bits */\r
+#define LFXTOFFG (0x0001u) /* LFXT Low Frequency Oscillator Fault Flag */\r
+#define HFXTOFFG (0x0002u) /* HFXT High Frequency Oscillator Fault Flag */\r
+#define ENSTFCNT1 (0x0040u) /* Enable start counter for XT1 */\r
+#define ENSTFCNT2 (0x0080u) /* Enable start counter for XT2 */\r
+\r
+/* CSCTL5 Control Bits */\r
+#define LFXTOFFG_L (0x0001u) /* LFXT Low Frequency Oscillator Fault Flag */\r
+#define HFXTOFFG_L (0x0002u) /* HFXT High Frequency Oscillator Fault Flag */\r
+#define ENSTFCNT1_L (0x0040u) /* Enable start counter for XT1 */\r
+#define ENSTFCNT2_L (0x0080u) /* Enable start counter for XT2 */\r
+\r
+/* CSCTL6 Control Bits */\r
+#define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */\r
+#define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */\r
+#define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */\r
+#define MODCLKREQEN (0x0008u) /* MODOSC Clock Request Enable */\r
+\r
+/* CSCTL6 Control Bits */\r
+#define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */\r
+#define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */\r
+#define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */\r
+#define MODCLKREQEN_L (0x0008u) /* MODOSC Clock Request Enable */\r
+\r
+#endif\r
+/************************************************************\r
+* DMA_X\r
+************************************************************/\r
+#ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */\r
+\r
+#define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */\r
+#define OFS_DMACTL0_L OFS_DMACTL0\r
+#define OFS_DMACTL0_H OFS_DMACTL0+1\r
+#define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */\r
+#define OFS_DMACTL1_L OFS_DMACTL1\r
+#define OFS_DMACTL1_H OFS_DMACTL1+1\r
+#define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */\r
+#define OFS_DMACTL2_L OFS_DMACTL2\r
+#define OFS_DMACTL2_H OFS_DMACTL2+1\r
+#define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */\r
+#define OFS_DMACTL3_L OFS_DMACTL3\r
+#define OFS_DMACTL3_H OFS_DMACTL3+1\r
+#define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */\r
+#define OFS_DMACTL4_L OFS_DMACTL4\r
+#define OFS_DMACTL4_H OFS_DMACTL4+1\r
+#define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */\r
+#define OFS_DMAIV_L OFS_DMAIV\r
+#define OFS_DMAIV_H OFS_DMAIV+1\r
+\r
+#define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */\r
+#define OFS_DMA0CTL_L OFS_DMA0CTL\r
+#define OFS_DMA0CTL_H OFS_DMA0CTL+1\r
+#define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */\r
+#define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */\r
+#define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */\r
+\r
+#define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */\r
+#define OFS_DMA1CTL_L OFS_DMA1CTL\r
+#define OFS_DMA1CTL_H OFS_DMA1CTL+1\r
+#define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */\r
+#define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */\r
+#define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */\r
+\r
+#define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */\r
+#define OFS_DMA2CTL_L OFS_DMA2CTL\r
+#define OFS_DMA2CTL_H OFS_DMA2CTL+1\r
+#define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */\r
+#define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */\r
+#define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */\r
+\r
+/* DMACTL0 Control Bits */\r
+#define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */\r
+#define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */\r
+#define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */\r
+#define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */\r
+#define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */\r
+#define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */\r
+#define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */\r
+#define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */\r
+#define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */\r
+#define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */\r
+\r
+/* DMACTL0 Control Bits */\r
+#define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */\r
+#define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */\r
+#define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */\r
+#define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */\r
+#define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */\r
+\r
+/* DMACTL0 Control Bits */\r
+#define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */\r
+#define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */\r
+#define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */\r
+#define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */\r
+#define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */\r
+\r
+/* DMACTL01 Control Bits */\r
+#define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */\r
+#define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */\r
+#define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */\r
+#define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */\r
+#define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */\r
+\r
+/* DMACTL01 Control Bits */\r
+#define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */\r
+#define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */\r
+#define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */\r
+#define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */\r
+#define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */\r
+\r
+/* DMACTL4 Control Bits */\r
+#define ENNMI (0x0001u) /* Enable NMI interruption of DMA */\r
+#define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */\r
+#define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
+\r
+/* DMACTL4 Control Bits */\r
+#define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */\r
+#define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */\r
+#define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
+\r
+/* DMAxCTL Control Bits */\r
+#define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */\r
+#define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */\r
+#define DMAIE (0x0004u) /* DMA interrupt enable */\r
+#define DMAIFG (0x0008u) /* DMA interrupt flag */\r
+#define DMAEN (0x0010u) /* DMA enable */\r
+#define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */\r
+#define DMASRCBYTE (0x0040u) /* DMA source byte */\r
+#define DMADSTBYTE (0x0080u) /* DMA destination byte */\r
+#define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */\r
+#define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */\r
+#define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */\r
+#define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */\r
+#define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */\r
+#define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */\r
+#define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */\r
+\r
+/* DMAxCTL Control Bits */\r
+#define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */\r
+#define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */\r
+#define DMAIE_L (0x0004u) /* DMA interrupt enable */\r
+#define DMAIFG_L (0x0008u) /* DMA interrupt flag */\r
+#define DMAEN_L (0x0010u) /* DMA enable */\r
+#define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */\r
+#define DMASRCBYTE_L (0x0040u) /* DMA source byte */\r
+#define DMADSTBYTE_L (0x0080u) /* DMA destination byte */\r
+\r
+/* DMAxCTL Control Bits */\r
+#define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */\r
+#define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */\r
+#define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */\r
+#define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */\r
+#define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */\r
+#define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */\r
+#define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */\r
+\r
+#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */\r
+#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */\r
+#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */\r
+#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */\r
+\r
+#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */\r
+#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */\r
+#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */\r
+#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */\r
+\r
+#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */\r
+#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */\r
+#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */\r
+#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */\r
+\r
+#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */\r
+#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */\r
+#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */\r
+#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */\r
+#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */\r
+#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */\r
+#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */\r
+#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */\r
+\r
+/* DMAIV Definitions */\r
+#define DMAIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/\r
+#define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/\r
+#define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/\r
+\r
+#endif\r
+/************************************************************\r
+* EXTENDED SCAN INTERFACE\r
+************************************************************/\r
+#ifdef __MSP430_HAS_ESI__ /* Definition to show that Module is available */\r
+\r
+#define OFS_ESIDEBUG1 (0x0000u) /* ESI debug register 1 */\r
+#define OFS_ESIDEBUG1_L OFS_ESIDEBUG1\r
+#define OFS_ESIDEBUG1_H OFS_ESIDEBUG1+1\r
+#define OFS_ESIDEBUG2 (0x0002u) /* ESI debug register 2 */\r
+#define OFS_ESIDEBUG2_L OFS_ESIDEBUG2\r
+#define OFS_ESIDEBUG2_H OFS_ESIDEBUG2+1\r
+#define OFS_ESIDEBUG3 (0x0004u) /* ESI debug register 3 */\r
+#define OFS_ESIDEBUG3_L OFS_ESIDEBUG3\r
+#define OFS_ESIDEBUG3_H OFS_ESIDEBUG3+1\r
+#define OFS_ESIDEBUG4 (0x0006u) /* ESI debug register 4 */\r
+#define OFS_ESIDEBUG4_L OFS_ESIDEBUG4\r
+#define OFS_ESIDEBUG4_H OFS_ESIDEBUG4+1\r
+#define OFS_ESIDEBUG5 (0x0008u) /* ESI debug register 5 */\r
+#define OFS_ESIDEBUG5_L OFS_ESIDEBUG5\r
+#define OFS_ESIDEBUG5_H OFS_ESIDEBUG5+1\r
+#define OFS_ESICNT0 (0x0010u) /* ESI PSM counter 0 */\r
+#define OFS_ESICNT0_L OFS_ESICNT0\r
+#define OFS_ESICNT0_H OFS_ESICNT0+1\r
+#define OFS_ESICNT1 (0x0012u) /* ESI PSM counter 1 */\r
+#define OFS_ESICNT1_L OFS_ESICNT1\r
+#define OFS_ESICNT1_H OFS_ESICNT1+1\r
+#define OFS_ESICNT2 (0x0014u) /* ESI PSM counter 2 */\r
+#define OFS_ESICNT2_L OFS_ESICNT2\r
+#define OFS_ESICNT2_H OFS_ESICNT2+1\r
+#define OFS_ESICNT3 (0x0016u) /* ESI oscillator counter register */\r
+#define OFS_ESICNT3_L OFS_ESICNT3\r
+#define OFS_ESICNT3_H OFS_ESICNT3+1\r
+#define OFS_ESIIV (0x001Au) /* ESI interrupt vector */\r
+#define OFS_ESIIV_L OFS_ESIIV\r
+#define OFS_ESIIV_H OFS_ESIIV+1\r
+#define OFS_ESIINT1 (0x001Cu) /* ESI interrupt register 1 */\r
+#define OFS_ESIINT1_L OFS_ESIINT1\r
+#define OFS_ESIINT1_H OFS_ESIINT1+1\r
+#define OFS_ESIINT2 (0x001Eu) /* ESI interrupt register 2 */\r
+#define OFS_ESIINT2_L OFS_ESIINT2\r
+#define OFS_ESIINT2_H OFS_ESIINT2+1\r
+#define OFS_ESIAFE (0x0020u) /* ESI AFE control register */\r
+#define OFS_ESIAFE_L OFS_ESIAFE\r
+#define OFS_ESIAFE_H OFS_ESIAFE+1\r
+#define OFS_ESIPPU (0x0022u) /* ESI PPU control register */\r
+#define OFS_ESIPPU_L OFS_ESIPPU\r
+#define OFS_ESIPPU_H OFS_ESIPPU+1\r
+#define OFS_ESITSM (0x0024u) /* ESI TSM control register */\r
+#define OFS_ESITSM_L OFS_ESITSM\r
+#define OFS_ESITSM_H OFS_ESITSM+1\r
+#define OFS_ESIPSM (0x0026u) /* ESI PSM control register */\r
+#define OFS_ESIPSM_L OFS_ESIPSM\r
+#define OFS_ESIPSM_H OFS_ESIPSM+1\r
+#define OFS_ESIOSC (0x0028u) /* ESI oscillator control register*/\r
+#define OFS_ESIOSC_L OFS_ESIOSC\r
+#define OFS_ESIOSC_H OFS_ESIOSC+1\r
+#define OFS_ESICTL (0x002Au) /* ESI control register */\r
+#define OFS_ESICTL_L OFS_ESICTL\r
+#define OFS_ESICTL_H OFS_ESICTL+1\r
+#define OFS_ESITHR1 (0x002Cu) /* ESI PSM Counter Threshold 1 register */\r
+#define OFS_ESITHR1_L OFS_ESITHR1\r
+#define OFS_ESITHR1_H OFS_ESITHR1+1\r
+#define OFS_ESITHR2 (0x002Eu) /* ESI PSM Counter Threshold 2 register */\r
+#define OFS_ESITHR2_L OFS_ESITHR2\r
+#define OFS_ESITHR2_H OFS_ESITHR2+1\r
+#define OFS_ESIDAC1R0 (0x0040u) /* ESI DAC1 register 0 */\r
+#define OFS_ESIDAC1R0_L OFS_ESIDAC1R0\r
+#define OFS_ESIDAC1R0_H OFS_ESIDAC1R0+1\r
+#define OFS_ESIDAC1R1 (0x0042u) /* ESI DAC1 register 1 */\r
+#define OFS_ESIDAC1R1_L OFS_ESIDAC1R1\r
+#define OFS_ESIDAC1R1_H OFS_ESIDAC1R1+1\r
+#define OFS_ESIDAC1R2 (0x0044u) /* ESI DAC1 register 2 */\r
+#define OFS_ESIDAC1R2_L OFS_ESIDAC1R2\r
+#define OFS_ESIDAC1R2_H OFS_ESIDAC1R2+1\r
+#define OFS_ESIDAC1R3 (0x0046u) /* ESI DAC1 register 3 */\r
+#define OFS_ESIDAC1R3_L OFS_ESIDAC1R3\r
+#define OFS_ESIDAC1R3_H OFS_ESIDAC1R3+1\r
+#define OFS_ESIDAC1R4 (0x0048u) /* ESI DAC1 register 4 */\r
+#define OFS_ESIDAC1R4_L OFS_ESIDAC1R4\r
+#define OFS_ESIDAC1R4_H OFS_ESIDAC1R4+1\r
+#define OFS_ESIDAC1R5 (0x004Au) /* ESI DAC1 register 5 */\r
+#define OFS_ESIDAC1R5_L OFS_ESIDAC1R5\r
+#define OFS_ESIDAC1R5_H OFS_ESIDAC1R5+1\r
+#define OFS_ESIDAC1R6 (0x004Cu) /* ESI DAC1 register 6 */\r
+#define OFS_ESIDAC1R6_L OFS_ESIDAC1R6\r
+#define OFS_ESIDAC1R6_H OFS_ESIDAC1R6+1\r
+#define OFS_ESIDAC1R7 (0x004Eu) /* ESI DAC1 register 7 */\r
+#define OFS_ESIDAC1R7_L OFS_ESIDAC1R7\r
+#define OFS_ESIDAC1R7_H OFS_ESIDAC1R7+1\r
+#define OFS_ESIDAC2R0 (0x0050u) /* ESI DAC2 register 0 */\r
+#define OFS_ESIDAC2R0_L OFS_ESIDAC2R0\r
+#define OFS_ESIDAC2R0_H OFS_ESIDAC2R0+1\r
+#define OFS_ESIDAC2R1 (0x0052u) /* ESI DAC2 register 1 */\r
+#define OFS_ESIDAC2R1_L OFS_ESIDAC2R1\r
+#define OFS_ESIDAC2R1_H OFS_ESIDAC2R1+1\r
+#define OFS_ESIDAC2R2 (0x0054u) /* ESI DAC2 register 2 */\r
+#define OFS_ESIDAC2R2_L OFS_ESIDAC2R2\r
+#define OFS_ESIDAC2R2_H OFS_ESIDAC2R2+1\r
+#define OFS_ESIDAC2R3 (0x0056u) /* ESI DAC2 register 3 */\r
+#define OFS_ESIDAC2R3_L OFS_ESIDAC2R3\r
+#define OFS_ESIDAC2R3_H OFS_ESIDAC2R3+1\r
+#define OFS_ESIDAC2R4 (0x0058u) /* ESI DAC2 register 4 */\r
+#define OFS_ESIDAC2R4_L OFS_ESIDAC2R4\r
+#define OFS_ESIDAC2R4_H OFS_ESIDAC2R4+1\r
+#define OFS_ESIDAC2R5 (0x005Au) /* ESI DAC2 register 5 */\r
+#define OFS_ESIDAC2R5_L OFS_ESIDAC2R5\r
+#define OFS_ESIDAC2R5_H OFS_ESIDAC2R5+1\r
+#define OFS_ESIDAC2R6 (0x005Cu) /* ESI DAC2 register 6 */\r
+#define OFS_ESIDAC2R6_L OFS_ESIDAC2R6\r
+#define OFS_ESIDAC2R6_H OFS_ESIDAC2R6+1\r
+#define OFS_ESIDAC2R7 (0x005Eu) /* ESI DAC2 register 7 */\r
+#define OFS_ESIDAC2R7_L OFS_ESIDAC2R7\r
+#define OFS_ESIDAC2R7_H OFS_ESIDAC2R7+1\r
+#define OFS_ESITSM0 (0x0060u) /* ESI TSM 0 */\r
+#define OFS_ESITSM0_L OFS_ESITSM0\r
+#define OFS_ESITSM0_H OFS_ESITSM0+1\r
+#define OFS_ESITSM1 (0x0062u) /* ESI TSM 1 */\r
+#define OFS_ESITSM1_L OFS_ESITSM1\r
+#define OFS_ESITSM1_H OFS_ESITSM1+1\r
+#define OFS_ESITSM2 (0x0064u) /* ESI TSM 2 */\r
+#define OFS_ESITSM2_L OFS_ESITSM2\r
+#define OFS_ESITSM2_H OFS_ESITSM2+1\r
+#define OFS_ESITSM3 (0x0066u) /* ESI TSM 3 */\r
+#define OFS_ESITSM3_L OFS_ESITSM3\r
+#define OFS_ESITSM3_H OFS_ESITSM3+1\r
+#define OFS_ESITSM4 (0x0068u) /* ESI TSM 4 */\r
+#define OFS_ESITSM4_L OFS_ESITSM4\r
+#define OFS_ESITSM4_H OFS_ESITSM4+1\r
+#define OFS_ESITSM5 (0x006Au) /* ESI TSM 5 */\r
+#define OFS_ESITSM5_L OFS_ESITSM5\r
+#define OFS_ESITSM5_H OFS_ESITSM5+1\r
+#define OFS_ESITSM6 (0x006Cu) /* ESI TSM 6 */\r
+#define OFS_ESITSM6_L OFS_ESITSM6\r
+#define OFS_ESITSM6_H OFS_ESITSM6+1\r
+#define OFS_ESITSM7 (0x006Eu) /* ESI TSM 7 */\r
+#define OFS_ESITSM7_L OFS_ESITSM7\r
+#define OFS_ESITSM7_H OFS_ESITSM7+1\r
+#define OFS_ESITSM8 (0x0070u) /* ESI TSM 8 */\r
+#define OFS_ESITSM8_L OFS_ESITSM8\r
+#define OFS_ESITSM8_H OFS_ESITSM8+1\r
+#define OFS_ESITSM9 (0x0072u) /* ESI TSM 9 */\r
+#define OFS_ESITSM9_L OFS_ESITSM9\r
+#define OFS_ESITSM9_H OFS_ESITSM9+1\r
+#define OFS_ESITSM10 (0x0074u) /* ESI TSM 10 */\r
+#define OFS_ESITSM10_L OFS_ESITSM10\r
+#define OFS_ESITSM10_H OFS_ESITSM10+1\r
+#define OFS_ESITSM11 (0x0076u) /* ESI TSM 11 */\r
+#define OFS_ESITSM11_L OFS_ESITSM11\r
+#define OFS_ESITSM11_H OFS_ESITSM11+1\r
+#define OFS_ESITSM12 (0x0078u) /* ESI TSM 12 */\r
+#define OFS_ESITSM12_L OFS_ESITSM12\r
+#define OFS_ESITSM12_H OFS_ESITSM12+1\r
+#define OFS_ESITSM13 (0x007Au) /* ESI TSM 13 */\r
+#define OFS_ESITSM13_L OFS_ESITSM13\r
+#define OFS_ESITSM13_H OFS_ESITSM13+1\r
+#define OFS_ESITSM14 (0x007Cu) /* ESI TSM 14 */\r
+#define OFS_ESITSM14_L OFS_ESITSM14\r
+#define OFS_ESITSM14_H OFS_ESITSM14+1\r
+#define OFS_ESITSM15 (0x007Eu) /* ESI TSM 15 */\r
+#define OFS_ESITSM15_L OFS_ESITSM15\r
+#define OFS_ESITSM15_H OFS_ESITSM15+1\r
+#define OFS_ESITSM16 (0x0080u) /* ESI TSM 16 */\r
+#define OFS_ESITSM16_L OFS_ESITSM16\r
+#define OFS_ESITSM16_H OFS_ESITSM16+1\r
+#define OFS_ESITSM17 (0x0082u) /* ESI TSM 17 */\r
+#define OFS_ESITSM17_L OFS_ESITSM17\r
+#define OFS_ESITSM17_H OFS_ESITSM17+1\r
+#define OFS_ESITSM18 (0x0084u) /* ESI TSM 18 */\r
+#define OFS_ESITSM18_L OFS_ESITSM18\r
+#define OFS_ESITSM18_H OFS_ESITSM18+1\r
+#define OFS_ESITSM19 (0x0086u) /* ESI TSM 19 */\r
+#define OFS_ESITSM19_L OFS_ESITSM19\r
+#define OFS_ESITSM19_H OFS_ESITSM19+1\r
+#define OFS_ESITSM20 (0x0088u) /* ESI TSM 20 */\r
+#define OFS_ESITSM20_L OFS_ESITSM20\r
+#define OFS_ESITSM20_H OFS_ESITSM20+1\r
+#define OFS_ESITSM21 (0x008Au) /* ESI TSM 21 */\r
+#define OFS_ESITSM21_L OFS_ESITSM21\r
+#define OFS_ESITSM21_H OFS_ESITSM21+1\r
+#define OFS_ESITSM22 (0x008Cu) /* ESI TSM 22 */\r
+#define OFS_ESITSM22_L OFS_ESITSM22\r
+#define OFS_ESITSM22_H OFS_ESITSM22+1\r
+#define OFS_ESITSM23 (0x008Eu) /* ESI TSM 23 */\r
+#define OFS_ESITSM23_L OFS_ESITSM23\r
+#define OFS_ESITSM23_H OFS_ESITSM23+1\r
+#define OFS_ESITSM24 (0x0090u) /* ESI TSM 24 */\r
+#define OFS_ESITSM24_L OFS_ESITSM24\r
+#define OFS_ESITSM24_H OFS_ESITSM24+1\r
+#define OFS_ESITSM25 (0x0092u) /* ESI TSM 25 */\r
+#define OFS_ESITSM25_L OFS_ESITSM25\r
+#define OFS_ESITSM25_H OFS_ESITSM25+1\r
+#define OFS_ESITSM26 (0x0094u) /* ESI TSM 26 */\r
+#define OFS_ESITSM26_L OFS_ESITSM26\r
+#define OFS_ESITSM26_H OFS_ESITSM26+1\r
+#define OFS_ESITSM27 (0x0096u) /* ESI TSM 27 */\r
+#define OFS_ESITSM27_L OFS_ESITSM27\r
+#define OFS_ESITSM27_H OFS_ESITSM27+1\r
+#define OFS_ESITSM28 (0x0098u) /* ESI TSM 28 */\r
+#define OFS_ESITSM28_L OFS_ESITSM28\r
+#define OFS_ESITSM28_H OFS_ESITSM28+1\r
+#define OFS_ESITSM29 (0x009Au) /* ESI TSM 29 */\r
+#define OFS_ESITSM29_L OFS_ESITSM29\r
+#define OFS_ESITSM29_H OFS_ESITSM29+1\r
+#define OFS_ESITSM30 (0x009Cu) /* ESI TSM 30 */\r
+#define OFS_ESITSM30_L OFS_ESITSM30\r
+#define OFS_ESITSM30_H OFS_ESITSM30+1\r
+#define OFS_ESITSM31 (0x009Eu) /* ESI TSM 31 */\r
+#define OFS_ESITSM31_L OFS_ESITSM31\r
+#define OFS_ESITSM31_H OFS_ESITSM31+1\r
+\r
+/* ESIIV Control Bits */\r
+\r
+#define ESIIV_NONE (0x0000u) /* No ESI Interrupt Pending */\r
+#define ESIIV_ESIIFG1 (0x0002u) /* rising edge of the ESISTOP(tsm) */\r
+#define ESIIV_ESIIFG0 (0x0004u) /* ESIOUT0 to ESIOUT3 conditions selected by ESIIFGSETx bits */\r
+#define ESIIV_ESIIFG8 (0x0006u) /* ESIOUT4 to ESIOUT7 conditions selected by ESIIFGSET2x bits */\r
+#define ESIIV_ESIIFG3 (0x0008u) /* ESICNT1 counter conditions selected with the ESITHR1 and ESITHR2 registers */\r
+#define ESIIV_ESIIFG6 (0x000Au) /* PSM transitions to a state with a Q7 bit */\r
+#define ESIIV_ESIIFG5 (0x000Cu) /* PSM transitions to a state with a Q6 bit */\r
+#define ESIIV_ESIIFG4 (0x000Eu) /* ESICNT2 counter conditions selected with the ESIIS2x bits */\r
+#define ESIIV_ESIIFG7 (0x0010u) /* ESICNT0 counter conditions selected with the ESIIS0x bits */\r
+#define ESIIV_ESIIFG2 (0x0012u) /* start of a TSM sequence */\r
+\r
+/* ESIINT1 Control Bits */\r
+#define ESIIFGSET22 (0x8000u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET21 (0x4000u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET20 (0x2000u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET12 (0x1000u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET11 (0x0800u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET10 (0x0400u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIE8 (0x0100u) /* Interrupt enable */\r
+#define ESIIE7 (0x0080u) /* Interrupt enable */\r
+#define ESIIE6 (0x0040u) /* Interrupt enable */\r
+#define ESIIE5 (0x0020u) /* Interrupt enable */\r
+#define ESIIE4 (0x0010u) /* Interrupt enable */\r
+#define ESIIE3 (0x0008u) /* Interrupt enable */\r
+#define ESIIE2 (0x0004u) /* Interrupt enable */\r
+#define ESIIE1 (0x0002u) /* Interrupt enable */\r
+#define ESIIE0 (0x0001u) /* Interrupt enable */\r
+\r
+/* ESIINT1 Control Bits */\r
+#define ESIIE7_L (0x0080u) /* Interrupt enable */\r
+#define ESIIE6_L (0x0040u) /* Interrupt enable */\r
+#define ESIIE5_L (0x0020u) /* Interrupt enable */\r
+#define ESIIE4_L (0x0010u) /* Interrupt enable */\r
+#define ESIIE3_L (0x0008u) /* Interrupt enable */\r
+#define ESIIE2_L (0x0004u) /* Interrupt enable */\r
+#define ESIIE1_L (0x0002u) /* Interrupt enable */\r
+#define ESIIE0_L (0x0001u) /* Interrupt enable */\r
+\r
+/* ESIINT1 Control Bits */\r
+#define ESIIFGSET22_H (0x0080u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET21_H (0x0040u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET20_H (0x0020u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET12_H (0x0010u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET11_H (0x0008u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET10_H (0x0004u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIE8_H (0x0001u) /* Interrupt enable */\r
+\r
+#define ESIIFGSET2_0 (0x0000u) /* ESIIFG8 is set when ESIOUT4 is set */\r
+#define ESIIFGSET2_1 (0x2000u) /* ESIIFG8 is set when ESIOUT4 is reset */\r
+#define ESIIFGSET2_2 (0x4000u) /* ESIIFG8 is set when ESIOUT5 is set */\r
+#define ESIIFGSET2_3 (0x6000u) /* ESIIFG8 is set when ESIOUT5 is reset */\r
+#define ESIIFGSET2_4 (0x8000u) /* ESIIFG8 is set when ESIOUT6 is set */\r
+#define ESIIFGSET2_5 (0xA000u) /* ESIIFG8 is set when ESIOUT6 is reset */\r
+#define ESIIFGSET2_6 (0xC000u) /* ESIIFG8 is set when ESIOUT7 is set */\r
+#define ESIIFGSET2_7 (0xE000u) /* ESIIFG8 is set when ESIOUT7 is reset */\r
+#define ESIIFGSET1_0 (0x0000u) /* ESIIFG0 is set when ESIOUT0 is set */\r
+#define ESIIFGSET1_1 (0x0400u) /* ESIIFG0 is set when ESIOUT0 is reset */\r
+#define ESIIFGSET1_2 (0x0800u) /* ESIIFG0 is set when ESIOUT1 is set */\r
+#define ESIIFGSET1_3 (0x0C00u) /* ESIIFG0 is set when ESIOUT1 is reset */\r
+#define ESIIFGSET1_4 (0x1000u) /* ESIIFG0 is set when ESIOUT2 is set */\r
+#define ESIIFGSET1_5 (0x1400u) /* ESIIFG0 is set when ESIOUT2 is reset */\r
+#define ESIIFGSET1_6 (0x1800u) /* ESIIFG0 is set when ESIOUT3 is set */\r
+#define ESIIFGSET1_7 (0x1C00u) /* ESIIFG0 is set when ESIOUT3 is reset */\r
+\r
+/* ESIINT2 Control Bits */\r
+#define ESIIS21 (0x4000u) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS20 (0x2000u) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS01 (0x0800u) /* SIFIFG7 interrupt flag source */\r
+#define ESIIS00 (0x0400u) /* SIFIFG7 interrupt flag source */\r
+#define ESIIFG8 (0x0100u) /* ESIIFG8 interrupt pending */\r
+#define ESIIFG7 (0x0080u) /* ESIIFG7 interrupt pending */\r
+#define ESIIFG6 (0x0040u) /* ESIIFG6 interrupt pending */\r
+#define ESIIFG5 (0x0020u) /* ESIIFG5 interrupt pending */\r
+#define ESIIFG4 (0x0010u) /* ESIIFG4 interrupt pending */\r
+#define ESIIFG3 (0x0008u) /* ESIIFG3 interrupt pending */\r
+#define ESIIFG2 (0x0004u) /* ESIIFG2 interrupt pending */\r
+#define ESIIFG1 (0x0002u) /* ESIIFG1 interrupt pending */\r
+#define ESIIFG0 (0x0001u) /* ESIIFG0 interrupt pending */\r
+\r
+/* ESIINT2 Control Bits */\r
+#define ESIIFG7_L (0x0080u) /* ESIIFG7 interrupt pending */\r
+#define ESIIFG6_L (0x0040u) /* ESIIFG6 interrupt pending */\r
+#define ESIIFG5_L (0x0020u) /* ESIIFG5 interrupt pending */\r
+#define ESIIFG4_L (0x0010u) /* ESIIFG4 interrupt pending */\r
+#define ESIIFG3_L (0x0008u) /* ESIIFG3 interrupt pending */\r
+#define ESIIFG2_L (0x0004u) /* ESIIFG2 interrupt pending */\r
+#define ESIIFG1_L (0x0002u) /* ESIIFG1 interrupt pending */\r
+#define ESIIFG0_L (0x0001u) /* ESIIFG0 interrupt pending */\r
+\r
+/* ESIINT2 Control Bits */\r
+#define ESIIS21_H (0x0040u) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS20_H (0x0020u) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS01_H (0x0008u) /* SIFIFG7 interrupt flag source */\r
+#define ESIIS00_H (0x0004u) /* SIFIFG7 interrupt flag source */\r
+#define ESIIFG8_H (0x0001u) /* ESIIFG8 interrupt pending */\r
+\r
+#define ESIIS2_0 (0x0000u) /* SIFIFG4 interrupt flag source: SIFCNT2 */\r
+#define ESIIS2_1 (0x2000u) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 4 */\r
+#define ESIIS2_2 (0x4000u) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 256 */\r
+#define ESIIS2_3 (0x6000u) /* SIFIFG4 interrupt flag source: SIFCNT2 decrements from 01h to 00h */\r
+#define ESIIS0_0 (0x0000u) /* SIFIFG7 interrupt flag source: SIFCNT0 */\r
+#define ESIIS0_1 (0x0400u) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 4 */\r
+#define ESIIS0_2 (0x0800u) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 256 */\r
+#define ESIIS0_3 (0x0C00u) /* SIFIFG7 interrupt flag source: SIFCNT0 increments from FFFFh to 00h */\r
+\r
+/* ESIAFE Control Bits */\r
+#define ESIDAC2EN (0x0800u) /* Enable ESIDAC(tsm) control for DAC in AFE2 */\r
+#define ESICA2EN (0x0400u) /* Enable ESICA(tsm) control for comparator in AFE2 */\r
+#define ESICA2INV (0x0200u) /* Invert AFE2's comparator output */\r
+#define ESICA1INV (0x0100u) /* Invert AFE1's comparator output */\r
+#define ESICA2X (0x0080u) /* AFE2's comparator input select */\r
+#define ESICA1X (0x0040u) /* AFE1's comparator input select */\r
+#define ESICISEL (0x0020u) /* Comparator input select for AFE1 only */\r
+#define ESICACI3 (0x0010u) /* Comparator input select for AFE1 only */\r
+#define ESIVSS (0x0008u) /* Sample-and-hold ESIVSS select */\r
+#define ESIVCC2 (0x0004u) /* Mid-voltage generator */\r
+#define ESISH (0x0002u) /* Sample-and-hold enable */\r
+#define ESITEN (0x0001u) /* Excitation enable */\r
+\r
+/* ESIAFE Control Bits */\r
+#define ESICA2X_L (0x0080u) /* AFE2's comparator input select */\r
+#define ESICA1X_L (0x0040u) /* AFE1's comparator input select */\r
+#define ESICISEL_L (0x0020u) /* Comparator input select for AFE1 only */\r
+#define ESICACI3_L (0x0010u) /* Comparator input select for AFE1 only */\r
+#define ESIVSS_L (0x0008u) /* Sample-and-hold ESIVSS select */\r
+#define ESIVCC2_L (0x0004u) /* Mid-voltage generator */\r
+#define ESISH_L (0x0002u) /* Sample-and-hold enable */\r
+#define ESITEN_L (0x0001u) /* Excitation enable */\r
+\r
+/* ESIAFE Control Bits */\r
+#define ESIDAC2EN_H (0x0008u) /* Enable ESIDAC(tsm) control for DAC in AFE2 */\r
+#define ESICA2EN_H (0x0004u) /* Enable ESICA(tsm) control for comparator in AFE2 */\r
+#define ESICA2INV_H (0x0002u) /* Invert AFE2's comparator output */\r
+#define ESICA1INV_H (0x0001u) /* Invert AFE1's comparator output */\r
+\r
+/* ESIPPU Control Bits */\r
+#define ESITCHOUT1 (0x0200u) /* Latched AFE1 comparator output for test channel 1 */\r
+#define ESITCHOUT0 (0x0100u) /* Lachted AFE1 comparator output for test channel 0 */\r
+#define ESIOUT7 (0x0080u) /* Latched AFE2 comparator output when ESICH3 input is selected */\r
+#define ESIOUT6 (0x0040u) /* Latched AFE2 comparator output when ESICH2 input is selected */\r
+#define ESIOUT5 (0x0020u) /* Latched AFE2 comparator output when ESICH1 input is selected */\r
+#define ESIOUT4 (0x0010u) /* Latched AFE2 comparator output when ESICH0 input is selected */\r
+#define ESIOUT3 (0x0008u) /* Latched AFE1 comparator output when ESICH3 input is selected */\r
+#define ESIOUT2 (0x0004u) /* Latched AFE1 comparator output when ESICH2 input is selected */\r
+#define ESIOUT1 (0x0002u) /* Latched AFE1 comparator output when ESICH1 input is selected */\r
+#define ESIOUT0 (0x0001u) /* Latched AFE1 comparator output when ESICH0 input is selected */\r
+\r
+/* ESIPPU Control Bits */\r
+#define ESIOUT7_L (0x0080u) /* Latched AFE2 comparator output when ESICH3 input is selected */\r
+#define ESIOUT6_L (0x0040u) /* Latched AFE2 comparator output when ESICH2 input is selected */\r
+#define ESIOUT5_L (0x0020u) /* Latched AFE2 comparator output when ESICH1 input is selected */\r
+#define ESIOUT4_L (0x0010u) /* Latched AFE2 comparator output when ESICH0 input is selected */\r
+#define ESIOUT3_L (0x0008u) /* Latched AFE1 comparator output when ESICH3 input is selected */\r
+#define ESIOUT2_L (0x0004u) /* Latched AFE1 comparator output when ESICH2 input is selected */\r
+#define ESIOUT1_L (0x0002u) /* Latched AFE1 comparator output when ESICH1 input is selected */\r
+#define ESIOUT0_L (0x0001u) /* Latched AFE1 comparator output when ESICH0 input is selected */\r
+\r
+/* ESIPPU Control Bits */\r
+#define ESITCHOUT1_H (0x0002u) /* Latched AFE1 comparator output for test channel 1 */\r
+#define ESITCHOUT0_H (0x0001u) /* Lachted AFE1 comparator output for test channel 0 */\r
+\r
+/* ESITSM Control Bits */\r
+#define ESICLKAZSEL (0x4000u) /* Functionality selection of ESITSMx bit5 */\r
+#define ESITSMTRG1 (0x2000u) /* TSM start trigger selection */\r
+#define ESITSMTRG0 (0x1000u) /* TSM start trigger selection */\r
+#define ESISTART (0x0800u) /* TSM software start trigger */\r
+#define ESITSMRP (0x0400u) /* TSM repeat modee */\r
+#define ESIDIV3B2 (0x0200u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B1 (0x0100u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B0 (0x0080u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A2 (0x0040u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A1 (0x0020u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A0 (0x0010u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV21 (0x0008u) /* ACLK divider */\r
+#define ESIDIV20 (0x0004u) /* ACLK divider */\r
+#define ESIDIV11 (0x0002u) /* TSM SMCLK divider */\r
+#define ESIDIV10 (0x0001u) /* TSM SMCLK divider */\r
+\r
+/* ESITSM Control Bits */\r
+#define ESIDIV3B0_L (0x0080u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A2_L (0x0040u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A1_L (0x0020u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A0_L (0x0010u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV21_L (0x0008u) /* ACLK divider */\r
+#define ESIDIV20_L (0x0004u) /* ACLK divider */\r
+#define ESIDIV11_L (0x0002u) /* TSM SMCLK divider */\r
+#define ESIDIV10_L (0x0001u) /* TSM SMCLK divider */\r
+\r
+/* ESITSM Control Bits */\r
+#define ESICLKAZSEL_H (0x0040u) /* Functionality selection of ESITSMx bit5 */\r
+#define ESITSMTRG1_H (0x0020u) /* TSM start trigger selection */\r
+#define ESITSMTRG0_H (0x0010u) /* TSM start trigger selection */\r
+#define ESISTART_H (0x0008u) /* TSM software start trigger */\r
+#define ESITSMRP_H (0x0004u) /* TSM repeat modee */\r
+#define ESIDIV3B2_H (0x0002u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B1_H (0x0001u) /* TSM start trigger ACLK divider */\r
+\r
+#define ESITSMTRG_0 (0x0000u) /* Halt mode */\r
+#define ESITSMTRG_1 (0x1000u) /* TSM start trigger ACLK divider */\r
+#define ESITSMTRG_2 (0x2000u) /* Software trigger for TSM */\r
+#define ESITSMTRG_3 (0x3000u) /* Either the ACLK divider or the ESISTART biT */\r
+#define ESIDIV3B_0 (0x0000u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_1 (0x0080u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_2 (0x0100u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_3 (0x0180u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_4 (0x0200u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_5 (0x0280u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_6 (0x0300u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_7 (0x0380u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_0 (0x0000u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_1 (0x0010u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_2 (0x0020u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_3 (0x0030u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_4 (0x0040u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_5 (0x0050u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_6 (0x0060u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_7 (0x0070u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV2_0 (0x0000u) /* ACLK divider mode: 0 */\r
+#define ESIDIV2_1 (0x0004u) /* ACLK divider mode: 1 */\r
+#define ESIDIV2_2 (0x0008u) /* ACLK divider mode: 2 */\r
+#define ESIDIV2_3 (0x000Cu) /* ACLK divider mode: 3 */\r
+#define ESIDIV2__1 (0x0000u) /* ACLK divider = /1 */\r
+#define ESIDIV2__2 (0x0004u) /* ACLK divider = /2 */\r
+#define ESIDIV2__4 (0x0008u) /* ACLK divider = /4 */\r
+#define ESIDIV2__8 (0x000Cu) /* ACLK divider = /8 */\r
+#define ESIDIV1_0 (0x0000u) /* TSM SMCLK/ESIOSC divider mode: 0 */\r
+#define ESIDIV1_1 (0x0001u) /* TSM SMCLK/ESIOSC divider mode: 1 */\r
+#define ESIDIV1_2 (0x0002u) /* TSM SMCLK/ESIOSC divider mode: 2 */\r
+#define ESIDIV1_3 (0x0003u) /* TSM SMCLK/ESIOSC divider mode: 3 */\r
+#define ESIDIV1__1 (0x0000u) /* TSM SMCLK/ESIOSC divider = /1 */\r
+#define ESIDIV1__2 (0x0001u) /* TSM SMCLK/ESIOSC divider = /2 */\r
+#define ESIDIV1__4 (0x0002u) /* TSM SMCLK/ESIOSC divider = /4 */\r
+#define ESIDIV1__8 (0x0003u) /* TSM SMCLK/ESIOSC divider = /8 */\r
+\r
+/* ESIPSM Control Bits */\r
+#define ESICNT2RST (0x8000u) /* ESI Counter 2 reset */\r
+#define ESICNT1RST (0x4000u) /* ESI Counter 1 reset */\r
+#define ESICNT0RST (0x2000u) /* ESI Counter 0 reset */\r
+#define ESITEST4SEL1 (0x0200u) /* Output signal selection for SIFTEST4 pin */\r
+#define ESITEST4SEL0 (0x0100u) /* Output signal selection for SIFTEST4 pin */\r
+#define ESIV2SEL (0x0080u) /* Source Selection for V2 bit*/\r
+#define ESICNT2EN (0x0020u) /* ESICNT2 enable (down counter) */\r
+#define ESICNT1EN (0x0010u) /* ESICNT1 enable (up/down counter) */\r
+#define ESICNT0EN (0x0008u) /* ESICNT0 enable (up counter) */\r
+#define ESIQ7TRG (0x0004u) /* Enabling to use Q7 as trigger for a TSM sequence */\r
+#define ESIQ6EN (0x0001u) /* Q6 enable */\r
+\r
+/* ESIPSM Control Bits */\r
+#define ESIV2SEL_L (0x0080u) /* Source Selection for V2 bit*/\r
+#define ESICNT2EN_L (0x0020u) /* ESICNT2 enable (down counter) */\r
+#define ESICNT1EN_L (0x0010u) /* ESICNT1 enable (up/down counter) */\r
+#define ESICNT0EN_L (0x0008u) /* ESICNT0 enable (up counter) */\r
+#define ESIQ7TRG_L (0x0004u) /* Enabling to use Q7 as trigger for a TSM sequence */\r
+#define ESIQ6EN_L (0x0001u) /* Q6 enable */\r
+\r
+/* ESIPSM Control Bits */\r
+#define ESICNT2RST_H (0x0080u) /* ESI Counter 2 reset */\r
+#define ESICNT1RST_H (0x0040u) /* ESI Counter 1 reset */\r
+#define ESICNT0RST_H (0x0020u) /* ESI Counter 0 reset */\r
+#define ESITEST4SEL1_H (0x0002u) /* Output signal selection for SIFTEST4 pin */\r
+#define ESITEST4SEL0_H (0x0001u) /* Output signal selection for SIFTEST4 pin */\r
+\r
+#define ESITEST4SEL_0 (0x0000u) /* Q1 signal from PSM table */\r
+#define ESITEST4SEL_1 (0x0100u) /* Q2 signal from PSM table */\r
+#define ESITEST4SEL_2 (0x0200u) /* TSM clock signal from Timing State Machine */\r
+#define ESITEST4SEL_3 (0x0300u) /* AFE1's comparator output signal Comp1Out */\r
+\r
+/* ESIOSC Control Bits */\r
+#define ESICLKFQ5 (0x2000u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ4 (0x1000u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ3 (0x0800u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ2 (0x0400u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ1 (0x0200u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ0 (0x0100u) /* Internal oscillator frequency adjust */\r
+#define ESICLKGON (0x0002u) /* Internal oscillator control */\r
+#define ESIHFSEL (0x0001u) /* Internal oscillator enable */\r
+\r
+/* ESIOSC Control Bits */\r
+#define ESICLKGON_L (0x0002u) /* Internal oscillator control */\r
+#define ESIHFSEL_L (0x0001u) /* Internal oscillator enable */\r
+\r
+/* ESIOSC Control Bits */\r
+#define ESICLKFQ5_H (0x0020u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ4_H (0x0010u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ3_H (0x0008u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ2_H (0x0004u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ1_H (0x0002u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ0_H (0x0001u) /* Internal oscillator frequency adjust */\r
+\r
+/* ESICTL Control Bits */\r
+#define ESIS3SEL2 (0x8000u) /* PPUS3 source select */\r
+#define ESIS3SEL1 (0x4000u) /* PPUS3 source select */\r
+#define ESIS3SEL0 (0x2000u) /* PPUS3 source select */\r
+#define ESIS2SEL2 (0x1000u) /* PPUS2 source select */\r
+#define ESIS2SEL1 (0x0800u) /* PPUS2 source select */\r
+#define ESIS2SEL0 (0x0400u) /* PPUS2 source select */\r
+#define ESIS1SEL2 (0x0200u) /* PPUS1 source select */\r
+#define ESIS1SEL1 (0x0100u) /* PPUS1 source select */\r
+#define ESIS1SEL0 (0x0080u) /* PPUS1 source select */\r
+#define ESITCH11 (0x0040u) /* select the comparator input for test channel 1 */\r
+#define ESITCH10 (0x0020u) /* select the comparator input for test channel 1 */\r
+#define ESITCH01 (0x0010u) /* select the comparator input for test channel 0 */\r
+#define ESITCH00 (0x0008u) /* select the comparator input for test channel 0 */\r
+#define ESICS (0x0004u) /* Comparator output/Timer_A input selection */\r
+#define ESITESTD (0x0002u) /* Test cycle insertion */\r
+#define ESIEN (0x0001u) /* Extended Scan interface enable */\r
+\r
+/* ESICTL Control Bits */\r
+#define ESIS1SEL0_L (0x0080u) /* PPUS1 source select */\r
+#define ESITCH11_L (0x0040u) /* select the comparator input for test channel 1 */\r
+#define ESITCH10_L (0x0020u) /* select the comparator input for test channel 1 */\r
+#define ESITCH01_L (0x0010u) /* select the comparator input for test channel 0 */\r
+#define ESITCH00_L (0x0008u) /* select the comparator input for test channel 0 */\r
+#define ESICS_L (0x0004u) /* Comparator output/Timer_A input selection */\r
+#define ESITESTD_L (0x0002u) /* Test cycle insertion */\r
+#define ESIEN_L (0x0001u) /* Extended Scan interface enable */\r
+\r
+/* ESICTL Control Bits */\r
+#define ESIS3SEL2_H (0x0080u) /* PPUS3 source select */\r
+#define ESIS3SEL1_H (0x0040u) /* PPUS3 source select */\r
+#define ESIS3SEL0_H (0x0020u) /* PPUS3 source select */\r
+#define ESIS2SEL2_H (0x0010u) /* PPUS2 source select */\r
+#define ESIS2SEL1_H (0x0008u) /* PPUS2 source select */\r
+#define ESIS2SEL0_H (0x0004u) /* PPUS2 source select */\r
+#define ESIS1SEL2_H (0x0002u) /* PPUS1 source select */\r
+#define ESIS1SEL1_H (0x0001u) /* PPUS1 source select */\r
+\r
+#define ESIS3SEL_0 (0x0000u) /* ESIOUT0 is the PPUS3 source */\r
+#define ESIS3SEL_1 (0x2000u) /* ESIOUT1 is the PPUS3 source */\r
+#define ESIS3SEL_2 (0x4000u) /* ESIOUT2 is the PPUS3 source */\r
+#define ESIS3SEL_3 (0x6000u) /* ESIOUT3 is the PPUS3 source */\r
+#define ESIS3SEL_4 (0x8000u) /* ESIOUT4 is the PPUS3 source */\r
+#define ESIS3SEL_5 (0xA000u) /* ESIOUT5 is the PPUS3 source */\r
+#define ESIS3SEL_6 (0xC000u) /* ESIOUT6 is the PPUS3 source */\r
+#define ESIS3SEL_7 (0xE000u) /* ESIOUT7 is the PPUS3 source */\r
+#define ESIS2SEL_0 (0x0000u) /* ESIOUT0 is the PPUS2 source */\r
+#define ESIS2SEL_1 (0x0400u) /* ESIOUT1 is the PPUS2 source */\r
+#define ESIS2SEL_2 (0x0800u) /* ESIOUT2 is the PPUS2 source */\r
+#define ESIS2SEL_3 (0x0C00u) /* ESIOUT3 is the PPUS2 source */\r
+#define ESIS2SEL_4 (0x1000u) /* ESIOUT4 is the PPUS2 source */\r
+#define ESIS2SEL_5 (0x1400u) /* ESIOUT5 is the PPUS2 source */\r
+#define ESIS2SEL_6 (0x1800u) /* ESIOUT6 is the PPUS2 source */\r
+#define ESIS2SEL_7 (0x1C00u) /* ESIOUT7 is the PPUS2 source */\r
+#define ESIS1SEL_0 (0x0000u) /* ESIOUT0 is the PPUS1 source */\r
+#define ESIS1SEL_1 (0x0080u) /* ESIOUT1 is the PPUS1 source */\r
+#define ESIS1SEL_2 (0x0100u) /* ESIOUT2 is the PPUS1 source */\r
+#define ESIS1SEL_3 (0x0180u) /* ESIOUT3 is the PPUS1 source */\r
+#define ESIS1SEL_4 (0x0200u) /* ESIOUT4 is the PPUS1 source */\r
+#define ESIS1SEL_5 (0x0280u) /* ESIOUT5 is the PPUS1 source */\r
+#define ESIS1SEL_6 (0x0300u) /* ESIOUT6 is the PPUS1 source */\r
+#define ESIS1SEL_7 (0x0380u) /* ESIOUT7 is the PPUS1 source */\r
+#define ESITCH1_0 (0x0000u) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */\r
+#define ESITCH1_1 (0x0400u) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */\r
+#define ESITCH1_2 (0x0800u) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */\r
+#define ESITCH1_3 (0x0C00u) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */\r
+#define ESITCH0_0 (0x0000u) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */\r
+#define ESITCH0_1 (0x0008u) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */\r
+#define ESITCH0_2 (0x0010u) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */\r
+#define ESITCH0_3 (0x0018u) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */\r
+\r
+/* Timing State Machine Control Bits */\r
+#define ESIREPEAT4 (0x8000u) /* These bits together with the ESICLK bit configure the duration of this state */\r
+#define ESIREPEAT3 (0x4000u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */\r
+#define ESIREPEAT2 (0x2000u) /* */\r
+#define ESIREPEAT1 (0x1000u) /* */\r
+#define ESIREPEAT0 (0x0800u) /* */\r
+#define ESICLK (0x0400u) /* This bit selects the clock source for the TSM */\r
+#define ESISTOP (0x0200u) /* This bit indicates the end of the TSM sequence */\r
+#define ESIDAC (0x0100u) /* TSM DAC on */\r
+#define ESITESTS1 (0x0080u) /* TSM test cycle control */\r
+#define ESIRSON (0x0040u) /* Internal output latches enabled */\r
+#define ESICLKON (0x0020u) /* High-frequency clock on */\r
+#define ESICA (0x0010u) /* TSM comparator on */\r
+#define ESIEX (0x0008u) /* Excitation and sample-and-hold */\r
+#define ESILCEN (0x0004u) /* LC enable */\r
+#define ESICH1 (0x0002u) /* Input channel select */\r
+#define ESICH0 (0x0001u) /* Input channel select */\r
+\r
+/* Timing State Machine Control Bits */\r
+#define ESITESTS1_L (0x0080u) /* TSM test cycle control */\r
+#define ESIRSON_L (0x0040u) /* Internal output latches enabled */\r
+#define ESICLKON_L (0x0020u) /* High-frequency clock on */\r
+#define ESICA_L (0x0010u) /* TSM comparator on */\r
+#define ESIEX_L (0x0008u) /* Excitation and sample-and-hold */\r
+#define ESILCEN_L (0x0004u) /* LC enable */\r
+#define ESICH1_L (0x0002u) /* Input channel select */\r
+#define ESICH0_L (0x0001u) /* Input channel select */\r
+\r
+/* Timing State Machine Control Bits */\r
+#define ESIREPEAT4_H (0x0080u) /* These bits together with the ESICLK bit configure the duration of this state */\r
+#define ESIREPEAT3_H (0x0040u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */\r
+#define ESIREPEAT2_H (0x0020u) /* */\r
+#define ESIREPEAT1_H (0x0010u) /* */\r
+#define ESIREPEAT0_H (0x0008u) /* */\r
+#define ESICLK_H (0x0004u) /* This bit selects the clock source for the TSM */\r
+#define ESISTOP_H (0x0002u) /* This bit indicates the end of the TSM sequence */\r
+#define ESIDAC_H (0x0001u) /* TSM DAC on */\r
+\r
+#define ESICAAZ (0x0020u) /* Comparator Offset calibration annulation */\r
+\r
+#define ESIREPEAT_0 (0x0000u) /* These bits configure the duration of this state */\r
+#define ESIREPEAT_1 (0x0800u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */\r
+#define ESIREPEAT_2 (0x1000u)\r
+#define ESIREPEAT_3 (0x1800u)\r
+#define ESIREPEAT_4 (0x2000u)\r
+#define ESIREPEAT_5 (0x2800u)\r
+#define ESIREPEAT_6 (0x3000u)\r
+#define ESIREPEAT_7 (0x3800u)\r
+#define ESIREPEAT_8 (0x4000u)\r
+#define ESIREPEAT_9 (0x4800u)\r
+#define ESIREPEAT_10 (0x5000u)\r
+#define ESIREPEAT_11 (0x5800u)\r
+#define ESIREPEAT_12 (0x6000u)\r
+#define ESIREPEAT_13 (0x6800u)\r
+#define ESIREPEAT_14 (0x7000u)\r
+#define ESIREPEAT_15 (0x7800u)\r
+#define ESIREPEAT_16 (0x8000u)\r
+#define ESIREPEAT_17 (0x8800u)\r
+#define ESIREPEAT_18 (0x9000u)\r
+#define ESIREPEAT_19 (0x9800u)\r
+#define ESIREPEAT_20 (0xA000u)\r
+#define ESIREPEAT_21 (0xA800u)\r
+#define ESIREPEAT_22 (0xB000u)\r
+#define ESIREPEAT_23 (0xB800u)\r
+#define ESIREPEAT_24 (0xC000u)\r
+#define ESIREPEAT_25 (0xC800u)\r
+#define ESIREPEAT_26 (0xD000u)\r
+#define ESIREPEAT_27 (0xD800u)\r
+#define ESIREPEAT_28 (0xE000u)\r
+#define ESIREPEAT_29 (0xE800u)\r
+#define ESIREPEAT_30 (0xF000u)\r
+#define ESIREPEAT_31 (0xF800u)\r
+#define ESICH_0 (0x0000u) /* Input channel select: ESICH0 */\r
+#define ESICH_1 (0x0001u) /* Input channel select: ESICH1 */\r
+#define ESICH_2 (0x0002u) /* Input channel select: ESICH2 */\r
+#define ESICH_3 (0x0003u) /* Input channel select: ESICH3 */\r
+#endif\r
+/************************************************************\r
+* EXTENDED SCAN INTERFACE RAM\r
+************************************************************/\r
+#ifdef __MSP430_HAS_ESI_RAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_ESIRAM0 (0x0000u) /* ESI RAM 0 */\r
+#define OFS_ESIRAM1 (0x0001u) /* ESI RAM 1 */\r
+#define OFS_ESIRAM2 (0x0002u) /* ESI RAM 2 */\r
+#define OFS_ESIRAM3 (0x0003u) /* ESI RAM 3 */\r
+#define OFS_ESIRAM4 (0x0004u) /* ESI RAM 4 */\r
+#define OFS_ESIRAM5 (0x0005u) /* ESI RAM 5 */\r
+#define OFS_ESIRAM6 (0x0006u) /* ESI RAM 6 */\r
+#define OFS_ESIRAM7 (0x0007u) /* ESI RAM 7 */\r
+#define OFS_ESIRAM8 (0x0008u) /* ESI RAM 8 */\r
+#define OFS_ESIRAM9 (0x0009u) /* ESI RAM 9 */\r
+#define OFS_ESIRAM10 (0x000Au) /* ESI RAM 10 */\r
+#define OFS_ESIRAM11 (0x000Bu) /* ESI RAM 11 */\r
+#define OFS_ESIRAM12 (0x000Cu) /* ESI RAM 12 */\r
+#define OFS_ESIRAM13 (0x000Du) /* ESI RAM 13 */\r
+#define OFS_ESIRAM14 (0x000Eu) /* ESI RAM 14 */\r
+#define OFS_ESIRAM15 (0x000Fu) /* ESI RAM 15 */\r
+#define OFS_ESIRAM16 (0x0010u) /* ESI RAM 16 */\r
+#define OFS_ESIRAM17 (0x0011u) /* ESI RAM 17 */\r
+#define OFS_ESIRAM18 (0x0012u) /* ESI RAM 18 */\r
+#define OFS_ESIRAM19 (0x0013u) /* ESI RAM 19 */\r
+#define OFS_ESIRAM20 (0x0014u) /* ESI RAM 20 */\r
+#define OFS_ESIRAM21 (0x0015u) /* ESI RAM 21 */\r
+#define OFS_ESIRAM22 (0x0016u) /* ESI RAM 22 */\r
+#define OFS_ESIRAM23 (0x0017u) /* ESI RAM 23 */\r
+#define OFS_ESIRAM24 (0x0018u) /* ESI RAM 24 */\r
+#define OFS_ESIRAM25 (0x0019u) /* ESI RAM 25 */\r
+#define OFS_ESIRAM26 (0x001Au) /* ESI RAM 26 */\r
+#define OFS_ESIRAM27 (0x001Bu) /* ESI RAM 27 */\r
+#define OFS_ESIRAM28 (0x001Cu) /* ESI RAM 28 */\r
+#define OFS_ESIRAM29 (0x001Du) /* ESI RAM 29 */\r
+#define OFS_ESIRAM30 (0x001Eu) /* ESI RAM 30 */\r
+#define OFS_ESIRAM31 (0x001Fu) /* ESI RAM 31 */\r
+#define OFS_ESIRAM32 (0x0020u) /* ESI RAM 32 */\r
+#define OFS_ESIRAM33 (0x0021u) /* ESI RAM 33 */\r
+#define OFS_ESIRAM34 (0x0022u) /* ESI RAM 34 */\r
+#define OFS_ESIRAM35 (0x0023u) /* ESI RAM 35 */\r
+#define OFS_ESIRAM36 (0x0024u) /* ESI RAM 36 */\r
+#define OFS_ESIRAM37 (0x0025u) /* ESI RAM 37 */\r
+#define OFS_ESIRAM38 (0x0026u) /* ESI RAM 38 */\r
+#define OFS_ESIRAM39 (0x0027u) /* ESI RAM 39 */\r
+#define OFS_ESIRAM40 (0x0028u) /* ESI RAM 40 */\r
+#define OFS_ESIRAM41 (0x0029u) /* ESI RAM 41 */\r
+#define OFS_ESIRAM42 (0x002Au) /* ESI RAM 42 */\r
+#define OFS_ESIRAM43 (0x002Bu) /* ESI RAM 43 */\r
+#define OFS_ESIRAM44 (0x002Cu) /* ESI RAM 44 */\r
+#define OFS_ESIRAM45 (0x002Du) /* ESI RAM 45 */\r
+#define OFS_ESIRAM46 (0x002Eu) /* ESI RAM 46 */\r
+#define OFS_ESIRAM47 (0x002Fu) /* ESI RAM 47 */\r
+#define OFS_ESIRAM48 (0x0030u) /* ESI RAM 48 */\r
+#define OFS_ESIRAM49 (0x0031u) /* ESI RAM 49 */\r
+#define OFS_ESIRAM50 (0x0032u) /* ESI RAM 50 */\r
+#define OFS_ESIRAM51 (0x0033u) /* ESI RAM 51 */\r
+#define OFS_ESIRAM52 (0x0034u) /* ESI RAM 52 */\r
+#define OFS_ESIRAM53 (0x0035u) /* ESI RAM 53 */\r
+#define OFS_ESIRAM54 (0x0036u) /* ESI RAM 54 */\r
+#define OFS_ESIRAM55 (0x0037u) /* ESI RAM 55 */\r
+#define OFS_ESIRAM56 (0x0038u) /* ESI RAM 56 */\r
+#define OFS_ESIRAM57 (0x0039u) /* ESI RAM 57 */\r
+#define OFS_ESIRAM58 (0x003Au) /* ESI RAM 58 */\r
+#define OFS_ESIRAM59 (0x003Bu) /* ESI RAM 59 */\r
+#define OFS_ESIRAM60 (0x003Cu) /* ESI RAM 60 */\r
+#define OFS_ESIRAM61 (0x003Du) /* ESI RAM 61 */\r
+#define OFS_ESIRAM62 (0x003Eu) /* ESI RAM 62 */\r
+#define OFS_ESIRAM63 (0x003Fu) /* ESI RAM 63 */\r
+#define OFS_ESIRAM64 (0x0040u) /* ESI RAM 64 */\r
+#define OFS_ESIRAM65 (0x0041u) /* ESI RAM 65 */\r
+#define OFS_ESIRAM66 (0x0042u) /* ESI RAM 66 */\r
+#define OFS_ESIRAM67 (0x0043u) /* ESI RAM 67 */\r
+#define OFS_ESIRAM68 (0x0044u) /* ESI RAM 68 */\r
+#define OFS_ESIRAM69 (0x0045u) /* ESI RAM 69 */\r
+#define OFS_ESIRAM70 (0x0046u) /* ESI RAM 70 */\r
+#define OFS_ESIRAM71 (0x0047u) /* ESI RAM 71 */\r
+#define OFS_ESIRAM72 (0x0048u) /* ESI RAM 72 */\r
+#define OFS_ESIRAM73 (0x0049u) /* ESI RAM 73 */\r
+#define OFS_ESIRAM74 (0x004Au) /* ESI RAM 74 */\r
+#define OFS_ESIRAM75 (0x004Bu) /* ESI RAM 75 */\r
+#define OFS_ESIRAM76 (0x004Cu) /* ESI RAM 76 */\r
+#define OFS_ESIRAM77 (0x004Du) /* ESI RAM 77 */\r
+#define OFS_ESIRAM78 (0x004Eu) /* ESI RAM 78 */\r
+#define OFS_ESIRAM79 (0x004Fu) /* ESI RAM 79 */\r
+#define OFS_ESIRAM80 (0x0050u) /* ESI RAM 80 */\r
+#define OFS_ESIRAM81 (0x0051u) /* ESI RAM 81 */\r
+#define OFS_ESIRAM82 (0x0052u) /* ESI RAM 82 */\r
+#define OFS_ESIRAM83 (0x0053u) /* ESI RAM 83 */\r
+#define OFS_ESIRAM84 (0x0054u) /* ESI RAM 84 */\r
+#define OFS_ESIRAM85 (0x0055u) /* ESI RAM 85 */\r
+#define OFS_ESIRAM86 (0x0056u) /* ESI RAM 86 */\r
+#define OFS_ESIRAM87 (0x0057u) /* ESI RAM 87 */\r
+#define OFS_ESIRAM88 (0x0058u) /* ESI RAM 88 */\r
+#define OFS_ESIRAM89 (0x0059u) /* ESI RAM 89 */\r
+#define OFS_ESIRAM90 (0x005Au) /* ESI RAM 90 */\r
+#define OFS_ESIRAM91 (0x005Bu) /* ESI RAM 91 */\r
+#define OFS_ESIRAM92 (0x005Cu) /* ESI RAM 92 */\r
+#define OFS_ESIRAM93 (0x005Du) /* ESI RAM 93 */\r
+#define OFS_ESIRAM94 (0x005Eu) /* ESI RAM 94 */\r
+#define OFS_ESIRAM95 (0x005Fu) /* ESI RAM 95 */\r
+#define OFS_ESIRAM96 (0x0060u) /* ESI RAM 96 */\r
+#define OFS_ESIRAM97 (0x0061u) /* ESI RAM 97 */\r
+#define OFS_ESIRAM98 (0x0062u) /* ESI RAM 98 */\r
+#define OFS_ESIRAM99 (0x0063u) /* ESI RAM 99 */\r
+#define OFS_ESIRAM100 (0x0064u) /* ESI RAM 100 */\r
+#define OFS_ESIRAM101 (0x0065u) /* ESI RAM 101 */\r
+#define OFS_ESIRAM102 (0x0066u) /* ESI RAM 102 */\r
+#define OFS_ESIRAM103 (0x0067u) /* ESI RAM 103 */\r
+#define OFS_ESIRAM104 (0x0068u) /* ESI RAM 104 */\r
+#define OFS_ESIRAM105 (0x0069u) /* ESI RAM 105 */\r
+#define OFS_ESIRAM106 (0x006Au) /* ESI RAM 106 */\r
+#define OFS_ESIRAM107 (0x006Bu) /* ESI RAM 107 */\r
+#define OFS_ESIRAM108 (0x006Cu) /* ESI RAM 108 */\r
+#define OFS_ESIRAM109 (0x006Du) /* ESI RAM 109 */\r
+#define OFS_ESIRAM110 (0x006Eu) /* ESI RAM 110 */\r
+#define OFS_ESIRAM111 (0x006Fu) /* ESI RAM 111 */\r
+#define OFS_ESIRAM112 (0x0070u) /* ESI RAM 112 */\r
+#define OFS_ESIRAM113 (0x0071u) /* ESI RAM 113 */\r
+#define OFS_ESIRAM114 (0x0072u) /* ESI RAM 114 */\r
+#define OFS_ESIRAM115 (0x0073u) /* ESI RAM 115 */\r
+#define OFS_ESIRAM116 (0x0074u) /* ESI RAM 116 */\r
+#define OFS_ESIRAM117 (0x0075u) /* ESI RAM 117 */\r
+#define OFS_ESIRAM118 (0x0076u) /* ESI RAM 118 */\r
+#define OFS_ESIRAM119 (0x0077u) /* ESI RAM 119 */\r
+#define OFS_ESIRAM120 (0x0078u) /* ESI RAM 120 */\r
+#define OFS_ESIRAM121 (0x0079u) /* ESI RAM 121 */\r
+#define OFS_ESIRAM122 (0x007Au) /* ESI RAM 122 */\r
+#define OFS_ESIRAM123 (0x007Bu) /* ESI RAM 123 */\r
+#define OFS_ESIRAM124 (0x007Cu) /* ESI RAM 124 */\r
+#define OFS_ESIRAM125 (0x007Du) /* ESI RAM 125 */\r
+#define OFS_ESIRAM126 (0x007Eu) /* ESI RAM 126 */\r
+#define OFS_ESIRAM127 (0x007Fu) /* ESI RAM 127 */\r
+#endif\r
+/*************************************************************\r
+* FRAM Memory\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_FRAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_FRCTL0 (0x0000u) /* FRAM Controller Control 0 */\r
+#define OFS_FRCTL0_L OFS_FRCTL0\r
+#define OFS_FRCTL0_H OFS_FRCTL0+1\r
+#define OFS_GCCTL0 (0x0004u) /* General Control 0 */\r
+#define OFS_GCCTL0_L OFS_GCCTL0\r
+#define OFS_GCCTL0_H OFS_GCCTL0+1\r
+#define OFS_GCCTL1 (0x0006u) /* General Control 1 */\r
+#define OFS_GCCTL1_L OFS_GCCTL1\r
+#define OFS_GCCTL1_H OFS_GCCTL1+1\r
+\r
+#define FRCTLPW (0xA500u) /* FRAM password for write */\r
+#define FRPW (0x9600u) /* FRAM password returned by read */\r
+#define FWPW (0xA500u) /* FRAM password for write */\r
+#define FXPW (0x3300u) /* for use with XOR instruction */\r
+\r
+/* FRCTL0 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+//#define RESERVED (0x0002u) /* RESERVED */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+#define NWAITS0 (0x0010u) /* FRAM Wait state control Bit: 0 */\r
+#define NWAITS1 (0x0020u) /* FRAM Wait state control Bit: 1 */\r
+#define NWAITS2 (0x0040u) /* FRAM Wait state control Bit: 2 */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+\r
+/* FRCTL0 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+//#define RESERVED (0x0002u) /* RESERVED */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+#define NWAITS0_L (0x0010u) /* FRAM Wait state control Bit: 0 */\r
+#define NWAITS1_L (0x0020u) /* FRAM Wait state control Bit: 1 */\r
+#define NWAITS2_L (0x0040u) /* FRAM Wait state control Bit: 2 */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+\r
+#define NWAITS_0 (0x0000u) /* FRAM Wait state control: 0 */\r
+#define NWAITS_1 (0x0010u) /* FRAM Wait state control: 1 */\r
+#define NWAITS_2 (0x0020u) /* FRAM Wait state control: 2 */\r
+#define NWAITS_3 (0x0030u) /* FRAM Wait state control: 3 */\r
+#define NWAITS_4 (0x0040u) /* FRAM Wait state control: 4 */\r
+#define NWAITS_5 (0x0050u) /* FRAM Wait state control: 5 */\r
+#define NWAITS_6 (0x0060u) /* FRAM Wait state control: 6 */\r
+#define NWAITS_7 (0x0070u) /* FRAM Wait state control: 7 */\r
+\r
+/* Legacy Defines */\r
+#define NAUTO (0x0008u) /* FRAM Disables the wait state generator (obsolete on Rev.E and later)*/\r
+#define NACCESS0 (0x0010u) /* FRAM Wait state Generator Access Time control Bit: 0 */\r
+#define NACCESS1 (0x0020u) /* FRAM Wait state Generator Access Time control Bit: 1 */\r
+#define NACCESS2 (0x0040u) /* FRAM Wait state Generator Access Time control Bit: 2 */\r
+#define NACCESS_0 (0x0000u) /* FRAM Wait state Generator Access Time control: 0 */\r
+#define NACCESS_1 (0x0010u) /* FRAM Wait state Generator Access Time control: 1 */\r
+#define NACCESS_2 (0x0020u) /* FRAM Wait state Generator Access Time control: 2 */\r
+#define NACCESS_3 (0x0030u) /* FRAM Wait state Generator Access Time control: 3 */\r
+#define NACCESS_4 (0x0040u) /* FRAM Wait state Generator Access Time control: 4 */\r
+#define NACCESS_5 (0x0050u) /* FRAM Wait state Generator Access Time control: 5 */\r
+#define NACCESS_6 (0x0060u) /* FRAM Wait state Generator Access Time control: 6 */\r
+#define NACCESS_7 (0x0070u) /* FRAM Wait state Generator Access Time control: 7 */\r
+\r
+/* GCCTL0 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+#define FRLPMPWR (0x0002u) /* FRAM Enable FRAM auto power up after LPM */\r
+#define FRPWR (0x0004u) /* FRAM Power Control */\r
+#define ACCTEIE (0x0008u) /* Enable NMI event if Access time error occurs */\r
+//#define RESERVED (0x0010u) /* RESERVED */\r
+#define CBDIE (0x0020u) /* Enable NMI event if correctable bit error detected */\r
+#define UBDIE (0x0040u) /* Enable NMI event if uncorrectable bit error detected */\r
+#define UBDRSTEN (0x0080u) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */\r
+\r
+/* GCCTL0 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+#define FRLPMPWR_L (0x0002u) /* FRAM Enable FRAM auto power up after LPM */\r
+#define FRPWR_L (0x0004u) /* FRAM Power Control */\r
+#define ACCTEIE_L (0x0008u) /* Enable NMI event if Access time error occurs */\r
+//#define RESERVED (0x0010u) /* RESERVED */\r
+#define CBDIE_L (0x0020u) /* Enable NMI event if correctable bit error detected */\r
+#define UBDIE_L (0x0040u) /* Enable NMI event if uncorrectable bit error detected */\r
+#define UBDRSTEN_L (0x0080u) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */\r
+\r
+/* GCCTL1 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+#define CBDIFG (0x0002u) /* FRAM correctable bit error flag */\r
+#define UBDIFG (0x0004u) /* FRAM uncorrectable bit error flag */\r
+#define ACCTEIFG (0x0008u) /* Access time error flag */\r
+\r
+/* GCCTL1 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+#define CBDIFG_L (0x0002u) /* FRAM correctable bit error flag */\r
+#define UBDIFG_L (0x0004u) /* FRAM uncorrectable bit error flag */\r
+#define ACCTEIFG_L (0x0008u) /* Access time error flag */\r
+\r
+#endif\r
+/************************************************************\r
+* LCD_C\r
+************************************************************/\r
+#ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */\r
+\r
+#define OFS_LCDCCTL0 (0x0000u) /* LCD_C Control Register 0 */\r
+#define OFS_LCDCCTL0_L OFS_LCDCCTL0\r
+#define OFS_LCDCCTL0_H OFS_LCDCCTL0+1\r
+#define OFS_LCDCCTL1 (0x0002u) /* LCD_C Control Register 1 */\r
+#define OFS_LCDCCTL1_L OFS_LCDCCTL1\r
+#define OFS_LCDCCTL1_H OFS_LCDCCTL1+1\r
+#define OFS_LCDCBLKCTL (0x0004u) /* LCD_C blinking control register */\r
+#define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL\r
+#define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1\r
+#define OFS_LCDCMEMCTL (0x0006u) /* LCD_C memory control register */\r
+#define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL\r
+#define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1\r
+#define OFS_LCDCVCTL (0x0008u) /* LCD_C Voltage Control Register */\r
+#define OFS_LCDCVCTL_L OFS_LCDCVCTL\r
+#define OFS_LCDCVCTL_H OFS_LCDCVCTL+1\r
+#define OFS_LCDCPCTL0 (0x000Au) /* LCD_C Port Control Register 0 */\r
+#define OFS_LCDCPCTL0_L OFS_LCDCPCTL0\r
+#define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1\r
+#define OFS_LCDCPCTL1 (0x000Cu) /* LCD_C Port Control Register 1 */\r
+#define OFS_LCDCPCTL1_L OFS_LCDCPCTL1\r
+#define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1\r
+#define OFS_LCDCPCTL2 (0x000Eu) /* LCD_C Port Control Register 2 */\r
+#define OFS_LCDCPCTL2_L OFS_LCDCPCTL2\r
+#define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1\r
+#define OFS_LCDCPCTL3 (0x0010u) /* LCD_C Port Control Register 3 */\r
+#define OFS_LCDCPCTL3_L OFS_LCDCPCTL3\r
+#define OFS_LCDCPCTL3_H OFS_LCDCPCTL3+1\r
+#define OFS_LCDCCPCTL (0x0012u) /* LCD_C Charge Pump Control Register 3 */\r
+#define OFS_LCDCCPCTL_L OFS_LCDCCPCTL\r
+#define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1\r
+#define OFS_LCDCIV (0x001Eu) /* LCD_C Interrupt Vector Register */\r
+\r
+// LCDCCTL0\r
+#define LCDON (0x0001u) /* LCD_C LCD On */\r
+#define LCDLP (0x0002u) /* LCD_C Low Power Waveform */\r
+#define LCDSON (0x0004u) /* LCD_C LCD Segments On */\r
+#define LCDMX0 (0x0008u) /* LCD_C Mux Rate Bit: 0 */\r
+#define LCDMX1 (0x0010u) /* LCD_C Mux Rate Bit: 1 */\r
+#define LCDMX2 (0x0020u) /* LCD_C Mux Rate Bit: 2 */\r
+//#define RESERVED (0x0040u) /* LCD_C RESERVED */\r
+#define LCDSSEL (0x0080u) /* LCD_C Clock Select */\r
+#define LCDPRE0 (0x0100u) /* LCD_C LCD frequency pre-scaler Bit: 0 */\r
+#define LCDPRE1 (0x0200u) /* LCD_C LCD frequency pre-scaler Bit: 1 */\r
+#define LCDPRE2 (0x0400u) /* LCD_C LCD frequency pre-scaler Bit: 2 */\r
+#define LCDDIV0 (0x0800u) /* LCD_C LCD frequency divider Bit: 0 */\r
+#define LCDDIV1 (0x1000u) /* LCD_C LCD frequency divider Bit: 1 */\r
+#define LCDDIV2 (0x2000u) /* LCD_C LCD frequency divider Bit: 2 */\r
+#define LCDDIV3 (0x4000u) /* LCD_C LCD frequency divider Bit: 3 */\r
+#define LCDDIV4 (0x8000u) /* LCD_C LCD frequency divider Bit: 4 */\r
+\r
+// LCDCCTL0\r
+#define LCDON_L (0x0001u) /* LCD_C LCD On */\r
+#define LCDLP_L (0x0002u) /* LCD_C Low Power Waveform */\r
+#define LCDSON_L (0x0004u) /* LCD_C LCD Segments On */\r
+#define LCDMX0_L (0x0008u) /* LCD_C Mux Rate Bit: 0 */\r
+#define LCDMX1_L (0x0010u) /* LCD_C Mux Rate Bit: 1 */\r
+#define LCDMX2_L (0x0020u) /* LCD_C Mux Rate Bit: 2 */\r
+//#define RESERVED (0x0040u) /* LCD_C RESERVED */\r
+#define LCDSSEL_L (0x0080u) /* LCD_C Clock Select */\r
+\r
+// LCDCCTL0\r
+//#define RESERVED (0x0040u) /* LCD_C RESERVED */\r
+#define LCDPRE0_H (0x0001u) /* LCD_C LCD frequency pre-scaler Bit: 0 */\r
+#define LCDPRE1_H (0x0002u) /* LCD_C LCD frequency pre-scaler Bit: 1 */\r
+#define LCDPRE2_H (0x0004u) /* LCD_C LCD frequency pre-scaler Bit: 2 */\r
+#define LCDDIV0_H (0x0008u) /* LCD_C LCD frequency divider Bit: 0 */\r
+#define LCDDIV1_H (0x0010u) /* LCD_C LCD frequency divider Bit: 1 */\r
+#define LCDDIV2_H (0x0020u) /* LCD_C LCD frequency divider Bit: 2 */\r
+#define LCDDIV3_H (0x0040u) /* LCD_C LCD frequency divider Bit: 3 */\r
+#define LCDDIV4_H (0x0080u) /* LCD_C LCD frequency divider Bit: 4 */\r
+\r
+#define LCDPRE_0 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */\r
+#define LCDPRE_1 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */\r
+#define LCDPRE_2 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */\r
+#define LCDPRE_3 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */\r
+#define LCDPRE_4 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */\r
+#define LCDPRE_5 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */\r
+#define LCDPRE__1 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */\r
+#define LCDPRE__2 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */\r
+#define LCDPRE__4 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */\r
+#define LCDPRE__8 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */\r
+#define LCDPRE__16 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */\r
+#define LCDPRE__32 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */\r
+\r
+#define LCDDIV_0 (0x0000u) /* LCD_C LCD frequency divider: /1 */\r
+#define LCDDIV_1 (0x0800u) /* LCD_C LCD frequency divider: /2 */\r
+#define LCDDIV_2 (0x1000u) /* LCD_C LCD frequency divider: /3 */\r
+#define LCDDIV_3 (0x1800u) /* LCD_C LCD frequency divider: /4 */\r
+#define LCDDIV_4 (0x2000u) /* LCD_C LCD frequency divider: /5 */\r
+#define LCDDIV_5 (0x2800u) /* LCD_C LCD frequency divider: /6 */\r
+#define LCDDIV_6 (0x3000u) /* LCD_C LCD frequency divider: /7 */\r
+#define LCDDIV_7 (0x3800u) /* LCD_C LCD frequency divider: /8 */\r
+#define LCDDIV_8 (0x4000u) /* LCD_C LCD frequency divider: /9 */\r
+#define LCDDIV_9 (0x4800u) /* LCD_C LCD frequency divider: /10 */\r
+#define LCDDIV_10 (0x5000u) /* LCD_C LCD frequency divider: /11 */\r
+#define LCDDIV_11 (0x5800u) /* LCD_C LCD frequency divider: /12 */\r
+#define LCDDIV_12 (0x6000u) /* LCD_C LCD frequency divider: /13 */\r
+#define LCDDIV_13 (0x6800u) /* LCD_C LCD frequency divider: /14 */\r
+#define LCDDIV_14 (0x7000u) /* LCD_C LCD frequency divider: /15 */\r
+#define LCDDIV_15 (0x7800u) /* LCD_C LCD frequency divider: /16 */\r
+#define LCDDIV_16 (0x8000u) /* LCD_C LCD frequency divider: /17 */\r
+#define LCDDIV_17 (0x8800u) /* LCD_C LCD frequency divider: /18 */\r
+#define LCDDIV_18 (0x9000u) /* LCD_C LCD frequency divider: /19 */\r
+#define LCDDIV_19 (0x9800u) /* LCD_C LCD frequency divider: /20 */\r
+#define LCDDIV_20 (0xA000u) /* LCD_C LCD frequency divider: /21 */\r
+#define LCDDIV_21 (0xA800u) /* LCD_C LCD frequency divider: /22 */\r
+#define LCDDIV_22 (0xB000u) /* LCD_C LCD frequency divider: /23 */\r
+#define LCDDIV_23 (0xB800u) /* LCD_C LCD frequency divider: /24 */\r
+#define LCDDIV_24 (0xC000u) /* LCD_C LCD frequency divider: /25 */\r
+#define LCDDIV_25 (0xC800u) /* LCD_C LCD frequency divider: /26 */\r
+#define LCDDIV_26 (0xD000u) /* LCD_C LCD frequency divider: /27 */\r
+#define LCDDIV_27 (0xD800u) /* LCD_C LCD frequency divider: /28 */\r
+#define LCDDIV_28 (0xE000u) /* LCD_C LCD frequency divider: /29 */\r
+#define LCDDIV_29 (0xE800u) /* LCD_C LCD frequency divider: /30 */\r
+#define LCDDIV_30 (0xF000u) /* LCD_C LCD frequency divider: /31 */\r
+#define LCDDIV_31 (0xF800u) /* LCD_C LCD frequency divider: /32 */\r
+#define LCDDIV__1 (0x0000u) /* LCD_C LCD frequency divider: /1 */\r
+#define LCDDIV__2 (0x0800u) /* LCD_C LCD frequency divider: /2 */\r
+#define LCDDIV__3 (0x1000u) /* LCD_C LCD frequency divider: /3 */\r
+#define LCDDIV__4 (0x1800u) /* LCD_C LCD frequency divider: /4 */\r
+#define LCDDIV__5 (0x2000u) /* LCD_C LCD frequency divider: /5 */\r
+#define LCDDIV__6 (0x2800u) /* LCD_C LCD frequency divider: /6 */\r
+#define LCDDIV__7 (0x3000u) /* LCD_C LCD frequency divider: /7 */\r
+#define LCDDIV__8 (0x3800u) /* LCD_C LCD frequency divider: /8 */\r
+#define LCDDIV__9 (0x4000u) /* LCD_C LCD frequency divider: /9 */\r
+#define LCDDIV__10 (0x4800u) /* LCD_C LCD frequency divider: /10 */\r
+#define LCDDIV__11 (0x5000u) /* LCD_C LCD frequency divider: /11 */\r
+#define LCDDIV__12 (0x5800u) /* LCD_C LCD frequency divider: /12 */\r
+#define LCDDIV__13 (0x6000u) /* LCD_C LCD frequency divider: /13 */\r
+#define LCDDIV__14 (0x6800u) /* LCD_C LCD frequency divider: /14 */\r
+#define LCDDIV__15 (0x7000u) /* LCD_C LCD frequency divider: /15 */\r
+#define LCDDIV__16 (0x7800u) /* LCD_C LCD frequency divider: /16 */\r
+#define LCDDIV__17 (0x8000u) /* LCD_C LCD frequency divider: /17 */\r
+#define LCDDIV__18 (0x8800u) /* LCD_C LCD frequency divider: /18 */\r
+#define LCDDIV__19 (0x9000u) /* LCD_C LCD frequency divider: /19 */\r
+#define LCDDIV__20 (0x9800u) /* LCD_C LCD frequency divider: /20 */\r
+#define LCDDIV__21 (0xA000u) /* LCD_C LCD frequency divider: /21 */\r
+#define LCDDIV__22 (0xA800u) /* LCD_C LCD frequency divider: /22 */\r
+#define LCDDIV__23 (0xB000u) /* LCD_C LCD frequency divider: /23 */\r
+#define LCDDIV__24 (0xB800u) /* LCD_C LCD frequency divider: /24 */\r
+#define LCDDIV__25 (0xC000u) /* LCD_C LCD frequency divider: /25 */\r
+#define LCDDIV__26 (0xC800u) /* LCD_C LCD frequency divider: /26 */\r
+#define LCDDIV__27 (0xD000u) /* LCD_C LCD frequency divider: /27 */\r
+#define LCDDIV__28 (0xD800u) /* LCD_C LCD frequency divider: /28 */\r
+#define LCDDIV__29 (0xE000u) /* LCD_C LCD frequency divider: /29 */\r
+#define LCDDIV__30 (0xE800u) /* LCD_C LCD frequency divider: /30 */\r
+#define LCDDIV__31 (0xF000u) /* LCD_C LCD frequency divider: /31 */\r
+#define LCDDIV__32 (0xF800u) /* LCD_C LCD frequency divider: /32 */\r
+\r
+/* Display modes coded with Bits 2-4 */\r
+#define LCDSTATIC (LCDSON)\r
+#define LCD2MUX (LCDMX0+LCDSON)\r
+#define LCD3MUX (LCDMX1+LCDSON)\r
+#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)\r
+#define LCD5MUX (LCDMX2+LCDSON)\r
+#define LCD6MUX (LCDMX2+LCDMX0+LCDSON)\r
+#define LCD7MUX (LCDMX2+LCDMX1+LCDSON)\r
+#define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON)\r
+\r
+// LCDCCTL1\r
+#define LCDFRMIFG (0x0001u) /* LCD_C LCD frame interrupt flag */\r
+#define LCDBLKOFFIFG (0x0002u) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIFG (0x0004u) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIFG (0x0008u) /* LCD_C No cpacitance connected interrupt flag */\r
+#define LCDFRMIE (0x0100u) /* LCD_C LCD frame interrupt enable */\r
+#define LCDBLKOFFIE (0x0200u) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIE (0x0400u) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIE (0x0800u) /* LCD_C No cpacitance connected interrupt enable */\r
+\r
+// LCDCCTL1\r
+#define LCDFRMIFG_L (0x0001u) /* LCD_C LCD frame interrupt flag */\r
+#define LCDBLKOFFIFG_L (0x0002u) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIFG_L (0x0004u) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIFG_L (0x0008u) /* LCD_C No cpacitance connected interrupt flag */\r
+\r
+// LCDCCTL1\r
+#define LCDFRMIE_H (0x0001u) /* LCD_C LCD frame interrupt enable */\r
+#define LCDBLKOFFIE_H (0x0002u) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIE_H (0x0004u) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIE_H (0x0008u) /* LCD_C No cpacitance connected interrupt enable */\r
+\r
+// LCDCBLKCTL\r
+#define LCDBLKMOD0 (0x0001u) /* LCD_C Blinking mode Bit: 0 */\r
+#define LCDBLKMOD1 (0x0002u) /* LCD_C Blinking mode Bit: 1 */\r
+#define LCDBLKPRE0 (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */\r
+#define LCDBLKPRE1 (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */\r
+#define LCDBLKPRE2 (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */\r
+#define LCDBLKDIV0 (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */\r
+#define LCDBLKDIV1 (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */\r
+#define LCDBLKDIV2 (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */\r
+\r
+// LCDCBLKCTL\r
+#define LCDBLKMOD0_L (0x0001u) /* LCD_C Blinking mode Bit: 0 */\r
+#define LCDBLKMOD1_L (0x0002u) /* LCD_C Blinking mode Bit: 1 */\r
+#define LCDBLKPRE0_L (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */\r
+#define LCDBLKPRE1_L (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */\r
+#define LCDBLKPRE2_L (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */\r
+#define LCDBLKDIV0_L (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */\r
+#define LCDBLKDIV1_L (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */\r
+#define LCDBLKDIV2_L (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */\r
+\r
+#define LCDBLKMOD_0 (0x0000u) /* LCD_C Blinking mode: Off */\r
+#define LCDBLKMOD_1 (0x0001u) /* LCD_C Blinking mode: Individual */\r
+#define LCDBLKMOD_2 (0x0002u) /* LCD_C Blinking mode: All */\r
+#define LCDBLKMOD_3 (0x0003u) /* LCD_C Blinking mode: Switching */\r
+\r
+// LCDCMEMCTL\r
+#define LCDDISP (0x0001u) /* LCD_C LCD memory registers for display */\r
+#define LCDCLRM (0x0002u) /* LCD_C Clear LCD memory */\r
+#define LCDCLRBM (0x0004u) /* LCD_C Clear LCD blinking memory */\r
+\r
+// LCDCMEMCTL\r
+#define LCDDISP_L (0x0001u) /* LCD_C LCD memory registers for display */\r
+#define LCDCLRM_L (0x0002u) /* LCD_C Clear LCD memory */\r
+#define LCDCLRBM_L (0x0004u) /* LCD_C Clear LCD blinking memory */\r
+\r
+// LCDCVCTL\r
+#define LCD2B (0x0001u) /* Selects 1/2 bias. */\r
+#define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */\r
+#define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */\r
+#define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */\r
+#define VLCDEXT (0x0010u) /* Select external source for VLCD. */\r
+#define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */\r
+#define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */\r
+#define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */\r
+#define VLCD0 (0x0200u) /* VLCD select: 0 */\r
+#define VLCD1 (0x0400u) /* VLCD select: 1 */\r
+#define VLCD2 (0x0800u) /* VLCD select: 2 */\r
+#define VLCD3 (0x1000u) /* VLCD select: 3 */\r
+#define VLCD4 (0x2000u) /* VLCD select: 4 */\r
+#define VLCD5 (0x4000u) /* VLCD select: 5 */\r
+\r
+// LCDCVCTL\r
+#define LCD2B_L (0x0001u) /* Selects 1/2 bias. */\r
+#define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */\r
+#define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */\r
+#define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */\r
+#define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */\r
+#define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */\r
+#define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */\r
+#define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */\r
+\r
+// LCDCVCTL\r
+#define VLCD0_H (0x0002u) /* VLCD select: 0 */\r
+#define VLCD1_H (0x0004u) /* VLCD select: 1 */\r
+#define VLCD2_H (0x0008u) /* VLCD select: 2 */\r
+#define VLCD3_H (0x0010u) /* VLCD select: 3 */\r
+#define VLCD4_H (0x0020u) /* VLCD select: 4 */\r
+#define VLCD5_H (0x0040u) /* VLCD select: 5 */\r
+\r
+/* Reference voltage source select for the regulated charge pump */\r
+#define VLCDREF_0 (0x0000u) /* Internal */\r
+#define VLCDREF_1 (0x0002u) /* External */\r
+#define VLCDREF_2 (0x0004u) /* Reserved */\r
+#define VLCDREF_3 (0x0006u) /* Reserved */\r
+\r
+/* Charge pump voltage selections */\r
+#define VLCD_0 (0x0000u) /* Charge pump disabled */\r
+#define VLCD_1 (0x0200u) /* VLCD = 2.60V */\r
+#define VLCD_2 (0x0400u) /* VLCD = 2.66V */\r
+#define VLCD_3 (0x0600u) /* VLCD = 2.72V */\r
+#define VLCD_4 (0x0800u) /* VLCD = 2.78V */\r
+#define VLCD_5 (0x0A00u) /* VLCD = 2.84V */\r
+#define VLCD_6 (0x0C00u) /* VLCD = 2.90V */\r
+#define VLCD_7 (0x0E00u) /* VLCD = 2.96V */\r
+#define VLCD_8 (0x1000u) /* VLCD = 3.02V */\r
+#define VLCD_9 (0x1200u) /* VLCD = 3.08V */\r
+#define VLCD_10 (0x1400u) /* VLCD = 3.14V */\r
+#define VLCD_11 (0x1600u) /* VLCD = 3.20V */\r
+#define VLCD_12 (0x1800u) /* VLCD = 3.26V */\r
+#define VLCD_13 (0x1A00u) /* VLCD = 3.32V */\r
+#define VLCD_14 (0x1C00u) /* VLCD = 3.38V */\r
+#define VLCD_15 (0x1E00u) /* VLCD = 3.44V */\r
+\r
+#define VLCD_DISABLED (0x0000u) /* Charge pump disabled */\r
+#define VLCD_2_60 (0x0200u) /* VLCD = 2.60V */\r
+#define VLCD_2_66 (0x0400u) /* VLCD = 2.66V */\r
+#define VLCD_2_72 (0x0600u) /* VLCD = 2.72V */\r
+#define VLCD_2_78 (0x0800u) /* VLCD = 2.78V */\r
+#define VLCD_2_84 (0x0A00u) /* VLCD = 2.84V */\r
+#define VLCD_2_90 (0x0C00u) /* VLCD = 2.90V */\r
+#define VLCD_2_96 (0x0E00u) /* VLCD = 2.96V */\r
+#define VLCD_3_02 (0x1000u) /* VLCD = 3.02V */\r
+#define VLCD_3_08 (0x1200u) /* VLCD = 3.08V */\r
+#define VLCD_3_14 (0x1400u) /* VLCD = 3.14V */\r
+#define VLCD_3_20 (0x1600u) /* VLCD = 3.20V */\r
+#define VLCD_3_26 (0x1800u) /* VLCD = 3.26V */\r
+#define VLCD_3_32 (0x1A00u) /* VLCD = 3.32V */\r
+#define VLCD_3_38 (0x1C00u) /* VLCD = 3.38V */\r
+#define VLCD_3_44 (0x1E00u) /* VLCD = 3.44V */\r
+\r
+// LCDCPCTL0\r
+#define LCDS0 (0x0001u) /* LCD Segment 0 enable. */\r
+#define LCDS1 (0x0002u) /* LCD Segment 1 enable. */\r
+#define LCDS2 (0x0004u) /* LCD Segment 2 enable. */\r
+#define LCDS3 (0x0008u) /* LCD Segment 3 enable. */\r
+#define LCDS4 (0x0010u) /* LCD Segment 4 enable. */\r
+#define LCDS5 (0x0020u) /* LCD Segment 5 enable. */\r
+#define LCDS6 (0x0040u) /* LCD Segment 6 enable. */\r
+#define LCDS7 (0x0080u) /* LCD Segment 7 enable. */\r
+#define LCDS8 (0x0100u) /* LCD Segment 8 enable. */\r
+#define LCDS9 (0x0200u) /* LCD Segment 9 enable. */\r
+#define LCDS10 (0x0400u) /* LCD Segment 10 enable. */\r
+#define LCDS11 (0x0800u) /* LCD Segment 11 enable. */\r
+#define LCDS12 (0x1000u) /* LCD Segment 12 enable. */\r
+#define LCDS13 (0x2000u) /* LCD Segment 13 enable. */\r
+#define LCDS14 (0x4000u) /* LCD Segment 14 enable. */\r
+#define LCDS15 (0x8000u) /* LCD Segment 15 enable. */\r
+\r
+// LCDCPCTL0\r
+#define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */\r
+#define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */\r
+#define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */\r
+#define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */\r
+#define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */\r
+#define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */\r
+#define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */\r
+#define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */\r
+\r
+// LCDCPCTL0\r
+#define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */\r
+#define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */\r
+#define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */\r
+#define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */\r
+#define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */\r
+#define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */\r
+#define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */\r
+#define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */\r
+\r
+// LCDCPCTL1\r
+#define LCDS16 (0x0001u) /* LCD Segment 16 enable. */\r
+#define LCDS17 (0x0002u) /* LCD Segment 17 enable. */\r
+#define LCDS18 (0x0004u) /* LCD Segment 18 enable. */\r
+#define LCDS19 (0x0008u) /* LCD Segment 19 enable. */\r
+#define LCDS20 (0x0010u) /* LCD Segment 20 enable. */\r
+#define LCDS21 (0x0020u) /* LCD Segment 21 enable. */\r
+#define LCDS22 (0x0040u) /* LCD Segment 22 enable. */\r
+#define LCDS23 (0x0080u) /* LCD Segment 23 enable. */\r
+#define LCDS24 (0x0100u) /* LCD Segment 24 enable. */\r
+#define LCDS25 (0x0200u) /* LCD Segment 25 enable. */\r
+#define LCDS26 (0x0400u) /* LCD Segment 26 enable. */\r
+#define LCDS27 (0x0800u) /* LCD Segment 27 enable. */\r
+#define LCDS28 (0x1000u) /* LCD Segment 28 enable. */\r
+#define LCDS29 (0x2000u) /* LCD Segment 29 enable. */\r
+#define LCDS30 (0x4000u) /* LCD Segment 30 enable. */\r
+#define LCDS31 (0x8000u) /* LCD Segment 31 enable. */\r
+\r
+// LCDCPCTL1\r
+#define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */\r
+#define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */\r
+#define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */\r
+#define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */\r
+#define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */\r
+#define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */\r
+#define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */\r
+#define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */\r
+\r
+// LCDCPCTL1\r
+#define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */\r
+#define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */\r
+#define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */\r
+#define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */\r
+#define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */\r
+#define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */\r
+#define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */\r
+#define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */\r
+\r
+// LCDCPCTL2\r
+#define LCDS32 (0x0001u) /* LCD Segment 32 enable. */\r
+#define LCDS33 (0x0002u) /* LCD Segment 33 enable. */\r
+#define LCDS34 (0x0004u) /* LCD Segment 34 enable. */\r
+#define LCDS35 (0x0008u) /* LCD Segment 35 enable. */\r
+#define LCDS36 (0x0010u) /* LCD Segment 36 enable. */\r
+#define LCDS37 (0x0020u) /* LCD Segment 37 enable. */\r
+#define LCDS38 (0x0040u) /* LCD Segment 38 enable. */\r
+#define LCDS39 (0x0080u) /* LCD Segment 39 enable. */\r
+#define LCDS40 (0x0100u) /* LCD Segment 40 enable. */\r
+#define LCDS41 (0x0200u) /* LCD Segment 41 enable. */\r
+#define LCDS42 (0x0400u) /* LCD Segment 42 enable. */\r
+#define LCDS43 (0x0800u) /* LCD Segment 43 enable. */\r
+#define LCDS44 (0x1000u) /* LCD Segment 44 enable. */\r
+#define LCDS45 (0x2000u) /* LCD Segment 45 enable. */\r
+#define LCDS46 (0x4000u) /* LCD Segment 46 enable. */\r
+#define LCDS47 (0x8000u) /* LCD Segment 47 enable. */\r
+\r
+// LCDCPCTL2\r
+#define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */\r
+#define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */\r
+#define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */\r
+#define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */\r
+#define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */\r
+#define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */\r
+#define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */\r
+#define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */\r
+\r
+// LCDCPCTL2\r
+#define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */\r
+#define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */\r
+#define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */\r
+#define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */\r
+#define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */\r
+#define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */\r
+#define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */\r
+#define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */\r
+\r
+// LCDCPCTL3\r
+#define LCDS48 (0x0001u) /* LCD Segment 48 enable. */\r
+#define LCDS49 (0x0002u) /* LCD Segment 49 enable. */\r
+#define LCDS50 (0x0004u) /* LCD Segment 50 enable. */\r
+#define LCDS51 (0x0008u) /* LCD Segment 51 enable. */\r
+#define LCDS52 (0x0010u) /* LCD Segment 52 enable. */\r
+#define LCDS53 (0x0020u) /* LCD Segment 53 enable. */\r
+\r
+// LCDCPCTL3\r
+#define LCDS48_L (0x0001u) /* LCD Segment 48 enable. */\r
+#define LCDS49_L (0x0002u) /* LCD Segment 49 enable. */\r
+#define LCDS50_L (0x0004u) /* LCD Segment 50 enable. */\r
+#define LCDS51_L (0x0008u) /* LCD Segment 51 enable. */\r
+#define LCDS52_L (0x0010u) /* LCD Segment 52 enable. */\r
+#define LCDS53_L (0x0020u) /* LCD Segment 53 enable. */\r
+\r
+// LCDCCPCTL\r
+#define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */\r
+#define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */\r
+#define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */\r
+#define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */\r
+#define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */\r
+#define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */\r
+#define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */\r
+#define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */\r
+#define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */\r
+\r
+// LCDCCPCTL\r
+#define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */\r
+#define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */\r
+#define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */\r
+#define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */\r
+#define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */\r
+#define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */\r
+#define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */\r
+#define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */\r
+\r
+// LCDCCPCTL\r
+#define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */\r
+\r
+#define OFS_LCDM1 (0x0020u) /* LCD Memory 1 */\r
+#define LCDMEM_ LCDM1 /* LCD Memory */\r
+#ifndef __IAR_SYSTEMS_ICC__\r
+#define LCDMEM LCDM1 /* LCD Memory (for assembler) */\r
+#else\r
+#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */\r
+#endif\r
+#define OFS_LCDM2 (0x0021u) /* LCD Memory 2 */\r
+#define OFS_LCDM3 (0x0022u) /* LCD Memory 3 */\r
+#define OFS_LCDM4 (0x0023u) /* LCD Memory 4 */\r
+#define OFS_LCDM5 (0x0024u) /* LCD Memory 5 */\r
+#define OFS_LCDM6 (0x0025u) /* LCD Memory 6 */\r
+#define OFS_LCDM7 (0x0026u) /* LCD Memory 7 */\r
+#define OFS_LCDM8 (0x0027u) /* LCD Memory 8 */\r
+#define OFS_LCDM9 (0x0028u) /* LCD Memory 9 */\r
+#define OFS_LCDM10 (0x0029u) /* LCD Memory 10 */\r
+#define OFS_LCDM11 (0x002Au) /* LCD Memory 11 */\r
+#define OFS_LCDM12 (0x002Bu) /* LCD Memory 12 */\r
+#define OFS_LCDM13 (0x002Cu) /* LCD Memory 13 */\r
+#define OFS_LCDM14 (0x002Du) /* LCD Memory 14 */\r
+#define OFS_LCDM15 (0x002Eu) /* LCD Memory 15 */\r
+#define OFS_LCDM16 (0x002Fu) /* LCD Memory 16 */\r
+#define OFS_LCDM17 (0x0030u) /* LCD Memory 17 */\r
+#define OFS_LCDM18 (0x0031u) /* LCD Memory 18 */\r
+#define OFS_LCDM19 (0x0032u) /* LCD Memory 19 */\r
+#define OFS_LCDM20 (0x0033u) /* LCD Memory 20 */\r
+#define OFS_LCDM21 (0x0034u) /* LCD Memory 21 */\r
+#define OFS_LCDM22 (0x0035u) /* LCD Memory 22 */\r
+#define OFS_LCDM23 (0x0036u) /* LCD Memory 23 */\r
+#define OFS_LCDM24 (0x0037u) /* LCD Memory 24 */\r
+#define OFS_LCDM25 (0x0038u) /* LCD Memory 25 */\r
+#define OFS_LCDM26 (0x0039u) /* LCD Memory 26 */\r
+#define OFS_LCDM27 (0x003Au) /* LCD Memory 27 */\r
+#define OFS_LCDM28 (0x003Bu) /* LCD Memory 28 */\r
+#define OFS_LCDM29 (0x003Cu) /* LCD Memory 29 */\r
+#define OFS_LCDM30 (0x003Du) /* LCD Memory 30 */\r
+#define OFS_LCDM31 (0x003Eu) /* LCD Memory 31 */\r
+#define OFS_LCDM32 (0x003Fu) /* LCD Memory 32 */\r
+#define OFS_LCDM33 (0x0040u) /* LCD Memory 33 */\r
+#define OFS_LCDM34 (0x0041u) /* LCD Memory 34 */\r
+#define OFS_LCDM35 (0x0042u) /* LCD Memory 35 */\r
+#define OFS_LCDM36 (0x0043u) /* LCD Memory 36 */\r
+#define OFS_LCDM37 (0x0044u) /* LCD Memory 37 */\r
+#define OFS_LCDM38 (0x0045u) /* LCD Memory 38 */\r
+#define OFS_LCDM39 (0x0046u) /* LCD Memory 39 */\r
+#define OFS_LCDM40 (0x0047u) /* LCD Memory 40 */\r
+\r
+#define OFS_LCDBM1 (0x0040u) /* LCD Blinking Memory 1 */\r
+#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */\r
+#ifndef __IAR_SYSTEMS_ICC__\r
+#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */\r
+#else\r
+#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */\r
+#endif\r
+#define OFS_LCDBM2 (0x0041u) /* LCD Blinking Memory 2 */\r
+#define OFS_LCDBM3 (0x0042u) /* LCD Blinking Memory 3 */\r
+#define OFS_LCDBM4 (0x0043u) /* LCD Blinking Memory 4 */\r
+#define OFS_LCDBM5 (0x0044u) /* LCD Blinking Memory 5 */\r
+#define OFS_LCDBM6 (0x0045u) /* LCD Blinking Memory 6 */\r
+#define OFS_LCDBM7 (0x0046u) /* LCD Blinking Memory 7 */\r
+#define OFS_LCDBM8 (0x0047u) /* LCD Blinking Memory 8 */\r
+#define OFS_LCDBM9 (0x0048u) /* LCD Blinking Memory 9 */\r
+#define OFS_LCDBM10 (0x0049u) /* LCD Blinking Memory 10 */\r
+#define OFS_LCDBM11 (0x004Au) /* LCD Blinking Memory 11 */\r
+#define OFS_LCDBM12 (0x004Bu) /* LCD Blinking Memory 12 */\r
+#define OFS_LCDBM13 (0x004Cu) /* LCD Blinking Memory 13 */\r
+#define OFS_LCDBM14 (0x004Du) /* LCD Blinking Memory 14 */\r
+#define OFS_LCDBM15 (0x004Eu) /* LCD Blinking Memory 15 */\r
+#define OFS_LCDBM16 (0x004Fu) /* LCD Blinking Memory 16 */\r
+#define OFS_LCDBM17 (0x0050u) /* LCD Blinking Memory 17 */\r
+#define OFS_LCDBM18 (0x0051u) /* LCD Blinking Memory 18 */\r
+#define OFS_LCDBM19 (0x0052u) /* LCD Blinking Memory 19 */\r
+#define OFS_LCDBM20 (0x0053u) /* LCD Blinking Memory 20 */\r
+\r
+/* LCDCIV Definitions */\r
+#define LCDCIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define LCDCIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */\r
+#define LCDCIV_LCDCLKOFFIFG (0x0004u) /* Blink, segments off */\r
+#define LCDCIV_LCDCLKONIFG (0x0006u) /* Blink, segments on */\r
+#define LCDCIV_LCDFRMIFG (0x0008u) /* Frame interrupt */\r
+\r
+#endif\r
+/************************************************************\r
+* Memory Protection Unit\r
+************************************************************/\r
+#ifdef __MSP430_HAS_MPU__ /* Definition to show that Module is available */\r
+\r
+#define OFS_MPUCTL0 (0x0000u) /* MPU Control Register 0 */\r
+#define OFS_MPUCTL0_L OFS_MPUCTL0\r
+#define OFS_MPUCTL0_H OFS_MPUCTL0+1\r
+#define OFS_MPUCTL1 (0x0002u) /* MPU Control Register 1 */\r
+#define OFS_MPUCTL1_L OFS_MPUCTL1\r
+#define OFS_MPUCTL1_H OFS_MPUCTL1+1\r
+#define OFS_MPUSEGB2 (0x0004u) /* MPU Segmentation Border 2 Register */\r
+#define OFS_MPUSEGB2_L OFS_MPUSEGB2\r
+#define OFS_MPUSEGB2_H OFS_MPUSEGB2+1\r
+#define OFS_MPUSEGB1 (0x0006u) /* MPU Segmentation Border 1 Register */\r
+#define OFS_MPUSEGB1_L OFS_MPUSEGB1\r
+#define OFS_MPUSEGB1_H OFS_MPUSEGB1+1\r
+#define OFS_MPUSAM (0x0008u) /* MPU Access Management Register */\r
+#define OFS_MPUSAM_L OFS_MPUSAM\r
+#define OFS_MPUSAM_H OFS_MPUSAM+1\r
+#define OFS_MPUIPC0 (0x000Au) /* MPU IP Control 0 Register */\r
+#define OFS_MPUIPC0_L OFS_MPUIPC0\r
+#define OFS_MPUIPC0_H OFS_MPUIPC0+1\r
+#define OFS_MPUIPSEGB2 (0x000Cu) /* MPU IP Segment Border 2 Register */\r
+#define OFS_MPUIPSEGB2_L OFS_MPUIPSEGB2\r
+#define OFS_MPUIPSEGB2_H OFS_MPUIPSEGB2+1\r
+#define OFS_MPUIPSEGB1 (0x000Eu) /* MPU IP Segment Border 1 Register */\r
+#define OFS_MPUIPSEGB1_L OFS_MPUIPSEGB1\r
+#define OFS_MPUIPSEGB1_H OFS_MPUIPSEGB1+1\r
+\r
+/* MPUCTL0 Control Bits */\r
+#define MPUENA (0x0001u) /* MPU Enable */\r
+#define MPULOCK (0x0002u) /* MPU Lock */\r
+#define MPUSEGIE (0x0010u) /* MPU Enable NMI on Segment violation */\r
+\r
+/* MPUCTL0 Control Bits */\r
+#define MPUENA_L (0x0001u) /* MPU Enable */\r
+#define MPULOCK_L (0x0002u) /* MPU Lock */\r
+#define MPUSEGIE_L (0x0010u) /* MPU Enable NMI on Segment violation */\r
+\r
+#define MPUPW (0xA500u) /* MPU Access Password */\r
+#define MPUPW_H (0xA5) /* MPU Access Password */\r
+\r
+/* MPUCTL1 Control Bits */\r
+#define MPUSEG1IFG (0x0001u) /* MPU Main Memory Segment 1 violation interupt flag */\r
+#define MPUSEG2IFG (0x0002u) /* MPU Main Memory Segment 2 violation interupt flag */\r
+#define MPUSEG3IFG (0x0004u) /* MPU Main Memory Segment 3 violation interupt flag */\r
+#define MPUSEGIIFG (0x0008u) /* MPU Info Memory Segment violation interupt flag */\r
+#define MPUSEGIPIFG (0x0010u) /* MPU IP Memory Segment violation interupt flag */\r
+\r
+/* MPUCTL1 Control Bits */\r
+#define MPUSEG1IFG_L (0x0001u) /* MPU Main Memory Segment 1 violation interupt flag */\r
+#define MPUSEG2IFG_L (0x0002u) /* MPU Main Memory Segment 2 violation interupt flag */\r
+#define MPUSEG3IFG_L (0x0004u) /* MPU Main Memory Segment 3 violation interupt flag */\r
+#define MPUSEGIIFG_L (0x0008u) /* MPU Info Memory Segment violation interupt flag */\r
+#define MPUSEGIPIFG_L (0x0010u) /* MPU IP Memory Segment violation interupt flag */\r
+\r
+/* MPUSEGB2 Control Bits */\r
+\r
+/* MPUSEGB2 Control Bits */\r
+\r
+/* MPUSEGB2 Control Bits */\r
+\r
+/* MPUSEGB1 Control Bits */\r
+\r
+/* MPUSEGB1 Control Bits */\r
+\r
+/* MPUSEGB1 Control Bits */\r
+\r
+/* MPUSAM Control Bits */\r
+#define MPUSEG1RE (0x0001u) /* MPU Main memory Segment 1 Read enable */\r
+#define MPUSEG1WE (0x0002u) /* MPU Main memory Segment 1 Write enable */\r
+#define MPUSEG1XE (0x0004u) /* MPU Main memory Segment 1 Execute enable */\r
+#define MPUSEG1VS (0x0008u) /* MPU Main memory Segment 1 Violation select */\r
+#define MPUSEG2RE (0x0010u) /* MPU Main memory Segment 2 Read enable */\r
+#define MPUSEG2WE (0x0020u) /* MPU Main memory Segment 2 Write enable */\r
+#define MPUSEG2XE (0x0040u) /* MPU Main memory Segment 2 Execute enable */\r
+#define MPUSEG2VS (0x0080u) /* MPU Main memory Segment 2 Violation select */\r
+#define MPUSEG3RE (0x0100u) /* MPU Main memory Segment 3 Read enable */\r
+#define MPUSEG3WE (0x0200u) /* MPU Main memory Segment 3 Write enable */\r
+#define MPUSEG3XE (0x0400u) /* MPU Main memory Segment 3 Execute enable */\r
+#define MPUSEG3VS (0x0800u) /* MPU Main memory Segment 3 Violation select */\r
+#define MPUSEGIRE (0x1000u) /* MPU Info memory Segment Read enable */\r
+#define MPUSEGIWE (0x2000u) /* MPU Info memory Segment Write enable */\r
+#define MPUSEGIXE (0x4000u) /* MPU Info memory Segment Execute enable */\r
+#define MPUSEGIVS (0x8000u) /* MPU Info memory Segment Violation select */\r
+\r
+/* MPUSAM Control Bits */\r
+#define MPUSEG1RE_L (0x0001u) /* MPU Main memory Segment 1 Read enable */\r
+#define MPUSEG1WE_L (0x0002u) /* MPU Main memory Segment 1 Write enable */\r
+#define MPUSEG1XE_L (0x0004u) /* MPU Main memory Segment 1 Execute enable */\r
+#define MPUSEG1VS_L (0x0008u) /* MPU Main memory Segment 1 Violation select */\r
+#define MPUSEG2RE_L (0x0010u) /* MPU Main memory Segment 2 Read enable */\r
+#define MPUSEG2WE_L (0x0020u) /* MPU Main memory Segment 2 Write enable */\r
+#define MPUSEG2XE_L (0x0040u) /* MPU Main memory Segment 2 Execute enable */\r
+#define MPUSEG2VS_L (0x0080u) /* MPU Main memory Segment 2 Violation select */\r
+\r
+/* MPUSAM Control Bits */\r
+#define MPUSEG3RE_H (0x0001u) /* MPU Main memory Segment 3 Read enable */\r
+#define MPUSEG3WE_H (0x0002u) /* MPU Main memory Segment 3 Write enable */\r
+#define MPUSEG3XE_H (0x0004u) /* MPU Main memory Segment 3 Execute enable */\r
+#define MPUSEG3VS_H (0x0008u) /* MPU Main memory Segment 3 Violation select */\r
+#define MPUSEGIRE_H (0x0010u) /* MPU Info memory Segment Read enable */\r
+#define MPUSEGIWE_H (0x0020u) /* MPU Info memory Segment Write enable */\r
+#define MPUSEGIXE_H (0x0040u) /* MPU Info memory Segment Execute enable */\r
+#define MPUSEGIVS_H (0x0080u) /* MPU Info memory Segment Violation select */\r
+\r
+/* MPUIPC0 Control Bits */\r
+#define MPUIPVS (0x0020u) /* MPU MPU IP protection segment Violation Select */\r
+#define MPUIPENA (0x0040u) /* MPU MPU IP Protection Enable */\r
+#define MPUIPLOCK (0x0080u) /* MPU IP Protection Lock */\r
+\r
+/* MPUIPC0 Control Bits */\r
+#define MPUIPVS_L (0x0020u) /* MPU MPU IP protection segment Violation Select */\r
+#define MPUIPENA_L (0x0040u) /* MPU MPU IP Protection Enable */\r
+#define MPUIPLOCK_L (0x0080u) /* MPU IP Protection Lock */\r
+\r
+/* MPUIPSEGB2 Control Bits */\r
+\r
+/* MPUIPSEGB2 Control Bits */\r
+\r
+/* MPUIPSEGB2 Control Bits */\r
+\r
+/* MPUIPSEGB1 Control Bits */\r
+\r
+/* MPUIPSEGB1 Control Bits */\r
+\r
+/* MPUIPSEGB1 Control Bits */\r
+\r
+#endif\r
+/************************************************************\r
+* HARDWARE MULTIPLIER 32Bit\r
+************************************************************/\r
+#ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */\r
+\r
+#define OFS_MPY (0x0000u) /* Multiply Unsigned/Operand 1 */\r
+#define OFS_MPY_L OFS_MPY\r
+#define OFS_MPY_H OFS_MPY+1\r
+#define OFS_MPYS (0x0002u) /* Multiply Signed/Operand 1 */\r
+#define OFS_MPYS_L OFS_MPYS\r
+#define OFS_MPYS_H OFS_MPYS+1\r
+#define OFS_MAC (0x0004u) /* Multiply Unsigned and Accumulate/Operand 1 */\r
+#define OFS_MAC_L OFS_MAC\r
+#define OFS_MAC_H OFS_MAC+1\r
+#define OFS_MACS (0x0006u) /* Multiply Signed and Accumulate/Operand 1 */\r
+#define OFS_MACS_L OFS_MACS\r
+#define OFS_MACS_H OFS_MACS+1\r
+#define OFS_OP2 (0x0008u) /* Operand 2 */\r
+#define OFS_OP2_L OFS_OP2\r
+#define OFS_OP2_H OFS_OP2+1\r
+#define OFS_RESLO (0x000Au) /* Result Low Word */\r
+#define OFS_RESLO_L OFS_RESLO\r
+#define OFS_RESLO_H OFS_RESLO+1\r
+#define OFS_RESHI (0x000Cu) /* Result High Word */\r
+#define OFS_RESHI_L OFS_RESHI\r
+#define OFS_RESHI_H OFS_RESHI+1\r
+#define OFS_SUMEXT (0x000Eu) /* Sum Extend */\r
+#define OFS_SUMEXT_L OFS_SUMEXT\r
+#define OFS_SUMEXT_H OFS_SUMEXT+1\r
+#define OFS_MPY32CTL0 (0x002Cu)\r
+#define OFS_MPY32CTL0_L OFS_MPY32CTL0\r
+#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1\r
+\r
+#define OFS_MPY32L (0x0010u) /* 32-bit operand 1 - multiply - low word */\r
+#define OFS_MPY32L_L OFS_MPY32L\r
+#define OFS_MPY32L_H OFS_MPY32L+1\r
+#define OFS_MPY32H (0x0012u) /* 32-bit operand 1 - multiply - high word */\r
+#define OFS_MPY32H_L OFS_MPY32H\r
+#define OFS_MPY32H_H OFS_MPY32H+1\r
+#define OFS_MPYS32L (0x0014u) /* 32-bit operand 1 - signed multiply - low word */\r
+#define OFS_MPYS32L_L OFS_MPYS32L\r
+#define OFS_MPYS32L_H OFS_MPYS32L+1\r
+#define OFS_MPYS32H (0x0016u) /* 32-bit operand 1 - signed multiply - high word */\r
+#define OFS_MPYS32H_L OFS_MPYS32H\r
+#define OFS_MPYS32H_H OFS_MPYS32H+1\r
+#define OFS_MAC32L (0x0018u) /* 32-bit operand 1 - multiply accumulate - low word */\r
+#define OFS_MAC32L_L OFS_MAC32L\r
+#define OFS_MAC32L_H OFS_MAC32L+1\r
+#define OFS_MAC32H (0x001Au) /* 32-bit operand 1 - multiply accumulate - high word */\r
+#define OFS_MAC32H_L OFS_MAC32H\r
+#define OFS_MAC32H_H OFS_MAC32H+1\r
+#define OFS_MACS32L (0x001Cu) /* 32-bit operand 1 - signed multiply accumulate - low word */\r
+#define OFS_MACS32L_L OFS_MACS32L\r
+#define OFS_MACS32L_H OFS_MACS32L+1\r
+#define OFS_MACS32H (0x001Eu) /* 32-bit operand 1 - signed multiply accumulate - high word */\r
+#define OFS_MACS32H_L OFS_MACS32H\r
+#define OFS_MACS32H_H OFS_MACS32H+1\r
+#define OFS_OP2L (0x0020u) /* 32-bit operand 2 - low word */\r
+#define OFS_OP2L_L OFS_OP2L\r
+#define OFS_OP2L_H OFS_OP2L+1\r
+#define OFS_OP2H (0x0022u) /* 32-bit operand 2 - high word */\r
+#define OFS_OP2H_L OFS_OP2H\r
+#define OFS_OP2H_H OFS_OP2H+1\r
+#define OFS_RES0 (0x0024u) /* 32x32-bit result 0 - least significant word */\r
+#define OFS_RES0_L OFS_RES0\r
+#define OFS_RES0_H OFS_RES0+1\r
+#define OFS_RES1 (0x0026u) /* 32x32-bit result 1 */\r
+#define OFS_RES1_L OFS_RES1\r
+#define OFS_RES1_H OFS_RES1+1\r
+#define OFS_RES2 (0x0028u) /* 32x32-bit result 2 */\r
+#define OFS_RES2_L OFS_RES2\r
+#define OFS_RES2_H OFS_RES2+1\r
+#define OFS_RES3 (0x002Au) /* 32x32-bit result 3 - most significant word */\r
+#define OFS_RES3_L OFS_RES3\r
+#define OFS_RES3_H OFS_RES3+1\r
+#define OFS_SUMEXT (0x000Eu)\r
+#define OFS_SUMEXT_L OFS_SUMEXT\r
+#define OFS_SUMEXT_H OFS_SUMEXT+1\r
+#define OFS_MPY32CTL0 (0x002Cu) /* MPY32 Control Register 0 */\r
+#define OFS_MPY32CTL0_L OFS_MPY32CTL0\r
+#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1\r
+\r
+#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */\r
+#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */\r
+#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */\r
+#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */\r
+#define OP2_B OP2_L /* Operand 2 (Byte Access) */\r
+#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */\r
+#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */\r
+#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */\r
+#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */\r
+#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */\r
+#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */\r
+#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */\r
+#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */\r
+#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */\r
+#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+#define MPYC (0x0001u) /* Carry of the multiplier */\r
+//#define RESERVED (0x0002u) /* Reserved */\r
+#define MPYFRAC (0x0004u) /* Fractional mode */\r
+#define MPYSAT (0x0008u) /* Saturation mode */\r
+#define MPYM0 (0x0010u) /* Multiplier mode Bit:0 */\r
+#define MPYM1 (0x0020u) /* Multiplier mode Bit:1 */\r
+#define OP1_32 (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */\r
+#define OP2_32 (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */\r
+#define MPYDLYWRTEN (0x0100u) /* Delayed write enable */\r
+#define MPYDLY32 (0x0200u) /* Delayed write mode */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+#define MPYC_L (0x0001u) /* Carry of the multiplier */\r
+//#define RESERVED (0x0002u) /* Reserved */\r
+#define MPYFRAC_L (0x0004u) /* Fractional mode */\r
+#define MPYSAT_L (0x0008u) /* Saturation mode */\r
+#define MPYM0_L (0x0010u) /* Multiplier mode Bit:0 */\r
+#define MPYM1_L (0x0020u) /* Multiplier mode Bit:1 */\r
+#define OP1_32_L (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */\r
+#define OP2_32_L (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+//#define RESERVED (0x0002u) /* Reserved */\r
+#define MPYDLYWRTEN_H (0x0001u) /* Delayed write enable */\r
+#define MPYDLY32_H (0x0002u) /* Delayed write mode */\r
+\r
+#define MPYM_0 (0x0000u) /* Multiplier mode: MPY */\r
+#define MPYM_1 (0x0010u) /* Multiplier mode: MPYS */\r
+#define MPYM_2 (0x0020u) /* Multiplier mode: MAC */\r
+#define MPYM_3 (0x0030u) /* Multiplier mode: MACS */\r
+#define MPYM__MPY (0x0000u) /* Multiplier mode: MPY */\r
+#define MPYM__MPYS (0x0010u) /* Multiplier mode: MPYS */\r
+#define MPYM__MAC (0x0020u) /* Multiplier mode: MAC */\r
+#define MPYM__MACS (0x0030u) /* Multiplier mode: MACS */\r
+\r
+#endif\r
+/************************************************************\r
+* PMM - Power Management System for FRAM\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PMM_FRAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PMMCTL0 (0x0000u) /* PMM Control 0 */\r
+#define OFS_PMMCTL0_L OFS_PMMCTL0\r
+#define OFS_PMMCTL0_H OFS_PMMCTL0+1\r
+#define OFS_PMMCTL1 (0x0002u) /* PMM Control 1 */\r
+#define OFS_PMMIFG (0x000Au) /* PMM Interrupt Flag */\r
+#define OFS_PMMIFG_L OFS_PMMIFG\r
+#define OFS_PMMIFG_H OFS_PMMIFG+1\r
+#define OFS_PM5CTL0 (0x0010u) /* PMM Power Mode 5 Control Register 0 */\r
+#define OFS_PM5CTL0_L OFS_PM5CTL0\r
+#define OFS_PM5CTL0_H OFS_PM5CTL0+1\r
+\r
+#define PMMPW (0xA500u) /* PMM Register Write Password */\r
+#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */\r
+\r
+/* PMMCTL0 Control Bits */\r
+#define PMMSWBOR (0x0004u) /* PMM Software BOR */\r
+#define PMMSWPOR (0x0008u) /* PMM Software POR */\r
+#define PMMREGOFF (0x0010u) /* PMM Turn Regulator off */\r
+#define SVSHE (0x0040u) /* SVS high side enable */\r
+#define PMMLPRST (0x0080u) /* PMM Low-Power Reset Enable */\r
+\r
+/* PMMCTL0 Control Bits */\r
+#define PMMSWBOR_L (0x0004u) /* PMM Software BOR */\r
+#define PMMSWPOR_L (0x0008u) /* PMM Software POR */\r
+#define PMMREGOFF_L (0x0010u) /* PMM Turn Regulator off */\r
+#define SVSHE_L (0x0040u) /* SVS high side enable */\r
+#define PMMLPRST_L (0x0080u) /* PMM Low-Power Reset Enable */\r
+\r
+/* PMMCTL1 Control Bits */\r
+#define PMMLPSVEN (0x0002u) /* PMM Low-Power Supervision Enable */\r
+#define PMMLPRNG0 (0x0004u) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 0 */\r
+#define PMMLPRNG1 (0x0008u) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 1 */\r
+#define PMMAMRNG0 (0x0010u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 0 */\r
+#define PMMAMRNG1 (0x0020u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 1 */\r
+#define PMMAMRNG2 (0x0040u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 2 */\r
+#define PMMAMRNG3 (0x0080u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 3 */\r
+#define PMMCTL1KEY (0xCC00u) /* PMM PMMCTL1 Register Write Password */\r
+\r
+/* PMMIFG Control Bits */\r
+#define PMMBORIFG (0x0100u) /* PMM Software BOR interrupt flag */\r
+#define PMMRSTIFG (0x0200u) /* PMM RESET pin interrupt flag */\r
+#define PMMPORIFG (0x0400u) /* PMM Software POR interrupt flag */\r
+#define SVSHIFG (0x2000u) /* SVS low side interrupt flag */\r
+#define PMMLPM5IFG (0x8000u) /* LPM5 indication Flag */\r
+\r
+/* PMMIFG Control Bits */\r
+#define PMMBORIFG_H (0x0001u) /* PMM Software BOR interrupt flag */\r
+#define PMMRSTIFG_H (0x0002u) /* PMM RESET pin interrupt flag */\r
+#define PMMPORIFG_H (0x0004u) /* PMM Software POR interrupt flag */\r
+#define SVSHIFG_H (0x0020u) /* SVS low side interrupt flag */\r
+#define PMMLPM5IFG_H (0x0080u) /* LPM5 indication Flag */\r
+\r
+/* PM5CTL0 Power Mode 5 Control Bits */\r
+#define LOCKLPM5 (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */\r
+\r
+/* PM5CTL0 Power Mode 5 Control Bits */\r
+#define LOCKLPM5_L (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */\r
+\r
+\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port1/2 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PAIN (0x0000u) /* Port A Input */\r
+#define OFS_PAIN_L OFS_PAIN\r
+#define OFS_PAIN_H OFS_PAIN+1\r
+#define OFS_PAOUT (0x0002u) /* Port A Output */\r
+#define OFS_PAOUT_L OFS_PAOUT\r
+#define OFS_PAOUT_H OFS_PAOUT+1\r
+#define OFS_PADIR (0x0004u) /* Port A Direction */\r
+#define OFS_PADIR_L OFS_PADIR\r
+#define OFS_PADIR_H OFS_PADIR+1\r
+#define OFS_PAREN (0x0006u) /* Port A Resistor Enable */\r
+#define OFS_PAREN_L OFS_PAREN\r
+#define OFS_PAREN_H OFS_PAREN+1\r
+#define OFS_PASEL0 (0x000Au) /* Port A Selection 0 */\r
+#define OFS_PASEL0_L OFS_PASEL0\r
+#define OFS_PASEL0_H OFS_PASEL0+1\r
+#define OFS_PASEL1 (0x000Cu) /* Port A Selection 1 */\r
+#define OFS_PASEL1_L OFS_PASEL1\r
+#define OFS_PASEL1_H OFS_PASEL1+1\r
+#define OFS_PASELC (0x0016u) /* Port A Complement Selection */\r
+#define OFS_PASELC_L OFS_PASELC\r
+#define OFS_PASELC_H OFS_PASELC+1\r
+#define OFS_PAIES (0x0018u) /* Port A Interrupt Edge Select */\r
+#define OFS_PAIES_L OFS_PAIES\r
+#define OFS_PAIES_H OFS_PAIES+1\r
+#define OFS_PAIE (0x001Au) /* Port A Interrupt Enable */\r
+#define OFS_PAIE_L OFS_PAIE\r
+#define OFS_PAIE_H OFS_PAIE+1\r
+#define OFS_PAIFG (0x001Cu) /* Port A Interrupt Flag */\r
+#define OFS_PAIFG_L OFS_PAIFG\r
+#define OFS_PAIFG_H OFS_PAIFG+1\r
+\r
+\r
+#define OFS_P1IN (0x0000u)\r
+#define OFS_P1OUT (0x0002u)\r
+#define OFS_P1DIR (0x0004u)\r
+#define OFS_P1REN (0x0006u)\r
+#define OFS_P1SEL0 (0x000Au)\r
+#define OFS_P1SEL1 (0x000Cu)\r
+#define OFS_P1SELC (0x0016u)\r
+#define OFS_P1IV (0x000Eu) /* Port 1 Interrupt Vector Word */\r
+#define OFS_P1IES (0x0018u)\r
+#define OFS_P1IE (0x001Au)\r
+#define OFS_P1IFG (0x001Cu)\r
+#define OFS_P2IN (0x0001u)\r
+#define OFS_P2OUT (0x0003u)\r
+#define OFS_P2DIR (0x0005u)\r
+#define OFS_P2REN (0x0007u)\r
+#define OFS_P2SEL0 (0x000Bu)\r
+#define OFS_P2SEL1 (0x000Du)\r
+#define OFS_P2SELC (0x0017u)\r
+#define OFS_P2IV (0x001Eu) /* Port 2 Interrupt Vector Word */\r
+#define OFS_P2IES (0x0019u)\r
+#define OFS_P2IE (0x001Bu)\r
+#define OFS_P2IFG (0x001du)\r
+#define P1IN (PAIN_L) /* Port 1 Input */\r
+#define P1OUT (PAOUT_L) /* Port 1 Output */\r
+#define P1DIR (PADIR_L) /* Port 1 Direction */\r
+#define P1REN (PAREN_L) /* Port 1 Resistor Enable */\r
+#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */\r
+#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */\r
+#define P1SELC (PASELC_L) /* Port 1 Complement Selection */\r
+#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */\r
+#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */\r
+#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */\r
+\r
+//Definitions for P1IV\r
+#define P1IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P1IV_P1IFG0 (0x0002u) /* P1IV P1IFG.0 */\r
+#define P1IV_P1IFG1 (0x0004u) /* P1IV P1IFG.1 */\r
+#define P1IV_P1IFG2 (0x0006u) /* P1IV P1IFG.2 */\r
+#define P1IV_P1IFG3 (0x0008u) /* P1IV P1IFG.3 */\r
+#define P1IV_P1IFG4 (0x000Au) /* P1IV P1IFG.4 */\r
+#define P1IV_P1IFG5 (0x000Cu) /* P1IV P1IFG.5 */\r
+#define P1IV_P1IFG6 (0x000Eu) /* P1IV P1IFG.6 */\r
+#define P1IV_P1IFG7 (0x0010u) /* P1IV P1IFG.7 */\r
+\r
+#define P2IN (PAIN_H) /* Port 2 Input */\r
+#define P2OUT (PAOUT_H) /* Port 2 Output */\r
+#define P2DIR (PADIR_H) /* Port 2 Direction */\r
+#define P2REN (PAREN_H) /* Port 2 Resistor Enable */\r
+#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */\r
+#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */\r
+#define P2SELC (PASELC_H) /* Port 2 Complement Selection */\r
+#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */\r
+#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */\r
+#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */\r
+\r
+//Definitions for P2IV\r
+#define P2IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P2IV_P2IFG0 (0x0002u) /* P2IV P2IFG.0 */\r
+#define P2IV_P2IFG1 (0x0004u) /* P2IV P2IFG.1 */\r
+#define P2IV_P2IFG2 (0x0006u) /* P2IV P2IFG.2 */\r
+#define P2IV_P2IFG3 (0x0008u) /* P2IV P2IFG.3 */\r
+#define P2IV_P2IFG4 (0x000Au) /* P2IV P2IFG.4 */\r
+#define P2IV_P2IFG5 (0x000Cu) /* P2IV P2IFG.5 */\r
+#define P2IV_P2IFG6 (0x000Eu) /* P2IV P2IFG.6 */\r
+#define P2IV_P2IFG7 (0x0010u) /* P2IV P2IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port3/4 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PBIN (0x0000u) /* Port B Input */\r
+#define OFS_PBIN_L OFS_PBIN\r
+#define OFS_PBIN_H OFS_PBIN+1\r
+#define OFS_PBOUT (0x0002u) /* Port B Output */\r
+#define OFS_PBOUT_L OFS_PBOUT\r
+#define OFS_PBOUT_H OFS_PBOUT+1\r
+#define OFS_PBDIR (0x0004u) /* Port B Direction */\r
+#define OFS_PBDIR_L OFS_PBDIR\r
+#define OFS_PBDIR_H OFS_PBDIR+1\r
+#define OFS_PBREN (0x0006u) /* Port B Resistor Enable */\r
+#define OFS_PBREN_L OFS_PBREN\r
+#define OFS_PBREN_H OFS_PBREN+1\r
+#define OFS_PBSEL0 (0x000Au) /* Port B Selection 0 */\r
+#define OFS_PBSEL0_L OFS_PBSEL0\r
+#define OFS_PBSEL0_H OFS_PBSEL0+1\r
+#define OFS_PBSEL1 (0x000Cu) /* Port B Selection 1 */\r
+#define OFS_PBSEL1_L OFS_PBSEL1\r
+#define OFS_PBSEL1_H OFS_PBSEL1+1\r
+#define OFS_PBSELC (0x0016u) /* Port B Complement Selection */\r
+#define OFS_PBSELC_L OFS_PBSELC\r
+#define OFS_PBSELC_H OFS_PBSELC+1\r
+#define OFS_PBIES (0x0018u) /* Port B Interrupt Edge Select */\r
+#define OFS_PBIES_L OFS_PBIES\r
+#define OFS_PBIES_H OFS_PBIES+1\r
+#define OFS_PBIE (0x001Au) /* Port B Interrupt Enable */\r
+#define OFS_PBIE_L OFS_PBIE\r
+#define OFS_PBIE_H OFS_PBIE+1\r
+#define OFS_PBIFG (0x001Cu) /* Port B Interrupt Flag */\r
+#define OFS_PBIFG_L OFS_PBIFG\r
+#define OFS_PBIFG_H OFS_PBIFG+1\r
+\r
+\r
+#define OFS_P3IN (0x0000u)\r
+#define OFS_P3OUT (0x0002u)\r
+#define OFS_P3DIR (0x0004u)\r
+#define OFS_P3REN (0x0006u)\r
+#define OFS_P3SEL0 (0x000Au)\r
+#define OFS_P3SEL1 (0x000Cu)\r
+#define OFS_P3SELC (0x0016u)\r
+#define OFS_P3IV (0x000Eu) /* Port 3 Interrupt Vector Word */\r
+#define OFS_P3IES (0x0018u)\r
+#define OFS_P3IE (0x001Au)\r
+#define OFS_P3IFG (0x001Cu)\r
+#define OFS_P4IN (0x0001u)\r
+#define OFS_P4OUT (0x0003u)\r
+#define OFS_P4DIR (0x0005u)\r
+#define OFS_P4REN (0x0007u)\r
+#define OFS_P4SEL0 (0x000Bu)\r
+#define OFS_P4SEL1 (0x000Du)\r
+#define OFS_P4SELC (0x0017u)\r
+#define OFS_P4IV (0x001Eu) /* Port 4 Interrupt Vector Word */\r
+#define OFS_P4IES (0x0019u)\r
+#define OFS_P4IE (0x001Bu)\r
+#define OFS_P4IFG (0x001du)\r
+#define P3IN (PBIN_L) /* Port 3 Input */\r
+#define P3OUT (PBOUT_L) /* Port 3 Output */\r
+#define P3DIR (PBDIR_L) /* Port 3 Direction */\r
+#define P3REN (PBREN_L) /* Port 3 Resistor Enable */\r
+#define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */\r
+#define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */\r
+#define P3SELC (PBSELC_L) /* Port 3 Complement Selection */\r
+#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */\r
+#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */\r
+#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */\r
+\r
+//Definitions for P3IV\r
+#define P3IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P3IV_P3IFG0 (0x0002u) /* P3IV P3IFG.0 */\r
+#define P3IV_P3IFG1 (0x0004u) /* P3IV P3IFG.1 */\r
+#define P3IV_P3IFG2 (0x0006u) /* P3IV P3IFG.2 */\r
+#define P3IV_P3IFG3 (0x0008u) /* P3IV P3IFG.3 */\r
+#define P3IV_P3IFG4 (0x000Au) /* P3IV P3IFG.4 */\r
+#define P3IV_P3IFG5 (0x000Cu) /* P3IV P3IFG.5 */\r
+#define P3IV_P3IFG6 (0x000Eu) /* P3IV P3IFG.6 */\r
+#define P3IV_P3IFG7 (0x0010u) /* P3IV P3IFG.7 */\r
+\r
+#define P4IN (PBIN_H) /* Port 4 Input */\r
+#define P4OUT (PBOUT_H) /* Port 4 Output */\r
+#define P4DIR (PBDIR_H) /* Port 4 Direction */\r
+#define P4REN (PBREN_H) /* Port 4 Resistor Enable */\r
+#define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */\r
+#define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */\r
+#define P4SELC (PBSELC_H) /* Port 4 Complement Selection */\r
+#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */\r
+#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */\r
+#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */\r
+\r
+//Definitions for P4IV\r
+#define P4IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P4IV_P4IFG0 (0x0002u) /* P4IV P4IFG.0 */\r
+#define P4IV_P4IFG1 (0x0004u) /* P4IV P4IFG.1 */\r
+#define P4IV_P4IFG2 (0x0006u) /* P4IV P4IFG.2 */\r
+#define P4IV_P4IFG3 (0x0008u) /* P4IV P4IFG.3 */\r
+#define P4IV_P4IFG4 (0x000Au) /* P4IV P4IFG.4 */\r
+#define P4IV_P4IFG5 (0x000Cu) /* P4IV P4IFG.5 */\r
+#define P4IV_P4IFG6 (0x000Eu) /* P4IV P4IFG.6 */\r
+#define P4IV_P4IFG7 (0x0010u) /* P4IV P4IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port5/6 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PCIN (0x0000u) /* Port C Input */\r
+#define OFS_PCIN_L OFS_PCIN\r
+#define OFS_PCIN_H OFS_PCIN+1\r
+#define OFS_PCOUT (0x0002u) /* Port C Output */\r
+#define OFS_PCOUT_L OFS_PCOUT\r
+#define OFS_PCOUT_H OFS_PCOUT+1\r
+#define OFS_PCDIR (0x0004u) /* Port C Direction */\r
+#define OFS_PCDIR_L OFS_PCDIR\r
+#define OFS_PCDIR_H OFS_PCDIR+1\r
+#define OFS_PCREN (0x0006u) /* Port C Resistor Enable */\r
+#define OFS_PCREN_L OFS_PCREN\r
+#define OFS_PCREN_H OFS_PCREN+1\r
+#define OFS_PCSEL0 (0x000Au) /* Port C Selection 0 */\r
+#define OFS_PCSEL0_L OFS_PCSEL0\r
+#define OFS_PCSEL0_H OFS_PCSEL0+1\r
+#define OFS_PCSEL1 (0x000Cu) /* Port C Selection 1 */\r
+#define OFS_PCSEL1_L OFS_PCSEL1\r
+#define OFS_PCSEL1_H OFS_PCSEL1+1\r
+#define OFS_PCSELC (0x0016u) /* Port C Complement Selection */\r
+#define OFS_PCSELC_L OFS_PCSELC\r
+#define OFS_PCSELC_H OFS_PCSELC+1\r
+#define OFS_PCIES (0x0018u) /* Port C Interrupt Edge Select */\r
+#define OFS_PCIES_L OFS_PCIES\r
+#define OFS_PCIES_H OFS_PCIES+1\r
+#define OFS_PCIE (0x001Au) /* Port C Interrupt Enable */\r
+#define OFS_PCIE_L OFS_PCIE\r
+#define OFS_PCIE_H OFS_PCIE+1\r
+#define OFS_PCIFG (0x001Cu) /* Port C Interrupt Flag */\r
+#define OFS_PCIFG_L OFS_PCIFG\r
+#define OFS_PCIFG_H OFS_PCIFG+1\r
+\r
+\r
+#define OFS_P5IN (0x0000u)\r
+#define OFS_P5OUT (0x0002u)\r
+#define OFS_P5DIR (0x0004u)\r
+#define OFS_P5REN (0x0006u)\r
+#define OFS_P5SEL0 (0x000Au)\r
+#define OFS_P5SEL1 (0x000Cu)\r
+#define OFS_P5SELC (0x0016u)\r
+#define OFS_P5IV (0x000Eu) /* Port 5 Interrupt Vector Word */\r
+#define OFS_P5IES (0x0018u)\r
+#define OFS_P5IE (0x001Au)\r
+#define OFS_P5IFG (0x001Cu)\r
+#define OFS_P6IN (0x0001u)\r
+#define OFS_P6OUT (0x0003u)\r
+#define OFS_P6DIR (0x0005u)\r
+#define OFS_P6REN (0x0007u)\r
+#define OFS_P6SEL0 (0x000Bu)\r
+#define OFS_P6SEL1 (0x000Du)\r
+#define OFS_P6SELC (0x0017u)\r
+#define OFS_P6IV (0x001Eu) /* Port 6 Interrupt Vector Word */\r
+#define OFS_P6IES (0x0019u)\r
+#define OFS_P6IE (0x001Bu)\r
+#define OFS_P6IFG (0x001du)\r
+#define P5IN (PCIN_L) /* Port 5 Input */\r
+#define P5OUT (PCOUT_L) /* Port 5 Output */\r
+#define P5DIR (PCDIR_L) /* Port 5 Direction */\r
+#define P5REN (PCREN_L) /* Port 5 Resistor Enable */\r
+#define P5SEL0 (PCSEL0_L) /* Port 5 Selection 0 */\r
+#define P5SEL1 (PCSEL1_L) /* Port 5 Selection 1 */\r
+#define P5SELC (PCSELC_L) /* Port 5 Complement Selection */\r
+#define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */\r
+#define P5IE (PCIE_L) /* Port 5 Interrupt Enable */\r
+#define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */\r
+\r
+//Definitions for P5IV\r
+#define P5IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P5IV_P5IFG0 (0x0002u) /* P5IV P5IFG.0 */\r
+#define P5IV_P5IFG1 (0x0004u) /* P5IV P5IFG.1 */\r
+#define P5IV_P5IFG2 (0x0006u) /* P5IV P5IFG.2 */\r
+#define P5IV_P5IFG3 (0x0008u) /* P5IV P5IFG.3 */\r
+#define P5IV_P5IFG4 (0x000Au) /* P5IV P5IFG.4 */\r
+#define P5IV_P5IFG5 (0x000Cu) /* P5IV P5IFG.5 */\r
+#define P5IV_P5IFG6 (0x000Eu) /* P5IV P5IFG.6 */\r
+#define P5IV_P5IFG7 (0x0010u) /* P5IV P5IFG.7 */\r
+\r
+#define P6IN (PCIN_H) /* Port 6 Input */\r
+#define P6OUT (PCOUT_H) /* Port 6 Output */\r
+#define P6DIR (PCDIR_H) /* Port 6 Direction */\r
+#define P6REN (PCREN_H) /* Port 6 Resistor Enable */\r
+#define P6SEL0 (PCSEL0_H) /* Port 6 Selection 0 */\r
+#define P6SEL1 (PCSEL1_H) /* Port 6 Selection 1 */\r
+#define P6SELC (PCSELC_H) /* Port 6 Complement Selection */\r
+#define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */\r
+#define P6IE (PCIE_H) /* Port 6 Interrupt Enable */\r
+#define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */\r
+\r
+//Definitions for P6IV\r
+#define P6IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P6IV_P6IFG0 (0x0002u) /* P6IV P6IFG.0 */\r
+#define P6IV_P6IFG1 (0x0004u) /* P6IV P6IFG.1 */\r
+#define P6IV_P6IFG2 (0x0006u) /* P6IV P6IFG.2 */\r
+#define P6IV_P6IFG3 (0x0008u) /* P6IV P6IFG.3 */\r
+#define P6IV_P6IFG4 (0x000Au) /* P6IV P6IFG.4 */\r
+#define P6IV_P6IFG5 (0x000Cu) /* P6IV P6IFG.5 */\r
+#define P6IV_P6IFG6 (0x000Eu) /* P6IV P6IFG.6 */\r
+#define P6IV_P6IFG7 (0x0010u) /* P6IV P6IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port7/8 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PDIN (0x0000u) /* Port D Input */\r
+#define OFS_PDIN_L OFS_PDIN\r
+#define OFS_PDIN_H OFS_PDIN+1\r
+#define OFS_PDOUT (0x0002u) /* Port D Output */\r
+#define OFS_PDOUT_L OFS_PDOUT\r
+#define OFS_PDOUT_H OFS_PDOUT+1\r
+#define OFS_PDDIR (0x0004u) /* Port D Direction */\r
+#define OFS_PDDIR_L OFS_PDDIR\r
+#define OFS_PDDIR_H OFS_PDDIR+1\r
+#define OFS_PDREN (0x0006u) /* Port D Resistor Enable */\r
+#define OFS_PDREN_L OFS_PDREN\r
+#define OFS_PDREN_H OFS_PDREN+1\r
+#define OFS_PDSEL0 (0x000Au) /* Port D Selection 0 */\r
+#define OFS_PDSEL0_L OFS_PDSEL0\r
+#define OFS_PDSEL0_H OFS_PDSEL0+1\r
+#define OFS_PDSEL1 (0x000Cu) /* Port D Selection 1 */\r
+#define OFS_PDSEL1_L OFS_PDSEL1\r
+#define OFS_PDSEL1_H OFS_PDSEL1+1\r
+#define OFS_PDSELC (0x0016u) /* Port D Complement Selection */\r
+#define OFS_PDSELC_L OFS_PDSELC\r
+#define OFS_PDSELC_H OFS_PDSELC+1\r
+#define OFS_PDIES (0x0018u) /* Port D Interrupt Edge Select */\r
+#define OFS_PDIES_L OFS_PDIES\r
+#define OFS_PDIES_H OFS_PDIES+1\r
+#define OFS_PDIE (0x001Au) /* Port D Interrupt Enable */\r
+#define OFS_PDIE_L OFS_PDIE\r
+#define OFS_PDIE_H OFS_PDIE+1\r
+#define OFS_PDIFG (0x001Cu) /* Port D Interrupt Flag */\r
+#define OFS_PDIFG_L OFS_PDIFG\r
+#define OFS_PDIFG_H OFS_PDIFG+1\r
+\r
+\r
+#define OFS_P7IN (0x0000u)\r
+#define OFS_P7OUT (0x0002u)\r
+#define OFS_P7DIR (0x0004u)\r
+#define OFS_P7REN (0x0006u)\r
+#define OFS_P7SEL0 (0x000Au)\r
+#define OFS_P7SEL1 (0x000Cu)\r
+#define OFS_P7SELC (0x0016u)\r
+#define OFS_P7IV (0x000Eu) /* Port 7 Interrupt Vector Word */\r
+#define OFS_P7IES (0x0018u)\r
+#define OFS_P7IE (0x001Au)\r
+#define OFS_P7IFG (0x001Cu)\r
+#define OFS_P8IN (0x0001u)\r
+#define OFS_P8OUT (0x0003u)\r
+#define OFS_P8DIR (0x0005u)\r
+#define OFS_P8REN (0x0007u)\r
+#define OFS_P8SEL0 (0x000Bu)\r
+#define OFS_P8SEL1 (0x000Du)\r
+#define OFS_P8SELC (0x0017u)\r
+#define OFS_P8IV (0x001Eu) /* Port 8 Interrupt Vector Word */\r
+#define OFS_P8IES (0x0019u)\r
+#define OFS_P8IE (0x001Bu)\r
+#define OFS_P8IFG (0x001du)\r
+#define P7IN (PDIN_L) /* Port 7 Input */\r
+#define P7OUT (PDOUT_L) /* Port 7 Output */\r
+#define P7DIR (PDDIR_L) /* Port 7 Direction */\r
+#define P7REN (PDREN_L) /* Port 7 Resistor Enable */\r
+#define P7SEL0 (PDSEL0_L) /* Port 7 Selection 0 */\r
+#define P7SEL1 (PDSEL1_L) /* Port 7 Selection 1 */\r
+#define P7SELC (PDSELC_L) /* Port 7 Complement Selection */\r
+#define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */\r
+#define P7IE (PDIE_L) /* Port 7 Interrupt Enable */\r
+#define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */\r
+\r
+//Definitions for P7IV\r
+#define P7IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P7IV_P7IFG0 (0x0002u) /* P7IV P7IFG.0 */\r
+#define P7IV_P7IFG1 (0x0004u) /* P7IV P7IFG.1 */\r
+#define P7IV_P7IFG2 (0x0006u) /* P7IV P7IFG.2 */\r
+#define P7IV_P7IFG3 (0x0008u) /* P7IV P7IFG.3 */\r
+#define P7IV_P7IFG4 (0x000Au) /* P7IV P7IFG.4 */\r
+#define P7IV_P7IFG5 (0x000Cu) /* P7IV P7IFG.5 */\r
+#define P7IV_P7IFG6 (0x000Eu) /* P7IV P7IFG.6 */\r
+#define P7IV_P7IFG7 (0x0010u) /* P7IV P7IFG.7 */\r
+\r
+#define P8IN (PDIN_H) /* Port 8 Input */\r
+#define P8OUT (PDOUT_H) /* Port 8 Output */\r
+#define P8DIR (PDDIR_H) /* Port 8 Direction */\r
+#define P8REN (PDREN_H) /* Port 8 Resistor Enable */\r
+#define P8SEL0 (PDSEL0_H) /* Port 8 Selection 0 */\r
+#define P8SEL1 (PDSEL1_H) /* Port 8 Selection 1 */\r
+#define P8SELC (PDSELC_H) /* Port 8 Complement Selection */\r
+#define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */\r
+#define P8IE (PDIE_H) /* Port 8 Interrupt Enable */\r
+#define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */\r
+\r
+//Definitions for P8IV\r
+#define P8IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P8IV_P8IFG0 (0x0002u) /* P8IV P8IFG.0 */\r
+#define P8IV_P8IFG1 (0x0004u) /* P8IV P8IFG.1 */\r
+#define P8IV_P8IFG2 (0x0006u) /* P8IV P8IFG.2 */\r
+#define P8IV_P8IFG3 (0x0008u) /* P8IV P8IFG.3 */\r
+#define P8IV_P8IFG4 (0x000Au) /* P8IV P8IFG.4 */\r
+#define P8IV_P8IFG5 (0x000Cu) /* P8IV P8IFG.5 */\r
+#define P8IV_P8IFG6 (0x000Eu) /* P8IV P8IFG.6 */\r
+#define P8IV_P8IFG7 (0x0010u) /* P8IV P8IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port9/10 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PEIN (0x0000u) /* Port E Input */\r
+#define OFS_PEIN_L OFS_PEIN\r
+#define OFS_PEIN_H OFS_PEIN+1\r
+#define OFS_PEOUT (0x0002u) /* Port E Output */\r
+#define OFS_PEOUT_L OFS_PEOUT\r
+#define OFS_PEOUT_H OFS_PEOUT+1\r
+#define OFS_PEDIR (0x0004u) /* Port E Direction */\r
+#define OFS_PEDIR_L OFS_PEDIR\r
+#define OFS_PEDIR_H OFS_PEDIR+1\r
+#define OFS_PEREN (0x0006u) /* Port E Resistor Enable */\r
+#define OFS_PEREN_L OFS_PEREN\r
+#define OFS_PEREN_H OFS_PEREN+1\r
+#define OFS_PESEL0 (0x000Au) /* Port E Selection 0 */\r
+#define OFS_PESEL0_L OFS_PESEL0\r
+#define OFS_PESEL0_H OFS_PESEL0+1\r
+#define OFS_PESEL1 (0x000Cu) /* Port E Selection 1 */\r
+#define OFS_PESEL1_L OFS_PESEL1\r
+#define OFS_PESEL1_H OFS_PESEL1+1\r
+#define OFS_PESELC (0x0016u) /* Port E Complement Selection */\r
+#define OFS_PESELC_L OFS_PESELC\r
+#define OFS_PESELC_H OFS_PESELC+1\r
+#define OFS_PEIES (0x0018u) /* Port E Interrupt Edge Select */\r
+#define OFS_PEIES_L OFS_PEIES\r
+#define OFS_PEIES_H OFS_PEIES+1\r
+#define OFS_PEIE (0x001Au) /* Port E Interrupt Enable */\r
+#define OFS_PEIE_L OFS_PEIE\r
+#define OFS_PEIE_H OFS_PEIE+1\r
+#define OFS_PEIFG (0x001Cu) /* Port E Interrupt Flag */\r
+#define OFS_PEIFG_L OFS_PEIFG\r
+#define OFS_PEIFG_H OFS_PEIFG+1\r
+\r
+\r
+#define OFS_P9IN (0x0000u)\r
+#define OFS_P9OUT (0x0002u)\r
+#define OFS_P9DIR (0x0004u)\r
+#define OFS_P9REN (0x0006u)\r
+#define OFS_P9SEL0 (0x000Au)\r
+#define OFS_P9SEL1 (0x000Cu)\r
+#define OFS_P9SELC (0x0016u)\r
+#define OFS_P9IV (0x000Eu) /* Port 9 Interrupt Vector Word */\r
+#define OFS_P9IES (0x0018u)\r
+#define OFS_P9IE (0x001Au)\r
+#define OFS_P9IFG (0x001Cu)\r
+#define OFS_P10IN (0x0001u)\r
+#define OFS_P10OUT (0x0003u)\r
+#define OFS_P10DIR (0x0005u)\r
+#define OFS_P10REN (0x0007u)\r
+#define OFS_P10SEL0 (0x000Bu)\r
+#define OFS_P10SEL1 (0x000Du)\r
+#define OFS_P10SELC (0x0017u)\r
+#define OFS_P10IV (0x001Eu) /* Port 10 Interrupt Vector Word */\r
+#define OFS_P10IES (0x0019u)\r
+#define OFS_P10IE (0x001Bu)\r
+#define OFS_P10IFG (0x001du)\r
+#define P9IN (PEIN_L) /* Port 9 Input */\r
+#define P9OUT (PEOUT_L) /* Port 9 Output */\r
+#define P9DIR (PEDIR_L) /* Port 9 Direction */\r
+#define P9REN (PEREN_L) /* Port 9 Resistor Enable */\r
+#define P9SEL0 (PESEL0_L) /* Port 9 Selection 0 */\r
+#define P9SEL1 (PESEL1_L) /* Port 9 Selection 1 */\r
+#define P9SELC (PESELC_L) /* Port 9 Complement Selection */\r
+#define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */\r
+#define P9IE (PEIE_L) /* Port 9 Interrupt Enable */\r
+#define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */\r
+\r
+//Definitions for P9IV\r
+#define P9IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P9IV_P9IFG0 (0x0002u) /* P9IV P9IFG.0 */\r
+#define P9IV_P9IFG1 (0x0004u) /* P9IV P9IFG.1 */\r
+#define P9IV_P9IFG2 (0x0006u) /* P9IV P9IFG.2 */\r
+#define P9IV_P9IFG3 (0x0008u) /* P9IV P9IFG.3 */\r
+#define P9IV_P9IFG4 (0x000Au) /* P9IV P9IFG.4 */\r
+#define P9IV_P9IFG5 (0x000Cu) /* P9IV P9IFG.5 */\r
+#define P9IV_P9IFG6 (0x000Eu) /* P9IV P9IFG.6 */\r
+#define P9IV_P9IFG7 (0x0010u) /* P9IV P9IFG.7 */\r
+\r
+#define P10IN (PEIN_H) /* Port 10 Input */\r
+#define P10OUT (PEOUT_H) /* Port 10 Output */\r
+#define P10DIR (PEDIR_H) /* Port 10 Direction */\r
+#define P10REN (PEREN_H) /* Port 10 Resistor Enable */\r
+#define P10SEL0 (PESEL0_H) /* Port 10 Selection 0 */\r
+#define P10SEL1 (PESEL1_H) /* Port 10 Selection 1 */\r
+#define P10SELC (PESELC_H) /* Port 10 Complement Selection */\r
+#define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */\r
+#define P10IE (PEIE_H) /* Port 10 Interrupt Enable */\r
+#define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */\r
+\r
+//Definitions for P10IV\r
+#define P10IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P10IV_P10IFG0 (0x0002u) /* P10IV P10IFG.0 */\r
+#define P10IV_P10IFG1 (0x0004u) /* P10IV P10IFG.1 */\r
+#define P10IV_P10IFG2 (0x0006u) /* P10IV P10IFG.2 */\r
+#define P10IV_P10IFG3 (0x0008u) /* P10IV P10IFG.3 */\r
+#define P10IV_P10IFG4 (0x000Au) /* P10IV P10IFG.4 */\r
+#define P10IV_P10IFG5 (0x000Cu) /* P10IV P10IFG.5 */\r
+#define P10IV_P10IFG6 (0x000Eu) /* P10IV P10IFG.6 */\r
+#define P10IV_P10IFG7 (0x0010u) /* P10IV P10IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port11 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PFIN (0x0000u) /* Port F Input */\r
+#define OFS_PFIN_L OFS_PFIN\r
+#define OFS_PFIN_H OFS_PFIN+1\r
+#define OFS_PFOUT (0x0002u) /* Port F Output */\r
+#define OFS_PFOUT_L OFS_PFOUT\r
+#define OFS_PFOUT_H OFS_PFOUT+1\r
+#define OFS_PFDIR (0x0004u) /* Port F Direction */\r
+#define OFS_PFDIR_L OFS_PFDIR\r
+#define OFS_PFDIR_H OFS_PFDIR+1\r
+#define OFS_PFREN (0x0006u) /* Port F Resistor Enable */\r
+#define OFS_PFREN_L OFS_PFREN\r
+#define OFS_PFREN_H OFS_PFREN+1\r
+#define OFS_PFSEL0 (0x000Au) /* Port F Selection 0 */\r
+#define OFS_PFSEL0_L OFS_PFSEL0\r
+#define OFS_PFSEL0_H OFS_PFSEL0+1\r
+#define OFS_PFSEL1 (0x000Cu) /* Port F Selection 1 */\r
+#define OFS_PFSEL1_L OFS_PFSEL1\r
+#define OFS_PFSEL1_H OFS_PFSEL1+1\r
+#define OFS_PFSELC (0x0016u) /* Port F Complement Selection */\r
+#define OFS_PFSELC_L OFS_PFSELC\r
+#define OFS_PFSELC_H OFS_PFSELC+1\r
+#define OFS_PFIES (0x0018u) /* Port F Interrupt Edge Select */\r
+#define OFS_PFIES_L OFS_PFIES\r
+#define OFS_PFIES_H OFS_PFIES+1\r
+#define OFS_PFIE (0x001Au) /* Port F Interrupt Enable */\r
+#define OFS_PFIE_L OFS_PFIE\r
+#define OFS_PFIE_H OFS_PFIE+1\r
+#define OFS_PFIFG (0x001Cu) /* Port F Interrupt Flag */\r
+#define OFS_PFIFG_L OFS_PFIFG\r
+#define OFS_PFIFG_H OFS_PFIFG+1\r
+\r
+\r
+#define OFS_P11IN (0x0000u)\r
+#define OFS_P11OUT (0x0002u)\r
+#define OFS_P11DIR (0x0004u)\r
+#define OFS_P11REN (0x0006u)\r
+#define OFS_P11SEL0 (0x000Au)\r
+#define OFS_P11SEL1 (0x000Cu)\r
+#define OFS_P11SELC (0x0016u)\r
+#define OFS_P11IV (0x000Eu) /* Port 11 Interrupt Vector Word */\r
+#define OFS_P11IES (0x0018u)\r
+#define OFS_P11IE (0x001Au)\r
+#define OFS_P11IFG (0x001Cu)\r
+#define P11IN (PFIN_L) /* Port 11 Input */\r
+#define P11OUT (PFOUT_L) /* Port 11 Output */\r
+#define P11DIR (PFDIR_L) /* Port 11 Direction */\r
+#define P11REN (PFREN_L) /* Port 11 Resistor Enable */\r
+#define P11SEL0 (PFSEL0_L) /* Port 11 Selection0 */\r
+#define P11SEL1 (PFSEL1_L) /* Port 11 Selection1 */\r
+#define OFS_P11SELC (0x0017u)\r
+\r
+#define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */\r
+#define P11IE (PFIE_L) /* Port 11 Interrupt Enable */\r
+#define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */\r
+\r
+//Definitions for P11IV\r
+#define P11IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P11IV_P11IFG0 (0x0002u) /* P11IV P11IFG.0 */\r
+#define P11IV_P11IFG1 (0x0004u) /* P11IV P11IFG.1 */\r
+#define P11IV_P11IFG2 (0x0006u) /* P11IV P11IFG.2 */\r
+#define P11IV_P11IFG3 (0x0008u) /* P11IV P11IFG.3 */\r
+#define P11IV_P11IFG4 (0x000Au) /* P11IV P11IFG.4 */\r
+#define P11IV_P11IFG5 (0x000Cu) /* P11IV P11IFG.5 */\r
+#define P11IV_P11IFG6 (0x000Eu) /* P11IV P11IFG.6 */\r
+#define P11IV_P11IFG7 (0x0010u) /* P11IV P11IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O PortJ Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PJIN (0x0000u) /* Port J Input */\r
+#define OFS_PJIN_L OFS_PJIN\r
+#define OFS_PJIN_H OFS_PJIN+1\r
+#define OFS_PJOUT (0x0002u) /* Port J Output */\r
+#define OFS_PJOUT_L OFS_PJOUT\r
+#define OFS_PJOUT_H OFS_PJOUT+1\r
+#define OFS_PJDIR (0x0004u) /* Port J Direction */\r
+#define OFS_PJDIR_L OFS_PJDIR\r
+#define OFS_PJDIR_H OFS_PJDIR+1\r
+#define OFS_PJREN (0x0006u) /* Port J Resistor Enable */\r
+#define OFS_PJREN_L OFS_PJREN\r
+#define OFS_PJREN_H OFS_PJREN+1\r
+#define OFS_PJSEL0 (0x000Au) /* Port J Selection 0 */\r
+#define OFS_PJSEL0_L OFS_PJSEL0\r
+#define OFS_PJSEL0_H OFS_PJSEL0+1\r
+#define OFS_PJSEL1 (0x000Cu) /* Port J Selection 1 */\r
+#define OFS_PJSEL1_L OFS_PJSEL1\r
+#define OFS_PJSEL1_H OFS_PJSEL1+1\r
+#define OFS_PJSELC (0x0016u) /* Port J Complement Selection */\r
+#define OFS_PJSELC_L OFS_PJSELC\r
+#define OFS_PJSELC_H OFS_PJSELC+1\r
+\r
+#endif\r
+/*************************************************************\r
+* RAM Control Module for FRAM\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_RC_FRAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_RCCTL0 (0x0000u) /* Ram Controller Control Register */\r
+#define OFS_RCCTL0_L OFS_RCCTL0\r
+#define OFS_RCCTL0_H OFS_RCCTL0+1\r
+\r
+/* RCCTL0 Control Bits */\r
+#define RCRS0OFF0 (0x0001u) /* RAM Controller RAM Sector 0 Off Bit: 0 */\r
+#define RCRS0OFF1 (0x0002u) /* RAM Controller RAM Sector 0 Off Bit: 1 */\r
+#define RCRS4OFF0 (0x0100u) /* RAM Controller RAM Sector 4 Off Bit: 0 */\r
+#define RCRS4OFF1 (0x0200u) /* RAM Controller RAM Sector 4 Off Bit: 1 */\r
+#define RCRS5OFF0 (0x0400u) /* RAM Controller RAM Sector 5 Off Bit: 0 */\r
+#define RCRS5OFF1 (0x0800u) /* RAM Controller RAM Sector 5 Off Bit: 1 */\r
+#define RCRS6OFF0 (0x1000u) /* RAM Controller RAM Sector 6 Off Bit: 0 */\r
+#define RCRS6OFF1 (0x2000u) /* RAM Controller RAM Sector 6 Off Bit: 1 */\r
+#define RCRS7OFF0 (0x4000u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */\r
+#define RCRS7OFF1 (0x8000u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */\r
+\r
+/* RCCTL0 Control Bits */\r
+#define RCRS0OFF0_L (0x0001u) /* RAM Controller RAM Sector 0 Off Bit: 0 */\r
+#define RCRS0OFF1_L (0x0002u) /* RAM Controller RAM Sector 0 Off Bit: 1 */\r
+\r
+/* RCCTL0 Control Bits */\r
+#define RCRS4OFF0_H (0x0001u) /* RAM Controller RAM Sector 4 Off Bit: 0 */\r
+#define RCRS4OFF1_H (0x0002u) /* RAM Controller RAM Sector 4 Off Bit: 1 */\r
+#define RCRS5OFF0_H (0x0004u) /* RAM Controller RAM Sector 5 Off Bit: 0 */\r
+#define RCRS5OFF1_H (0x0008u) /* RAM Controller RAM Sector 5 Off Bit: 1 */\r
+#define RCRS6OFF0_H (0x0010u) /* RAM Controller RAM Sector 6 Off Bit: 0 */\r
+#define RCRS6OFF1_H (0x0020u) /* RAM Controller RAM Sector 6 Off Bit: 1 */\r
+#define RCRS7OFF0_H (0x0040u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */\r
+#define RCRS7OFF1_H (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */\r
+\r
+#define RCKEY (0x5A00u)\r
+\r
+#define RCRS0OFF_0 (0x0000u) /* RAM Controller RAM Sector 0 Off : 0 */\r
+#define RCRS0OFF_1 (0x0001u) /* RAM Controller RAM Sector 0 Off : 1 */\r
+#define RCRS0OFF_2 (0x0002u) /* RAM Controller RAM Sector 0 Off : 2 */\r
+#define RCRS0OFF_3 (0x0003u) /* RAM Controller RAM Sector 0 Off : 3 */\r
+#define RCRS4OFF_0 (0x0000u) /* RAM Controller RAM Sector 4 Off : 0 */\r
+#define RCRS4OFF_2 (0x0100u) /* RAM Controller RAM Sector 4 Off : 1 */\r
+#define RCRS4OFF_3 (0x0200u) /* RAM Controller RAM Sector 4 Off : 2 */\r
+#define RCRS4OFF_4 (0x0300u) /* RAM Controller RAM Sector 4 Off : 3 */\r
+#define RCRS5OFF_0 (0x0000u) /* RAM Controller RAM Sector 5 Off : 0 */\r
+#define RCRS5OFF_1 (0x0400u) /* RAM Controller RAM Sector 5 Off : 1 */\r
+#define RCRS5OFF_2 (0x0800u) /* RAM Controller RAM Sector 5 Off : 2 */\r
+#define RCRS5OFF_3 (0x0C00u) /* RAM Controller RAM Sector 5 Off : 3 */\r
+#define RCRS6OFF_0 (0x0000u) /* RAM Controller RAM Sector 6 Off : 0 */\r
+#define RCRS6OFF_1 (0x0100u) /* RAM Controller RAM Sector 6 Off : 1 */\r
+#define RCRS6OFF_2 (0x0200u) /* RAM Controller RAM Sector 6 Off : 2 */\r
+#define RCRS6OFF_3 (0x0300u) /* RAM Controller RAM Sector 6 Off : 3 */\r
+#define RCRS7OFF_0 (0x0000u) /* RAM Controller RAM Sector 7 Off : 0 */\r
+#define RCRS7OFF_1 (0x4000u) /* RAM Controller RAM Sector 7 Off : 1 */\r
+#define RCRS7OFF_2 (0x8000u) /* RAM Controller RAM Sector 7 Off : 2*/\r
+#define RCRS7OFF_3 (0xC000u) /* RAM Controller RAM Sector 7 Off : 3*/\r
+\r
+#endif\r
+/************************************************************\r
+* Shared Reference\r
+************************************************************/\r
+#ifdef __MSP430_HAS_REF_A__ /* Definition to show that Module is available */\r
+\r
+#define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */\r
+#define OFS_REFCTL0_L OFS_REFCTL0\r
+#define OFS_REFCTL0_H OFS_REFCTL0+1\r
+\r
+/* REFCTL0 Control Bits */\r
+#define REFON (0x0001u) /* REF Reference On */\r
+#define REFOUT (0x0002u) /* REF Reference output Buffer On */\r
+//#define RESERVED (0x0004u) /* Reserved */\r
+#define REFTCOFF (0x0008u) /* REF Temp.Sensor off */\r
+#define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */\r
+#define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */\r
+#define REFGENOT (0x0040u) /* REF Reference generator one-time trigger */\r
+#define REFBGOT (0x0080u) /* REF Bandgap and bandgap buffer one-time trigger */\r
+#define REFGENACT (0x0100u) /* REF Reference generator active */\r
+#define REFBGACT (0x0200u) /* REF Reference bandgap active */\r
+#define REFGENBUSY (0x0400u) /* REF Reference generator busy */\r
+#define BGMODE (0x0800u) /* REF Bandgap mode */\r
+#define REFGENRDY (0x1000u) /* REF Reference generator ready */\r
+#define REFBGRDY (0x2000u) /* REF Reference bandgap ready */\r
+//#define RESERVED (0x4000u) /* Reserved */\r
+//#define RESERVED (0x8000u) /* Reserved */\r
+\r
+/* REFCTL0 Control Bits */\r
+#define REFON_L (0x0001u) /* REF Reference On */\r
+#define REFOUT_L (0x0002u) /* REF Reference output Buffer On */\r
+//#define RESERVED (0x0004u) /* Reserved */\r
+#define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */\r
+#define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */\r
+#define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */\r
+#define REFGENOT_L (0x0040u) /* REF Reference generator one-time trigger */\r
+#define REFBGOT_L (0x0080u) /* REF Bandgap and bandgap buffer one-time trigger */\r
+//#define RESERVED (0x4000u) /* Reserved */\r
+//#define RESERVED (0x8000u) /* Reserved */\r
+\r
+/* REFCTL0 Control Bits */\r
+//#define RESERVED (0x0004u) /* Reserved */\r
+#define REFGENACT_H (0x0001u) /* REF Reference generator active */\r
+#define REFBGACT_H (0x0002u) /* REF Reference bandgap active */\r
+#define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */\r
+#define BGMODE_H (0x0008u) /* REF Bandgap mode */\r
+#define REFGENRDY_H (0x0010u) /* REF Reference generator ready */\r
+#define REFBGRDY_H (0x0020u) /* REF Reference bandgap ready */\r
+//#define RESERVED (0x4000u) /* Reserved */\r
+//#define RESERVED (0x8000u) /* Reserved */\r
+\r
+#define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.2V */\r
+#define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */\r
+#define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */\r
+#define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */\r
+\r
+#endif\r
+/************************************************************\r
+* Real Time Clock\r
+************************************************************/\r
+#ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */\r
+\r
+#define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */\r
+#define OFS_RTCCTL01_L OFS_RTCCTL01\r
+#define OFS_RTCCTL01_H OFS_RTCCTL01+1\r
+#define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */\r
+#define OFS_RTCCTL23_L OFS_RTCCTL23\r
+#define OFS_RTCCTL23_H OFS_RTCCTL23+1\r
+#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */\r
+#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
+#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
+#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */\r
+#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
+#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
+#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */\r
+#define OFS_RTCPS_L OFS_RTCPS\r
+#define OFS_RTCPS_H OFS_RTCPS+1\r
+#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */\r
+#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */\r
+#define OFS_RTCTIM0_L OFS_RTCTIM0\r
+#define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
+#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */\r
+#define OFS_RTCTIM1_L OFS_RTCTIM1\r
+#define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
+#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */\r
+#define OFS_RTCDATE_L OFS_RTCDATE\r
+#define OFS_RTCDATE_H OFS_RTCDATE+1\r
+#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */\r
+#define OFS_RTCYEAR_L OFS_RTCYEAR\r
+#define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
+#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */\r
+#define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
+#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
+#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */\r
+#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
+#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
+#define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */\r
+#define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */\r
+#define OFS_RTCSEC (0x0010u)\r
+#define OFS_RTCMIN (0x0011u)\r
+#define OFS_RTCHOUR (0x0012u)\r
+#define OFS_RTCDOW (0x0013u)\r
+#define OFS_RTCDAY (0x0014u)\r
+#define OFS_RTCMON (0x0015u)\r
+#define OFS_RTCAMIN (0x0018u)\r
+#define OFS_RTCAHOUR (0x0019u)\r
+#define OFS_RTCADOW (0x001Au)\r
+#define OFS_RTCADAY (0x001Bu)\r
+\r
+#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */\r
+#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */\r
+#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */\r
+#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */\r
+#define RTCNT12 RTCTIM0\r
+#define RTCNT34 RTCTIM1\r
+#define RTCNT1 RTCTIM0_L\r
+#define RTCNT2 RTCTIM0_H\r
+#define RTCNT3 RTCTIM1_L\r
+#define RTCNT4 RTCTIM1_H\r
+#define RTCSEC RTCTIM0_L\r
+#define RTCMIN RTCTIM0_H\r
+#define RTCHOUR RTCTIM1_L\r
+#define RTCDOW RTCTIM1_H\r
+#define RTCDAY RTCDATE_L\r
+#define RTCMON RTCDATE_H\r
+#define RTCYEARL RTCYEAR_L\r
+#define RTCYEARH RTCYEAR_H\r
+#define RT0PS RTCPS_L\r
+#define RT1PS RTCPS_H\r
+#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
+#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
+#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
+#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
+\r
+/* RTCCTL01 Control Bits */\r
+#define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD (0x4000u) /* RTC Hold */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+#define RTCRDY (0x1000u) /* RTC Ready */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+#define RTCTEV1 (0x0200u) /* RTC Time Event 1 */\r
+#define RTCTEV0 (0x0100u) /* RTC Time Event 0 */\r
+#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */\r
+\r
+/* RTCCTL01 Control Bits */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */\r
+\r
+/* RTCCTL01 Control Bits */\r
+#define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD_H (0x0040u) /* RTC Hold */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+#define RTCRDY_H (0x0010u) /* RTC Ready */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+#define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */\r
+#define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */\r
+\r
+#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */\r
+#define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */\r
+#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */\r
+#define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */\r
+\r
+/* RTCCTL23 Control Bits */\r
+#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */\r
+#define RTCCALS (0x0080u) /* RTC Calibration Sign */\r
+//#define Reserved (0x0040u)\r
+#define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */\r
+#define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */\r
+#define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */\r
+#define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */\r
+#define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */\r
+#define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */\r
+\r
+/* RTCCTL23 Control Bits */\r
+#define RTCCALS_L (0x0080u) /* RTC Calibration Sign */\r
+//#define Reserved (0x0040u)\r
+#define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */\r
+#define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */\r
+#define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */\r
+#define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */\r
+#define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */\r
+#define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */\r
+\r
+/* RTCCTL23 Control Bits */\r
+#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */\r
+//#define Reserved (0x0040u)\r
+\r
+#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */\r
+#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */\r
+#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */\r
+#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */\r
+\r
+#define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
+#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
+#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
+#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
+#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
+#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
+#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
+#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
+\r
+#define RT0IP__2 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
+#define RT0IP__4 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
+#define RT0IP__8 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
+#define RT0IP__16 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
+#define RT0IP__32 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
+#define RT0IP__64 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
+#define RT0IP__128 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
+#define RT0IP__256 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
+#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
+#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
+#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
+#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
+#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
+#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
+#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
+\r
+#define RT1IP__2 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
+#define RT1IP__4 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
+#define RT1IP__8 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
+#define RT1IP__16 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
+#define RT1IP__32 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
+#define RT1IP__64 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
+#define RT1IP__128 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
+#define RT1IP__256 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
+\r
+/* RTC Definitions */\r
+#define RTCIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */\r
+#define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */\r
+#define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */\r
+#define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */\r
+#define RTCIV_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */\r
+\r
+/* Legacy Definitions */\r
+#define RTC_NONE (0x0000u) /* No Interrupt pending */\r
+#define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */\r
+#define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */\r
+#define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */\r
+#define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */\r
+#define RTC_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */\r
+\r
+#endif\r
+/************************************************************\r
+* Real Time Clock\r
+************************************************************/\r
+#ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */\r
+\r
+#define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */\r
+#define OFS_RTCCTL0_L OFS_RTCCTL0\r
+#define OFS_RTCCTL0_H OFS_RTCCTL0+1\r
+#define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */\r
+#define OFS_RTCCTL13_L OFS_RTCCTL13\r
+#define OFS_RTCCTL13_H OFS_RTCCTL13+1\r
+#define RTCCTL1 RTCCTL13_L\r
+#define RTCCTL3 RTCCTL13_H\r
+#define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */\r
+#define OFS_RTCOCAL_L OFS_RTCOCAL\r
+#define OFS_RTCOCAL_H OFS_RTCOCAL+1\r
+#define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */\r
+#define OFS_RTCTCMP_L OFS_RTCTCMP\r
+#define OFS_RTCTCMP_H OFS_RTCTCMP+1\r
+#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */\r
+#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
+#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
+#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */\r
+#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
+#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
+#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */\r
+#define OFS_RTCPS_L OFS_RTCPS\r
+#define OFS_RTCPS_H OFS_RTCPS+1\r
+#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */\r
+#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */\r
+#define OFS_RTCTIM0_L OFS_RTCTIM0\r
+#define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
+#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */\r
+#define OFS_RTCTIM1_L OFS_RTCTIM1\r
+#define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
+#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */\r
+#define OFS_RTCDATE_L OFS_RTCDATE\r
+#define OFS_RTCDATE_H OFS_RTCDATE+1\r
+#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */\r
+#define OFS_RTCYEAR_L OFS_RTCYEAR\r
+#define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
+#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */\r
+#define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
+#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
+#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */\r
+#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
+#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
+#define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */\r
+#define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */\r
+#define OFS_RTCSEC (0x0010u)\r
+#define OFS_RTCMIN (0x0011u)\r
+#define OFS_RTCHOUR (0x0012u)\r
+#define OFS_RTCDOW (0x0013u)\r
+#define OFS_RTCDAY (0x0014u)\r
+#define OFS_RTCMON (0x0015u)\r
+#define OFS_RTCAMIN (0x0018u)\r
+#define OFS_RTCAHOUR (0x0019u)\r
+#define OFS_RTCADOW (0x001Au)\r
+#define OFS_RTCADAY (0x001Bu)\r
+\r
+#define RTCSEC RTCTIM0_L\r
+#define RTCMIN RTCTIM0_H\r
+#define RTCHOUR RTCTIM1_L\r
+#define RTCDOW RTCTIM1_H\r
+#define RTCDAY RTCDATE_L\r
+#define RTCMON RTCDATE_H\r
+#define RTCYEARL RTCYEAR_L\r
+#define RT0PS RTCPS_L\r
+#define RT1PS RTCPS_H\r
+#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
+#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
+#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
+#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
+\r
+/* RTCCTL0 Control Bits */\r
+#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */\r
+\r
+/* RTCCTL0 Control Bits */\r
+#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */\r
+\r
+#define RTCKEY (0xA500u) /* RTC Key for RTC write access */\r
+#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */\r
+\r
+/* RTCCTL13 Control Bits */\r
+#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */\r
+#define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD (0x0040u) /* RTC Hold */\r
+#define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */\r
+#define RTCRDY (0x0010u) /* RTC Ready */\r
+#define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */\r
+#define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */\r
+#define RTCTEV1 (0x0002u) /* RTC Time Event 1 */\r
+#define RTCTEV0 (0x0001u) /* RTC Time Event 0 */\r
+\r
+/* RTCCTL13 Control Bits */\r
+#define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD_L (0x0040u) /* RTC Hold */\r
+#define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */\r
+#define RTCRDY_L (0x0010u) /* RTC Ready */\r
+#define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */\r
+#define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */\r
+#define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */\r
+#define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */\r
+\r
+/* RTCCTL13 Control Bits */\r
+#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */\r
+\r
+#define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */\r
+#define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */\r
+#define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */\r
+#define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */\r
+#define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */\r
+#define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */\r
+#define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */\r
+\r
+#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */\r
+#define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */\r
+#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */\r
+#define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */\r
+\r
+#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */\r
+#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */\r
+#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */\r
+#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */\r
+\r
+/* RTCOCAL Control Bits */\r
+#define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */\r
+#define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */\r
+#define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */\r
+#define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */\r
+#define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */\r
+#define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */\r
+#define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */\r
+#define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */\r
+#define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */\r
+\r
+/* RTCOCAL Control Bits */\r
+#define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */\r
+#define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */\r
+#define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */\r
+#define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */\r
+#define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */\r
+#define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */\r
+#define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */\r
+#define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */\r
+\r
+/* RTCOCAL Control Bits */\r
+#define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */\r
+\r
+/* RTCTCMP Control Bits */\r
+#define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */\r
+#define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */\r
+#define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */\r
+#define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */\r
+#define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */\r
+#define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */\r
+#define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */\r
+#define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */\r
+#define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */\r
+#define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */\r
+#define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */\r
+\r
+/* RTCTCMP Control Bits */\r
+#define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */\r
+#define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */\r
+#define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */\r
+#define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */\r
+#define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */\r
+#define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */\r
+#define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */\r
+#define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */\r
+\r
+/* RTCTCMP Control Bits */\r
+#define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */\r
+#define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */\r
+#define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */\r
+\r
+#define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x8000u)\r
+//#define Reserved (0x4000u)\r
+#define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
+#define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
+#define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+#define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x8000u)\r
+//#define Reserved (0x4000u)\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x8000u)\r
+//#define Reserved (0x4000u)\r
+#define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
+#define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
+#define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+#define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+\r
+#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
+#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
+#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
+#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
+#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
+#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
+#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
+#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+#define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
+#define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
+#define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
+#define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
+#define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+#define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+#define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
+#define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
+#define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
+#define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
+#define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+#define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+\r
+#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
+#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
+#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
+#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
+#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
+#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
+#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
+#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
+\r
+/* RTC Definitions */\r
+#define RTCIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */\r
+#define RTCIV_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */\r
+#define RTCIV_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */\r
+#define RTCIV_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */\r
+#define RTCIV_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTCIV_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */\r
+\r
+/* Legacy Definitions */\r
+#define RTC_NONE (0x0000u) /* No Interrupt pending */\r
+#define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */\r
+#define RTC_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */\r
+#define RTC_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */\r
+#define RTC_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */\r
+#define RTC_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTC_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */\r
+\r
+#endif\r
+/************************************************************\r
+* SFR - Special Function Register Module\r
+************************************************************/\r
+#ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */\r
+\r
+#define OFS_SFRIE1 (0x0000u) /* Interrupt Enable 1 */\r
+#define OFS_SFRIE1_L OFS_SFRIE1\r
+#define OFS_SFRIE1_H OFS_SFRIE1+1\r
+\r
+/* SFRIE1 Control Bits */\r
+#define WDTIE (0x0001u) /* WDT Interrupt Enable */\r
+#define OFIE (0x0002u) /* Osc Fault Enable */\r
+//#define Reserved (0x0004u)\r
+#define VMAIE (0x0008u) /* Vacant Memory Interrupt Enable */\r
+#define NMIIE (0x0010u) /* NMI Interrupt Enable */\r
+#define JMBINIE (0x0040u) /* JTAG Mail Box input Interrupt Enable */\r
+#define JMBOUTIE (0x0080u) /* JTAG Mail Box output Interrupt Enable */\r
+\r
+#define WDTIE_L (0x0001u) /* WDT Interrupt Enable */\r
+#define OFIE_L (0x0002u) /* Osc Fault Enable */\r
+//#define Reserved (0x0004u)\r
+#define VMAIE_L (0x0008u) /* Vacant Memory Interrupt Enable */\r
+#define NMIIE_L (0x0010u) /* NMI Interrupt Enable */\r
+#define JMBINIE_L (0x0040u) /* JTAG Mail Box input Interrupt Enable */\r
+#define JMBOUTIE_L (0x0080u) /* JTAG Mail Box output Interrupt Enable */\r
+\r
+#define OFS_SFRIFG1 (0x0002u) /* Interrupt Flag 1 */\r
+#define OFS_SFRIFG1_L OFS_SFRIFG1\r
+#define OFS_SFRIFG1_H OFS_SFRIFG1+1\r
+/* SFRIFG1 Control Bits */\r
+#define WDTIFG (0x0001u) /* WDT Interrupt Flag */\r
+#define OFIFG (0x0002u) /* Osc Fault Flag */\r
+//#define Reserved (0x0004u)\r
+#define VMAIFG (0x0008u) /* Vacant Memory Interrupt Flag */\r
+#define NMIIFG (0x0010u) /* NMI Interrupt Flag */\r
+//#define Reserved (0x0020u)\r
+#define JMBINIFG (0x0040u) /* JTAG Mail Box input Interrupt Flag */\r
+#define JMBOUTIFG (0x0080u) /* JTAG Mail Box output Interrupt Flag */\r
+\r
+#define WDTIFG_L (0x0001u) /* WDT Interrupt Flag */\r
+#define OFIFG_L (0x0002u) /* Osc Fault Flag */\r
+//#define Reserved (0x0004u)\r
+#define VMAIFG_L (0x0008u) /* Vacant Memory Interrupt Flag */\r
+#define NMIIFG_L (0x0010u) /* NMI Interrupt Flag */\r
+//#define Reserved (0x0020u)\r
+#define JMBINIFG_L (0x0040u) /* JTAG Mail Box input Interrupt Flag */\r
+#define JMBOUTIFG_L (0x0080u) /* JTAG Mail Box output Interrupt Flag */\r
+\r
+#define OFS_SFRRPCR (0x0004u) /* RESET Pin Control Register */\r
+#define OFS_SFRRPCR_L OFS_SFRRPCR\r
+#define OFS_SFRRPCR_H OFS_SFRRPCR+1\r
+/* SFRRPCR Control Bits */\r
+#define SYSNMI (0x0001u) /* NMI select */\r
+#define SYSNMIIES (0x0002u) /* NMI edge select */\r
+#define SYSRSTUP (0x0004u) /* RESET Pin pull down/up select */\r
+#define SYSRSTRE (0x0008u) /* RESET Pin Resistor enable */\r
+\r
+#define SYSNMI_L (0x0001u) /* NMI select */\r
+#define SYSNMIIES_L (0x0002u) /* NMI edge select */\r
+#define SYSRSTUP_L (0x0004u) /* RESET Pin pull down/up select */\r
+#define SYSRSTRE_L (0x0008u) /* RESET Pin Resistor enable */\r
+\r
+#endif\r
+/************************************************************\r
+* SYS - System Module\r
+************************************************************/\r
+#ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */\r
+\r
+#define OFS_SYSCTL (0x0000u) /* System control */\r
+#define OFS_SYSCTL_L OFS_SYSCTL\r
+#define OFS_SYSCTL_H OFS_SYSCTL+1\r
+#define OFS_SYSBSLC (0x0002u) /* Boot strap configuration area */\r
+#define OFS_SYSBSLC_L OFS_SYSBSLC\r
+#define OFS_SYSBSLC_H OFS_SYSBSLC+1\r
+#define OFS_SYSJMBC (0x0006u) /* JTAG mailbox control */\r
+#define OFS_SYSJMBC_L OFS_SYSJMBC\r
+#define OFS_SYSJMBC_H OFS_SYSJMBC+1\r
+#define OFS_SYSJMBI0 (0x0008u) /* JTAG mailbox input 0 */\r
+#define OFS_SYSJMBI0_L OFS_SYSJMBI0\r
+#define OFS_SYSJMBI0_H OFS_SYSJMBI0+1\r
+#define OFS_SYSJMBI1 (0x000Au) /* JTAG mailbox input 1 */\r
+#define OFS_SYSJMBI1_L OFS_SYSJMBI1\r
+#define OFS_SYSJMBI1_H OFS_SYSJMBI1+1\r
+#define OFS_SYSJMBO0 (0x000Cu) /* JTAG mailbox output 0 */\r
+#define OFS_SYSJMBO0_L OFS_SYSJMBO0\r
+#define OFS_SYSJMBO0_H OFS_SYSJMBO0+1\r
+#define OFS_SYSJMBO1 (0x000Eu) /* JTAG mailbox output 1 */\r
+#define OFS_SYSJMBO1_L OFS_SYSJMBO1\r
+#define OFS_SYSJMBO1_H OFS_SYSJMBO1+1\r
+\r
+#define OFS_SYSBERRIV (0x0018u) /* Bus Error vector generator */\r
+#define OFS_SYSBERRIV_L OFS_SYSBERRIV\r
+#define OFS_SYSBERRIV_H OFS_SYSBERRIV+1\r
+#define OFS_SYSUNIV (0x001Au) /* User NMI vector generator */\r
+#define OFS_SYSUNIV_L OFS_SYSUNIV\r
+#define OFS_SYSUNIV_H OFS_SYSUNIV+1\r
+#define OFS_SYSSNIV (0x001Cu) /* System NMI vector generator */\r
+#define OFS_SYSSNIV_L OFS_SYSSNIV\r
+#define OFS_SYSSNIV_H OFS_SYSSNIV+1\r
+#define OFS_SYSRSTIV (0x001Eu) /* Reset vector generator */\r
+#define OFS_SYSRSTIV_L OFS_SYSRSTIV\r
+#define OFS_SYSRSTIV_H OFS_SYSRSTIV+1\r
+\r
+/* SYSCTL Control Bits */\r
+#define SYSRIVECT (0x0001u) /* SYS - RAM based interrupt vectors */\r
+//#define RESERVED (0x0002u) /* SYS - Reserved */\r
+#define SYSPMMPE (0x0004u) /* SYS - PMM access protect */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+#define SYSBSLIND (0x0010u) /* SYS - TCK/RST indication detected */\r
+#define SYSJTAGPIN (0x0020u) /* SYS - Dedicated JTAG pins enabled */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+//#define RESERVED (0x4000u) /* SYS - Reserved */\r
+//#define RESERVED (0x8000u) /* SYS - Reserved */\r
+\r
+/* SYSCTL Control Bits */\r
+#define SYSRIVECT_L (0x0001u) /* SYS - RAM based interrupt vectors */\r
+//#define RESERVED (0x0002u) /* SYS - Reserved */\r
+#define SYSPMMPE_L (0x0004u) /* SYS - PMM access protect */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+#define SYSBSLIND_L (0x0010u) /* SYS - TCK/RST indication detected */\r
+#define SYSJTAGPIN_L (0x0020u) /* SYS - Dedicated JTAG pins enabled */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+//#define RESERVED (0x4000u) /* SYS - Reserved */\r
+//#define RESERVED (0x8000u) /* SYS - Reserved */\r
+\r
+/* SYSBSLC Control Bits */\r
+#define SYSBSLSIZE0 (0x0001u) /* SYS - BSL Protection Size 0 */\r
+#define SYSBSLSIZE1 (0x0002u) /* SYS - BSL Protection Size 1 */\r
+#define SYSBSLR (0x0004u) /* SYS - RAM assigned to BSL */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+//#define RESERVED (0x0010u) /* SYS - Reserved */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+#define SYSBSLOFF (0x4000u) /* SYS - BSL Memory disabled */\r
+#define SYSBSLPE (0x8000u) /* SYS - BSL Memory protection enabled */\r
+\r
+/* SYSBSLC Control Bits */\r
+#define SYSBSLSIZE0_L (0x0001u) /* SYS - BSL Protection Size 0 */\r
+#define SYSBSLSIZE1_L (0x0002u) /* SYS - BSL Protection Size 1 */\r
+#define SYSBSLR_L (0x0004u) /* SYS - RAM assigned to BSL */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+//#define RESERVED (0x0010u) /* SYS - Reserved */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+\r
+/* SYSBSLC Control Bits */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+//#define RESERVED (0x0010u) /* SYS - Reserved */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+#define SYSBSLOFF_H (0x0040u) /* SYS - BSL Memory disabled */\r
+#define SYSBSLPE_H (0x0080u) /* SYS - BSL Memory protection enabled */\r
+\r
+/* SYSJMBC Control Bits */\r
+#define JMBIN0FG (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */\r
+#define JMBIN1FG (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */\r
+#define JMBOUT0FG (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */\r
+#define JMBOUT1FG (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */\r
+#define JMBMODE (0x0010u) /* SYS - JMB 16/32 Bit Mode */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+#define JMBCLR0OFF (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */\r
+#define JMBCLR1OFF (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+//#define RESERVED (0x4000u) /* SYS - Reserved */\r
+//#define RESERVED (0x8000u) /* SYS - Reserved */\r
+\r
+/* SYSJMBC Control Bits */\r
+#define JMBIN0FG_L (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */\r
+#define JMBIN1FG_L (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */\r
+#define JMBOUT0FG_L (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */\r
+#define JMBOUT1FG_L (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */\r
+#define JMBMODE_L (0x0010u) /* SYS - JMB 16/32 Bit Mode */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+#define JMBCLR0OFF_L (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */\r
+#define JMBCLR1OFF_L (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+//#define RESERVED (0x4000u) /* SYS - Reserved */\r
+//#define RESERVED (0x8000u) /* SYS - Reserved */\r
+\r
+\r
+#endif\r
+/************************************************************\r
+* Timerx_A7\r
+************************************************************/\r
+#ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */\r
+\r
+#define OFS_TAxCTL (0x0000u) /* Timerx_A7 Control */\r
+#define OFS_TAxCCTL0 (0x0002u) /* Timerx_A7 Capture/Compare Control 0 */\r
+#define OFS_TAxCCTL1 (0x0004u) /* Timerx_A7 Capture/Compare Control 1 */\r
+#define OFS_TAxCCTL2 (0x0006u) /* Timerx_A7 Capture/Compare Control 2 */\r
+#define OFS_TAxCCTL3 (0x0008u) /* Timerx_A7 Capture/Compare Control 3 */\r
+#define OFS_TAxCCTL4 (0x000Au) /* Timerx_A7 Capture/Compare Control 4 */\r
+#define OFS_TAxCCTL5 (0x000Cu) /* Timerx_A7 Capture/Compare Control 5 */\r
+#define OFS_TAxCCTL6 (0x000Eu) /* Timerx_A7 Capture/Compare Control 6 */\r
+#define OFS_TAxR (0x0010u) /* Timerx_A7 */\r
+#define OFS_TAxCCR0 (0x0012u) /* Timerx_A7 Capture/Compare 0 */\r
+#define OFS_TAxCCR1 (0x0014u) /* Timerx_A7 Capture/Compare 1 */\r
+#define OFS_TAxCCR2 (0x0016u) /* Timerx_A7 Capture/Compare 2 */\r
+#define OFS_TAxCCR3 (0x0018u) /* Timerx_A7 Capture/Compare 3 */\r
+#define OFS_TAxCCR4 (0x001Au) /* Timerx_A7 Capture/Compare 4 */\r
+#define OFS_TAxCCR5 (0x001Cu) /* Timerx_A7 Capture/Compare 5 */\r
+#define OFS_TAxCCR6 (0x001Eu) /* Timerx_A7 Capture/Compare 6 */\r
+#define OFS_TAxIV (0x002Eu) /* Timerx_A7 Interrupt Vector Word */\r
+#define OFS_TAxEX0 (0x0020u) /* Timerx_A7 Expansion Register 0 */\r
+\r
+/* Bits are already defined within the Timer0_Ax */\r
+\r
+/* TAxIV Definitions */\r
+#define TAxIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define TAxIV_TACCR1 (0x0002u) /* TAxCCR1_CCIFG */\r
+#define TAxIV_TACCR2 (0x0004u) /* TAxCCR2_CCIFG */\r
+#define TAxIV_TACCR3 (0x0006u) /* TAxCCR3_CCIFG */\r
+#define TAxIV_TACCR4 (0x0008u) /* TAxCCR4_CCIFG */\r
+#define TAxIV_TACCR5 (0x000Au) /* TAxCCR5_CCIFG */\r
+#define TAxIV_TACCR6 (0x000Cu) /* TAxCCR6_CCIFG */\r
+#define TAxIV_TAIFG (0x000Eu) /* TAxIFG */\r
+\r
+/* Legacy Defines */\r
+#define TAxIV_TAxCCR1 (0x0002u) /* TAxCCR1_CCIFG */\r
+#define TAxIV_TAxCCR2 (0x0004u) /* TAxCCR2_CCIFG */\r
+#define TAxIV_TAxCCR3 (0x0006u) /* TAxCCR3_CCIFG */\r
+#define TAxIV_TAxCCR4 (0x0008u) /* TAxCCR4_CCIFG */\r
+#define TAxIV_TAxCCR5 (0x000Au) /* TAxCCR5_CCIFG */\r
+#define TAxIV_TAxCCR6 (0x000Cu) /* TAxCCR6_CCIFG */\r
+#define TAxIV_TAxIFG (0x000Eu) /* TAxIFG */\r
+\r
+/* TAxCTL Control Bits */\r
+#define TASSEL1 (0x0200u) /* Timer A clock source select 1 */\r
+#define TASSEL0 (0x0100u) /* Timer A clock source select 0 */\r
+#define ID1 (0x0080u) /* Timer A clock input divider 1 */\r
+#define ID0 (0x0040u) /* Timer A clock input divider 0 */\r
+#define MC1 (0x0020u) /* Timer A mode control 1 */\r
+#define MC0 (0x0010u) /* Timer A mode control 0 */\r
+#define TACLR (0x0004u) /* Timer A counter clear */\r
+#define TAIE (0x0002u) /* Timer A counter interrupt enable */\r
+#define TAIFG (0x0001u) /* Timer A counter interrupt flag */\r
+\r
+#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */\r
+#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */\r
+#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */\r
+#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */\r
+#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */\r
+#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */\r
+#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */\r
+#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */\r
+#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */\r
+#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */\r
+#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */\r
+#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */\r
+#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */\r
+#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */\r
+#define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */\r
+#define MC__CONTINOUS (2*0x10u) /* Legacy define */\r
+#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */\r
+#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */\r
+#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */\r
+#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */\r
+#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */\r
+#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */\r
+#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */\r
+#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */\r
+#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */\r
+\r
+/* TAxCCTLx Control Bits */\r
+#define CM1 (0x8000u) /* Capture mode 1 */\r
+#define CM0 (0x4000u) /* Capture mode 0 */\r
+#define CCIS1 (0x2000u) /* Capture input select 1 */\r
+#define CCIS0 (0x1000u) /* Capture input select 0 */\r
+#define SCS (0x0800u) /* Capture sychronize */\r
+#define SCCI (0x0400u) /* Latched capture signal (read) */\r
+#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */\r
+#define OUTMOD2 (0x0080u) /* Output mode 2 */\r
+#define OUTMOD1 (0x0040u) /* Output mode 1 */\r
+#define OUTMOD0 (0x0020u) /* Output mode 0 */\r
+#define CCIE (0x0010u) /* Capture/compare interrupt enable */\r
+#define CCI (0x0008u) /* Capture input signal (read) */\r
+#define OUT (0x0004u) /* PWM Output signal if output mode 0 */\r
+#define COV (0x0002u) /* Capture/compare overflow flag */\r
+#define CCIFG (0x0001u) /* Capture/compare interrupt flag */\r
+\r
+#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */\r
+#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */\r
+#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */\r
+#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */\r
+#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */\r
+#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */\r
+#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */\r
+#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */\r
+#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */\r
+#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */\r
+#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */\r
+#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */\r
+#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */\r
+#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */\r
+#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */\r
+#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */\r
+\r
+/* TAxEX0 Control Bits */\r
+#define TAIDEX0 (0x0001u) /* Timer A Input divider expansion Bit: 0 */\r
+#define TAIDEX1 (0x0002u) /* Timer A Input divider expansion Bit: 1 */\r
+#define TAIDEX2 (0x0004u) /* Timer A Input divider expansion Bit: 2 */\r
+\r
+#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */\r
+#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */\r
+#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */\r
+#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */\r
+#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */\r
+#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */\r
+#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */\r
+#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */\r
+\r
+#endif\r
+/************************************************************\r
+* Timerx_B7\r
+************************************************************/\r
+#ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */\r
+\r
+#define OFS_TBxCTL (0x0000u) /* Timerx_B7 Control */\r
+#define OFS_TBxCCTL0 (0x0002u) /* Timerx_B7 Capture/Compare Control 0 */\r
+#define OFS_TBxCCTL1 (0x0004u) /* Timerx_B7 Capture/Compare Control 1 */\r
+#define OFS_TBxCCTL2 (0x0006u) /* Timerx_B7 Capture/Compare Control 2 */\r
+#define OFS_TBxCCTL3 (0x0008u) /* Timerx_B7 Capture/Compare Control 3 */\r
+#define OFS_TBxCCTL4 (0x000Au) /* Timerx_B7 Capture/Compare Control 4 */\r
+#define OFS_TBxCCTL5 (0x000Cu) /* Timerx_B7 Capture/Compare Control 5 */\r
+#define OFS_TBxCCTL6 (0x000Eu) /* Timerx_B7 Capture/Compare Control 6 */\r
+#define OFS_TBxR (0x0010u) /* Timerx_B7 */\r
+#define OFS_TBxCCR0 (0x0012u) /* Timerx_B7 Capture/Compare 0 */\r
+#define OFS_TBxCCR1 (0x0014u) /* Timerx_B7 Capture/Compare 1 */\r
+#define OFS_TBxCCR2 (0x0016u) /* Timerx_B7 Capture/Compare 2 */\r
+#define OFS_TBxCCR3 (0x0018u) /* Timerx_B7 Capture/Compare 3 */\r
+#define OFS_TBxCCR4 (0x001Au) /* Timerx_B7 Capture/Compare 4 */\r
+#define OFS_TBxCCR5 (0x001Cu) /* Timerx_B7 Capture/Compare 5 */\r
+#define OFS_TBxCCR6 (0x001Eu) /* Timerx_B7 Capture/Compare 6 */\r
+#define OFS_TBxIV (0x002Eu) /* Timerx_B7 Interrupt Vector Word */\r
+#define OFS_TBxEX0 (0x0020u) /* Timerx_B7 Expansion Register 0 */\r
+\r
+/* Bits are already defined within the Timer0_Ax */\r
+\r
+/* TBxIV Definitions */\r
+#define TBxIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define TBxIV_TBCCR1 (0x0002u) /* TBxCCR1_CCIFG */\r
+#define TBxIV_TBCCR2 (0x0004u) /* TBxCCR2_CCIFG */\r
+#define TBxIV_TBCCR3 (0x0006u) /* TBxCCR3_CCIFG */\r
+#define TBxIV_TBCCR4 (0x0008u) /* TBxCCR4_CCIFG */\r
+#define TBxIV_TBCCR5 (0x000Au) /* TBxCCR5_CCIFG */\r
+#define TBxIV_TBCCR6 (0x000Cu) /* TBxCCR6_CCIFG */\r
+#define TBxIV_TBIFG (0x000Eu) /* TBxIFG */\r
+\r
+/* Legacy Defines */\r
+#define TBxIV_TBxCCR1 (0x0002u) /* TBxCCR1_CCIFG */\r
+#define TBxIV_TBxCCR2 (0x0004u) /* TBxCCR2_CCIFG */\r
+#define TBxIV_TBxCCR3 (0x0006u) /* TBxCCR3_CCIFG */\r
+#define TBxIV_TBxCCR4 (0x0008u) /* TBxCCR4_CCIFG */\r
+#define TBxIV_TBxCCR5 (0x000Au) /* TBxCCR5_CCIFG */\r
+#define TBxIV_TBxCCR6 (0x000Cu) /* TBxCCR6_CCIFG */\r
+#define TBxIV_TBxIFG (0x000Eu) /* TBxIFG */\r
+\r
+/* TBxCTL Control Bits */\r
+#define TBCLGRP1 (0x4000u) /* Timer_B7 Compare latch load group 1 */\r
+#define TBCLGRP0 (0x2000u) /* Timer_B7 Compare latch load group 0 */\r
+#define CNTL1 (0x1000u) /* Counter lenght 1 */\r
+#define CNTL0 (0x0800u) /* Counter lenght 0 */\r
+#define TBSSEL1 (0x0200u) /* Clock source 1 */\r
+#define TBSSEL0 (0x0100u) /* Clock source 0 */\r
+#define TBCLR (0x0004u) /* Timer_B7 counter clear */\r
+#define TBIE (0x0002u) /* Timer_B7 interrupt enable */\r
+#define TBIFG (0x0001u) /* Timer_B7 interrupt flag */\r
+\r
+#define SHR1 (0x4000u) /* Timer_B7 Compare latch load group 1 */\r
+#define SHR0 (0x2000u) /* Timer_B7 Compare latch load group 0 */\r
+\r
+#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */\r
+#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */\r
+#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */\r
+#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */\r
+#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */\r
+#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */\r
+#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */\r
+#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */\r
+#define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */\r
+#define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
+#define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/\r
+#define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */\r
+#define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */\r
+#define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
+#define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/\r
+#define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */\r
+#define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */\r
+#define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */\r
+#define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */\r
+#define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */\r
+#define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */\r
+#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */\r
+#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */\r
+#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */\r
+#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */\r
+\r
+/* Additional Timer B Control Register bits are defined in Timer A */\r
+/* TBxCCTLx Control Bits */\r
+#define CLLD1 (0x0400u) /* Compare latch load source 1 */\r
+#define CLLD0 (0x0200u) /* Compare latch load source 0 */\r
+\r
+#define SLSHR1 (0x0400u) /* Compare latch load source 1 */\r
+#define SLSHR0 (0x0200u) /* Compare latch load source 0 */\r
+\r
+#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
+#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */\r
+#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
+#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */\r
+\r
+#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
+#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */\r
+#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
+#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */\r
+\r
+/* TBxEX0 Control Bits */\r
+#define TBIDEX0 (0x0001u) /* Timer_B7 Input divider expansion Bit: 0 */\r
+#define TBIDEX1 (0x0002u) /* Timer_B7 Input divider expansion Bit: 1 */\r
+#define TBIDEX2 (0x0004u) /* Timer_B7 Input divider expansion Bit: 2 */\r
+\r
+#define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */\r
+#define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */\r
+#define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */\r
+#define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */\r
+#define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */\r
+#define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */\r
+#define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */\r
+#define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */\r
+#define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */\r
+#define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */\r
+#define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */\r
+#define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */\r
+#define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */\r
+#define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */\r
+#define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */\r
+#define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */\r
+\r
+\r
+#define ID1 (0x0080u) /* Timer B clock input divider 1 */\r
+#define ID0 (0x0040u) /* Timer B clock input divider 0 */\r
+#define MC1 (0x0020u) /* Timer B mode control 1 */\r
+#define MC0 (0x0010u) /* Timer B mode control 0 */\r
+#define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */\r
+#define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */\r
+#define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */\r
+#define MC__CONTINOUS (2*0x10u) /* Legacy define */\r
+#define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */\r
+#define CM1 (0x8000u) /* Capture mode 1 */\r
+#define CM0 (0x4000u) /* Capture mode 0 */\r
+#define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */\r
+#define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */\r
+#define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */\r
+#define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */\r
+#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */\r
+#define CCIE (0x0010u) /* Capture/compare interrupt enable */\r
+#define CCIFG (0x0001u) /* Capture/compare interrupt flag */\r
+#define CCIS_0 (0*0x1000u)\r
+#define CCIS_1 (1*0x1000u)\r
+#define CCIS_2 (2*0x1000u)\r
+#define CCIS_3 (3*0x1000u)\r
+#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */\r
+#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */\r
+#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */\r
+#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */\r
+#define OUT (0x0004u) /* PWM Output signal if output mode 0 */\r
+#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */\r
+#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */\r
+#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */\r
+#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */\r
+#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */\r
+#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */\r
+#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */\r
+#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */\r
+#define SCCI (0x0400u) /* Latched capture signal (read) */\r
+#define SCS (0x0800u) /* Capture sychronize */\r
+#define CCI (0x0008u) /* Capture input signal (read) */\r
+#define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */\r
+#define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */\r
+#define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */\r
+#define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */\r
+#define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */\r
+#define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */\r
+#define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */\r
+#define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */\r
+\r
+#endif\r
+/************************************************************\r
+* USCI Ax\r
+************************************************************/\r
+#ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */\r
+\r
+#define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */\r
+#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0\r
+#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1\r
+#define OFS_UCAxCTL0 (0x0001u)\r
+#define OFS_UCAxCTL1 (0x0000u)\r
+#define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */\r
+#define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */\r
+#define OFS_UCAxCTLW1 (0x0002u) /* USCI Ax Control Word Register 1 */\r
+#define OFS_UCAxCTLW1_L OFS_UCAxCTLW1\r
+#define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1\r
+#define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */\r
+#define OFS_UCAxBRW_L OFS_UCAxBRW\r
+#define OFS_UCAxBRW_H OFS_UCAxBRW+1\r
+#define OFS_UCAxBR0 (0x0006u)\r
+#define OFS_UCAxBR1 (0x0007u)\r
+#define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */\r
+#define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */\r
+#define OFS_UCAxMCTLW (0x0008u) /* USCI Ax Modulation Control */\r
+#define OFS_UCAxMCTLW_L OFS_UCAxMCTLW\r
+#define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1\r
+#define OFS_UCAxSTATW (0x000Au) /* USCI Ax Status Register */\r
+#define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */\r
+#define OFS_UCAxRXBUF_L OFS_UCAxRXBUF\r
+#define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1\r
+#define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */\r
+#define OFS_UCAxTXBUF_L OFS_UCAxTXBUF\r
+#define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1\r
+#define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */\r
+#define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */\r
+#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL\r
+#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1\r
+#define OFS_UCAxIRTCTL (0x0012u)\r
+#define OFS_UCAxIRRCTL (0x0013u)\r
+#define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */\r
+#define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */\r
+#define OFS_UCAxIE (0x001Au) /* USCI Ax Interrupt Enable Register */\r
+#define OFS_UCAxIE_L OFS_UCAxIE\r
+#define OFS_UCAxIE_H OFS_UCAxIE+1\r
+#define OFS_UCAxIFG (0x001Cu) /* USCI Ax Interrupt Flags Register */\r
+#define OFS_UCAxIFG_L OFS_UCAxIFG\r
+#define OFS_UCAxIFG_H OFS_UCAxIFG+1\r
+#define OFS_UCAxIE__UART (0x001Au)\r
+#define OFS_UCAxIE__UART_L OFS_UCAxIE__UART\r
+#define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1\r
+#define OFS_UCAxIFG__UART (0x001Cu)\r
+#define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART\r
+#define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1\r
+#define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */\r
+\r
+#define OFS_UCAxCTLW0__SPI (0x0000u)\r
+#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI\r
+#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1\r
+#define OFS_UCAxCTL0__SPI (0x0001u)\r
+#define OFS_UCAxCTL1__SPI (0x0000u)\r
+#define OFS_UCAxBRW__SPI (0x0006u)\r
+#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI\r
+#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1\r
+#define OFS_UCAxBR0__SPI (0x0006u)\r
+#define OFS_UCAxBR1__SPI (0x0007u)\r
+#define OFS_UCAxSTATW__SPI (0x000Au)\r
+#define OFS_UCAxRXBUF__SPI (0x000Cu)\r
+#define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI\r
+#define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1\r
+#define OFS_UCAxTXBUF__SPI (0x000Eu)\r
+#define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI\r
+#define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1\r
+#define OFS_UCAxIE__SPI (0x001Au)\r
+#define OFS_UCAxIFG__SPI (0x001Cu)\r
+#define OFS_UCAxIV__SPI (0x001Eu)\r
+\r
+#endif\r
+/************************************************************\r
+* USCI Bx\r
+************************************************************/\r
+#ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */\r
+\r
+#define OFS_UCBxCTLW0__SPI (0x0000u)\r
+#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI\r
+#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1\r
+#define OFS_UCBxCTL0__SPI (0x0001u)\r
+#define OFS_UCBxCTL1__SPI (0x0000u)\r
+#define OFS_UCBxBRW__SPI (0x0006u)\r
+#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI\r
+#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1\r
+#define OFS_UCBxBR0__SPI (0x0006u)\r
+#define OFS_UCBxBR1__SPI (0x0007u)\r
+#define OFS_UCBxSTATW__SPI (0x0008u)\r
+#define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI\r
+#define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1\r
+#define OFS_UCBxRXBUF__SPI (0x000Cu)\r
+#define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI\r
+#define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1\r
+#define OFS_UCBxTXBUF__SPI (0x000Eu)\r
+#define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI\r
+#define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1\r
+#define OFS_UCBxIE__SPI (0x002Au)\r
+#define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI\r
+#define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1\r
+#define OFS_UCBxIFG__SPI (0x002Cu)\r
+#define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI\r
+#define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1\r
+#define OFS_UCBxIV__SPI (0x002Eu)\r
+\r
+#define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */\r
+#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0\r
+#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1\r
+#define OFS_UCBxCTL0 (0x0001u)\r
+#define OFS_UCBxCTL1 (0x0000u)\r
+#define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */\r
+#define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */\r
+#define OFS_UCBxCTLW1 (0x0002u) /* USCI Bx Control Word Register 1 */\r
+#define OFS_UCBxCTLW1_L OFS_UCBxCTLW1\r
+#define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1\r
+#define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */\r
+#define OFS_UCBxBRW_L OFS_UCBxBRW\r
+#define OFS_UCBxBRW_H OFS_UCBxBRW+1\r
+#define OFS_UCBxBR0 (0x0006u)\r
+#define OFS_UCBxBR1 (0x0007u)\r
+#define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */\r
+#define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */\r
+#define OFS_UCBxSTATW (0x0008u) /* USCI Bx Status Word Register */\r
+#define OFS_UCBxSTATW_L OFS_UCBxSTATW\r
+#define OFS_UCBxSTATW_H OFS_UCBxSTATW+1\r
+#define OFS_UCBxSTATW__I2C (0x0008u)\r
+#define OFS_UCBxSTAT__I2C (0x0008u)\r
+#define OFS_UCBxBCNT__I2C (0x0009u)\r
+#define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */\r
+#define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */\r
+#define OFS_UCBxTBCNT (0x000Au) /* USCI Bx Byte Counter Threshold Register */\r
+#define OFS_UCBxTBCNT_L OFS_UCBxTBCNT\r
+#define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1\r
+#define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */\r
+#define OFS_UCBxRXBUF_L OFS_UCBxRXBUF\r
+#define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1\r
+#define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */\r
+#define OFS_UCBxTXBUF_L OFS_UCBxTXBUF\r
+#define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1\r
+#define OFS_UCBxI2COA0 (0x0014u) /* USCI Bx I2C Own Address 0 */\r
+#define OFS_UCBxI2COA0_L OFS_UCBxI2COA0\r
+#define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1\r
+#define OFS_UCBxI2COA1 (0x0016u) /* USCI Bx I2C Own Address 1 */\r
+#define OFS_UCBxI2COA1_L OFS_UCBxI2COA1\r
+#define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1\r
+#define OFS_UCBxI2COA2 (0x0018u) /* USCI Bx I2C Own Address 2 */\r
+#define OFS_UCBxI2COA2_L OFS_UCBxI2COA2\r
+#define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1\r
+#define OFS_UCBxI2COA3 (0x001Au) /* USCI Bx I2C Own Address 3 */\r
+#define OFS_UCBxI2COA3_L OFS_UCBxI2COA3\r
+#define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1\r
+#define OFS_UCBxADDRX (0x001Cu) /* USCI Bx Received Address Register */\r
+#define OFS_UCBxADDRX_L OFS_UCBxADDRX\r
+#define OFS_UCBxADDRX_H OFS_UCBxADDRX+1\r
+#define OFS_UCBxADDMASK (0x001Eu) /* USCI Bx Address Mask Register */\r
+#define OFS_UCBxADDMASK_L OFS_UCBxADDMASK\r
+#define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1\r
+#define OFS_UCBxI2CSA (0x0020u) /* USCI Bx I2C Slave Address */\r
+#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA\r
+#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1\r
+#define OFS_UCBxIE (0x002Au) /* USCI Bx Interrupt Enable Register */\r
+#define OFS_UCBxIE_L OFS_UCBxIE\r
+#define OFS_UCBxIE_H OFS_UCBxIE+1\r
+#define OFS_UCBxIFG (0x002Cu) /* USCI Bx Interrupt Flags Register */\r
+#define OFS_UCBxIFG_L OFS_UCBxIFG\r
+#define OFS_UCBxIFG_H OFS_UCBxIFG+1\r
+#define OFS_UCBxIE__I2C (0x002Au)\r
+#define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C\r
+#define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1\r
+#define OFS_UCBxIFG__I2C (0x002Cu)\r
+#define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C\r
+#define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1\r
+#define OFS_UCBxIV (0x002Eu) /* USCI Bx Interrupt Vector Register */\r
+\r
+#endif\r
+#if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__))\r
+\r
+// UCAxCTLW0 UART-Mode Control Bits\r
+#define UCPEN (0x8000u) /* Async. Mode: Parity enable */\r
+#define UCPAR (0x4000u) /* Async. Mode: Parity 0:odd / 1:even */\r
+#define UCMSB (0x2000u) /* Async. Mode: MSB first 0:LSB / 1:MSB */\r
+#define UC7BIT (0x1000u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */\r
+#define UCSPB (0x0800u) /* Async. Mode: Stop Bits 0:one / 1: two */\r
+#define UCMODE1 (0x0400u) /* Async. Mode: USCI Mode 1 */\r
+#define UCMODE0 (0x0200u) /* Async. Mode: USCI Mode 0 */\r
+#define UCSYNC (0x0100u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */\r
+#define UCSSEL1 (0x0080u) /* USCI 0 Clock Source Select 1 */\r
+#define UCSSEL0 (0x0040u) /* USCI 0 Clock Source Select 0 */\r
+#define UCRXEIE (0x0020u) /* RX Error interrupt enable */\r
+#define UCBRKIE (0x0010u) /* Break interrupt enable */\r
+#define UCDORM (0x0008u) /* Dormant (Sleep) Mode */\r
+#define UCTXADDR (0x0004u) /* Send next Data as Address */\r
+#define UCTXBRK (0x0002u) /* Send next Data as Break */\r
+#define UCSWRST (0x0001u) /* USCI Software Reset */\r
+\r
+// UCAxCTLW0 UART-Mode Control Bits\r
+#define UCSSEL1_L (0x0080u) /* USCI 0 Clock Source Select 1 */\r
+#define UCSSEL0_L (0x0040u) /* USCI 0 Clock Source Select 0 */\r
+#define UCRXEIE_L (0x0020u) /* RX Error interrupt enable */\r
+#define UCBRKIE_L (0x0010u) /* Break interrupt enable */\r
+#define UCDORM_L (0x0008u) /* Dormant (Sleep) Mode */\r
+#define UCTXADDR_L (0x0004u) /* Send next Data as Address */\r
+#define UCTXBRK_L (0x0002u) /* Send next Data as Break */\r
+#define UCSWRST_L (0x0001u) /* USCI Software Reset */\r
+\r
+// UCAxCTLW0 UART-Mode Control Bits\r
+#define UCPEN_H (0x0080u) /* Async. Mode: Parity enable */\r
+#define UCPAR_H (0x0040u) /* Async. Mode: Parity 0:odd / 1:even */\r
+#define UCMSB_H (0x0020u) /* Async. Mode: MSB first 0:LSB / 1:MSB */\r
+#define UC7BIT_H (0x0010u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */\r
+#define UCSPB_H (0x0008u) /* Async. Mode: Stop Bits 0:one / 1: two */\r
+#define UCMODE1_H (0x0004u) /* Async. Mode: USCI Mode 1 */\r
+#define UCMODE0_H (0x0002u) /* Async. Mode: USCI Mode 0 */\r
+#define UCSYNC_H (0x0001u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */\r
+\r
+// UCxxCTLW0 SPI-Mode Control Bits\r
+#define UCCKPH (0x8000u) /* Sync. Mode: Clock Phase */\r
+#define UCCKPL (0x4000u) /* Sync. Mode: Clock Polarity */\r
+#define UCMST (0x0800u) /* Sync. Mode: Master Select */\r
+//#define res (0x0020u) /* reserved */\r
+//#define res (0x0010u) /* reserved */\r
+//#define res (0x0008u) /* reserved */\r
+//#define res (0x0004u) /* reserved */\r
+#define UCSTEM (0x0002u) /* USCI STE Mode */\r
+\r
+// UCBxCTLW0 I2C-Mode Control Bits\r
+#define UCA10 (0x8000u) /* 10-bit Address Mode */\r
+#define UCSLA10 (0x4000u) /* 10-bit Slave Address Mode */\r
+#define UCMM (0x2000u) /* Multi-Master Environment */\r
+//#define res (0x1000u) /* reserved */\r
+//#define res (0x0100u) /* reserved */\r
+#define UCTXACK (0x0020u) /* Transmit ACK */\r
+#define UCTR (0x0010u) /* Transmit/Receive Select/Flag */\r
+#define UCTXNACK (0x0008u) /* Transmit NACK */\r
+#define UCTXSTP (0x0004u) /* Transmit STOP */\r
+#define UCTXSTT (0x0002u) /* Transmit START */\r
+\r
+// UCBxCTLW0 I2C-Mode Control Bits\r
+//#define res (0x1000u) /* reserved */\r
+//#define res (0x0100u) /* reserved */\r
+#define UCTXACK_L (0x0020u) /* Transmit ACK */\r
+#define UCTR_L (0x0010u) /* Transmit/Receive Select/Flag */\r
+#define UCTXNACK_L (0x0008u) /* Transmit NACK */\r
+#define UCTXSTP_L (0x0004u) /* Transmit STOP */\r
+#define UCTXSTT_L (0x0002u) /* Transmit START */\r
+\r
+// UCBxCTLW0 I2C-Mode Control Bits\r
+#define UCA10_H (0x0080u) /* 10-bit Address Mode */\r
+#define UCSLA10_H (0x0040u) /* 10-bit Slave Address Mode */\r
+#define UCMM_H (0x0020u) /* Multi-Master Environment */\r
+//#define res (0x1000u) /* reserved */\r
+//#define res (0x0100u) /* reserved */\r
+\r
+#define UCMODE_0 (0x0000u) /* Sync. Mode: USCI Mode: 0 */\r
+#define UCMODE_1 (0x0200u) /* Sync. Mode: USCI Mode: 1 */\r
+#define UCMODE_2 (0x0400u) /* Sync. Mode: USCI Mode: 2 */\r
+#define UCMODE_3 (0x0600u) /* Sync. Mode: USCI Mode: 3 */\r
+\r
+#define UCSSEL_0 (0x0000u) /* USCI 0 Clock Source: 0 */\r
+#define UCSSEL_1 (0x0040u) /* USCI 0 Clock Source: 1 */\r
+#define UCSSEL_2 (0x0080u) /* USCI 0 Clock Source: 2 */\r
+#define UCSSEL_3 (0x00C0u) /* USCI 0 Clock Source: 3 */\r
+#define UCSSEL__UCLK (0x0000u) /* USCI 0 Clock Source: UCLK */\r
+#define UCSSEL__ACLK (0x0040u) /* USCI 0 Clock Source: ACLK */\r
+#define UCSSEL__SMCLK (0x0080u) /* USCI 0 Clock Source: SMCLK */\r
+\r
+// UCAxCTLW1 UART-Mode Control Bits\r
+#define UCGLIT1 (0x0002u) /* USCI Deglitch Time Bit 1 */\r
+#define UCGLIT0 (0x0001u) /* USCI Deglitch Time Bit 0 */\r
+\r
+// UCAxCTLW1 UART-Mode Control Bits\r
+#define UCGLIT1_L (0x0002u) /* USCI Deglitch Time Bit 1 */\r
+#define UCGLIT0_L (0x0001u) /* USCI Deglitch Time Bit 0 */\r
+\r
+// UCBxCTLW1 I2C-Mode Control Bits\r
+#define UCETXINT (0x0100u) /* USCI Early UCTXIFG0 */\r
+#define UCCLTO1 (0x0080u) /* USCI Clock low timeout Bit: 1 */\r
+#define UCCLTO0 (0x0040u) /* USCI Clock low timeout Bit: 0 */\r
+#define UCSTPNACK (0x0020u) /* USCI Acknowledge Stop last byte */\r
+#define UCSWACK (0x0010u) /* USCI Software controlled ACK */\r
+#define UCASTP1 (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */\r
+#define UCASTP0 (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */\r
+#define UCGLIT1 (0x0002u) /* USCI Deglitch time Bit: 1 */\r
+#define UCGLIT0 (0x0001u) /* USCI Deglitch time Bit: 0 */\r
+\r
+// UCBxCTLW1 I2C-Mode Control Bits\r
+#define UCCLTO1_L (0x0080u) /* USCI Clock low timeout Bit: 1 */\r
+#define UCCLTO0_L (0x0040u) /* USCI Clock low timeout Bit: 0 */\r
+#define UCSTPNACK_L (0x0020u) /* USCI Acknowledge Stop last byte */\r
+#define UCSWACK_L (0x0010u) /* USCI Software controlled ACK */\r
+#define UCASTP1_L (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */\r
+#define UCASTP0_L (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */\r
+#define UCGLIT1_L (0x0002u) /* USCI Deglitch time Bit: 1 */\r
+#define UCGLIT0_L (0x0001u) /* USCI Deglitch time Bit: 0 */\r
+\r
+// UCBxCTLW1 I2C-Mode Control Bits\r
+#define UCETXINT_H (0x0001u) /* USCI Early UCTXIFG0 */\r
+\r
+#define UCGLIT_0 (0x0000u) /* USCI Deglitch time: 0 */\r
+#define UCGLIT_1 (0x0001u) /* USCI Deglitch time: 1 */\r
+#define UCGLIT_2 (0x0002u) /* USCI Deglitch time: 2 */\r
+#define UCGLIT_3 (0x0003u) /* USCI Deglitch time: 3 */\r
+\r
+#define UCASTP_0 (0x0000u) /* USCI Automatic Stop condition generation: 0 */\r
+#define UCASTP_1 (0x0004u) /* USCI Automatic Stop condition generation: 1 */\r
+#define UCASTP_2 (0x0008u) /* USCI Automatic Stop condition generation: 2 */\r
+#define UCASTP_3 (0x000Cu) /* USCI Automatic Stop condition generation: 3 */\r
+\r
+#define UCCLTO_0 (0x0000u) /* USCI Clock low timeout: 0 */\r
+#define UCCLTO_1 (0x0040u) /* USCI Clock low timeout: 1 */\r
+#define UCCLTO_2 (0x0080u) /* USCI Clock low timeout: 2 */\r
+#define UCCLTO_3 (0x00C0u) /* USCI Clock low timeout: 3 */\r
+\r
+/* UCAxMCTLW Control Bits */\r
+#define UCBRS7 (0x8000u) /* USCI Second Stage Modulation Select 7 */\r
+#define UCBRS6 (0x4000u) /* USCI Second Stage Modulation Select 6 */\r
+#define UCBRS5 (0x2000u) /* USCI Second Stage Modulation Select 5 */\r
+#define UCBRS4 (0x1000u) /* USCI Second Stage Modulation Select 4 */\r
+#define UCBRS3 (0x0800u) /* USCI Second Stage Modulation Select 3 */\r
+#define UCBRS2 (0x0400u) /* USCI Second Stage Modulation Select 2 */\r
+#define UCBRS1 (0x0200u) /* USCI Second Stage Modulation Select 1 */\r
+#define UCBRS0 (0x0100u) /* USCI Second Stage Modulation Select 0 */\r
+#define UCBRF3 (0x0080u) /* USCI First Stage Modulation Select 3 */\r
+#define UCBRF2 (0x0040u) /* USCI First Stage Modulation Select 2 */\r
+#define UCBRF1 (0x0020u) /* USCI First Stage Modulation Select 1 */\r
+#define UCBRF0 (0x0010u) /* USCI First Stage Modulation Select 0 */\r
+#define UCOS16 (0x0001u) /* USCI 16-times Oversampling enable */\r
+\r
+/* UCAxMCTLW Control Bits */\r
+#define UCBRF3_L (0x0080u) /* USCI First Stage Modulation Select 3 */\r
+#define UCBRF2_L (0x0040u) /* USCI First Stage Modulation Select 2 */\r
+#define UCBRF1_L (0x0020u) /* USCI First Stage Modulation Select 1 */\r
+#define UCBRF0_L (0x0010u) /* USCI First Stage Modulation Select 0 */\r
+#define UCOS16_L (0x0001u) /* USCI 16-times Oversampling enable */\r
+\r
+/* UCAxMCTLW Control Bits */\r
+#define UCBRS7_H (0x0080u) /* USCI Second Stage Modulation Select 7 */\r
+#define UCBRS6_H (0x0040u) /* USCI Second Stage Modulation Select 6 */\r
+#define UCBRS5_H (0x0020u) /* USCI Second Stage Modulation Select 5 */\r
+#define UCBRS4_H (0x0010u) /* USCI Second Stage Modulation Select 4 */\r
+#define UCBRS3_H (0x0008u) /* USCI Second Stage Modulation Select 3 */\r
+#define UCBRS2_H (0x0004u) /* USCI Second Stage Modulation Select 2 */\r
+#define UCBRS1_H (0x0002u) /* USCI Second Stage Modulation Select 1 */\r
+#define UCBRS0_H (0x0001u) /* USCI Second Stage Modulation Select 0 */\r
+\r
+#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */\r
+#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */\r
+#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */\r
+#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */\r
+#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */\r
+#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */\r
+#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */\r
+#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */\r
+#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */\r
+#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */\r
+#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */\r
+#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */\r
+#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */\r
+#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */\r
+#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */\r
+#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */\r
+\r
+/* UCAxSTATW Control Bits */\r
+#define UCLISTEN (0x0080u) /* USCI Listen mode */\r
+#define UCFE (0x0040u) /* USCI Frame Error Flag */\r
+#define UCOE (0x0020u) /* USCI Overrun Error Flag */\r
+#define UCPE (0x0010u) /* USCI Parity Error Flag */\r
+#define UCBRK (0x0008u) /* USCI Break received */\r
+#define UCRXERR (0x0004u) /* USCI RX Error Flag */\r
+#define UCADDR (0x0002u) /* USCI Address received Flag */\r
+#define UCBUSY (0x0001u) /* USCI Busy Flag */\r
+#define UCIDLE (0x0002u) /* USCI Idle line detected Flag */\r
+\r
+/* UCBxSTATW I2C Control Bits */\r
+#define UCBCNT7 (0x8000u) /* USCI Byte Counter Bit 7 */\r
+#define UCBCNT6 (0x4000u) /* USCI Byte Counter Bit 6 */\r
+#define UCBCNT5 (0x2000u) /* USCI Byte Counter Bit 5 */\r
+#define UCBCNT4 (0x1000u) /* USCI Byte Counter Bit 4 */\r
+#define UCBCNT3 (0x0800u) /* USCI Byte Counter Bit 3 */\r
+#define UCBCNT2 (0x0400u) /* USCI Byte Counter Bit 2 */\r
+#define UCBCNT1 (0x0200u) /* USCI Byte Counter Bit 1 */\r
+#define UCBCNT0 (0x0100u) /* USCI Byte Counter Bit 0 */\r
+#define UCSCLLOW (0x0040u) /* SCL low */\r
+#define UCGC (0x0020u) /* General Call address received Flag */\r
+#define UCBBUSY (0x0010u) /* Bus Busy Flag */\r
+\r
+/* UCBxTBCNT I2C Control Bits */\r
+#define UCTBCNT7 (0x0080u) /* USCI Byte Counter Bit 7 */\r
+#define UCTBCNT6 (0x0040u) /* USCI Byte Counter Bit 6 */\r
+#define UCTBCNT5 (0x0020u) /* USCI Byte Counter Bit 5 */\r
+#define UCTBCNT4 (0x0010u) /* USCI Byte Counter Bit 4 */\r
+#define UCTBCNT3 (0x0008u) /* USCI Byte Counter Bit 3 */\r
+#define UCTBCNT2 (0x0004u) /* USCI Byte Counter Bit 2 */\r
+#define UCTBCNT1 (0x0002u) /* USCI Byte Counter Bit 1 */\r
+#define UCTBCNT0 (0x0001u) /* USCI Byte Counter Bit 0 */\r
+\r
+/* UCAxIRCTL Control Bits */\r
+#define UCIRRXFL5 (0x8000u) /* IRDA Receive Filter Length 5 */\r
+#define UCIRRXFL4 (0x4000u) /* IRDA Receive Filter Length 4 */\r
+#define UCIRRXFL3 (0x2000u) /* IRDA Receive Filter Length 3 */\r
+#define UCIRRXFL2 (0x1000u) /* IRDA Receive Filter Length 2 */\r
+#define UCIRRXFL1 (0x0800u) /* IRDA Receive Filter Length 1 */\r
+#define UCIRRXFL0 (0x0400u) /* IRDA Receive Filter Length 0 */\r
+#define UCIRRXPL (0x0200u) /* IRDA Receive Input Polarity */\r
+#define UCIRRXFE (0x0100u) /* IRDA Receive Filter enable */\r
+#define UCIRTXPL5 (0x0080u) /* IRDA Transmit Pulse Length 5 */\r
+#define UCIRTXPL4 (0x0040u) /* IRDA Transmit Pulse Length 4 */\r
+#define UCIRTXPL3 (0x0020u) /* IRDA Transmit Pulse Length 3 */\r
+#define UCIRTXPL2 (0x0010u) /* IRDA Transmit Pulse Length 2 */\r
+#define UCIRTXPL1 (0x0008u) /* IRDA Transmit Pulse Length 1 */\r
+#define UCIRTXPL0 (0x0004u) /* IRDA Transmit Pulse Length 0 */\r
+#define UCIRTXCLK (0x0002u) /* IRDA Transmit Pulse Clock Select */\r
+#define UCIREN (0x0001u) /* IRDA Encoder/Decoder enable */\r
+\r
+/* UCAxIRCTL Control Bits */\r
+#define UCIRTXPL5_L (0x0080u) /* IRDA Transmit Pulse Length 5 */\r
+#define UCIRTXPL4_L (0x0040u) /* IRDA Transmit Pulse Length 4 */\r
+#define UCIRTXPL3_L (0x0020u) /* IRDA Transmit Pulse Length 3 */\r
+#define UCIRTXPL2_L (0x0010u) /* IRDA Transmit Pulse Length 2 */\r
+#define UCIRTXPL1_L (0x0008u) /* IRDA Transmit Pulse Length 1 */\r
+#define UCIRTXPL0_L (0x0004u) /* IRDA Transmit Pulse Length 0 */\r
+#define UCIRTXCLK_L (0x0002u) /* IRDA Transmit Pulse Clock Select */\r
+#define UCIREN_L (0x0001u) /* IRDA Encoder/Decoder enable */\r
+\r
+/* UCAxIRCTL Control Bits */\r
+#define UCIRRXFL5_H (0x0080u) /* IRDA Receive Filter Length 5 */\r
+#define UCIRRXFL4_H (0x0040u) /* IRDA Receive Filter Length 4 */\r
+#define UCIRRXFL3_H (0x0020u) /* IRDA Receive Filter Length 3 */\r
+#define UCIRRXFL2_H (0x0010u) /* IRDA Receive Filter Length 2 */\r
+#define UCIRRXFL1_H (0x0008u) /* IRDA Receive Filter Length 1 */\r
+#define UCIRRXFL0_H (0x0004u) /* IRDA Receive Filter Length 0 */\r
+#define UCIRRXPL_H (0x0002u) /* IRDA Receive Input Polarity */\r
+#define UCIRRXFE_H (0x0001u) /* IRDA Receive Filter enable */\r
+\r
+/* UCAxABCTL Control Bits */\r
+//#define res (0x80) /* reserved */\r
+//#define res (0x40) /* reserved */\r
+#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */\r
+#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */\r
+#define UCSTOE (0x08) /* Sync-Field Timeout error */\r
+#define UCBTOE (0x04) /* Break Timeout error */\r
+//#define res (0x02) /* reserved */\r
+#define UCABDEN (0x01) /* Auto Baud Rate detect enable */\r
+\r
+/* UCBxI2COA0 Control Bits */\r
+#define UCGCEN (0x8000u) /* I2C General Call enable */\r
+#define UCOAEN (0x0400u) /* I2C Own Address enable */\r
+#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */\r
+#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */\r
+#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */\r
+#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */\r
+#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */\r
+#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */\r
+#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */\r
+#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */\r
+#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */\r
+#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COA0 Control Bits */\r
+#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */\r
+#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */\r
+#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */\r
+#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */\r
+#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */\r
+#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */\r
+#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */\r
+#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COA0 Control Bits */\r
+#define UCGCEN_H (0x0080u) /* I2C General Call enable */\r
+#define UCOAEN_H (0x0004u) /* I2C Own Address enable */\r
+#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */\r
+#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */\r
+\r
+/* UCBxI2COAx Control Bits */\r
+#define UCOAEN (0x0400u) /* I2C Own Address enable */\r
+#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */\r
+#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */\r
+#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */\r
+#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */\r
+#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */\r
+#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */\r
+#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */\r
+#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */\r
+#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */\r
+#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COAx Control Bits */\r
+#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */\r
+#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */\r
+#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */\r
+#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */\r
+#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */\r
+#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */\r
+#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */\r
+#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COAx Control Bits */\r
+#define UCOAEN_H (0x0004u) /* I2C Own Address enable */\r
+#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */\r
+#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */\r
+\r
+/* UCBxADDRX Control Bits */\r
+#define UCADDRX9 (0x0200u) /* I2C Receive Address Bit 9 */\r
+#define UCADDRX8 (0x0100u) /* I2C Receive Address Bit 8 */\r
+#define UCADDRX7 (0x0080u) /* I2C Receive Address Bit 7 */\r
+#define UCADDRX6 (0x0040u) /* I2C Receive Address Bit 6 */\r
+#define UCADDRX5 (0x0020u) /* I2C Receive Address Bit 5 */\r
+#define UCADDRX4 (0x0010u) /* I2C Receive Address Bit 4 */\r
+#define UCADDRX3 (0x0008u) /* I2C Receive Address Bit 3 */\r
+#define UCADDRX2 (0x0004u) /* I2C Receive Address Bit 2 */\r
+#define UCADDRX1 (0x0002u) /* I2C Receive Address Bit 1 */\r
+#define UCADDRX0 (0x0001u) /* I2C Receive Address Bit 0 */\r
+\r
+/* UCBxADDRX Control Bits */\r
+#define UCADDRX7_L (0x0080u) /* I2C Receive Address Bit 7 */\r
+#define UCADDRX6_L (0x0040u) /* I2C Receive Address Bit 6 */\r
+#define UCADDRX5_L (0x0020u) /* I2C Receive Address Bit 5 */\r
+#define UCADDRX4_L (0x0010u) /* I2C Receive Address Bit 4 */\r
+#define UCADDRX3_L (0x0008u) /* I2C Receive Address Bit 3 */\r
+#define UCADDRX2_L (0x0004u) /* I2C Receive Address Bit 2 */\r
+#define UCADDRX1_L (0x0002u) /* I2C Receive Address Bit 1 */\r
+#define UCADDRX0_L (0x0001u) /* I2C Receive Address Bit 0 */\r
+\r
+/* UCBxADDRX Control Bits */\r
+#define UCADDRX9_H (0x0002u) /* I2C Receive Address Bit 9 */\r
+#define UCADDRX8_H (0x0001u) /* I2C Receive Address Bit 8 */\r
+\r
+/* UCBxADDMASK Control Bits */\r
+#define UCADDMASK9 (0x0200u) /* I2C Address Mask Bit 9 */\r
+#define UCADDMASK8 (0x0100u) /* I2C Address Mask Bit 8 */\r
+#define UCADDMASK7 (0x0080u) /* I2C Address Mask Bit 7 */\r
+#define UCADDMASK6 (0x0040u) /* I2C Address Mask Bit 6 */\r
+#define UCADDMASK5 (0x0020u) /* I2C Address Mask Bit 5 */\r
+#define UCADDMASK4 (0x0010u) /* I2C Address Mask Bit 4 */\r
+#define UCADDMASK3 (0x0008u) /* I2C Address Mask Bit 3 */\r
+#define UCADDMASK2 (0x0004u) /* I2C Address Mask Bit 2 */\r
+#define UCADDMASK1 (0x0002u) /* I2C Address Mask Bit 1 */\r
+#define UCADDMASK0 (0x0001u) /* I2C Address Mask Bit 0 */\r
+\r
+/* UCBxADDMASK Control Bits */\r
+#define UCADDMASK7_L (0x0080u) /* I2C Address Mask Bit 7 */\r
+#define UCADDMASK6_L (0x0040u) /* I2C Address Mask Bit 6 */\r
+#define UCADDMASK5_L (0x0020u) /* I2C Address Mask Bit 5 */\r
+#define UCADDMASK4_L (0x0010u) /* I2C Address Mask Bit 4 */\r
+#define UCADDMASK3_L (0x0008u) /* I2C Address Mask Bit 3 */\r
+#define UCADDMASK2_L (0x0004u) /* I2C Address Mask Bit 2 */\r
+#define UCADDMASK1_L (0x0002u) /* I2C Address Mask Bit 1 */\r
+#define UCADDMASK0_L (0x0001u) /* I2C Address Mask Bit 0 */\r
+\r
+/* UCBxADDMASK Control Bits */\r
+#define UCADDMASK9_H (0x0002u) /* I2C Address Mask Bit 9 */\r
+#define UCADDMASK8_H (0x0001u) /* I2C Address Mask Bit 8 */\r
+\r
+/* UCBxI2CSA Control Bits */\r
+#define UCSA9 (0x0200u) /* I2C Slave Address Bit 9 */\r
+#define UCSA8 (0x0100u) /* I2C Slave Address Bit 8 */\r
+#define UCSA7 (0x0080u) /* I2C Slave Address Bit 7 */\r
+#define UCSA6 (0x0040u) /* I2C Slave Address Bit 6 */\r
+#define UCSA5 (0x0020u) /* I2C Slave Address Bit 5 */\r
+#define UCSA4 (0x0010u) /* I2C Slave Address Bit 4 */\r
+#define UCSA3 (0x0008u) /* I2C Slave Address Bit 3 */\r
+#define UCSA2 (0x0004u) /* I2C Slave Address Bit 2 */\r
+#define UCSA1 (0x0002u) /* I2C Slave Address Bit 1 */\r
+#define UCSA0 (0x0001u) /* I2C Slave Address Bit 0 */\r
+\r
+/* UCBxI2CSA Control Bits */\r
+#define UCSA7_L (0x0080u) /* I2C Slave Address Bit 7 */\r
+#define UCSA6_L (0x0040u) /* I2C Slave Address Bit 6 */\r
+#define UCSA5_L (0x0020u) /* I2C Slave Address Bit 5 */\r
+#define UCSA4_L (0x0010u) /* I2C Slave Address Bit 4 */\r
+#define UCSA3_L (0x0008u) /* I2C Slave Address Bit 3 */\r
+#define UCSA2_L (0x0004u) /* I2C Slave Address Bit 2 */\r
+#define UCSA1_L (0x0002u) /* I2C Slave Address Bit 1 */\r
+#define UCSA0_L (0x0001u) /* I2C Slave Address Bit 0 */\r
+\r
+/* UCBxI2CSA Control Bits */\r
+#define UCSA9_H (0x0002u) /* I2C Slave Address Bit 9 */\r
+#define UCSA8_H (0x0001u) /* I2C Slave Address Bit 8 */\r
+\r
+/* UCAxIE UART Control Bits */\r
+#define UCTXCPTIE (0x0008u) /* UART Transmit Complete Interrupt Enable */\r
+#define UCSTTIE (0x0004u) /* UART Start Bit Interrupt Enalble */\r
+#define UCTXIE (0x0002u) /* UART Transmit Interrupt Enable */\r
+#define UCRXIE (0x0001u) /* UART Receive Interrupt Enable */\r
+\r
+/* UCAxIE/UCBxIE SPI Control Bits */\r
+\r
+/* UCBxIE I2C Control Bits */\r
+#define UCBIT9IE (0x4000u) /* I2C Bit 9 Position Interrupt Enable 3 */\r
+#define UCTXIE3 (0x2000u) /* I2C Transmit Interrupt Enable 3 */\r
+#define UCRXIE3 (0x1000u) /* I2C Receive Interrupt Enable 3 */\r
+#define UCTXIE2 (0x0800u) /* I2C Transmit Interrupt Enable 2 */\r
+#define UCRXIE2 (0x0400u) /* I2C Receive Interrupt Enable 2 */\r
+#define UCTXIE1 (0x0200u) /* I2C Transmit Interrupt Enable 1 */\r
+#define UCRXIE1 (0x0100u) /* I2C Receive Interrupt Enable 1 */\r
+#define UCCLTOIE (0x0080u) /* I2C Clock Low Timeout interrupt enable */\r
+#define UCBCNTIE (0x0040u) /* I2C Automatic stop assertion interrupt enable */\r
+#define UCNACKIE (0x0020u) /* I2C NACK Condition interrupt enable */\r
+#define UCALIE (0x0010u) /* I2C Arbitration Lost interrupt enable */\r
+#define UCSTPIE (0x0008u) /* I2C STOP Condition interrupt enable */\r
+#define UCSTTIE (0x0004u) /* I2C START Condition interrupt enable */\r
+#define UCTXIE0 (0x0002u) /* I2C Transmit Interrupt Enable 0 */\r
+#define UCRXIE0 (0x0001u) /* I2C Receive Interrupt Enable 0 */\r
+\r
+/* UCAxIFG UART Control Bits */\r
+#define UCTXCPTIFG (0x0008u) /* UART Transmit Complete Interrupt Flag */\r
+#define UCSTTIFG (0x0004u) /* UART Start Bit Interrupt Flag */\r
+#define UCTXIFG (0x0002u) /* UART Transmit Interrupt Flag */\r
+#define UCRXIFG (0x0001u) /* UART Receive Interrupt Flag */\r
+\r
+/* UCAxIFG/UCBxIFG SPI Control Bits */\r
+#define UCTXIFG (0x0002u) /* SPI Transmit Interrupt Flag */\r
+#define UCRXIFG (0x0001u) /* SPI Receive Interrupt Flag */\r
+\r
+/* UCBxIFG Control Bits */\r
+#define UCBIT9IFG (0x4000u) /* I2C Bit 9 Possition Interrupt Flag 3 */\r
+#define UCTXIFG3 (0x2000u) /* I2C Transmit Interrupt Flag 3 */\r
+#define UCRXIFG3 (0x1000u) /* I2C Receive Interrupt Flag 3 */\r
+#define UCTXIFG2 (0x0800u) /* I2C Transmit Interrupt Flag 2 */\r
+#define UCRXIFG2 (0x0400u) /* I2C Receive Interrupt Flag 2 */\r
+#define UCTXIFG1 (0x0200u) /* I2C Transmit Interrupt Flag 1 */\r
+#define UCRXIFG1 (0x0100u) /* I2C Receive Interrupt Flag 1 */\r
+#define UCCLTOIFG (0x0080u) /* I2C Clock low Timeout interrupt Flag */\r
+#define UCBCNTIFG (0x0040u) /* I2C Byte counter interrupt flag */\r
+#define UCNACKIFG (0x0020u) /* I2C NACK Condition interrupt Flag */\r
+#define UCALIFG (0x0010u) /* I2C Arbitration Lost interrupt Flag */\r
+#define UCSTPIFG (0x0008u) /* I2C STOP Condition interrupt Flag */\r
+#define UCSTTIFG (0x0004u) /* I2C START Condition interrupt Flag */\r
+#define UCTXIFG0 (0x0002u) /* I2C Transmit Interrupt Flag 0 */\r
+#define UCRXIFG0 (0x0001u) /* I2C Receive Interrupt Flag 0 */\r
+\r
+/* USCI UART Definitions */\r
+#define USCI_NONE (0x0000u) /* No Interrupt pending */\r
+#define USCI_UART_UCRXIFG (0x0002u) /* USCI UCRXIFG */\r
+#define USCI_UART_UCTXIFG (0x0004u) /* USCI UCTXIFG */\r
+#define USCI_UART_UCSTTIFG (0x0006u) /* USCI UCSTTIFG */\r
+#define USCI_UART_UCTXCPTIFG (0x0008u) /* USCI UCTXCPTIFG */\r
+\r
+/* USCI SPI Definitions */\r
+#define USCI_SPI_UCRXIFG (0x0002u) /* USCI UCRXIFG */\r
+#define USCI_SPI_UCTXIFG (0x0004u) /* USCI UCTXIFG */\r
+\r
+/* USCI I2C Definitions */\r
+#define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */\r
+#define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */\r
+#define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/\r
+#define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/\r
+#define USCI_I2C_UCRXIFG3 (0x000Au) /* USCI I2C Mode: UCRXIFG3 */\r
+#define USCI_I2C_UCTXIFG3 (0x000Cu) /* USCI I2C Mode: UCTXIFG3 */\r
+#define USCI_I2C_UCRXIFG2 (0x000Eu) /* USCI I2C Mode: UCRXIFG2 */\r
+#define USCI_I2C_UCTXIFG2 (0x0010u) /* USCI I2C Mode: UCTXIFG2 */\r
+#define USCI_I2C_UCRXIFG1 (0x0012u) /* USCI I2C Mode: UCRXIFG1 */\r
+#define USCI_I2C_UCTXIFG1 (0x0014u) /* USCI I2C Mode: UCTXIFG1 */\r
+#define USCI_I2C_UCRXIFG0 (0x0016u) /* USCI I2C Mode: UCRXIFG0 */\r
+#define USCI_I2C_UCTXIFG0 (0x0018u) /* USCI I2C Mode: UCTXIFG0 */\r
+#define USCI_I2C_UCBCNTIFG (0x001Au) /* USCI I2C Mode: UCBCNTIFG */\r
+#define USCI_I2C_UCCLTOIFG (0x001Cu) /* USCI I2C Mode: UCCLTOIFG */\r
+#define USCI_I2C_UCBIT9IFG (0x001Eu) /* USCI I2C Mode: UCBIT9IFG */\r
+\r
+#endif\r
+/************************************************************\r
+* WATCHDOG TIMER A\r
+************************************************************/\r
+#ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */\r
+\r
+#define OFS_WDTCTL (0x000Cu) /* Watchdog Timer Control */\r
+#define OFS_WDTCTL_L OFS_WDTCTL\r
+#define OFS_WDTCTL_H OFS_WDTCTL+1\r
+/* The bit names have been prefixed with "WDT" */\r
+/* WDTCTL Control Bits */\r
+#define WDTIS0 (0x0001u) /* WDT - Timer Interval Select 0 */\r
+#define WDTIS1 (0x0002u) /* WDT - Timer Interval Select 1 */\r
+#define WDTIS2 (0x0004u) /* WDT - Timer Interval Select 2 */\r
+#define WDTCNTCL (0x0008u) /* WDT - Timer Clear */\r
+#define WDTTMSEL (0x0010u) /* WDT - Timer Mode Select */\r
+#define WDTSSEL0 (0x0020u) /* WDT - Timer Clock Source Select 0 */\r
+#define WDTSSEL1 (0x0040u) /* WDT - Timer Clock Source Select 1 */\r
+#define WDTHOLD (0x0080u) /* WDT - Timer hold */\r
+\r
+/* WDTCTL Control Bits */\r
+#define WDTIS0_L (0x0001u) /* WDT - Timer Interval Select 0 */\r
+#define WDTIS1_L (0x0002u) /* WDT - Timer Interval Select 1 */\r
+#define WDTIS2_L (0x0004u) /* WDT - Timer Interval Select 2 */\r
+#define WDTCNTCL_L (0x0008u) /* WDT - Timer Clear */\r
+#define WDTTMSEL_L (0x0010u) /* WDT - Timer Mode Select */\r
+#define WDTSSEL0_L (0x0020u) /* WDT - Timer Clock Source Select 0 */\r
+#define WDTSSEL1_L (0x0040u) /* WDT - Timer Clock Source Select 1 */\r
+#define WDTHOLD_L (0x0080u) /* WDT - Timer hold */\r
+\r
+#define WDTPW (0x5A00u)\r
+\r
+#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */\r
+#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */\r
+#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */\r
+#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */\r
+#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */\r
+#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */\r
+#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */\r
+#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */\r
+#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */\r
+#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */\r
+#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */\r
+#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */\r
+#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */\r
+#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */\r
+#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */\r
+#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */\r
+\r
+#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */\r
+#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */\r
+#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */\r
+#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */\r
+#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */\r
+#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */\r
+#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */\r
+\r
+/* WDT-interval times [1ms] coded with Bits 0-2 */\r
+/* WDT is clocked by fSMCLK (assumed 1MHz) */\r
+#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */\r
+#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */\r
+#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */\r
+#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */\r
+/* WDT is clocked by fACLK (assumed 32KHz) */\r
+#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */\r
+#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */\r
+#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */\r
+#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */\r
+/* Watchdog mode -> reset after expired time */\r
+/* WDT is clocked by fSMCLK (assumed 1MHz) */\r
+#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */\r
+#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */\r
+#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */\r
+#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */\r
+/* WDT is clocked by fACLK (assumed 32KHz) */\r
+#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */\r
+#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */\r
+#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */\r
+#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */\r
+\r
+#endif\r
+\r
+/************************************************************\r
+* TLV Descriptors\r
+************************************************************/\r
+#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */\r
+#define TLV_BASE __MSP430_BASEADDRESS_TLV__\r
+\r
+#define TLV_START (0x1A08u) /* Start Address of the TLV structure */\r
+#define TLV_END (0x1AFFu) /* End Address of the TLV structure */\r
+\r
+#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */\r
+#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */\r
+#define TLV_Reserved3 (0x03) /* Future usage */\r
+#define TLV_Reserved4 (0x04) /* Future usage */\r
+#define TLV_BLANK (0x05) /* Blank descriptor */\r
+#define TLV_Reserved6 (0x06) /* Future usage */\r
+#define TLV_Reserved7 (0x07) /* Serial Number */\r
+#define TLV_DIERECORD (0x08) /* Die Record */\r
+#define TLV_ADCCAL (0x11) /* ADC12 calibration */\r
+#define TLV_ADC12CAL (0x11) /* ADC12 calibration */\r
+#define TLV_REFCAL (0x12) /* REF calibration */\r
+#define TLV_ADC10CAL (0x13) /* ADC10 calibration */\r
+#define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */\r
+#define TLV_TAGEXT (0xFE) /* Tag extender */\r
+#define TLV_TAGEND (0xFF) /* Tag End of Table */\r
+\r
+/************************************************************\r
+* Interrupt Vectors (offset from 0xFF80)\r
+************************************************************/\r
+\r
+\r
+/************************************************************\r
+* End of Modules\r
+************************************************************/\r
+#pragma language=default\r
+\r
+#endif /* #ifndef __msp430FR5XX_FR6XXGENERIC */\r
+\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// dma.c - Driver for the dma Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup dma_api dma\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__)\r
+#include "dma.h"\r
+\r
+#include <assert.h>\r
+\r
+void DMA_init(DMA_initParam *param){\r
+ uint8_t triggerOffset = (param->channelSelect >> 4);\r
+\r
+ //Reset and Set DMA Control 0 Register\r
+ HWREG16(DMA_BASE + param->channelSelect + OFS_DMA0CTL) =\r
+ param->transferModeSelect //Set Transfer Mode\r
+ + param->transferUnitSelect //Set Transfer Unit Size\r
+ + param->triggerTypeSelect; //Set Trigger Type\r
+\r
+ //Set Transfer Size Amount\r
+ HWREG16(DMA_BASE + param->channelSelect + OFS_DMA0SZ) = param->transferSize;\r
+\r
+ if(triggerOffset & 0x01) //Odd Channel\r
+ {\r
+ HWREG16(DMA_BASE + (triggerOffset & 0x0E)) &= 0x00FF; //Reset Trigger Select\r
+ HWREG16(DMA_BASE +\r
+ (triggerOffset & 0x0E)) |= (param->triggerSourceSelect << 8);\r
+ }\r
+ else //Even Channel\r
+ {\r
+ HWREG16(DMA_BASE + (triggerOffset & 0x0E)) &= 0xFF00; //Reset Trigger Select\r
+ HWREG16(DMA_BASE +\r
+ (triggerOffset & 0x0E)) |= param->triggerSourceSelect;\r
+ }\r
+}\r
+\r
+void DMA_setTransferSize(uint8_t channelSelect,\r
+ uint16_t transferSize)\r
+{\r
+ //Set Transfer Size Amount\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0SZ) = transferSize;\r
+}\r
+\r
+uint16_t DMA_getTransferSize(uint8_t channelSelect)\r
+{\r
+ //Get Transfer Size Amount\r
+ return(HWREG16(DMA_BASE + channelSelect + OFS_DMA0SZ));\r
+}\r
+\r
+void DMA_setSrcAddress(uint8_t channelSelect,\r
+ uint32_t srcAddress,\r
+ uint16_t directionSelect)\r
+{\r
+ //Set the Source Address\r
+ __data16_write_addr((unsigned short)(DMA_BASE + channelSelect + OFS_DMA0SA),\r
+ srcAddress);\r
+\r
+ //Reset bits before setting them\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMASRCINCR_3);\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= directionSelect;\r
+}\r
+\r
+void DMA_setDstAddress(uint8_t channelSelect,\r
+ uint32_t dstAddress,\r
+ uint16_t directionSelect)\r
+{\r
+ //Set the Destination Address\r
+ __data16_write_addr((unsigned short)(DMA_BASE + channelSelect + OFS_DMA0DA),\r
+ dstAddress);\r
+\r
+ //Reset bits before setting them\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMADSTINCR_3);\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= (directionSelect << 2);\r
+}\r
+\r
+void DMA_enableTransfers(uint8_t channelSelect)\r
+{\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= DMAEN;\r
+}\r
+\r
+void DMA_disableTransfers(uint8_t channelSelect)\r
+{\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAEN);\r
+}\r
+\r
+void DMA_startTransfer(uint8_t channelSelect)\r
+{\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= DMAREQ;\r
+}\r
+\r
+void DMA_enableInterrupt(uint8_t channelSelect)\r
+{\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= DMAIE;\r
+}\r
+\r
+void DMA_disableInterrupt(uint8_t channelSelect)\r
+{\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAIE);\r
+}\r
+\r
+uint16_t DMA_getInterruptStatus(uint8_t channelSelect)\r
+{\r
+ return (HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) & DMAIFG);\r
+}\r
+\r
+void DMA_clearInterrupt(uint8_t channelSelect)\r
+{\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAIFG);\r
+}\r
+\r
+uint16_t DMA_getNMIAbortStatus(uint8_t channelSelect)\r
+{\r
+ return (HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) & DMAABORT);\r
+}\r
+\r
+void DMA_clearNMIAbort(uint8_t channelSelect)\r
+{\r
+ HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAABORT);\r
+}\r
+\r
+void DMA_disableTransferDuringReadModifyWrite(void)\r
+{\r
+ HWREG16(DMA_BASE + OFS_DMACTL4) |= DMARMWDIS;\r
+}\r
+\r
+void DMA_enableTransferDuringReadModifyWrite(void)\r
+{\r
+ HWREG16(DMA_BASE + OFS_DMACTL4) &= ~(DMARMWDIS);\r
+}\r
+\r
+void DMA_enableRoundRobinPriority(void)\r
+{\r
+ HWREG16(DMA_BASE + OFS_DMACTL4) |= ROUNDROBIN;\r
+}\r
+\r
+void DMA_disableRoundRobinPriority(void)\r
+{\r
+ HWREG16(DMA_BASE + OFS_DMACTL4) &= ~(ROUNDROBIN);\r
+}\r
+\r
+void DMA_enableNMIAbort(void)\r
+{\r
+ HWREG16(DMA_BASE + OFS_DMACTL4) |= ENNMI;\r
+}\r
+\r
+void DMA_disableNMIAbort(void)\r
+{\r
+ HWREG16(DMA_BASE + OFS_DMACTL4) &= ~(ENNMI);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for dma_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// dma.h - Driver for the DMA Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_DMA_H__\r
+#define __MSP430WARE_DMA_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__)\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the DMA_init() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct DMA_initParam\r
+{\r
+ //! Is the specified channel to initialize.\r
+ //! \n Valid values are:\r
+ //! - \b DMA_CHANNEL_0\r
+ //! - \b DMA_CHANNEL_1\r
+ //! - \b DMA_CHANNEL_2\r
+ //! - \b DMA_CHANNEL_3\r
+ //! - \b DMA_CHANNEL_4\r
+ //! - \b DMA_CHANNEL_5\r
+ //! - \b DMA_CHANNEL_6\r
+ //! - \b DMA_CHANNEL_7\r
+ uint8_t channelSelect;\r
+ //! Is the transfer mode of the selected channel.\r
+ //! \n Valid values are:\r
+ //! - \b DMA_TRANSFER_SINGLE [Default]\r
+ //! - \b DMA_TRANSFER_BLOCK\r
+ //! - \b DMA_TRANSFER_BURSTBLOCK\r
+ //! - \b DMA_TRANSFER_REPEATED_SINGLE\r
+ //! - \b DMA_TRANSFER_REPEATED_BLOCK\r
+ //! - \b DMA_TRANSFER_REPEATED_BURSTBLOCK\r
+ uint16_t transferModeSelect;\r
+ //! Is the amount of transfers to complete in a block transfer mode, as\r
+ //! well as how many transfers to complete before the interrupt flag is\r
+ //! set. Valid value is between 1-65535, if 0, no transfers will occur.\r
+ uint16_t transferSize;\r
+ //! Is the source that will trigger the start of each transfer, note that\r
+ //! the sources are device specific.\r
+ //! \n Valid values are:\r
+ //! - \b DMA_TRIGGERSOURCE_0 [Default]\r
+ //! - \b DMA_TRIGGERSOURCE_1\r
+ //! - \b DMA_TRIGGERSOURCE_2\r
+ //! - \b DMA_TRIGGERSOURCE_3\r
+ //! - \b DMA_TRIGGERSOURCE_4\r
+ //! - \b DMA_TRIGGERSOURCE_5\r
+ //! - \b DMA_TRIGGERSOURCE_6\r
+ //! - \b DMA_TRIGGERSOURCE_7\r
+ //! - \b DMA_TRIGGERSOURCE_8\r
+ //! - \b DMA_TRIGGERSOURCE_9\r
+ //! - \b DMA_TRIGGERSOURCE_10\r
+ //! - \b DMA_TRIGGERSOURCE_11\r
+ //! - \b DMA_TRIGGERSOURCE_12\r
+ //! - \b DMA_TRIGGERSOURCE_13\r
+ //! - \b DMA_TRIGGERSOURCE_14\r
+ //! - \b DMA_TRIGGERSOURCE_15\r
+ //! - \b DMA_TRIGGERSOURCE_16\r
+ //! - \b DMA_TRIGGERSOURCE_17\r
+ //! - \b DMA_TRIGGERSOURCE_18\r
+ //! - \b DMA_TRIGGERSOURCE_19\r
+ //! - \b DMA_TRIGGERSOURCE_20\r
+ //! - \b DMA_TRIGGERSOURCE_21\r
+ //! - \b DMA_TRIGGERSOURCE_22\r
+ //! - \b DMA_TRIGGERSOURCE_23\r
+ //! - \b DMA_TRIGGERSOURCE_24\r
+ //! - \b DMA_TRIGGERSOURCE_25\r
+ //! - \b DMA_TRIGGERSOURCE_26\r
+ //! - \b DMA_TRIGGERSOURCE_27\r
+ //! - \b DMA_TRIGGERSOURCE_28\r
+ //! - \b DMA_TRIGGERSOURCE_29\r
+ //! - \b DMA_TRIGGERSOURCE_30\r
+ //! - \b DMA_TRIGGERSOURCE_31\r
+ uint8_t triggerSourceSelect;\r
+ //! Is the specified size of transfers.\r
+ //! \n Valid values are:\r
+ //! - \b DMA_SIZE_SRCWORD_DSTWORD [Default]\r
+ //! - \b DMA_SIZE_SRCBYTE_DSTWORD\r
+ //! - \b DMA_SIZE_SRCWORD_DSTBYTE\r
+ //! - \b DMA_SIZE_SRCBYTE_DSTBYTE\r
+ uint8_t transferUnitSelect;\r
+ //! Is the type of trigger that the trigger signal needs to be to start a\r
+ //! transfer.\r
+ //! \n Valid values are:\r
+ //! - \b DMA_TRIGGER_RISINGEDGE [Default]\r
+ //! - \b DMA_TRIGGER_HIGH\r
+ uint8_t triggerTypeSelect;\r
+} DMA_initParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the triggerSourceSelect\r
+// parameter for functions: DMA_init(); the param parameter for functions:\r
+// DMA_init().\r
+//\r
+//*****************************************************************************\r
+#define DMA_TRIGGERSOURCE_0 (0x00)\r
+#define DMA_TRIGGERSOURCE_1 (0x01)\r
+#define DMA_TRIGGERSOURCE_2 (0x02)\r
+#define DMA_TRIGGERSOURCE_3 (0x03)\r
+#define DMA_TRIGGERSOURCE_4 (0x04)\r
+#define DMA_TRIGGERSOURCE_5 (0x05)\r
+#define DMA_TRIGGERSOURCE_6 (0x06)\r
+#define DMA_TRIGGERSOURCE_7 (0x07)\r
+#define DMA_TRIGGERSOURCE_8 (0x08)\r
+#define DMA_TRIGGERSOURCE_9 (0x09)\r
+#define DMA_TRIGGERSOURCE_10 (0x0A)\r
+#define DMA_TRIGGERSOURCE_11 (0x0B)\r
+#define DMA_TRIGGERSOURCE_12 (0x0C)\r
+#define DMA_TRIGGERSOURCE_13 (0x0D)\r
+#define DMA_TRIGGERSOURCE_14 (0x0E)\r
+#define DMA_TRIGGERSOURCE_15 (0x0F)\r
+#define DMA_TRIGGERSOURCE_16 (0x10)\r
+#define DMA_TRIGGERSOURCE_17 (0x11)\r
+#define DMA_TRIGGERSOURCE_18 (0x12)\r
+#define DMA_TRIGGERSOURCE_19 (0x13)\r
+#define DMA_TRIGGERSOURCE_20 (0x14)\r
+#define DMA_TRIGGERSOURCE_21 (0x15)\r
+#define DMA_TRIGGERSOURCE_22 (0x16)\r
+#define DMA_TRIGGERSOURCE_23 (0x17)\r
+#define DMA_TRIGGERSOURCE_24 (0x18)\r
+#define DMA_TRIGGERSOURCE_25 (0x19)\r
+#define DMA_TRIGGERSOURCE_26 (0x1A)\r
+#define DMA_TRIGGERSOURCE_27 (0x1B)\r
+#define DMA_TRIGGERSOURCE_28 (0x1C)\r
+#define DMA_TRIGGERSOURCE_29 (0x1D)\r
+#define DMA_TRIGGERSOURCE_30 (0x1E)\r
+#define DMA_TRIGGERSOURCE_31 (0x1F)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: DMA_init(); the transferModeSelect parameter for functions:\r
+// DMA_init().\r
+//\r
+//*****************************************************************************\r
+#define DMA_TRANSFER_SINGLE (DMADT_0)\r
+#define DMA_TRANSFER_BLOCK (DMADT_1)\r
+#define DMA_TRANSFER_BURSTBLOCK (DMADT_2)\r
+#define DMA_TRANSFER_REPEATED_SINGLE (DMADT_4)\r
+#define DMA_TRANSFER_REPEATED_BLOCK (DMADT_5)\r
+#define DMA_TRANSFER_REPEATED_BURSTBLOCK (DMADT_6)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the channelSelect parameter\r
+// for functions: DMA_init(), DMA_setTransferSize(), DMA_getTransferSize(),\r
+// DMA_setSrcAddress(), DMA_setDstAddress(), DMA_enableTransfers(),\r
+// DMA_disableTransfers(), DMA_startTransfer(), DMA_enableInterrupt(),\r
+// DMA_disableInterrupt(), DMA_getInterruptStatus(), DMA_clearInterrupt(),\r
+// DMA_getNMIAbortStatus(), and DMA_clearNMIAbort(); the param parameter for\r
+// functions: DMA_init().\r
+//\r
+//*****************************************************************************\r
+#define DMA_CHANNEL_0 (0x00)\r
+#define DMA_CHANNEL_1 (0x10)\r
+#define DMA_CHANNEL_2 (0x20)\r
+#define DMA_CHANNEL_3 (0x30)\r
+#define DMA_CHANNEL_4 (0x40)\r
+#define DMA_CHANNEL_5 (0x50)\r
+#define DMA_CHANNEL_6 (0x60)\r
+#define DMA_CHANNEL_7 (0x70)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the triggerTypeSelect\r
+// parameter for functions: DMA_init(); the param parameter for functions:\r
+// DMA_init().\r
+//\r
+//*****************************************************************************\r
+#define DMA_TRIGGER_RISINGEDGE (!(DMALEVEL))\r
+#define DMA_TRIGGER_HIGH (DMALEVEL)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the transferUnitSelect\r
+// parameter for functions: DMA_init(); the param parameter for functions:\r
+// DMA_init().\r
+//\r
+//*****************************************************************************\r
+#define DMA_SIZE_SRCWORD_DSTWORD (!(DMASRCBYTE + DMADSTBYTE))\r
+#define DMA_SIZE_SRCBYTE_DSTWORD (DMASRCBYTE)\r
+#define DMA_SIZE_SRCWORD_DSTBYTE (DMADSTBYTE)\r
+#define DMA_SIZE_SRCBYTE_DSTBYTE (DMASRCBYTE + DMADSTBYTE)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the directionSelect parameter\r
+// for functions: DMA_setSrcAddress(), and DMA_setDstAddress().\r
+//\r
+//*****************************************************************************\r
+#define DMA_DIRECTION_UNCHANGED (DMASRCINCR_0)\r
+#define DMA_DIRECTION_DECREMENT (DMASRCINCR_2)\r
+#define DMA_DIRECTION_INCREMENT (DMASRCINCR_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the DMA_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define DMA_INT_INACTIVE (0x0)\r
+#define DMA_INT_ACTIVE (DMAIFG)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the DMA_getNMIAbortStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define DMA_NOTABORTED (0x0)\r
+#define DMA_ABORTED (DMAABORT)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the specified DMA channel.\r
+//!\r
+//! This function initializes the specified DMA channel. Upon successful\r
+//! completion of initialization of the selected channel the control registers\r
+//! will be cleared and the given variables will be set. Please note, if\r
+//! transfers have been enabled with the enableTransfers() function, then a\r
+//! call to disableTransfers() is necessary before re-initialization. Also\r
+//! note, that the trigger sources are device dependent and can be found in the\r
+//! device family data sheet. The amount of DMA channels available are also\r
+//! device specific.\r
+//!\r
+//! \param param is the pointer to struct for initialization.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process.\r
+//\r
+//*****************************************************************************\r
+extern void DMA_init(DMA_initParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the specified amount of transfers for the selected DMA channel.\r
+//!\r
+//! This function sets the specified amount of transfers for the selected DMA\r
+//! channel without having to reinitialize the DMA channel.\r
+//!\r
+//! \param channelSelect is the specified channel to set source address\r
+//! direction for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//! \param transferSize is the amount of transfers to complete in a block\r
+//! transfer mode, as well as how many transfers to complete before the\r
+//! interrupt flag is set. Valid value is between 1-65535, if 0, no\r
+//! transfers will occur.\r
+//! \n Modified bits are \b DMAxSZ of \b DMAxSZ register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_setTransferSize(uint8_t channelSelect,\r
+ uint16_t transferSize);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the amount of transfers for the selected DMA channel.\r
+//!\r
+//! This function gets the amount of transfers for the selected DMA channel\r
+//! without having to reinitialize the DMA channel.\r
+//!\r
+//! \param channelSelect is the specified channel to set source address\r
+//! direction for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return the amount of transfers\r
+//\r
+//*****************************************************************************\r
+extern uint16_t DMA_getTransferSize(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets source address and the direction that the source address will\r
+//! move after a transfer.\r
+//!\r
+//! This function sets the source address and the direction that the source\r
+//! address will move after a transfer is complete. It may be incremented,\r
+//! decremented or unchanged.\r
+//!\r
+//! \param channelSelect is the specified channel to set source address\r
+//! direction for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//! \param srcAddress is the address of where the data will be transferred\r
+//! from.\r
+//! \n Modified bits are \b DMAxSA of \b DMAxSA register.\r
+//! \param directionSelect is the specified direction of the source address\r
+//! after a transfer.\r
+//! Valid values are:\r
+//! - \b DMA_DIRECTION_UNCHANGED\r
+//! - \b DMA_DIRECTION_DECREMENT\r
+//! - \b DMA_DIRECTION_INCREMENT\r
+//! \n Modified bits are \b DMASRCINCR of \b DMAxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_setSrcAddress(uint8_t channelSelect,\r
+ uint32_t srcAddress,\r
+ uint16_t directionSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the destination address and the direction that the destination\r
+//! address will move after a transfer.\r
+//!\r
+//! This function sets the destination address and the direction that the\r
+//! destination address will move after a transfer is complete. It may be\r
+//! incremented, decremented, or unchanged.\r
+//!\r
+//! \param channelSelect is the specified channel to set the destination\r
+//! address direction for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//! \param dstAddress is the address of where the data will be transferred to.\r
+//! \n Modified bits are \b DMAxDA of \b DMAxDA register.\r
+//! \param directionSelect is the specified direction of the destination\r
+//! address after a transfer.\r
+//! Valid values are:\r
+//! - \b DMA_DIRECTION_UNCHANGED\r
+//! - \b DMA_DIRECTION_DECREMENT\r
+//! - \b DMA_DIRECTION_INCREMENT\r
+//! \n Modified bits are \b DMADSTINCR of \b DMAxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_setDstAddress(uint8_t channelSelect,\r
+ uint32_t dstAddress,\r
+ uint16_t directionSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables transfers to be triggered.\r
+//!\r
+//! This function enables transfers upon appropriate trigger of the selected\r
+//! trigger source for the selected channel.\r
+//!\r
+//! \param channelSelect is the specified channel to enable transfer for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_enableTransfers(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables transfers from being triggered.\r
+//!\r
+//! This function disables transfer from being triggered for the selected\r
+//! channel. This function should be called before any re-initialization of the\r
+//! selected DMA channel.\r
+//!\r
+//! \param channelSelect is the specified channel to disable transfers for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_disableTransfers(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts a transfer if using the default trigger source selected in\r
+//! initialization.\r
+//!\r
+//! This functions triggers a transfer of data from source to destination if\r
+//! the trigger source chosen from initialization is the DMA_TRIGGERSOURCE_0.\r
+//! Please note, this function needs to be called for each (repeated-)single\r
+//! transfer, and when transferAmount of transfers have been complete in\r
+//! (repeated-)block transfers.\r
+//!\r
+//! \param channelSelect is the specified channel to start transfers for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_startTransfer(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the DMA interrupt for the selected channel.\r
+//!\r
+//! Enables the DMA interrupt source. Only the sources that are enabled can be\r
+//! reflected to the processor interrupt; disabled sources have no effect on\r
+//! the processor. Does not clear interrupt flags.\r
+//!\r
+//! \param channelSelect is the specified channel to enable the interrupt for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_enableInterrupt(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the DMA interrupt for the selected channel.\r
+//!\r
+//! Disables the DMA interrupt source. Only the sources that are enabled can be\r
+//! reflected to the processor interrupt; disabled sources have no effect on\r
+//! the processor.\r
+//!\r
+//! \param channelSelect is the specified channel to disable the interrupt for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_disableInterrupt(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the status of the interrupt flag for the selected channel.\r
+//!\r
+//! Returns the status of the interrupt flag for the selected channel.\r
+//!\r
+//! \param channelSelect is the specified channel to return the interrupt flag\r
+//! status from.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return One of the following:\r
+//! - \b DMA_INT_INACTIVE\r
+//! - \b DMA_INT_ACTIVE\r
+//! \n indicating the status of the current interrupt flag\r
+//\r
+//*****************************************************************************\r
+extern uint16_t DMA_getInterruptStatus(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the interrupt flag for the selected channel.\r
+//!\r
+//! This function clears the DMA interrupt flag is cleared, so that it no\r
+//! longer asserts.\r
+//!\r
+//! \param channelSelect is the specified channel to clear the interrupt flag\r
+//! for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_clearInterrupt(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the status of the NMIAbort for the selected channel.\r
+//!\r
+//! This function returns the status of the NMI Abort flag for the selected\r
+//! channel. If this flag has been set, it is because a transfer on this\r
+//! channel was aborted due to a interrupt from an NMI.\r
+//!\r
+//! \param channelSelect is the specified channel to return the status of the\r
+//! NMI Abort flag for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return One of the following:\r
+//! - \b DMA_NOTABORTED\r
+//! - \b DMA_ABORTED\r
+//! \n indicating the status of the NMIAbort for the selected channel\r
+//\r
+//*****************************************************************************\r
+extern uint16_t DMA_getNMIAbortStatus(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the status of the NMIAbort to proceed with transfers for the\r
+//! selected channel.\r
+//!\r
+//! This function clears the status of the NMI Abort flag for the selected\r
+//! channel to allow for transfers on the channel to continue.\r
+//!\r
+//! \param channelSelect is the specified channel to clear the NMI Abort flag\r
+//! for.\r
+//! Valid values are:\r
+//! - \b DMA_CHANNEL_0\r
+//! - \b DMA_CHANNEL_1\r
+//! - \b DMA_CHANNEL_2\r
+//! - \b DMA_CHANNEL_3\r
+//! - \b DMA_CHANNEL_4\r
+//! - \b DMA_CHANNEL_5\r
+//! - \b DMA_CHANNEL_6\r
+//! - \b DMA_CHANNEL_7\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_clearNMIAbort(uint8_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the DMA from stopping the CPU during a Read-Modify-Write\r
+//! Operation to start a transfer.\r
+//!\r
+//! This function allows the CPU to finish any read-modify-write operations it\r
+//! may be in the middle of before transfers of and DMA channel stop the CPU.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_disableTransferDuringReadModifyWrite(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the DMA to stop the CPU during a Read-Modify-Write Operation\r
+//! to start a transfer.\r
+//!\r
+//! This function allows the DMA to stop the CPU in the middle of a read-\r
+//! modify-write operation to transfer data.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_enableTransferDuringReadModifyWrite(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables Round Robin prioritization.\r
+//!\r
+//! This function enables Round Robin Prioritization of DMA channels. In the\r
+//! case of Round Robin Prioritization, the last DMA channel to have\r
+//! transferred data then has the last priority, which comes into play when\r
+//! multiple DMA channels are ready to transfer at the same time.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_enableRoundRobinPriority(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables Round Robin prioritization.\r
+//!\r
+//! This function disables Round Robin Prioritization, enabling static\r
+//! prioritization of the DMA channels. In static prioritization, the DMA\r
+//! channels are prioritized with the lowest DMA channel index having the\r
+//! highest priority (i.e. DMA Channel 0 has the highest priority).\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_disableRoundRobinPriority(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables a NMI to interrupt a DMA transfer.\r
+//!\r
+//! This function allow NMI's to interrupting any DMA transfer currently in\r
+//! progress and stops any future transfers to begin before the NMI is done\r
+//! processing.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_enableNMIAbort(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables any NMI from interrupting a DMA transfer.\r
+//!\r
+//! This function disables NMI's from interrupting any DMA transfer currently\r
+//! in progress.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void DMA_disableNMIAbort(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_DMA_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+#include "inc/hw_memmap.h"\r
+\r
+#include "adc12_b.h"\r
+#include "aes256.h"\r
+#include "comp_e.h"\r
+#include "crc.h"\r
+#include "crc32.h"\r
+#include "cs.h"\r
+#include "dma.h"\r
+#include "esi.h"\r
+#include "eusci_a_spi.h"\r
+#include "eusci_a_uart.h"\r
+#include "eusci_b_i2c.h"\r
+#include "eusci_b_spi.h"\r
+#include "framctl.h"\r
+#include "gpio.h"\r
+#include "lcd_c.h"\r
+#include "mpu.h"\r
+#include "mpy32.h"\r
+#include "pmm.h"\r
+#include "ram.h"\r
+#include "ref_a.h"\r
+#include "rtc_b.h"\r
+#include "rtc_c.h"\r
+#include "sfr.h"\r
+#include "sysctl.h"\r
+#include "timer_a.h"\r
+#include "timer_b.h"\r
+#include "tlv.h"\r
+#include "wdt_a.h"\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// esi.h - Driver for the ESI Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup esi_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_ESI__\r
+#include "esi.h"\r
+\r
+#include <assert.h>\r
+\r
+// Uncomment for finding lower peak of the lower half cycle.\r
+// This required to set ESI comparator output as inverted\r
+#define INVERTED\r
+\r
+static uint16_t measureESIOSC(void);\r
+static void FindDAC(uint8_t selected_channel,\r
+ uint8_t software_trigger);\r
+\r
+const ESI_AFE1_InitParams ESI_AFE1_INITPARAMS_DEFAULT =\r
+{ESI_EXCITATION_CIRCUIT_DISABLED,\r
+ ESI_SAMPLE_HOLD_DISABLED,\r
+ ESI_MID_VOLTAGE_GENERATOR_DISABLED,\r
+ ESI_SAMPLE_HOLD_VSS_TO_ESIVSS,\r
+ ESI_INVERTER_FOR_AFE1_DISABLE};\r
+\r
+const ESI_AFE2_InitParams ESI_AFE2_INITPARAMS_DEFAULT = {\r
+ ESI_AFE2_INPUT_SELECT_CHx,\r
+ ESI_INVERTER_FOR_AFE2_DISABLE,\r
+ ESI_TSM_COMPARATOR_CONTROL_AFE2_DISABLE,\r
+ ESI_TSM_DAC_CONTROL_AFE2_DISABLE\r
+};\r
+\r
+const ESI_TSM_InitParams ESI_TSM_INITPARAMS_DEFAULT = { ESI_TSM_SMCLK_DIV_1,\r
+ ESI_TSM_ACLK_DIV_1,\r
+ ESI_TSM_START_TRIGGER_DIV_2,\r
+ ESI_TSM_REPEAT_NEW_TRIGGER,\r
+ ESI_TSM_STOP_SEQUENCE,\r
+ ESI_TSM_HIGH_FREQ_CLK_FUNCTION_ON};\r
+\r
+const ESI_PSM_InitParams ESI_PSM_INITPARAMS_DEFAULT = { ESI_PSM_Q6_DISABLE,\r
+ ESI_PSM_Q7_TRIGGER_DISABLE,\r
+ ESI_PSM_CNT0_DISABLE,\r
+ ESI_PSM_CNT0_RESET,\r
+ ESI_PSM_CNT1_DISABLE,\r
+ ESI_PSM_CNT1_RESET,\r
+ ESI_PSM_CNT2_DISABLE,\r
+ ESI_PSM_CNT2_RESET,\r
+ ESI_PSM_S3_SELECT,\r
+ ESI_PSM_TEST4_IS_Q2,};\r
+\r
+//*****************************************************************************\r
+//\r
+//! Get ESI PSM Counter 0 Value\r
+//!\r
+//! This function reads the ESI Counter 0 register\r
+//!\r
+//! \return Counter value\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_getCounter0(void)\r
+{\r
+ return (ESICNT0);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Get ESI PSM Counter 1 Value\r
+//!\r
+//! This function reads the ESI Counter1 register\r
+//!\r
+//! \return Counter value\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_getCounter1(void)\r
+{\r
+ return (ESICNT1);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Get ESI PSM Counter 2 Value\r
+//!\r
+//! This function reads the ESI Counter2 register\r
+//!\r
+//! \return Counter value\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_getCounter2(void)\r
+{\r
+ return (ESICNT2);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Get ESI PSM Oscillator Counter Value\r
+//!\r
+//! This function reads the ESI Oscillator Counter register\r
+//!\r
+//! \return Counter value\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_getOscCounter(void)\r
+{\r
+ return (ESICNT3);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the ESI analog front end AFE1\r
+//!\r
+//! \param params is ESI_AFE1_InitParams struct\r
+//!\r
+//! This functions initializes the ESI analog front end AFE1.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void ESI_AFE1_init(ESI_AFE1_InitParams *params)\r
+{\r
+ // Unset the AFE1 bits\r
+ ESIAFE &= ~(ESITEN + ESISH + ESIVCC2 + ESIVSS + ESICACI3 + ESICISEL +\r
+ ESICA1X + ESICA1INV);\r
+ ESIAFE |=\r
+ params->excitationCircuitSelect +\r
+ params->sampleAndHoldSelect +\r
+ params->midVoltageGeneratorSelect +\r
+ params->sampleAndHoldVSSConnect +\r
+ params->inverterSelectOutputAFE1\r
+ ;\r
+\r
+ switch(params->inputSelectAFE1)\r
+ {\r
+ case ESI_AFE1_INPUT_SELECT_CHx:\r
+ break;\r
+ case ESI_AFE1_INPUT_SELECT_CIx:\r
+ ESIAFE |= ESICA1X;\r
+ break;\r
+ case ESI_AFE1_INPUT_SELECT_CI3:\r
+ ESIAFE |= ESICA1X;\r
+ ESIAFE &= ~ESICISEL;\r
+ ESIAFE |= ESICACI3;\r
+ break;\r
+ case ESI_AFE1_INPUT_SELECT_CI:\r
+ ESIAFE |= ESICA1X;\r
+ ESIAFE |= ESICISEL;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the ESI analog front end - AFE2\r
+//!\r
+//! \param params is ESI_AFE2_InitParams struct\r
+//!\r
+//! This functions initializes the ESI analog front end AFE2\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void ESI_AFE2_init(ESI_AFE2_InitParams *params)\r
+{\r
+ // Unset the AFE2 bits\r
+ ESIAFE &= ~(ESICA2X + ESICA2INV + ESICA2EN + ESIDAC2EN);\r
+\r
+ ESIAFE |=\r
+ params->inputSelectAFE2 +\r
+ params->inverterSelectOutputAFE2 +\r
+ params->tsmControlComparatorAFE2 +\r
+ params->tsmControlDacAFE2\r
+ ;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Reads the latched comparator outputs form the AFEs\r
+//!\r
+//! \param channelSelect. Valid values are\r
+//! ESI_AFE1_CHANNEL0_SELECT\r
+//! ESI_AFE1_CHANNEL1_SELECT\r
+//! ESI_AFE1_CHANNEL2_SELECT\r
+//! ESI_AFE1_CHANNEL3_SELECT\r
+//! ESI_AFE2_CHANNEL0_SELECT\r
+//! ESI_AFE2_CHANNEL1_SELECT\r
+//! ESI_AFE2_CHANNEL2_SELECT\r
+//! ESI_AFE2_CHANNEL3_SELECT\r
+//! ESI_AFE1_TEST_CHANNEL0_SELECT\r
+//! ESI_AFE1_TEST_CHANNEL1_SELECT\r
+//!\r
+//! This function gets the ESIPPU register to get latched output values of the\r
+//! comparator outputs for AFE1 and AFE2\r
+//!\r
+//! \return Valid values are\r
+//! ESI_AFE_OUTPUT_LOW\r
+//! ESI_AFE_OUTPUT_HIGH\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_getLatchedComparatorOutput(uint16_t channelSelect)\r
+{\r
+ uint16_t result;\r
+\r
+ result = ESIPPU;\r
+\r
+ return (result &= channelSelect);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the TSM\r
+//!\r
+//! \param params is ESI_TSM_InitParams struct\r
+//!\r
+//! This function initializes the TSM.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void ESI_TSM_init(ESI_TSM_InitParams *params)\r
+{\r
+ ESITSM =\r
+ params->smclkDivider +\r
+ params->aclkDivider +\r
+ params->startTriggerAclkDivider +\r
+ params->repeatMode +\r
+ params->startTriggerSelection +\r
+ params->tsmFunctionSelection\r
+ ;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clear TSM entries\r
+//!\r
+//! This function clears all TSM entries\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_TSM_clearTable(void)\r
+{\r
+ uint16_t *pTsm, i;\r
+\r
+ // Clear TSM Table (for testing only. not neccessary in real application)\r
+ pTsm = (uint16_t *)&ESITSM0;\r
+ for(i = 0; i < 32; i++)\r
+ {\r
+ *pTsm++ = 0x0200;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Copy TSM entries\r
+//!\r
+//! This function copies all TSM entries\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_TSM_copyTable(uint16_t* tsmTable,\r
+ uint16_t size)\r
+{\r
+ uint16_t *pt_tsmTable;\r
+ uint16_t i;\r
+\r
+ // Copy the TSM_Table into ESI TSM registers\r
+ // Destination pointer\r
+ pt_tsmTable = (uint16_t *)&ESITSM0;\r
+ // Divided by 2 because of unsigned integer (2bytes)\r
+ i = size / 2;\r
+\r
+ do\r
+ {\r
+ *pt_tsmTable++ = *tsmTable++;\r
+ }\r
+ while(--i);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! TSM trigger using software\r
+//!\r
+//! This function starts a software initiated TSM sequence\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_TSM_softwareTrigger(void)\r
+{\r
+ ESITSM |= ESISTART;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! TSM trigger using software\r
+//!\r
+//! This function starts a software initiated TSM sequence\r
+//!\r
+//! \return ESIREATx bits from selected stateRegNum\r
+//\r
+//*****************************************************************************\r
+uint8_t ESI_TSM_getTSMStateDuration(uint8_t stateRegNum)\r
+{\r
+ volatile uint16_t* stateRegBase = (volatile uint16_t*)&ESITSM0;\r
+\r
+ return((*(stateRegBase + stateRegNum) & 0xf800) >> 11);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! TSM trigger using software\r
+//!\r
+//! This function starts a software initiated TSM sequence\r
+//!\r
+//! \return ESIREATx bits from selected stateRegNum\r
+//\r
+//*****************************************************************************\r
+void ESI_TSM_setTSMStateDuration(uint8_t stateRegNum,\r
+ uint8_t duration)\r
+{\r
+ assert(stateRegNum <= ESI_TSM_STATE_REG_31);\r
+ assert(duration <= ESI_TSM_STATE_DURATION_MAX);\r
+\r
+ volatile uint16_t* stateRegBase = (volatile uint16_t*)&ESITSM0;\r
+\r
+ *(stateRegBase + stateRegNum) &= ~0xF800;\r
+\r
+ *(stateRegBase + stateRegNum) |= (duration << 11);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initialize Processing State Machine\r
+//\r
+//! \param params is ESI_PSM_InitParams struct\r
+//!\r
+//! This function initializes the PSM registers.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_PSM_init(ESI_PSM_InitParams *params)\r
+{\r
+ ESIPSM =\r
+ params->Q6Select +\r
+ params->Q7TriggerSelect +\r
+ params->count0Select +\r
+ params->count0Reset +\r
+ params->count1Select +\r
+ params->count1Reset +\r
+ params->count2Select +\r
+ params->count2Reset +\r
+ params->V2Select +\r
+ params->TEST4Select\r
+ ;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clear PSM entries\r
+//!\r
+//! This function clears all PSM entries\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_PSM_clearTable(void)\r
+{\r
+ uint8_t *pPsm, i;\r
+\r
+ // Clear TSM Table (for testing only. not neccessary in real application)\r
+ pPsm = (uint8_t *)&ESIRAM0;\r
+ for(i = 0; i < 128; i++)\r
+ {\r
+ *pPsm++ = 0x0;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Copy PSM entries\r
+//!\r
+//! This function copies all PSM entries\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_PSM_copyTable(uint8_t* psmTable,\r
+ uint8_t size)\r
+{\r
+ uint8_t *pt_psmTable;\r
+ uint8_t i;\r
+\r
+ assert(size <= 128);\r
+\r
+ // Copy the TSM_Table into ESI TSM registers\r
+ pt_psmTable = (uint8_t *)&ESIRAM0; // Destination pointer\r
+ i = size;\r
+\r
+ do\r
+ {\r
+ *pt_psmTable++ = *psmTable++;\r
+ }\r
+ while(--i);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Reset PSM counters\r
+//!\r
+//! \param counterToReset is the counter that needs t be reset\r
+//!\r
+//! This function resets the PSM counters\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_PSM_resetCounter(uint16_t counterToReset)\r
+{\r
+ ESIPSM |= counterToReset;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the internal Oscillator\r
+//!\r
+//!\r
+//! This function enables the high frequency internal oscillator\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_enableInternalOscillator(void)\r
+{\r
+ ESIOSC |= ESIHFSEL;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the internal Oscillator\r
+//!\r
+//!\r
+//! This function disables the high frequency internal oscillator\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_disableInternalOscillator(void)\r
+{\r
+ ESIOSC &= ~ESIHFSEL;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Connects comparator output to timerA input\r
+//!\r
+//! \param counterToReset ESI_TIMERA_INPUT_TSM_COMPOUT or\r
+//! ESI_TIMERA_INPUT_TSM_PPUSRC\r
+//!\r
+//! This function connects the chosen comparator output to TimerA\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_timerAInputSelect(uint16_t select)\r
+{\r
+ ESICTL |= select;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Connects psm source to comparator output\r
+//!\r
+//! \param sourceNum PSM_S1_SOURCE, PSM_S2_SOURCE or PSM_S3_SOURCE\r
+//! \param sourceSelect can have the following values\r
+//! ESI_PSM_SOURCE_IS_ESIOUT0\r
+//! ESI_PSM_SOURCE_IS_ESIOUT1\r
+//! ESI_PSM_SOURCE_IS_ESIOUT2\r
+//! ESI_PSM_SOURCE_IS_ESIOUT3\r
+//! ESI_PSM_SOURCE_IS_ESIOUT4\r
+//! ESI_PSM_SOURCE_IS_ESIOUT5\r
+//! ESI_PSM_SOURCE_IS_ESIOUT6\r
+//! ESI_PSM_SOURCE_IS_ESIOUT7\r
+//!\r
+//! This function connects the chosen comparator output to TimerA\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_psmSourceSelect(uint16_t sourceNum,\r
+ uint16_t sourceSelect)\r
+{\r
+ switch(sourceNum)\r
+ {\r
+ case PSM_S1_SOURCE:\r
+ ESICTL &= ~(ESIS1SEL0 | ESIS1SEL1 | ESIS1SEL2);\r
+ ESICTL |= (sourceSelect << 7);\r
+ break;\r
+ case PSM_S2_SOURCE:\r
+ ESICTL &= ~(ESIS2SEL0 | ESIS2SEL1 | ESIS2SEL2);\r
+ ESICTL |= (sourceSelect << 10);\r
+ break;\r
+ case PSM_S3_SOURCE:\r
+ ESICTL &= ~(ESIS3SEL0 | ESIS3SEL1 | ESIS3SEL2);\r
+ ESICTL |= (sourceSelect << 13);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Connects testChannel0 to comparator input\r
+//!\r
+//! \param sourceSelect can have the following values\r
+//! ESI_TEST_CHANNEL0_SOURCE_IS_CH0_CI0\r
+//! ESI_TEST_CHANNEL0_SOURCE_IS_CH1_CI1\r
+//! ESI_TEST_CHANNEL0_SOURCE_IS_CH2_CI2\r
+//! ESI_TEST_CHANNEL0_SOURCE_IS_CH3_CI3\r
+//!\r
+//! This function connects the chosen comparator input to the test channel0\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_testChannel0SourceSelect(uint16_t sourceSelect)\r
+{\r
+ ESICTL &= ~(ESI_TEST_CHANNEL0_SOURCE_IS_CH3_CI3);\r
+ ESICTL |= sourceSelect;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Connects testChannel1to comparator input\r
+//!\r
+//! \param sourceSelect can have the following values\r
+//! ESI_TEST_CHANNEL1_SOURCE_IS_CH0_CI0\r
+//! ESI_TEST_CHANNEL1_SOURCE_IS_CH1_CI1\r
+//! ESI_TEST_CHANNEL1_SOURCE_IS_CH2_CI2\r
+//! ESI_TEST_CHANNEL1_SOURCE_IS_CH3_CI3\r
+//!\r
+//! This function connects the chosen comparator input to the test channel1\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_testChannel1SourceSelect(uint16_t sourceSelect)\r
+{\r
+ ESICTL &= ~(ESI_TEST_CHANNEL1_SOURCE_IS_CH3_CI3);\r
+ ESICTL |= sourceSelect;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable ESI peripheral\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_enable(void)\r
+{\r
+ ESICTL |= ESIEN;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disable ESI peripheral\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_disable(void)\r
+{\r
+ ESICTL &= ~ESIEN;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Start calibration on ESI internal Oscillator\r
+//!\r
+//! This function starts calibration of internal osciallator. After calling this\r
+//! function the user and use ESI_adjustInternalOscFreq() to adjust the freq. of\r
+//! the oscillator.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_startInternalOscCal(void)\r
+{\r
+ assert(ESIOSC | ESIHFSEL);\r
+ ESIOSC |= ESICLKGON;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Adjusts frequency ESI internal Oscillator\r
+//!\r
+//! This function adjusts frequency ESI internal Oscillator. It increases or\r
+//! decrease the freq by 3% based on incOrDec value.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_adjustInternalOscFreq(uint16_t incOrDec)\r
+{\r
+ uint16_t adjustValue;\r
+\r
+ assert(ESIOSC | ESIHFSEL);\r
+\r
+ adjustValue = ESIOSC >> 8;\r
+\r
+ if(incOrDec == ESI_INTERNAL_OSC_FREQ_INCREASE)\r
+ {\r
+ adjustValue = adjustValue + 1;\r
+ adjustValue = adjustValue << 8;\r
+ }\r
+ else\r
+ {\r
+ adjustValue = adjustValue - 1;\r
+ adjustValue = adjustValue << 8;\r
+ }\r
+\r
+ ESIOSC |= adjustValue;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets frequency of ESI internal Oscillator\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setNominalInternalOscFreq(void)\r
+{\r
+ ESIOSC = ESICLKFQ5 + ESICLKGON + ESIHFSEL;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! The following function return the number of ESIOSC cycle during an ACLK\r
+//! cycle.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+static uint16_t measureESIOSC(void){\r
+ // This and next instruction realizes a clear->set ESICLKGON bit.\r
+ ESIOSC &= ~(ESICLKGON);\r
+\r
+ // This starts measurement.\r
+ ESIOSC |= ESICLKGON + ESIHFSEL;\r
+\r
+ // Reading ESICNT3 while counting always result in reading a 0x01.\r
+ while(ESICNT3 == 1)\r
+ {\r
+ ;\r
+ }\r
+\r
+ // Stop ESIOSC oscillator\r
+ ESIOSC &= ~(ESICLKGON);\r
+\r
+ return (ESICNT3);\r
+}\r
+\r
+//******************************************************************************\r
+//! The following function returns the ESICLKFQx bits on ESIOSC register\r
+//\r
+//! \param none\r
+//\r
+//! \return ESICLKFQ bits only\r
+//******************************************************************************\r
+\r
+uint8_t ESI_getESICLKFQ(void){\r
+ uint16_t temp;\r
+\r
+ // Store ESIOSC content\r
+ temp = ESIOSC;\r
+ // Get ESICLKFQx bits\r
+ temp = (temp >> 8) & 0x3F;\r
+\r
+ return(temp);\r
+}\r
+\r
+//******************************************************************************\r
+//! The following function sets ESICLKFQx bits on ESIOSC register\r
+//\r
+//! \param setting is to the loaded to ESIOSC. Valid parameters a value between\r
+//! 0x00 and 0x3F. 0x00 corresponds to minimum frequency, 0x20\r
+//! corresponds to nominal frequency and 0x3F corresponds to maximum\r
+//! frequency.\r
+//\r
+//! \return none\r
+//******************************************************************************\r
+void ESI_setESICLKFQ(uint8_t setting)\r
+{\r
+ uint16_t temp;\r
+\r
+ assert(setting < 0x40);\r
+\r
+ temp = ESIOSC; // get actual ESIOSC register content\r
+ temp &= ~(0x3F00);\r
+ temp = ((uint16_t) setting << 8) + temp; // and update ESICLKFQ bits\r
+ ESIOSC = temp;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Calibrate ESI internal Oscillator\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_calibrateInternalOscFreq(uint16_t targetAclkCounts)\r
+{\r
+ ESI_setNominalInternalOscFreq();\r
+\r
+ ESI_measureESIOSC(ESI_ESIOSC_OVERSAMPLE_4);\r
+\r
+ if(ESICNT3 > targetAclkCounts)\r
+ {\r
+ //freq is too high\r
+ do\r
+ {\r
+ ESI_adjustInternalOscFreq(ESI_INTERNAL_OSC_FREQ_DECREASE);\r
+ }\r
+ while(ESI_measureESIOSC(ESI_ESIOSC_OVERSAMPLE_4) > targetAclkCounts);\r
+ }\r
+ else\r
+ {\r
+ //freq is too low\r
+ do\r
+ {\r
+ ESI_adjustInternalOscFreq(ESI_INTERNAL_OSC_FREQ_INCREASE);\r
+ }\r
+ while(ESI_measureESIOSC(ESI_ESIOSC_OVERSAMPLE_4) > targetAclkCounts);\r
+ ESI_adjustInternalOscFreq(ESI_INTERNAL_OSC_FREQ_DECREASE);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! The following function returns an average of ESIOSC measurement.\r
+//!\r
+//! \param\r
+//!\r
+//! \return averaged ESIOSC measurement.\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_measureESIOSC(uint8_t oversample){\r
+ uint8_t i;\r
+ uint16_t temp = 0;\r
+\r
+ assert(oversample < 9);\r
+\r
+ for(i = oversample; i > 0; i--)\r
+ {\r
+ temp += measureESIOSC();\r
+ }\r
+\r
+ temp /= oversample;\r
+ return(temp);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set upper threshold for PSM counter 1\r
+//!\r
+//! \param threshold is the upper threashold that causes ESIIFG3 to get set.\r
+//!\r
+//! This function sets the threshold value for PSM counter 1. ESIIFG3 gets set\r
+//! when counter value and this threahold are equal.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setPSMCounter1UpperThreshold(uint16_t threshold)\r
+{\r
+ ESITHR1 = threshold;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set lower threshold for PSM counter 1\r
+//!\r
+//! \param threshold is the lower threashold that causes ESIIFG3 to get set.\r
+//!\r
+//! This function set the threshold value for PSM counter 1. ESIIFG3 gets set\r
+//! when counter value and this threahold are equal.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setPSMCounter1LowerThreshold(uint16_t threshold)\r
+{\r
+ ESITHR2 = threshold;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! sets AFE1 DAC threshold Value\r
+//!\r
+//! \param dacValue is value to be written to DAC register.\r
+//! \param dacRegNum is DAC register number\r
+//!\r
+//! Write DAC threshold value into selected DAC register\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setAFE1DACValue(uint16_t dacValue,\r
+ uint8_t dacRegNum)\r
+{\r
+ volatile uint16_t* dacRegBase = (volatile uint16_t*) &ESIDAC1R0;\r
+ *(dacRegBase + dacRegNum) = dacValue;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! gets AFE1 DAC threshold Value\r
+//!\r
+//! \param dacValue is value to be written to DAC register.\r
+//! \param dacRegNum is DAC register number\r
+//!\r
+//! Read DAC threshold value into selected DAC register\r
+//!\r
+//! \return DAC value from selected DAC register.\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_getAFE1DACValue(uint8_t dacRegNum)\r
+{\r
+ volatile uint16_t* dacRegBase = (volatile uint16_t*) &ESIDAC1R0;\r
+ return(*(dacRegBase + dacRegNum));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! sets AFE2 DAC threshold Value\r
+//!\r
+//! \param dacValue is value to be written to DAC register.\r
+//! \param dacRegNum is DAC register number\r
+//!\r
+//! Write DAC threshold value into selected DAC register\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setAFE2DACValue(uint16_t dacValue,\r
+ uint8_t dacRegNum)\r
+{\r
+ volatile uint16_t* dacRegBase = (volatile uint16_t*) &ESIDAC2R0;\r
+ *(dacRegBase + dacRegNum) = dacValue;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! gets AFE2 DAC threshold Value\r
+//!\r
+//! \param dacValue is value to be written to DAC register.\r
+//! \param dacRegNum is DAC register number\r
+//!\r
+//! Read DAC threshold value into selected DAC register\r
+//!\r
+//! \return DAC value from selected DAC register.\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_getAFE2DACValue(uint8_t dacRegNum)\r
+{\r
+ volatile uint16_t* dacRegBase = (volatile uint16_t*) &ESIDAC2R0;\r
+ return(*(dacRegBase + dacRegNum));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! sets TSM state register\r
+//!\r
+//! \param params constructs the state value\r
+//! \param stateRegNum is state register offset\r
+//!\r
+//! Sets selected TSM state register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setTSMstateReg(ESI_TSM_StateParams *params,\r
+ uint8_t stateRegNum)\r
+{\r
+ volatile uint16_t* stateRegBase = (volatile uint16_t*) &ESITSM0;\r
+ *(stateRegBase + stateRegNum) =\r
+ (params->inputChannelSelect +\r
+ params->LCDampingSelect +\r
+ params->excitationSelect +\r
+ params->comparatorSelect +\r
+ params->highFreqClkOn_or_compAutoZeroCycle +\r
+ params->outputLatchSelect +\r
+ params->testCycleSelect +\r
+ params->dacSelect +\r
+ params->tsmStop +\r
+ params->tsmClkSrc) |\r
+ (params->duration << 11);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Get ESI interrupt Vector Register\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_getInterruptVectorRegister(void)\r
+{\r
+ return (ESIIV);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables ESI interrupts\r
+//!\r
+//! \param interruptMask is the bit mask of the interrupt sources to\r
+//! be enabled. Mask value is the logical OR of any of the following:\r
+//! \b ESI_INTERRUPT_AFE1_ESIOUTX\r
+//! \b ESI_INTERRUPT_ESISTOP\r
+//! \b ESI_INTERRUPT_ESISTART\r
+//! \b ESI_INTERRUPT_ESICNT1\r
+//! \b ESI_INTERRUPT_ESICNT2\r
+//! \b ESI_INTERRUPT_Q6_BIT_SET\r
+//! \b ESI_INTERRUPT_Q7_BIT_SET\r
+//! \b ESI_INTERRUPT_ESICNT0_COUNT_INTERVAL\r
+//! \b ESI_INTERRUPT_AFE2_ESIOUTX\r
+//!\r
+//! Modified bits of \b ESIINT1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_enableInterrupt(uint16_t interruptMask)\r
+{\r
+ ESIINT1 |= (interruptMask);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables ESI interrupts\r
+//!\r
+//! \param interruptMask is the bit mask of the interrupt sources to\r
+//! be disabled. Mask value is the logical OR of any of the following:\r
+//! \b ESI_INTERRUPT_AFE1_ESIOUTX\r
+//! \b ESI_INTERRUPT_ESISTOP\r
+//! \b ESI_INTERRUPT_ESISTART\r
+//! \b ESI_INTERRUPT_ESICNT1\r
+//! \b ESI_INTERRUPT_ESICNT2\r
+//! \b ESI_INTERRUPT_Q6_BIT_SET\r
+//! \b ESI_INTERRUPT_Q7_BIT_SET\r
+//! \b ESI_INTERRUPT_ESICNT0_COUNT_INTERVAL\r
+//! \b ESI_INTERRUPT_AFE2_ESIOUTX\r
+//!\r
+//! Modified bits of \b ESIINT1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_disableInterrupt(uint16_t interruptMask)\r
+{\r
+ ESIINT1 &= ~(interruptMask);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Get ESI interrupt status\r
+//!\r
+//! \param interruptMask is the masked interrupt flag status to be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b ESI_INTERRUPT_FLAG_AFE1_ESIOUTX\r
+//! - \b ESI_INTERRUPT_FLAG_ESISTOP\r
+//! - \b ESI_INTERRUPT_FLAG_ESISTART\r
+//! - \b ESI_INTERRUPT_FLAG_ESICNT1\r
+//! - \b ESI_INTERRUPT_FLAG_ESICNT2\r
+//! - \b ESI_INTERRUPT_FLAG_Q6_BIT_SET\r
+//! - \b ESI_INTERRUPT_FLAG_Q7_BIT_SET\r
+//! - \b ESI_INTERRUPT_FLAG_ESICNT0_COUNT_INTERVAL\r
+//! - \b ESI_INTERRUPT_FLAG_AFE2_ESIOUTX\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b ESI_INTERRUPT_FLAG_AFE1_ESIOUTX\r
+//! - \b ESI_INTERRUPT_FLAG_ESISTOP\r
+//! - \b ESI_INTERRUPT_FLAG_ESISTART\r
+//! - \b ESI_INTERRUPT_FLAG_ESICNT1\r
+//! - \b ESI_INTERRUPT_FLAG_ESICNT2\r
+//! - \b ESI_INTERRUPT_FLAG_Q6_BIT_SET\r
+//! - \b ESI_INTERRUPT_FLAG_Q7_BIT_SET\r
+//! - \b ESI_INTERRUPT_FLAG_ESICNT0_COUNT_INTERVAL\r
+//! - \b ESI_INTERRUPT_FLAG_AFE2_ESIOUTX\r
+//! \n indicating the status of the masked flags\r
+//\r
+//*****************************************************************************\r
+uint16_t ESI_getInterruptStatus(uint16_t interruptMask)\r
+{\r
+ return (ESIINT2 & interruptMask);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clear ESI interrupt flag\r
+//!\r
+//! \param interruptMask is the masked interrupt flag status to be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b ESI_INTERRUPT_FLAG_AFE1_ESIOUTX\r
+//! - \b ESI_INTERRUPT_FLAG_ESISTOP\r
+//! - \b ESI_INTERRUPT_FLAG_ESISTART\r
+//! - \b ESI_INTERRUPT_FLAG_ESICNT1\r
+//! - \b ESI_INTERRUPT_FLAG_ESICNT2\r
+//! - \b ESI_INTERRUPT_FLAG_Q6_BIT_SET\r
+//! - \b ESI_INTERRUPT_FLAG_Q7_BIT_SET\r
+//! - \b ESI_INTERRUPT_FLAG_ESICNT0_COUNT_INTERVAL\r
+//! - \b ESI_INTERRUPT_FLAG_AFE2_ESIOUTX\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_clearInterrupt(uint16_t interruptMask)\r
+{\r
+ ESIINT2 &= ~(interruptMask);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set source of IFG0 interrupt flag\r
+//!\r
+//! \param ifg0Src values are as follows\r
+//! ESI_IFG0_SET_WHEN_ESIOUT0_SET\r
+//! ESI_IFG0_SET_WHEN_ESIOUT0_RESET\r
+//! ESI_IFG0_SET_WHEN_ESIOUT1_SET\r
+//! ESI_IFG0_SET_WHEN_ESIOUT1_RESET\r
+//! ESI_IFG0_SET_WHEN_ESIOUT2_SET\r
+//! ESI_IFG0_SET_WHEN_ESIOUT2_RESET\r
+//! ESI_IFG0_SET_WHEN_ESIOUT3_SET\r
+//! ESI_IFG0_SET_WHEN_ESIOUT3_RESET\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setIFG0Source(uint16_t ifg0Src)\r
+{\r
+ ESIINT1 &= ~ESI_IFG0_SET_WHEN_ESIOUT3_RESET;\r
+ ESIINT1 |= ifg0Src;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set source of IFG8 interrupt flag\r
+//!\r
+//! \param ifg8Src values are as follows\r
+//! ESI_IFG8_SET_WHEN_ESIOUT4_SET\r
+//! ESI_IFG8_SET_WHEN_ESIOUT4_RESET\r
+//! ESI_IFG8_SET_WHEN_ESIOUT5_SET\r
+//! ESI_IFG8_SET_WHEN_ESIOUT5_RESET\r
+//! ESI_IFG8_SET_WHEN_ESIOUT6_SET\r
+//! ESI_IFG8_SET_WHEN_ESIOUT6_RESET\r
+//! ESI_IFG8_SET_WHEN_ESIOUT7_SET\r
+//! ESI_IFG8_SET_WHEN_ESIOUT7_RESET\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setIFG8Source(uint16_t ifg8Src)\r
+{\r
+ ESIINT1 &= ~ESI_IFG8_SET_WHEN_ESIOUT7_RESET;\r
+ ESIINT1 |= ifg8Src;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set source of IFG7 interrupt flag\r
+//!\r
+//! \param ifg7Src values are as follows\r
+//! ESI_IFG7_SOURCE_EVERY_COUNT_OF_CNT0\r
+//! ESI_IFG7_SOURCE_CNT0_MOD4\r
+//! ESI_IFG7_SOURCE_CNT0_MOD256\r
+//! ESI_IFG7_SOURCE_CNT0_ROLLOVER\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setIFG7Source(uint16_t ifg7Src)\r
+{\r
+ ESIINT2 &= ~ESI_IFG7_SOURCE_CNT0_ROLLOVER;\r
+ ESIINT2 |= ifg7Src;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set source of IFG4 interrupt flag\r
+//!\r
+//! \param ifg4Src values are as follows\r
+//! ESI_IFG4_SOURCE_EVERY_COUNT_OF_CNT2\r
+//! ESI_IFG4_SOURCE_CNT2_MOD4\r
+//! ESI_IFG4_SOURCE_CNT2_MOD256\r
+//! ESI_IFG4_SOURCE_CNT2_ROLLOVER\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_setIFG4Source(uint16_t ifg4Src)\r
+{\r
+ ESIINT2 &= ~ESI_IFG4_SOURCE_CNT2_ROLLOVER;\r
+ ESIINT2 |= ifg4Src;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Simple DAC calibration code using pre-defined TSM\r
+//! Supports AFE1 only.\r
+//! \param selected_channel acceptable values\r
+//! ESI_AFE1_CHANNEL0_SELECT\r
+//! ESI_AFE1_CHANNEL1_SELECT\r
+//! ESI_AFE1_CHANNEL2_SELECT\r
+//! ESI_AFE1_CHANNEL3_SELECT\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void ESI_LC_DAC_calibration(uint8_t selected_channel)\r
+{\r
+#define NUM_SENSOR_CAL 4\r
+#define MIN_HYSTERESIS 30\r
+#define STEP_TO_FINISH 4\r
+\r
+ unsigned int i;\r
+ unsigned char test_bit, done;\r
+ unsigned int hysteresis[NUM_SENSOR_CAL],\r
+ hysteresis_hi[NUM_SENSOR_CAL],\r
+ hysteresis_lo[NUM_SENSOR_CAL],\r
+ current[NUM_SENSOR_CAL],\r
+ average[NUM_SENSOR_CAL],\r
+ max[NUM_SENSOR_CAL],\r
+ min[NUM_SENSOR_CAL];\r
+\r
+ // State: 0 = output low\r
+ // 1 = output high\r
+ // 2 = undetermined (between 2 hysteresis level)\r
+ unsigned char previous_state[NUM_SENSOR_CAL],\r
+ current_state[NUM_SENSOR_CAL],\r
+ step[NUM_SENSOR_CAL];\r
+\r
+ // Reset values\r
+ for(i = 0; i < NUM_SENSOR_CAL; i++)\r
+ {\r
+ max[i] = 0;\r
+ min[i] = 0xffff;\r
+ previous_state[i] = 2;\r
+ step[i] = 0;\r
+ }\r
+\r
+ do\r
+ {\r
+ // Find the current oscillating level, using software mode\r
+ FindDAC(selected_channel, 1);\r
+\r
+ test_bit = 1;\r
+ done = 1;\r
+\r
+ for(i = 0; i < NUM_SENSOR_CAL; i++)\r
+ {\r
+ // skip if the channel is not selected\r
+ if(test_bit & selected_channel)\r
+ {\r
+ current[i] = ESI_getAFE1DACValue(i * 2);\r
+\r
+ // Record max and min value\r
+ if(current[i] > max[i])\r
+ {\r
+ max[i] = current[i];\r
+ }\r
+ if(current[i] < min[i])\r
+ {\r
+ min[i] = current[i];\r
+ }\r
+\r
+ // Update average and hysteresis level\r
+ average[i] = (max[i] + min[i]) >> 1;\r
+ hysteresis[i] = (max[i] - min[i]) >> 3;\r
+\r
+ if(hysteresis[i] < MIN_HYSTERESIS)\r
+ {\r
+ hysteresis[i] = MIN_HYSTERESIS;\r
+ }\r
+\r
+ hysteresis[i] >>= 1;\r
+ hysteresis_hi[i] = average[i] + hysteresis[i];\r
+ hysteresis_lo[i] = average[i] - hysteresis[i];\r
+\r
+ // Determine output state based on hysteresis_hi and hysteresis_lo\r
+ if(current[i] < hysteresis_lo[i])\r
+ {\r
+ current_state[i] = 0;\r
+ }\r
+ else if(current[i] > hysteresis_hi[i])\r
+ {\r
+ current_state[i] = 1;\r
+ }\r
+ else\r
+ {\r
+ current_state[i] = 2;\r
+ }\r
+\r
+ // If there is state change, proceed to next step\r
+ switch(current_state[i])\r
+ {\r
+ case 0:\r
+ case 1:\r
+ if(previous_state[i] != current_state[i])\r
+ {\r
+ step[i]++;\r
+ previous_state[i] = current_state[i];\r
+ }\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ // Any selected sensor which has not finished calibration will set done to zero\r
+ if(step[i] < STEP_TO_FINISH)\r
+ {\r
+ done = 0;\r
+ }\r
+ }\r
+ test_bit <<= 1;\r
+ }\r
+ }\r
+ while(!done);\r
+\r
+ // Record DAC Values\r
+ test_bit = 1;\r
+ done = ESI_DAC1_REG0; // Temp value for recording DAC\r
+ for(i = 0; i < NUM_SENSOR_CAL; i++)\r
+ {\r
+ if(test_bit & selected_channel)\r
+ {\r
+ ESI_setAFE1DACValue(hysteresis_hi[i], done++);\r
+ ESI_setAFE1DACValue(hysteresis_lo[i], done++);\r
+ }\r
+ test_bit <<= 1;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Find the current oscillating level, using software mode\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+static void FindDAC(unsigned char selected_channel,\r
+ unsigned char software_trigger)\r
+{\r
+ // DAC Level tester, using successive approximation approach\r
+ unsigned int DAC_BIT = 0x0800, Prev_DAC_BIT = 0x0C00;\r
+\r
+ unsigned int i;\r
+ unsigned int test_bit, DAC_index;\r
+\r
+ // Set initial DAC value for each selected channel\r
+\r
+ // AFE 1\r
+ if(selected_channel & 0x0f)\r
+ {\r
+ test_bit = 0x01;\r
+ DAC_index = ESI_DAC1_REG0;\r
+ for(i = 0; i < 4; i++)\r
+ {\r
+ if(selected_channel & test_bit)\r
+ {\r
+ ESI_setAFE1DACValue(DAC_BIT, DAC_index++);\r
+ ESI_setAFE1DACValue(DAC_BIT, DAC_index++);\r
+ }\r
+ else\r
+ {\r
+ DAC_index += 2;\r
+ }\r
+ test_bit <<= 1;\r
+ }\r
+ }\r
+\r
+ // AFE 2\r
+ if(selected_channel & 0xf0)\r
+ {\r
+ test_bit = 0x10;\r
+ DAC_index = ESI_DAC2_REG0;\r
+ for(i = 0; i < 4; i++)\r
+ {\r
+ if(selected_channel & test_bit)\r
+ {\r
+ ESI_setAFE2DACValue(DAC_BIT, DAC_index++);\r
+ ESI_setAFE2DACValue(DAC_BIT, DAC_index++);\r
+ }\r
+ else\r
+ {\r
+ DAC_index += 2;\r
+ }\r
+ test_bit <<= 1;\r
+ }\r
+ }\r
+\r
+ ESI_enableInterrupt(ESI_INTERRUPT_ESISTOP); // enable ESISTOP INT\r
+\r
+ // Find the DAC value for each selected channel\r
+ do\r
+ {\r
+ ESI_clearInterrupt (ESI_INTERRUPT_FLAG_ESISTOP);\r
+\r
+ if(software_trigger)\r
+ {\r
+ ESI_TSM_softwareTrigger();\r
+ }\r
+\r
+ __bis_SR_register(LPM3_bits + GIE); // wait for the ESISTOP flag\r
+ DAC_BIT >>= 1; // right shift one bit\r
+\r
+ // AFE 1\r
+ if(selected_channel & 0x0f)\r
+ {\r
+ test_bit = 0x01;\r
+ DAC_index = ESI_DAC1_REG0;\r
+ for(i = 0; i < 4; i++)\r
+ {\r
+ if(selected_channel & test_bit)\r
+ {\r
+#ifndef INVERTED\r
+ if(ESI_getLatchedComparatorOutput(test_bit) ==\r
+ ESI_AFE_OUTPUT_HIGH)\r
+#else\r
+ if(ESI_getLatchedComparatorOutput(test_bit) ==\r
+ ESI_AFE_OUTPUT_LOW)\r
+#endif\r
+ {\r
+ ESI_setAFE1DACValue(ESI_getAFE1DACValue(\r
+ DAC_index) | DAC_BIT,\r
+ DAC_index);\r
+ DAC_index++;\r
+ ESI_setAFE1DACValue(ESI_getAFE1DACValue(\r
+ DAC_index) | DAC_BIT,\r
+ DAC_index);\r
+ DAC_index++;\r
+ }\r
+ else\r
+ {\r
+ ESI_setAFE1DACValue(ESI_getAFE1DACValue(\r
+ DAC_index) ^ Prev_DAC_BIT,\r
+ DAC_index);\r
+ DAC_index++;\r
+ ESI_setAFE1DACValue(ESI_getAFE1DACValue(\r
+ DAC_index) ^ Prev_DAC_BIT,\r
+ DAC_index);\r
+ DAC_index++;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ DAC_index += 2;\r
+ }\r
+ test_bit <<= 1;\r
+ }\r
+ }\r
+\r
+ // AFE 2\r
+ if(selected_channel & 0xf0)\r
+ {\r
+ test_bit = 0x10;\r
+ DAC_index = ESI_DAC2_REG0;\r
+ for(i = 0; i < 4; i++)\r
+ {\r
+ if(selected_channel & test_bit)\r
+ {\r
+#ifndef INVERTED\r
+ if(ESI_getLatchedComparatorOutput(test_bit) ==\r
+ ESI_AFE_OUTPUT_HIGH)\r
+#else\r
+ if(ESI_getLatchedComparatorOutput(test_bit) ==\r
+ ESI_AFE_OUTPUT_LOW)\r
+#endif\r
+ {\r
+ ESI_setAFE1DACValue(ESI_getAFE2DACValue(\r
+ DAC_index) | DAC_BIT,\r
+ DAC_index);\r
+ DAC_index++;\r
+ ESI_setAFE1DACValue(ESI_getAFE2DACValue(\r
+ DAC_index) | DAC_BIT,\r
+ DAC_index);\r
+ DAC_index++;\r
+ }\r
+ else\r
+ {\r
+ ESI_setAFE1DACValue(ESI_getAFE2DACValue(\r
+ DAC_index) ^ Prev_DAC_BIT,\r
+ DAC_index);\r
+ DAC_index++;\r
+ ESI_setAFE1DACValue(ESI_getAFE2DACValue(\r
+ DAC_index) ^ Prev_DAC_BIT,\r
+ DAC_index);\r
+ DAC_index++;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ DAC_index += 2;\r
+ }\r
+ test_bit <<= 1;\r
+ }\r
+ }\r
+ Prev_DAC_BIT >>= 1; // right shift one bit\r
+ }\r
+ while(DAC_BIT);\r
+\r
+ ESI_disableInterrupt(ESI_INTERRUPT_ESISTOP);\r
+ __no_operation();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for esi_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
+#endif\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// esi.h - Driver for the ESI Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_ESI_H__\r
+#define __MSP430WARE_ESI_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_ESI__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+uint16_t ESI_getCounter0(void);\r
+uint16_t ESI_getCounter1(void);\r
+uint16_t ESI_getCounter2(void);\r
+uint16_t ESI_getOscCounter(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to excitationCircuitSelect\r
+//parameter in ESI_AFE_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_EXCITATION_CIRCUIT_DISABLED 0x0\r
+#define ESI_EXCITATION_CIRCUIT_ENABLED ESITEN\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to sampleAndHoldSelect\r
+//parameter in ESI_AFE_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_SAMPLE_HOLD_DISABLED 0x0\r
+#define ESI_SAMPLE_HOLD_ENABLED ESISH\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to midVoltageGeneratorSelect\r
+//parameter in ESI_AFE_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_MID_VOLTAGE_GENERATOR_DISABLED 0x0\r
+#define ESI_MID_VOLTAGE_GENERATOR_ENABLED ESIVCC2\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to sampleAndHoldVSSConnect\r
+//parameter in ESI_AFE_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_SAMPLE_HOLD_VSS_TO_ESIVSS 0x0\r
+#define ESI_SAMPLE_HOLD_VSS_BY_TSM ESIVSS\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//inputSelectAFE1 parameter in ESI_AFE1_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_AFE1_INPUT_SELECT_CHx 0\r
+#define ESI_AFE1_INPUT_SELECT_CIx 1\r
+#define ESI_AFE1_INPUT_SELECT_CI3 2\r
+#define ESI_AFE1_INPUT_SELECT_CI 3\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//inputSelectAFE2 parameter in ESI_AFE2_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_AFE2_INPUT_SELECT_CHx 0\r
+#define ESI_AFE2_INPUT_SELECT_CIx ESICA2X\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//inverterSelectOutputAFE1 parameter in ESI_AFE1_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_INVERTER_FOR_AFE1_DISABLE 0x0\r
+#define ESI_INVERTER_FOR_AFE1_ENABLE ESICA1INV\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//inverterSelectOutputAFE2 parameter in ESI_AFE2_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_INVERTER_FOR_AFE2_DISABLE 0x0\r
+#define ESI_INVERTER_FOR_AFE2_ENABLE ESICA2INV\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//tsmControlOfComparatorAFE2 parameter in ESI_AFE2_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_COMPARATOR_CONTROL_AFE2_DISABLE 0x0\r
+#define ESI_TSM_COMPARATOR_CONTROL_AFE2_ENABLE ESICA2EN\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//tsmControlDacAFE2 parameter in ESI_AFE2_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_DAC_CONTROL_AFE2_DISABLE 0x0\r
+#define ESI_TSM_DAC_CONTROL_AFE2_ENABLE ESIDAC2EN\r
+\r
+typedef struct ESI_AFE1_InitParams\r
+{\r
+ uint16_t excitationCircuitSelect;\r
+ uint16_t sampleAndHoldSelect;\r
+ uint16_t midVoltageGeneratorSelect;\r
+ uint16_t sampleAndHoldVSSConnect;\r
+ uint16_t inputSelectAFE1;\r
+ uint16_t inverterSelectOutputAFE1;\r
+} ESI_AFE1_InitParams;\r
+\r
+extern const ESI_AFE1_InitParams ESI_AFE1_INITPARAMS_DEFAULT;\r
+\r
+void ESI_AFE1_init(ESI_AFE1_InitParams *params);\r
+\r
+typedef struct ESI_AFE2_InitParams\r
+{\r
+ uint16_t inputSelectAFE2;\r
+ uint16_t inverterSelectOutputAFE2;\r
+ uint16_t tsmControlComparatorAFE2;\r
+ uint16_t tsmControlDacAFE2;\r
+} ESI_AFE2_InitParams;\r
+\r
+extern const ESI_AFE2_InitParams ESI_AFE2_INITPARAMS_DEFAULT;\r
+\r
+void ESI_AFE2_init(ESI_AFE2_InitParams *params);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//channelSelect parameter in ESI_getLatchedComparatorOutput\r
+//\r
+//*****************************************************************************\r
+#define ESI_AFE1_CHANNEL0_SELECT ESIOUT0\r
+#define ESI_AFE1_CHANNEL1_SELECT ESIOUT1\r
+#define ESI_AFE1_CHANNEL2_SELECT ESIOUT2\r
+#define ESI_AFE1_CHANNEL3_SELECT ESIOUT3\r
+#define ESI_AFE2_CHANNEL0_SELECT ESIOUT4\r
+#define ESI_AFE2_CHANNEL1_SELECT ESIOUT5\r
+#define ESI_AFE2_CHANNEL2_SELECT ESIOUT6\r
+#define ESI_AFE2_CHANNEL3_SELECT ESIOUT7\r
+#define ESI_AFE1_TEST_CHANNEL0_SELECT ESITCHOUT0\r
+#define ESI_AFE1_TEST_CHANNEL1_SELECT ESITCHOUT1\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that are returned by ESI_getLatchedComparatorOutput\r
+//\r
+//*****************************************************************************\r
+#define ESI_AFE_OUTPUT_HIGH 0x1\r
+#define ESI_AFE_OUTPUT_LOW 0x0\r
+\r
+uint16_t ESI_getLatchedComparatorOutput(uint16_t channelSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//smclkDivider parameter in ESI_TSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_SMCLK_DIV_1 0x0\r
+#define ESI_TSM_SMCLK_DIV_2 ESIDIV10\r
+#define ESI_TSM_SMCLK_DIV_4 ESIDIV11\r
+#define ESI_TSM_SMCLK_DIV_8 ESIDIV10 + ESIDIV11\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//aclkDivider parameter in ESI_TSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_ACLK_DIV_1 0x0\r
+#define ESI_TSM_ACLK_DIV_2 ESIDIV20\r
+#define ESI_TSM_ACLK_DIV_4 ESIDIV21\r
+#define ESI_TSM_ACLK_DIV_8 ESIDIV20 + ESIDIV21\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//startTriggerAclkDivider parameter in ESI_TSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_START_TRIGGER_DIV_2 0x0\r
+#define ESI_TSM_START_TRIGGER_DIV_6 ESIDIV3A0\r
+#define ESI_TSM_START_TRIGGER_DIV_10 ESIDIV3A1\r
+#define ESI_TSM_START_TRIGGER_DIV_14 ESIDIV3A0 + ESIDIV3A1\r
+#define ESI_TSM_START_TRIGGER_DIV_18 ESIDIV3A2\r
+#define ESI_TSM_START_TRIGGER_DIV_22 ESIDIV3A2 + ESIDIV3A0\r
+#define ESI_TSM_START_TRIGGER_DIV_26 ESIDIV3A2 + ESIDIV3A1\r
+#define ESI_TSM_START_TRIGGER_DIV_30 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0\r
+#define ESI_TSM_START_TRIGGER_DIV_42 ESIDIV3A0 + ESIDIV3A1 + ESIDIV3B0\r
+#define ESI_TSM_START_TRIGGER_DIV_50 ESIDIV3A1 + ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_54 ESIDIV3A2 + ESIDIV3B0\r
+#define ESI_TSM_START_TRIGGER_DIV_66 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B0\r
+#define ESI_TSM_START_TRIGGER_DIV_70 ESIDIV3A1 + ESIDIV3A0 + ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_78 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B0\r
+#define ESI_TSM_START_TRIGGER_DIV_90 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \\r
+ ESIDIV3B0\r
+#define ESI_TSM_START_TRIGGER_DIV_98 ESIDIV3A0 + ESIDIV3A1 + ESIDIV3B0 + \\r
+ ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_110 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_126 ESIDIV3A2 + ESIDIV3B0 + ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_130 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_150 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \\r
+ ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_154 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B0 + \\r
+ ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_162 ESIDIV3A2 + ESIDIV3B2\r
+#define ESI_TSM_START_TRIGGER_DIV_182 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B0 + \\r
+ ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_198 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B2\r
+#define ESI_TSM_START_TRIGGER_DIV_210 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \\r
+ ESIDIV3B0 + ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_234 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B2\r
+#define ESI_TSM_START_TRIGGER_DIV_242 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B2 + \\r
+ ESIDIV3B0\r
+#define ESI_TSM_START_TRIGGER_DIV_270 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \\r
+ ESIDIV3B2\r
+#define ESI_TSM_START_TRIGGER_DIV_286 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B2 + \\r
+ ESIDIV3B0\r
+#define ESI_TSM_START_TRIGGER_DIV_330 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \\r
+ ESIDIV3B2 + ESIDIV3B0\r
+#define ESI_TSM_START_TRIGGER_DIV_338 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B2 + \\r
+ ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_390 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \\r
+ ESIDIV3B2 + ESIDIV3B1\r
+#define ESI_TSM_START_TRIGGER_DIV_450 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \\r
+ ESIDIV3B2 + ESIDIV3B1 + ESIDIV3B0\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//repeatMode parameter in ESI_TSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_REPEAT_NEW_TRIGGER 0x0\r
+#define ESI_TSM_REPEAT_END_OF_PREVIOUS_SEQ ESITSMRP\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//startTriggerSelection parameter in ESI_TSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STOP_SEQUENCE 0x0\r
+#define ESI_TSM_START_TRIGGER_ACLK ESITSMTRG0\r
+#define ESI_TSM_START_TRIGGER_SOFTWARE ESITSMTRG1\r
+#define ESI_TSM_START_TRIGGER_ACLK_OR_SOFTWARE ESITSMTRG1 + ESITSMTRG0\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//tsmFunctionalitySelection parameter in ESI_TSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_HIGH_FREQ_CLK_FUNCTION_ON 0x0\r
+#define ESI_TSM_AUTOZERO_CYCLE_FUNCTION_ON ESICLKAZSEL\r
+\r
+typedef struct ESI_TSM_InitParams\r
+{\r
+ uint16_t smclkDivider;\r
+ uint16_t aclkDivider;\r
+ uint16_t startTriggerAclkDivider;\r
+ uint16_t repeatMode;\r
+ uint16_t startTriggerSelection;\r
+ uint16_t tsmFunctionSelection;\r
+} ESI_TSM_InitParams;\r
+\r
+extern const ESI_TSM_InitParams ESI_TSM_INITPARAMS_DEFAULT;\r
+\r
+void ESI_TSM_init(ESI_TSM_InitParams *params);\r
+\r
+void ESI_TSM_clearTable(void);\r
+\r
+void ESI_TSM_copyTable(uint16_t* tsmTable,\r
+ uint16_t size);\r
+\r
+void ESI_TSM_softwareTrigger(void);\r
+\r
+uint8_t ESI_TSM_getTSMStateDuration(uint8_t stateRegNum);\r
+\r
+void ESI_TSM_setTSMStateDuration(uint8_t stateRegNum,\r
+ uint8_t duration);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//Q6Select parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_Q6_DISABLE 0x0\r
+#define ESI_PSM_Q6_ENABLE ESIQ6EN\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//Q7TriggerSelect parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_Q7_TRIGGER_DISABLE 0x0\r
+#define ESI_PSM_Q7_TRIGGER_ENABLE ESIQ7TRG\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//count0Select parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_CNT0_DISABLE 0x0\r
+#define ESI_PSM_CNT0_ENABLE ESICNT0EN\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//count0Reset parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_CNT0_NO_RESET 0x0\r
+#define ESI_PSM_CNT0_RESET ESICNT0RST\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//count1Select parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_CNT1_DISABLE 0x0\r
+#define ESI_PSM_CNT1_ENABLE ESICNT1EN\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//count1Reset parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_CNT1_NO_RESET 0x0\r
+#define ESI_PSM_CNT1_RESET ESICNT1RST\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//count2Select parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_CNT2_DISABLE 0x0\r
+#define ESI_PSM_CNT2_ENABLE ESICNT2EN\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//count2Reset parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_CNT2_NO_RESET 0x0\r
+#define ESI_PSM_CNT2_RESET ESICNT2RST\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//V2Select parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_S3_SELECT 0x0\r
+#define ESI_PSM_Q0_SELECT ESIV2SEL\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//TEST4Select parameter in ESI_PSM_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_TEST4_IS_Q2 0x0\r
+#define ESI_PSM_TEST4_IS_Q1 ESITEST4SEL0\r
+#define ESI_PSM_TEST4_IS_TSM_CLK ESITEST4SEL1\r
+#define ESI_PSM_TEST4_IS_AFE1_COMPARATOR ESITEST4SEL0 + ESITEST4SEL1\r
+\r
+typedef struct ESI_PSM_InitParams\r
+{\r
+ uint16_t Q6Select;\r
+ uint16_t Q7TriggerSelect;\r
+ uint16_t count0Select;\r
+ uint16_t count0Reset;\r
+ uint16_t count1Select;\r
+ uint16_t count1Reset;\r
+ uint16_t count2Select;\r
+ uint16_t count2Reset;\r
+ uint16_t V2Select;\r
+ uint16_t TEST4Select;\r
+} ESI_PSM_InitParams;\r
+\r
+extern const ESI_PSM_InitParams ESI_PSM_INITPARAMS_DEFAULT;\r
+\r
+void ESI_PSM_init(ESI_PSM_InitParams *params);\r
+\r
+void ESI_PSM_clearTable(void);\r
+void ESI_PSM_copyTable(uint8_t * psmTable,\r
+ uint8_t size);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//counterToReset parameter in ESI_PSM_counterReset\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_CNT0_RST ESICNT0RST\r
+#define ESI_PSM_CNT1_RST ESICNT1RST\r
+#define ESI_PSM_CNT2_RST ESICNT2RST\r
+\r
+void ESI_PSM_resetCounter(uint16_t counterToReset);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//testCycleInsertion parameter in ESI_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TEST_CYCLE_INSERTION_DISABLE 0x0\r
+#define ESI_TEST_CYCLE_INSERTION_ENABLE ESITESTD\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//timerAInputSelection parameter in ESI_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TIMERA_INPUT_TSM_COMPOUT 0x0\r
+#define ESI_TIMERA_INPUT_TSM_PPUSRC ESICS\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//testChannel0Select parameter in ESI_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TEST_CHANNEL0_SOURCE_IS_CH0_CI0 0x0\r
+#define ESI_TEST_CHANNEL0_SOURCE_IS_CH1_CI1 ESITCH00\r
+#define ESI_TEST_CHANNEL0_SOURCE_IS_CH2_CI2 ESITCH01\r
+#define ESI_TEST_CHANNEL0_SOURCE_IS_CH3_CI3 ESITCH00 + ESITCH01\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//testChannel1Select parameter in ESI_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TEST_CHANNEL1_SOURCE_IS_CH0_CI0 0x0\r
+#define ESI_TEST_CHANNEL1_SOURCE_IS_CH1_CI1 ESITCH10\r
+#define ESI_TEST_CHANNEL1_SOURCE_IS_CH2_CI2 ESITCH11\r
+#define ESI_TEST_CHANNEL1_SOURCE_IS_CH3_CI3 ESITCH10 + ESITCH11\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//internalOscSelect parameter in ESI_InitParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_INTERNAL_OSC_DISABLE 0x0\r
+#define ESI_INTERNAL_OSC_ENABLE ESIHFSEL\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//sourceNum parameter in ESI_psmSourceSelect\r
+//\r
+//*****************************************************************************\r
+#define PSM_S1_SOURCE 1\r
+#define PSM_S2_SOURCE 2\r
+#define PSM_S3_SOURCE 3\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//sourceSelect parameter in ESI_psmSourceSelect\r
+//\r
+//*****************************************************************************\r
+#define ESI_PSM_SOURCE_IS_ESIOUT0 0\r
+#define ESI_PSM_SOURCE_IS_ESIOUT1 1\r
+#define ESI_PSM_SOURCE_IS_ESIOUT2 2\r
+#define ESI_PSM_SOURCE_IS_ESIOUT3 3\r
+#define ESI_PSM_SOURCE_IS_ESIOUT4 4\r
+#define ESI_PSM_SOURCE_IS_ESIOUT5 5\r
+#define ESI_PSM_SOURCE_IS_ESIOUT6 6\r
+#define ESI_PSM_SOURCE_IS_ESIOUT7 7\r
+\r
+void ESI_timerAInputSelect(uint16_t select);\r
+void ESI_psmSourceSelect(uint16_t sourceNum,\r
+ uint16_t sourceSelect);\r
+void ESI_testChannel0SourceSelect(uint16_t sourceSelect);\r
+void ESI_testChannel1SourceSelect(uint16_t sourceSelect);\r
+void ESI_enable(void);\r
+void ESI_disable(void);\r
+\r
+void ESI_enableInternalOscillator();\r
+void ESI_disableInternalOscillator();\r
+void ESI_startInternalOscCal(void);\r
+void ESI_stopInternalOscCal(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//oversample parameter in ESI_measureESIOSCOversample\r
+//\r
+//*****************************************************************************\r
+#define ESI_ESIOSC_NO_OVERSAMPLE 0\r
+#define ESI_ESIOSC_OVERSAMPLE_2 2\r
+#define ESI_ESIOSC_OVERSAMPLE_4 4\r
+#define ESI_ESIOSC_OVERSAMPLE_8 8\r
+uint16_t ESI_measureESIOSC(uint8_t oversample);\r
+uint8_t ESI_getESICLKFQ(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//incOrDec parameter in ESI_adjustInternalOscFreq\r
+//\r
+//*****************************************************************************\r
+#define ESI_INTERNAL_OSC_FREQ_DECREASE 0x0\r
+#define ESI_INTERNAL_OSC_FREQ_INCREASE 0x1\r
+\r
+void ESI_adjustInternalOscFreq(uint16_t incOrDec);\r
+void ESI_setNominalInternalOscFreq(void);\r
+void ESI_calibrateInternalOscFreq(uint16_t targetAclkCounts);\r
+void ESI_setPSMCounter1IncreaseThreshold(uint16_t threshold);\r
+\r
+void ESI_setPSMCounter1DecreaseThreshold(uint16_t threshold);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//resultNum parameter in ESI_getConversionResult\r
+//\r
+//*****************************************************************************\r
+#define ESI_CONVERSION_RESULT_1 ESIADMEM1\r
+#define ESI_CONVERSION_RESULT_2 ESIADMEM2\r
+#define ESI_CONVERSION_RESULT_3 ESIADMEM3\r
+#define ESI_CONVERSION_RESULT_4 ESIADMEM4\r
+\r
+uint16_t ESI_getConversionResult(uint16_t resultNum);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//dacRegNum parameter in ESI_setAFE1DACValue and ESI_getAFE1DACValue\r
+//\r
+//*****************************************************************************\r
+#define ESI_DAC1_REG0 0\r
+#define ESI_DAC1_REG1 1\r
+#define ESI_DAC1_REG2 2\r
+#define ESI_DAC1_REG3 3\r
+#define ESI_DAC1_REG4 4\r
+#define ESI_DAC1_REG5 5\r
+#define ESI_DAC1_REG6 6\r
+#define ESI_DAC1_REG7 7\r
+\r
+void ESI_setAFE1DACValue(uint16_t dacValue,\r
+ uint8_t dacRegNum);\r
+uint16_t ESI_getAFE1DACValue(uint8_t dacRegNum);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//dacRegNum parameter in ESI_setAFE2DACValue and ESI_getAFE2DACValue\r
+//\r
+//*****************************************************************************\r
+#define ESI_DAC2_REG0 0\r
+#define ESI_DAC2_REG1 1\r
+#define ESI_DAC2_REG2 2\r
+#define ESI_DAC2_REG3 3\r
+#define ESI_DAC2_REG4 4\r
+#define ESI_DAC2_REG5 5\r
+#define ESI_DAC2_REG6 6\r
+#define ESI_DAC2_REG7 7\r
+\r
+void ESI_setAFE2DACValue(uint16_t dacValue,\r
+ uint8_t dacRegNum);\r
+uint16_t ESI_getAFE2DACValue(uint8_t dacRegNum);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//stateRegNum parameter in ESI_setTSMstateReg\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_REG_0 0\r
+#define ESI_TSM_STATE_REG_1 1\r
+#define ESI_TSM_STATE_REG_2 2\r
+#define ESI_TSM_STATE_REG_3 3\r
+#define ESI_TSM_STATE_REG_4 4\r
+#define ESI_TSM_STATE_REG_5 5\r
+#define ESI_TSM_STATE_REG_6 6\r
+#define ESI_TSM_STATE_REG_7 7\r
+#define ESI_TSM_STATE_REG_8 8\r
+#define ESI_TSM_STATE_REG_9 9\r
+#define ESI_TSM_STATE_REG_10 10\r
+#define ESI_TSM_STATE_REG_11 11\r
+#define ESI_TSM_STATE_REG_12 12\r
+#define ESI_TSM_STATE_REG_13 13\r
+#define ESI_TSM_STATE_REG_14 14\r
+#define ESI_TSM_STATE_REG_15 15\r
+#define ESI_TSM_STATE_REG_16 16\r
+#define ESI_TSM_STATE_REG_17 17\r
+#define ESI_TSM_STATE_REG_18 18\r
+#define ESI_TSM_STATE_REG_19 19\r
+#define ESI_TSM_STATE_REG_20 20\r
+#define ESI_TSM_STATE_REG_21 21\r
+#define ESI_TSM_STATE_REG_22 22\r
+#define ESI_TSM_STATE_REG_23 23\r
+#define ESI_TSM_STATE_REG_24 24\r
+#define ESI_TSM_STATE_REG_25 25\r
+#define ESI_TSM_STATE_REG_26 26\r
+#define ESI_TSM_STATE_REG_27 27\r
+#define ESI_TSM_STATE_REG_28 28\r
+#define ESI_TSM_STATE_REG_29 29\r
+#define ESI_TSM_STATE_REG_30 30\r
+#define ESI_TSM_STATE_REG_31 31\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//inputChannelSelect parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_CHANNEL_SELECT_CH0 0\r
+#define ESI_TSM_STATE_CHANNEL_SELECT_CH1 ESICH0\r
+#define ESI_TSM_STATE_CHANNEL_SELECT_CH2 ESICH1\r
+#define ESI_TSM_STATE_CHANNEL_SELECT_CH3 (ESICH1 | ESICH0)\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//LCDampingSelect parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_LC_DAMPING_DISABLE 0x0\r
+#define ESI_TSM_STATE_LC_DAMPING_ENABLE ESILCEN\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//excitationSelect parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_EXCITATION_DISABLE 0x0\r
+#define ESI_TSM_STATE_EXCITATION_ENABLE ESIEX\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//comparatorSelect parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_COMPARATOR_DISABLE 0x0\r
+#define ESI_TSM_STATE_COMPARATOR_ENABLE ESICA\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//highFreqClkOn_or_compAutoZeroCycle parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_HIGH_FREQ_CLK_ON 0x0\r
+#define ESI_TSM_STATE_COMP_AUTOZERO_CYCLE ESICLKON\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//outputLatchSelect parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_OUTPUT_LATCH_DISABLE 0x0\r
+#define ESI_TSM_STATE_OUTPUT_LATCH_ENABLE ESIRSON\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//testCycleSelect parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_TEST_CYCLE_DISABLE 0x0\r
+#define ESI_TSM_STATE_TEST_CYCLE_ENABLE ESITESTS1\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//dacSelect parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_DAC_DISABLE 0x0\r
+#define ESI_TSM_STATE_DAC_ENABLE ESIDAC\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//tsmStop parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_CONTINUE 0x0\r
+#define ESI_TSM_STATE_STOP ESISTOP\r
+\r
+//*****************************************************************************\r
+//\r
+//The following are values that can be passed to\r
+//tsmClkSrc parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_HIGH_FREQ_CLK 0x0\r
+#define ESI_TSM_STATE_ACLK ESICLK\r
+\r
+//*****************************************************************************\r
+//\r
+//Values between these min and max can be pased to\r
+//duration parameter in ESI_TSM_StateParams\r
+//\r
+//*****************************************************************************\r
+#define ESI_TSM_STATE_DURATION_MIN 0x00\r
+#define ESI_TSM_STATE_DURATION_MAX 0x1F\r
+\r
+typedef struct ESI_TSM_StateParams\r
+{\r
+ uint16_t inputChannelSelect;\r
+ uint16_t LCDampingSelect;\r
+ uint16_t excitationSelect;\r
+ uint16_t comparatorSelect;\r
+ uint16_t highFreqClkOn_or_compAutoZeroCycle;\r
+ uint16_t outputLatchSelect;\r
+ uint16_t testCycleSelect;\r
+ uint16_t dacSelect;\r
+ uint16_t tsmStop;\r
+ uint16_t tsmClkSrc;\r
+ uint16_t duration;\r
+} ESI_TSM_StateParams;\r
+\r
+void ESI_setTSMstateReg(ESI_TSM_StateParams *params,\r
+ uint8_t stateRegNum);\r
+\r
+uint16_t ESIgetInterruptVectorRegister(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//The following values can be be used to form the interrupt mask for\r
+//ESI_enableInterrupt and ESI_disableInterrupt\r
+//\r
+//*****************************************************************************\r
+#define ESI_INTERRUPT_AFE1_ESIOUTX \\r
+ ESIIE0\r
+#define ESI_INTERRUPT_ESISTOP ESIIE1\r
+#define ESI_INTERRUPT_ESISTART ESIIE2\r
+#define ESI_INTERRUPT_ESICNT1 ESIIE3\r
+#define ESI_INTERRUPT_ESICNT2 ESIIE4\r
+#define ESI_INTERRUPT_Q6_BIT_SET ESIIE5\r
+#define ESI_INTERRUPT_Q7_BIT_SET ESIIE6\r
+#define ESI_INTERRUPT_ESICNT0_COUNT_INTERVAL ESIIE7\r
+#define ESI_INTERRUPT_AFE2_ESIOUTX \\r
+ ESIIE8\r
+\r
+void ESI_enableInterrupt(uint16_t interruptMask);\r
+void ESI_disableInterrupt(uint16_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//Return values for ESI_getInterruptStatus\r
+//\r
+//*****************************************************************************\r
+#define ESI_INTERRUPT_FLAG_AFE1_ESIOUTX ESIIFG0\r
+#define ESI_INTERRUPT_FLAG_ESISTOP ESIIFG1\r
+#define ESI_INTERRUPT_FLAG_ESISTART ESIIFG2\r
+#define ESI_INTERRUPT_FLAG_ESICNT1 ESIIFG3\r
+#define ESI_INTERRUPT_FLAG_ESICNT2 ESIIFG4\r
+#define ESI_INTERRUPT_FLAG_Q6_BIT_SET ESIIFG5\r
+#define ESI_INTERRUPT_FLAG_Q7_BIT_SET ESIIFG6\r
+#define ESI_INTERRUPT_FLAG_ESICNT0_COUNT_INTERVAL ESIIFG7\r
+#define ESI_INTERRUPT_FLAG_AFE2_ESIOUTX ESIIFG8\r
+\r
+uint16_t ESI_getInterruptStatus(uint16_t interruptMask);\r
+void ESI_clearInterrupt(uint16_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//Values for ifg0Src in ESI_setIFG0Source\r
+//\r
+//*****************************************************************************\r
+#define ESI_IFG0_SET_WHEN_ESIOUT0_SET ESIIFGSET1_0\r
+#define ESI_IFG0_SET_WHEN_ESIOUT0_RESET ESIIFGSET1_1\r
+#define ESI_IFG0_SET_WHEN_ESIOUT1_SET ESIIFGSET1_2\r
+#define ESI_IFG0_SET_WHEN_ESIOUT1_RESET ESIIFGSET1_3\r
+#define ESI_IFG0_SET_WHEN_ESIOUT2_SET ESIIFGSET1_4\r
+#define ESI_IFG0_SET_WHEN_ESIOUT2_RESET ESIIFGSET1_5\r
+#define ESI_IFG0_SET_WHEN_ESIOUT3_SET ESIIFGSET1_6\r
+#define ESI_IFG0_SET_WHEN_ESIOUT3_RESET ESIIFGSET1_7\r
+\r
+void ESI_setIFG0Source(uint16_t ifg0Src);\r
+\r
+//*****************************************************************************\r
+//\r
+//Values for ifg8Src in ESI_setIFG8Source\r
+//\r
+//*****************************************************************************\r
+#define ESI_IFG8_SET_WHEN_ESIOUT4_SET ESIIFGSET2_0\r
+#define ESI_IFG8_SET_WHEN_ESIOUT4_RESET ESIIFGSET2_1\r
+#define ESI_IFG8_SET_WHEN_ESIOUT5_SET ESIIFGSET2_2\r
+#define ESI_IFG8_SET_WHEN_ESIOUT5_RESET ESIIFGSET2_3\r
+#define ESI_IFG8_SET_WHEN_ESIOUT6_SET ESIIFGSET2_4\r
+#define ESI_IFG8_SET_WHEN_ESIOUT6_RESET ESIIFGSET2_5\r
+#define ESI_IFG8_SET_WHEN_ESIOUT7_SET ESIIFGSET2_6\r
+#define ESI_IFG8_SET_WHEN_ESIOUT7_RESET ESIIFGSET2_7\r
+\r
+void ESI_setIFG8Source(uint16_t ifg8Src);\r
+\r
+//*****************************************************************************\r
+//\r
+//Values for ifg7Src in ESI_setIFG7Source\r
+//\r
+//*****************************************************************************\r
+#define ESI_IFG7_SOURCE_EVERY_COUNT_OF_CNT0 ESIIS0_0\r
+#define ESI_IFG7_SOURCE_CNT0_MOD4 ESIIS0_1\r
+#define ESI_IFG7_SOURCE_CNT0_MOD256 ESIIS0_2\r
+#define ESI_IFG7_SOURCE_CNT0_ROLLOVER ESIIS0_3\r
+\r
+void ESI_setIFG7Source(uint16_t ifg7Src);\r
+\r
+//*****************************************************************************\r
+//\r
+//Values for ifg4Src in ESI_setIFG4Source\r
+//\r
+//*****************************************************************************\r
+#define ESI_IFG4_SOURCE_EVERY_COUNT_OF_CNT2 ESIIS2_0\r
+#define ESI_IFG4_SOURCE_CNT2_MOD4 ESIIS2_1\r
+#define ESI_IFG4_SOURCE_CNT2_MOD256 ESIIS2_2\r
+#define ESI_IFG4_SOURCE_CNT2_ROLLOVER ESIIS2_3\r
+\r
+void ESI_setIFG4Source(uint16_t ifg4Src);\r
+\r
+void ESI_setPSMCounter1UpperThreshold(uint16_t threshold);\r
+void ESI_setPSMCounter1LowerThreshold(uint16_t threshold);\r
+\r
+//*****************************************************************************\r
+//\r
+// Set correct DAC values for LC sensors\r
+//\r
+//*****************************************************************************\r
+void ESI_LC_DAC_calibration(uint8_t selected_channel);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_a_spi.c - Driver for the eusci_a_spi Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup eusci_a_spi_api eusci_a_spi\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Ax__\r
+#include "eusci_a_spi.h"\r
+\r
+#include <assert.h>\r
+\r
+void EUSCI_A_SPI_initMaster(uint16_t baseAddress,\r
+ EUSCI_A_SPI_initMasterParam *param)\r
+{\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
+\r
+ //Reset OFS_UCAxCTLW0 values\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB +\r
+ UCMST + UCMODE_3 + UCSYNC);\r
+\r
+ //Reset OFS_UCAxCTLW0 values\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSSEL_3);\r
+\r
+ //Select Clock\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource;\r
+\r
+ HWREG16(baseAddress + OFS_UCAxBRW) =\r
+ (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);\r
+\r
+ /*\r
+ * Configure as SPI master mode.\r
+ * Clock phase select, polarity, msb\r
+ * UCMST = Master mode\r
+ * UCSYNC = Synchronous mode\r
+ * UCMODE_0 = 3-pin SPI\r
+ */\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= (\r
+ param->msbFirst +\r
+ param->clockPhase +\r
+ param->clockPolarity +\r
+ UCMST +\r
+ UCSYNC +\r
+ param->spiMode\r
+ );\r
+ //No modulation\r
+ HWREG16(baseAddress + OFS_UCAxMCTLW) = 0;\r
+}\r
+\r
+void EUSCI_A_SPI_select4PinFunctionality(uint16_t baseAddress,\r
+ uint8_t select4PinFunctionality)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSTEM;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= select4PinFunctionality;\r
+}\r
+\r
+void EUSCI_A_SPI_changeMasterClock(uint16_t baseAddress,\r
+ EUSCI_A_SPI_changeMasterClockParam *param)\r
+{\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
+\r
+ HWREG16(baseAddress + OFS_UCAxBRW) =\r
+ (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);\r
+\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_A_SPI_initSlave(uint16_t baseAddress,\r
+ EUSCI_A_SPI_initSlaveParam *param)\r
+{\r
+ //Disable USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
+\r
+ //Reset OFS_UCAxCTLW0 register\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCMSB +\r
+ UC7BIT +\r
+ UCMST +\r
+ UCCKPL +\r
+ UCCKPH +\r
+ UCMODE_3\r
+ );\r
+\r
+ //Clock polarity, phase select, msbFirst, SYNC, Mode0\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= (param->clockPhase +\r
+ param->clockPolarity +\r
+ param->msbFirst +\r
+ UCSYNC +\r
+ param->spiMode\r
+ );\r
+}\r
+\r
+void EUSCI_A_SPI_changeClockPhasePolarity(uint16_t baseAddress,\r
+ uint16_t clockPhase,\r
+ uint16_t clockPolarity)\r
+{\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
+\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCCKPH + UCCKPL);\r
+\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= (\r
+ clockPhase +\r
+ clockPolarity\r
+ );\r
+\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_A_SPI_transmitData(uint16_t baseAddress,\r
+ uint8_t transmitData)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData;\r
+}\r
+\r
+uint8_t EUSCI_A_SPI_receiveData(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCAxRXBUF));\r
+}\r
+\r
+void EUSCI_A_SPI_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxIE) |= mask;\r
+}\r
+\r
+void EUSCI_A_SPI_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxIE) &= ~mask;\r
+}\r
+\r
+uint8_t EUSCI_A_SPI_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCAxIFG) & mask);\r
+}\r
+\r
+void EUSCI_A_SPI_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxIFG) &= ~mask;\r
+}\r
+\r
+void EUSCI_A_SPI_enable(uint16_t baseAddress)\r
+{\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_A_SPI_disable(uint16_t baseAddress)\r
+{\r
+ //Set the UCSWRST bit to disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
+}\r
+\r
+uint32_t EUSCI_A_SPI_getReceiveBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCAxRXBUF);\r
+}\r
+\r
+uint32_t EUSCI_A_SPI_getTransmitBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCAxTXBUF);\r
+}\r
+\r
+uint16_t EUSCI_A_SPI_isBusy(uint16_t baseAddress)\r
+{\r
+ //Return the bus busy status.\r
+ return (HWREG16(baseAddress + OFS_UCAxSTATW) & UCBUSY);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for eusci_a_spi_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_a_spi.h - Driver for the EUSCI_A_SPI Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_EUSCI_A_SPI_H__\r
+#define __MSP430WARE_EUSCI_A_SPI_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Ax__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the EUSCI_A_SPI_changeMasterClock() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct EUSCI_A_SPI_changeMasterClockParam\r
+{\r
+ //! Is the frequency of the selected clock source\r
+ uint32_t clockSourceFrequency;\r
+ //! Is the desired clock rate for SPI communication\r
+ uint32_t desiredSpiClock;\r
+} EUSCI_A_SPI_changeMasterClockParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the EUSCI_A_SPI_initSlave() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct EUSCI_A_SPI_initSlaveParam\r
+{\r
+ //! Controls the direction of the receive and transmit shift register.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_SPI_MSB_FIRST\r
+ //! - \b EUSCI_A_SPI_LSB_FIRST [Default]\r
+ uint16_t msbFirst;\r
+ //! Is clock phase select.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default]\r
+ //! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT\r
+ uint16_t clockPhase;\r
+ //! Is clock polarity select\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH\r
+ //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]\r
+ uint16_t clockPolarity;\r
+ //! Is SPI mode select\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_SPI_3PIN\r
+ //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH\r
+ //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW\r
+ uint16_t spiMode;\r
+} EUSCI_A_SPI_initSlaveParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the EUSCI_A_SPI_initMaster() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct EUSCI_A_SPI_initMasterParam\r
+{\r
+ //! Selects Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_SPI_CLOCKSOURCE_ACLK\r
+ //! - \b EUSCI_A_SPI_CLOCKSOURCE_SMCLK\r
+ uint8_t selectClockSource;\r
+ //! Is the frequency of the selected clock source\r
+ uint32_t clockSourceFrequency;\r
+ //! Is the desired clock rate for SPI communication\r
+ uint32_t desiredSpiClock;\r
+ //! Controls the direction of the receive and transmit shift register.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_SPI_MSB_FIRST\r
+ //! - \b EUSCI_A_SPI_LSB_FIRST [Default]\r
+ uint16_t msbFirst;\r
+ //! Is clock phase select.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default]\r
+ //! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT\r
+ uint16_t clockPhase;\r
+ //! Is clock polarity select\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH\r
+ //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]\r
+ uint16_t clockPolarity;\r
+ //! Is SPI mode select\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_SPI_3PIN\r
+ //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH\r
+ //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW\r
+ uint16_t spiMode;\r
+} EUSCI_A_SPI_initMasterParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockPhase parameter for\r
+// functions: EUSCI_A_SPI_changeClockPhasePolarity(); the param parameter for\r
+// functions: EUSCI_A_SPI_initMaster(), and EUSCI_A_SPI_initSlave().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00\r
+#define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_SPI_initMaster(), and EUSCI_A_SPI_initSlave().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_SPI_MSB_FIRST UCMSB\r
+#define EUSCI_A_SPI_LSB_FIRST 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_SPI_initMaster(), and EUSCI_A_SPI_initSlave(); the\r
+// clockPolarity parameter for functions:\r
+// EUSCI_A_SPI_changeClockPhasePolarity().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL\r
+#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_SPI_initMaster().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK\r
+#define EUSCI_A_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_SPI_initMaster(), and EUSCI_A_SPI_initSlave().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_SPI_3PIN UCMODE_0\r
+#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1\r
+#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the select4PinFunctionality\r
+// parameter for functions: EUSCI_A_SPI_select4PinFunctionality().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00\r
+#define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: EUSCI_A_SPI_enableInterrupt(), EUSCI_A_SPI_disableInterrupt(),\r
+// EUSCI_A_SPI_getInterruptStatus(), and EUSCI_A_SPI_clearInterrupt() as well\r
+// as returned by the EUSCI_A_SPI_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_SPI_TRANSMIT_INTERRUPT UCTXIE\r
+#define EUSCI_A_SPI_RECEIVE_INTERRUPT UCRXIE\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the EUSCI_A_SPI_isBusy() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_SPI_BUSY UCBUSY\r
+#define EUSCI_A_SPI_NOT_BUSY 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the SPI Master block.\r
+//!\r
+//! Upon successful initialization of the SPI master block, this function will\r
+//! have set the bus speed for the master, but the SPI Master block still\r
+//! remains disabled and must be enabled with EUSCI_A_SPI_enable()\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI Master module.\r
+//! \param param is the pointer to struct for master initialization.\r
+//!\r
+//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and\r
+//! \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return STATUS_SUCCESS\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_initMaster(uint16_t baseAddress,\r
+ EUSCI_A_SPI_initMasterParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects 4Pin Functionality\r
+//!\r
+//! This function should be invoked only in 4-wire mode. Invoking this function\r
+//! has no effect in 3-wire mode.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//! \param select4PinFunctionality selects 4 pin functionality\r
+//! Valid values are:\r
+//! - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS\r
+//! - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE\r
+//!\r
+//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_select4PinFunctionality(uint16_t baseAddress,\r
+ uint8_t select4PinFunctionality);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the SPI Master clock. At the end of this function call,\r
+//! SPI module is left enabled.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//! \param param is the pointer to struct for master clock setting.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_changeMasterClock(uint16_t baseAddress,\r
+ EUSCI_A_SPI_changeMasterClockParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the SPI Slave block.\r
+//!\r
+//! Upon successful initialization of the SPI slave block, this function will\r
+//! have initialized the slave block, but the SPI Slave block still remains\r
+//! disabled and must be enabled with EUSCI_A_SPI_enable()\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI Slave module.\r
+//! \param param is the pointer to struct for slave initialization.\r
+//!\r
+//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b\r
+//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return STATUS_SUCCESS\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_initSlave(uint16_t baseAddress,\r
+ EUSCI_A_SPI_initSlaveParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Changes the SPI clock phase and polarity. At the end of this\r
+//! function call, SPI module is left enabled.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//! \param clockPhase is clock phase select.\r
+//! Valid values are:\r
+//! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT\r
+//! [Default]\r
+//! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT\r
+//! \param clockPolarity is clock polarity select\r
+//! Valid values are:\r
+//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH\r
+//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]\r
+//!\r
+//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0\r
+//! register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_changeClockPhasePolarity(uint16_t baseAddress,\r
+ uint16_t clockPhase,\r
+ uint16_t clockPolarity);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Transmits a byte from the SPI Module.\r
+//!\r
+//! This function will place the supplied data into SPI transmit data register\r
+//! to start transmission.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//! \param transmitData data to be transmitted from the SPI module\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_transmitData(uint16_t baseAddress,\r
+ uint8_t transmitData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Receives a byte that has been sent to the SPI Module.\r
+//!\r
+//! This function reads a byte of data from the SPI receive data Register.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//!\r
+//! \return Returns the byte received from by the SPI module, cast as an\r
+//! uint8_t.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_A_SPI_receiveData(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables individual SPI interrupt sources.\r
+//!\r
+//! Enables the indicated SPI interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor. Does not clear interrupt flags.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//! \param mask is the bit mask of the interrupt sources to be enabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT\r
+//!\r
+//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables individual SPI interrupt sources.\r
+//!\r
+//! Disables the indicated SPI interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//! \param mask is the bit mask of the interrupt sources to be disabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT\r
+//!\r
+//! Modified bits of \b UCAxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the current SPI interrupt status.\r
+//!\r
+//! This returns the interrupt status for the SPI module based on which flag is\r
+//! passed.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//! \param mask is the masked interrupt flag status to be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_A_SPI_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the selected SPI interrupt status flag.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//! \param mask is the masked interrupt flag to be cleared.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT\r
+//!\r
+//! Modified bits of \b UCAxIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the SPI block.\r
+//!\r
+//! This will enable operation of the SPI block.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_enable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the SPI block.\r
+//!\r
+//! This will disable operation of the SPI block.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_SPI_disable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the RX Buffer of the SPI for the DMA module.\r
+//!\r
+//! Returns the address of the SPI RX Buffer. This can be used in conjunction\r
+//! with the DMA to store the received data directly to memory.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//!\r
+//! \return the address of the RX Buffer\r
+//\r
+//*****************************************************************************\r
+extern uint32_t EUSCI_A_SPI_getReceiveBufferAddress(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the TX Buffer of the SPI for the DMA module.\r
+//!\r
+//! Returns the address of the SPI TX Buffer. This can be used in conjunction\r
+//! with the DMA to obtain transmitted data directly from memory.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//!\r
+//! \return the address of the TX Buffer\r
+//\r
+//*****************************************************************************\r
+extern uint32_t EUSCI_A_SPI_getTransmitBufferAddress(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Indicates whether or not the SPI bus is busy.\r
+//!\r
+//! This function returns an indication of whether or not the SPI bus is\r
+//! busy.This function checks the status of the bus via UCBBUSY bit\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b EUSCI_A_SPI_BUSY\r
+//! - \b EUSCI_A_SPI_NOT_BUSY\r
+//! \n indicating if the EUSCI_A_SPI is busy\r
+//\r
+//*****************************************************************************\r
+extern uint16_t EUSCI_A_SPI_isBusy(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_EUSCI_A_SPI_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_a_uart.c - Driver for the eusci_a_uart Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup eusci_a_uart_api eusci_a_uart\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Ax__\r
+#include "eusci_a_uart.h"\r
+\r
+#include <assert.h>\r
+\r
+bool EUSCI_A_UART_init(uint16_t baseAddress,\r
+ EUSCI_A_UART_initParam *param)\r
+{\r
+ bool retVal = STATUS_SUCCESS;\r
+\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
+\r
+ //Clock source select\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSSEL_3;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource;\r
+\r
+ //MSB, LSB select\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCMSB;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->msborLsbFirst;\r
+\r
+ //UCSPB = 0(1 stop bit) OR 1(2 stop bits)\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSPB;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->numberofStopBits;\r
+\r
+ //Parity\r
+ switch(param->parity)\r
+ {\r
+ case EUSCI_A_UART_NO_PARITY:\r
+ //No Parity\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPEN;\r
+ break;\r
+ case EUSCI_A_UART_ODD_PARITY:\r
+ //Odd Parity\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPAR;\r
+ break;\r
+ case EUSCI_A_UART_EVEN_PARITY:\r
+ //Even Parity\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPAR;\r
+ break;\r
+ }\r
+\r
+ //BaudRate Control Register\r
+ HWREG16(baseAddress + OFS_UCAxBRW) = param->clockPrescalar;\r
+ //Modulation Control Register\r
+ HWREG16(baseAddress + OFS_UCAxMCTLW) = ((param->secondModReg << 8)\r
+ + (param->firstModReg <<\r
+ 4) + param->overSampling);\r
+\r
+ //Asynchronous mode & 8 bit character select & clear mode\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSYNC +\r
+ UC7BIT +\r
+ UCMODE_3\r
+ );\r
+\r
+ //Configure UART mode.\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->uartMode;\r
+\r
+ //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCRXEIE + UCBRKIE + UCDORM +\r
+ UCTXADDR + UCTXBRK\r
+ );\r
+ return (retVal);\r
+}\r
+\r
+void EUSCI_A_UART_transmitData(uint16_t baseAddress,\r
+ uint8_t transmitData)\r
+{\r
+ //If interrupts are not used, poll for flags\r
+ if(!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE))\r
+ {\r
+ //Poll for transmit interrupt flag\r
+ while(!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG))\r
+ {\r
+ ;\r
+ }\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData;\r
+}\r
+\r
+uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress)\r
+{\r
+ //If interrupts are not used, poll for flags\r
+ if(!(HWREG16(baseAddress + OFS_UCAxIE) & UCRXIE))\r
+ {\r
+ //Poll for receive interrupt flag\r
+ while(!(HWREG16(baseAddress + OFS_UCAxIFG) & UCRXIFG))\r
+ {\r
+ ;\r
+ }\r
+ }\r
+\r
+ return (HWREG16(baseAddress + OFS_UCAxRXBUF));\r
+}\r
+\r
+void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ uint8_t locMask;\r
+\r
+ locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT\r
+ | EUSCI_A_UART_TRANSMIT_INTERRUPT\r
+ | EUSCI_A_UART_STARTBIT_INTERRUPT\r
+ | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));\r
+\r
+ HWREG16(baseAddress + OFS_UCAxIE) |= locMask;\r
+\r
+ locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
+ | EUSCI_A_UART_BREAKCHAR_INTERRUPT));\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= locMask;\r
+}\r
+\r
+void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ uint8_t locMask;\r
+\r
+ locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT\r
+ | EUSCI_A_UART_TRANSMIT_INTERRUPT\r
+ | EUSCI_A_UART_STARTBIT_INTERRUPT\r
+ | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));\r
+ HWREG16(baseAddress + OFS_UCAxIE) &= ~locMask;\r
+\r
+ locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
+ | EUSCI_A_UART_BREAKCHAR_INTERRUPT));\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~locMask;\r
+}\r
+\r
+uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCAxIFG) & mask);\r
+}\r
+\r
+void EUSCI_A_UART_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ //Clear the UART interrupt source.\r
+ HWREG16(baseAddress + OFS_UCAxIFG) &= ~(mask);\r
+}\r
+\r
+void EUSCI_A_UART_enable(uint16_t baseAddress)\r
+{\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_A_UART_disable(uint16_t baseAddress)\r
+{\r
+ //Set the UCSWRST bit to disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
+}\r
+\r
+uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCAxSTATW) & mask);\r
+}\r
+\r
+void EUSCI_A_UART_setDormant(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCDORM;\r
+}\r
+\r
+void EUSCI_A_UART_resetDormant(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCDORM;\r
+}\r
+\r
+void EUSCI_A_UART_transmitAddress(uint16_t baseAddress,\r
+ uint8_t transmitAddress)\r
+{\r
+ //Set UCTXADDR bit\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXADDR;\r
+\r
+ //Place next byte to be sent into the transmit buffer\r
+ HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitAddress;\r
+}\r
+\r
+void EUSCI_A_UART_transmitBreak(uint16_t baseAddress)\r
+{\r
+ //Set UCTXADDR bit\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXBRK;\r
+\r
+ //If current mode is automatic baud-rate detection\r
+ if(EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE ==\r
+ (HWREG16(baseAddress + OFS_UCAxCTLW0) &\r
+ EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))\r
+ {\r
+ HWREG16(baseAddress +\r
+ OFS_UCAxTXBUF) = EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;\r
+ }\r
+ else\r
+ {\r
+ HWREG16(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC;\r
+ }\r
+\r
+ //If interrupts are not used, poll for flags\r
+ if(!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE))\r
+ {\r
+ //Poll for transmit interrupt flag\r
+ while(!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG))\r
+ {\r
+ ;\r
+ }\r
+ }\r
+}\r
+\r
+uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCAxRXBUF);\r
+}\r
+\r
+uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCAxTXBUF);\r
+}\r
+\r
+void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress,\r
+ uint16_t deglitchTime)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxCTLW1) &= ~(UCGLIT1 + UCGLIT0);\r
+\r
+ HWREG16(baseAddress + OFS_UCAxCTLW1) |= deglitchTime;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for eusci_a_uart_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_a_uart.h - Driver for the EUSCI_A_UART Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_EUSCI_A_UART_H__\r
+#define __MSP430WARE_EUSCI_A_UART_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Ax__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+// The following values are the sync characters possible.\r
+//\r
+//*****************************************************************************\r
+#define DEFAULT_SYNC 0x00\r
+#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the EUSCI_A_UART_init() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct EUSCI_A_UART_initParam\r
+{\r
+ //! Selects Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_UART_CLOCKSOURCE_SMCLK\r
+ //! - \b EUSCI_A_UART_CLOCKSOURCE_ACLK\r
+ uint8_t selectClockSource;\r
+ //! Is the value to be written into UCBRx bits\r
+ uint16_t clockPrescalar;\r
+ //! Is First modulation stage register setting. This value is a pre-\r
+ //! calculated value which can be obtained from the Device Users Guide.\r
+ //! This value is written into UCBRFx bits of UCAxMCTLW.\r
+ uint8_t firstModReg;\r
+ //! Is Second modulation stage register setting. This value is a pre-\r
+ //! calculated value which can be obtained from the Device Users Guide.\r
+ //! This value is written into UCBRSx bits of UCAxMCTLW.\r
+ uint8_t secondModReg;\r
+ //! Is the desired parity.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_UART_NO_PARITY [Default]\r
+ //! - \b EUSCI_A_UART_ODD_PARITY\r
+ //! - \b EUSCI_A_UART_EVEN_PARITY\r
+ uint8_t parity;\r
+ //! Controls direction of receive and transmit shift register.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_UART_MSB_FIRST\r
+ //! - \b EUSCI_A_UART_LSB_FIRST [Default]\r
+ uint16_t msborLsbFirst;\r
+ //! Indicates one/two STOP bits\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_UART_ONE_STOP_BIT [Default]\r
+ //! - \b EUSCI_A_UART_TWO_STOP_BITS\r
+ uint16_t numberofStopBits;\r
+ //! Selects the mode of operation\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_UART_MODE [Default]\r
+ //! - \b EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE\r
+ //! - \b EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE\r
+ //! - \b EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE\r
+ uint16_t uartMode;\r
+ //! Indicates low frequency or oversampling baud generation\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION\r
+ //! - \b EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION\r
+ uint8_t overSampling;\r
+} EUSCI_A_UART_initParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_UART_init().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_NO_PARITY 0x00\r
+#define EUSCI_A_UART_ODD_PARITY 0x01\r
+#define EUSCI_A_UART_EVEN_PARITY 0x02\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_UART_init().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_MSB_FIRST UCMSB\r
+#define EUSCI_A_UART_LSB_FIRST 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_UART_init().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_MODE UCMODE_0\r
+#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1\r
+#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2\r
+#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_UART_init().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK\r
+#define EUSCI_A_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_UART_init().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_ONE_STOP_BIT 0x00\r
+#define EUSCI_A_UART_TWO_STOP_BITS UCSPB\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_A_UART_init().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01\r
+#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: EUSCI_A_UART_enableInterrupt(), and\r
+// EUSCI_A_UART_disableInterrupt().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_RECEIVE_INTERRUPT UCRXIE\r
+#define EUSCI_A_UART_TRANSMIT_INTERRUPT UCTXIE\r
+#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE\r
+#define EUSCI_A_UART_BREAKCHAR_INTERRUPT UCBRKIE\r
+#define EUSCI_A_UART_STARTBIT_INTERRUPT UCSTTIE\r
+#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT UCTXCPTIE\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: EUSCI_A_UART_getInterruptStatus(), and\r
+// EUSCI_A_UART_clearInterrupt() as well as returned by the\r
+// EUSCI_A_UART_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG\r
+#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG\r
+#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG UCSTTIFG\r
+#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG UCTXCPTIFG\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: EUSCI_A_UART_queryStatusFlags() as well as returned by the\r
+// EUSCI_A_UART_queryStatusFlags() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_LISTEN_ENABLE UCLISTEN\r
+#define EUSCI_A_UART_FRAMING_ERROR UCFE\r
+#define EUSCI_A_UART_OVERRUN_ERROR UCOE\r
+#define EUSCI_A_UART_PARITY_ERROR UCPE\r
+#define EUSCI_A_UART_BREAK_DETECT UCBRK\r
+#define EUSCI_A_UART_RECEIVE_ERROR UCRXERR\r
+#define EUSCI_A_UART_ADDRESS_RECEIVED UCADDR\r
+#define EUSCI_A_UART_IDLELINE UCIDLE\r
+#define EUSCI_A_UART_BUSY UCBUSY\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the deglitchTime parameter\r
+// for functions: EUSCI_A_UART_selectDeglitchTime().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00\r
+#define EUSCI_A_UART_DEGLITCH_TIME_50ns UCGLIT0\r
+#define EUSCI_A_UART_DEGLITCH_TIME_100ns UCGLIT1\r
+#define EUSCI_A_UART_DEGLITCH_TIME_200ns (UCGLIT0 + UCGLIT1)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Advanced initialization routine for the UART block. The values to be\r
+//! written into the clockPrescalar, firstModReg, secondModReg and overSampling\r
+//! parameters should be pre-computed and passed into the initialization\r
+//! function.\r
+//!\r
+//! Upon successful initialization of the UART block, this function will have\r
+//! initialized the module, but the UART block still remains disabled and must\r
+//! be enabled with EUSCI_A_UART_enable(). To calculate values for\r
+//! clockPrescalar, firstModReg, secondModReg and overSampling please use the\r
+//! link below.\r
+//!\r
+//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//! \param param is the pointer to struct for initialization.\r
+//!\r
+//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b\r
+//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b\r
+//! UCSWRST of \b UCAxCTL1 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process\r
+//\r
+//*****************************************************************************\r
+extern bool EUSCI_A_UART_init(uint16_t baseAddress,\r
+ EUSCI_A_UART_initParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Transmits a byte from the UART Module.\r
+//!\r
+//! This function will place the supplied data into UART transmit data register\r
+//! to start transmission\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//! \param transmitData data to be transmitted from the UART module\r
+//!\r
+//! Modified bits of \b UCAxTXBUF register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_transmitData(uint16_t baseAddress,\r
+ uint8_t transmitData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Receives a byte that has been sent to the UART Module.\r
+//!\r
+//! This function reads a byte of data from the UART receive data Register.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//!\r
+//! Modified bits of \b UCAxRXBUF register.\r
+//!\r
+//! \return Returns the byte received from by the UART module, cast as an\r
+//! uint8_t.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables individual UART interrupt sources.\r
+//!\r
+//! Enables the indicated UART interrupt sources. The interrupt flag is first\r
+//! and then the corresponding interrupt is enabled. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor. Does not clear interrupt flags.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//! \param mask is the bit mask of the interrupt sources to be enabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt\r
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt\r
+//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive\r
+//! erroneous-character interrupt enable\r
+//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character\r
+//! interrupt enable\r
+//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT - Start bit received interrupt\r
+//! enable\r
+//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete\r
+//! interrupt enable\r
+//!\r
+//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables individual UART interrupt sources.\r
+//!\r
+//! Disables the indicated UART interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//! \param mask is the bit mask of the interrupt sources to be disabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt\r
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt\r
+//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive\r
+//! erroneous-character interrupt enable\r
+//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character\r
+//! interrupt enable\r
+//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT - Start bit received interrupt\r
+//! enable\r
+//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete\r
+//! interrupt enable\r
+//!\r
+//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the current UART interrupt status.\r
+//!\r
+//! This returns the interrupt status for the UART module based on which flag\r
+//! is passed.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//! \param mask is the masked interrupt flag status to be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG\r
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG\r
+//!\r
+//! Modified bits of \b UCAxIFG register.\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG\r
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG\r
+//! \n indicating the status of the masked flags\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears UART interrupt sources.\r
+//!\r
+//! The UART interrupt source is cleared, so that it no longer asserts. The\r
+//! highest interrupt flag is automatically cleared when an interrupt vector\r
+//! generator is used.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//! \param mask is a bit mask of the interrupt sources to be cleared.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG\r
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG\r
+//!\r
+//! Modified bits of \b UCAxIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the UART block.\r
+//!\r
+//! This will enable operation of the UART block.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_enable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the UART block.\r
+//!\r
+//! This will disable operation of the UART block.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_disable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the current UART status flags.\r
+//!\r
+//! This returns the status for the UART module based on which flag is passed.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//! \param mask is the masked interrupt flag status to be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_A_UART_LISTEN_ENABLE\r
+//! - \b EUSCI_A_UART_FRAMING_ERROR\r
+//! - \b EUSCI_A_UART_OVERRUN_ERROR\r
+//! - \b EUSCI_A_UART_PARITY_ERROR\r
+//! - \b EUSCI_A_UART_BREAK_DETECT\r
+//! - \b EUSCI_A_UART_RECEIVE_ERROR\r
+//! - \b EUSCI_A_UART_ADDRESS_RECEIVED\r
+//! - \b EUSCI_A_UART_IDLELINE\r
+//! - \b EUSCI_A_UART_BUSY\r
+//!\r
+//! Modified bits of \b UCAxSTAT register.\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b EUSCI_A_UART_LISTEN_ENABLE\r
+//! - \b EUSCI_A_UART_FRAMING_ERROR\r
+//! - \b EUSCI_A_UART_OVERRUN_ERROR\r
+//! - \b EUSCI_A_UART_PARITY_ERROR\r
+//! - \b EUSCI_A_UART_BREAK_DETECT\r
+//! - \b EUSCI_A_UART_RECEIVE_ERROR\r
+//! - \b EUSCI_A_UART_ADDRESS_RECEIVED\r
+//! - \b EUSCI_A_UART_IDLELINE\r
+//! - \b EUSCI_A_UART_BUSY\r
+//! \n indicating the status of the masked interrupt flags\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the UART module in dormant mode\r
+//!\r
+//! Puts USCI in sleep mode Only characters that are preceded by an idle-line\r
+//! or with address bit set UCRXIFG. In UART mode with automatic baud-rate\r
+//! detection, only the combination of a break and sync field sets UCRXIFG.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//!\r
+//! Modified bits of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_setDormant(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Re-enables UART module from dormant mode\r
+//!\r
+//! Not dormant. All received characters set UCRXIFG.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//!\r
+//! Modified bits are \b UCDORM of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_resetDormant(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Transmits the next byte to be transmitted marked as address\r
+//! depending on selected multiprocessor mode\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//! \param transmitAddress is the next byte to be transmitted\r
+//!\r
+//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_transmitAddress(uint16_t baseAddress,\r
+ uint8_t transmitAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Transmit break.\r
+//!\r
+//! Transmits a break with the next write to the transmit buffer. In UART mode\r
+//! with automatic baud-rate detection,\r
+//! EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to\r
+//! generate the required break/sync fields. Otherwise, DEFAULT_SYNC(0x00) must\r
+//! be written into the transmit buffer. Also ensures module is ready for\r
+//! transmitting the next data.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//!\r
+//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_transmitBreak(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the RX Buffer of the UART for the DMA module.\r
+//!\r
+//! Returns the address of the UART RX Buffer. This can be used in conjunction\r
+//! with the DMA to store the received data directly to memory.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//!\r
+//! \return Address of RX Buffer\r
+//\r
+//*****************************************************************************\r
+extern uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the TX Buffer of the UART for the DMA module.\r
+//!\r
+//! Returns the address of the UART TX Buffer. This can be used in conjunction\r
+//! with the DMA to obtain transmitted data directly from memory.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//!\r
+//! \return Address of TX Buffer\r
+//\r
+//*****************************************************************************\r
+extern uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the deglitch time\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_A_UART module.\r
+//! \param deglitchTime is the selected deglitch time\r
+//! Valid values are:\r
+//! - \b EUSCI_A_UART_DEGLITCH_TIME_2ns\r
+//! - \b EUSCI_A_UART_DEGLITCH_TIME_50ns\r
+//! - \b EUSCI_A_UART_DEGLITCH_TIME_100ns\r
+//! - \b EUSCI_A_UART_DEGLITCH_TIME_200ns\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress,\r
+ uint16_t deglitchTime);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_EUSCI_A_UART_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_b_i2c.c - Driver for the eusci_b_i2c Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup eusci_b_i2c_api eusci_b_i2c\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Bx__\r
+#include "eusci_b_i2c.h"\r
+\r
+#include <assert.h>\r
+\r
+void EUSCI_B_I2C_initMaster(uint16_t baseAddress,\r
+ EUSCI_B_I2C_initMasterParam *param)\r
+{\r
+ uint16_t preScalarValue;\r
+\r
+ //Disable the USCI module and clears the other bits of control register\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) = UCSWRST;\r
+\r
+ //Configure Automatic STOP condition generation\r
+ HWREG16(baseAddress + OFS_UCBxCTLW1) &= ~UCASTP_3;\r
+ HWREG16(baseAddress + OFS_UCBxCTLW1) |= param->autoSTOPGeneration;\r
+\r
+ //Byte Count Threshold\r
+ HWREG16(baseAddress + OFS_UCBxTBCNT) = param->byteCounterThreshold;\r
+ /*\r
+ * Configure as I2C master mode.\r
+ * UCMST = Master mode\r
+ * UCMODE_3 = I2C mode\r
+ * UCSYNC = Synchronous mode\r
+ */\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMST + UCMODE_3 + UCSYNC;\r
+\r
+ //Configure I2C clock source\r
+ HWREG16(baseAddress +\r
+ OFS_UCBxCTLW0) |= (param->selectClockSource + UCSWRST);\r
+\r
+ /*\r
+ * Compute the clock divider that achieves the fastest speed less than or\r
+ * equal to the desired speed. The numerator is biased to favor a larger\r
+ * clock divider so that the resulting clock is always less than or equal\r
+ * to the desired clock, never greater.\r
+ */\r
+ preScalarValue = (uint16_t)(param->i2cClk / param->dataRate);\r
+ HWREG16(baseAddress + OFS_UCBxBRW) = preScalarValue;\r
+}\r
+\r
+void EUSCI_B_I2C_initSlave(uint16_t baseAddress,\r
+ EUSCI_B_I2C_initSlaveParam *param)\r
+{\r
+ //Disable the USCI module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+\r
+ //Clear USCI master mode\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCMST;\r
+\r
+ //Configure I2C as Slave and Synchronous mode\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMODE_3 + UCSYNC;\r
+\r
+ //Set up the slave address.\r
+ HWREG16(baseAddress + OFS_UCBxI2COA0 + param->slaveAddressOffset)\r
+ = param->slaveAddress + param->slaveOwnAddressEnable;\r
+}\r
+\r
+void EUSCI_B_I2C_enable(uint16_t baseAddress)\r
+{\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_B_I2C_disable(uint16_t baseAddress)\r
+{\r
+ //Set the UCSWRST bit to disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+}\r
+\r
+void EUSCI_B_I2C_setSlaveAddress(uint16_t baseAddress,\r
+ uint8_t slaveAddress)\r
+{\r
+ //Set the address of the slave with which the master will communicate.\r
+ HWREG16(baseAddress + OFS_UCBxI2CSA) = (slaveAddress);\r
+}\r
+\r
+void EUSCI_B_I2C_setMode(uint16_t baseAddress,\r
+ uint8_t mode)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~EUSCI_B_I2C_TRANSMIT_MODE;\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= mode;\r
+}\r
+\r
+uint8_t EUSCI_B_I2C_getMode(uint16_t baseAddress)\r
+{\r
+ //Read the I2C mode.\r
+ return ((HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTR));\r
+}\r
+\r
+void EUSCI_B_I2C_slavePutData(uint16_t baseAddress,\r
+ uint8_t transmitData)\r
+{\r
+ //Send single byte data.\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData;\r
+}\r
+\r
+uint8_t EUSCI_B_I2C_slaveGetData(uint16_t baseAddress)\r
+{\r
+ //Read a byte.\r
+ return (HWREG16(baseAddress + OFS_UCBxRXBUF));\r
+}\r
+\r
+uint16_t EUSCI_B_I2C_isBusBusy(uint16_t baseAddress)\r
+{\r
+ //Return the bus busy status.\r
+ return (HWREG16(baseAddress + OFS_UCBxSTATW) & UCBBUSY);\r
+}\r
+\r
+uint16_t EUSCI_B_I2C_masterIsStopSent(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP);\r
+}\r
+\r
+uint16_t EUSCI_B_I2C_masterIsStartSent(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTT);\r
+}\r
+\r
+void EUSCI_B_I2C_enableInterrupt(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ //Enable the interrupt masked bit\r
+ HWREG16(baseAddress + OFS_UCBxIE) |= mask;\r
+}\r
+\r
+void EUSCI_B_I2C_disableInterrupt(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ //Disable the interrupt masked bit\r
+ HWREG16(baseAddress + OFS_UCBxIE) &= ~(mask);\r
+}\r
+\r
+void EUSCI_B_I2C_clearInterrupt(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ //Clear the I2C interrupt source.\r
+ HWREG16(baseAddress + OFS_UCBxIFG) &= ~(mask);\r
+}\r
+\r
+uint16_t EUSCI_B_I2C_getInterruptStatus(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ //Return the interrupt status of the request masked bit.\r
+ return (HWREG16(baseAddress + OFS_UCBxIFG) & mask);\r
+}\r
+\r
+void EUSCI_B_I2C_masterSendSingleByte(uint16_t baseAddress,\r
+ uint8_t txData)\r
+{\r
+ //Store current TXIE status\r
+ uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE;\r
+\r
+ //Disable transmit interrupt enable\r
+ HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE);\r
+\r
+ //Send start condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT;\r
+\r
+ //Poll for transmit interrupt flag.\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG))\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Send single byte data.\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = txData;\r
+\r
+ //Poll for transmit interrupt flag.\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG))\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Send stop condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP;\r
+\r
+ //Clear transmit interrupt flag before enabling interrupt again\r
+ HWREG16(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG);\r
+\r
+ //Reinstate transmit interrupt enable\r
+ HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus;\r
+}\r
+\r
+uint8_t EUSCI_B_I2C_masterReceiveSingleByte(uint16_t baseAddress)\r
+{\r
+ //Set USCI in Receive mode\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCTR;\r
+\r
+ //Send start\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= (UCTXSTT + UCTXSTP);\r
+\r
+ //Poll for receive interrupt flag.\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG))\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Send single byte data.\r
+ return (HWREG16(baseAddress + OFS_UCBxRXBUF));\r
+}\r
+\r
+bool EUSCI_B_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress,\r
+ uint8_t txData,\r
+ uint32_t timeout)\r
+{\r
+ // Creating variable for second timeout scenario\r
+ uint32_t timeout2 = timeout;\r
+\r
+ //Store current TXIE status\r
+ uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE;\r
+\r
+ //Disable transmit interrupt enable\r
+ HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE);\r
+\r
+ //Send start condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT;\r
+\r
+ //Poll for transmit interrupt flag.\r
+ while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout)\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Check if transfer timed out\r
+ if(timeout == 0)\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+\r
+ //Send single byte data.\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = txData;\r
+\r
+ //Poll for transmit interrupt flag.\r
+ while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2)\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Check if transfer timed out\r
+ if(timeout2 == 0)\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+\r
+ //Send stop condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP;\r
+\r
+ //Clear transmit interrupt flag before enabling interrupt again\r
+ HWREG16(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG);\r
+\r
+ //Reinstate transmit interrupt enable\r
+ HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus;\r
+\r
+ return (STATUS_SUCCESS);\r
+}\r
+\r
+void EUSCI_B_I2C_masterSendMultiByteStart(uint16_t baseAddress,\r
+ uint8_t txData)\r
+{\r
+ //Store current transmit interrupt enable\r
+ uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE;\r
+\r
+ //Disable transmit interrupt enable\r
+ HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE);\r
+\r
+ //Send start condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT;\r
+\r
+ //Poll for transmit interrupt flag.\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG))\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Send single byte data.\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = txData;\r
+\r
+ //Reinstate transmit interrupt enable\r
+ HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus;\r
+}\r
+\r
+bool EUSCI_B_I2C_masterSendMultiByteStartWithTimeout(uint16_t baseAddress,\r
+ uint8_t txData,\r
+ uint32_t timeout)\r
+{\r
+ //Store current transmit interrupt enable\r
+ uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE;\r
+\r
+ //Disable transmit interrupt enable\r
+ HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE);\r
+\r
+ //Send start condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT;\r
+\r
+ //Poll for transmit interrupt flag.\r
+ while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout)\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Check if transfer timed out\r
+ if(timeout == 0)\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+\r
+ //Send single byte data.\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = txData;\r
+\r
+ //Reinstate transmit interrupt enable\r
+ HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus;\r
+\r
+ return(STATUS_SUCCESS);\r
+}\r
+\r
+void EUSCI_B_I2C_masterSendMultiByteNext(uint16_t baseAddress,\r
+ uint8_t txData)\r
+{\r
+ //If interrupts are not used, poll for flags\r
+ if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE))\r
+ {\r
+ //Poll for transmit interrupt flag.\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG))\r
+ {\r
+ ;\r
+ }\r
+ }\r
+\r
+ //Send single byte data.\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = txData;\r
+}\r
+\r
+bool EUSCI_B_I2C_masterSendMultiByteNextWithTimeout(uint16_t baseAddress,\r
+ uint8_t txData,\r
+ uint32_t timeout)\r
+{\r
+ //If interrupts are not used, poll for flags\r
+ if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE))\r
+ {\r
+ //Poll for transmit interrupt flag.\r
+ while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout)\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Check if transfer timed out\r
+ if(timeout == 0)\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+ }\r
+\r
+ //Send single byte data.\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = txData;\r
+\r
+ return(STATUS_SUCCESS);\r
+}\r
+\r
+void EUSCI_B_I2C_masterSendMultiByteFinish(uint16_t baseAddress,\r
+ uint8_t txData)\r
+{\r
+ //If interrupts are not used, poll for flags\r
+ if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE))\r
+ {\r
+ //Poll for transmit interrupt flag.\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG))\r
+ {\r
+ ;\r
+ }\r
+ }\r
+\r
+ //Send single byte data.\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = txData;\r
+\r
+ //Poll for transmit interrupt flag.\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG))\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Send stop condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP;\r
+}\r
+\r
+bool EUSCI_B_I2C_masterSendMultiByteFinishWithTimeout(uint16_t baseAddress,\r
+ uint8_t txData,\r
+ uint32_t timeout)\r
+{\r
+ uint32_t timeout2 = timeout;\r
+\r
+ //If interrupts are not used, poll for flags\r
+ if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE))\r
+ {\r
+ //Poll for transmit interrupt flag.\r
+ while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout)\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Check if transfer timed out\r
+ if(timeout == 0)\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+ }\r
+\r
+ //Send single byte data.\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = txData;\r
+\r
+ //Poll for transmit interrupt flag.\r
+ while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2)\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Check if transfer timed out\r
+ if(timeout2 == 0)\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+\r
+ //Send stop condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP;\r
+\r
+ return(STATUS_SUCCESS);\r
+}\r
+\r
+void EUSCI_B_I2C_masterSendStart(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTT;\r
+}\r
+\r
+void EUSCI_B_I2C_masterSendMultiByteStop(uint16_t baseAddress)\r
+{\r
+ //If interrupts are not used, poll for flags\r
+ if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE))\r
+ {\r
+ //Poll for transmit interrupt flag.\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG))\r
+ {\r
+ ;\r
+ }\r
+ }\r
+\r
+ //Send stop condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP;\r
+}\r
+\r
+bool EUSCI_B_I2C_masterSendMultiByteStopWithTimeout(uint16_t baseAddress,\r
+ uint32_t timeout)\r
+{\r
+ //If interrupts are not used, poll for flags\r
+ if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE))\r
+ {\r
+ //Poll for transmit interrupt flag.\r
+ while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout)\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Check if transfer timed out\r
+ if(timeout == 0)\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+ }\r
+\r
+ //Send stop condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP;\r
+\r
+ return (STATUS_SUCCESS);\r
+}\r
+\r
+void EUSCI_B_I2C_masterReceiveStart(uint16_t baseAddress)\r
+{\r
+ //Set USCI in Receive mode\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCTR;\r
+ //Send start\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTT;\r
+}\r
+\r
+uint8_t EUSCI_B_I2C_masterReceiveMultiByteNext(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCBxRXBUF));\r
+}\r
+\r
+uint8_t EUSCI_B_I2C_masterReceiveMultiByteFinish(uint16_t baseAddress)\r
+{\r
+ //Send stop condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP;\r
+\r
+ //Wait for Stop to finish\r
+ while(HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP)\r
+ {\r
+ // Wait for RX buffer\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG))\r
+ {\r
+ ;\r
+ }\r
+ }\r
+\r
+ //Capture data from receive buffer after setting stop bit due to\r
+ //MSP430 I2C critical timing.\r
+ return (HWREG16(baseAddress + OFS_UCBxRXBUF));\r
+}\r
+\r
+bool EUSCI_B_I2C_masterReceiveMultiByteFinishWithTimeout(uint16_t baseAddress,\r
+ uint8_t *txData,\r
+ uint32_t timeout)\r
+{\r
+ uint32_t timeout2 = timeout;\r
+\r
+ //Send stop condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP;\r
+\r
+ //Wait for Stop to finish\r
+ while((HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP) && --timeout)\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Check if transfer timed out\r
+ if(timeout == 0)\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+\r
+ // Wait for RX buffer\r
+ while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) && --timeout2)\r
+ {\r
+ ;\r
+ }\r
+\r
+ //Check if transfer timed out\r
+ if(timeout2 == 0)\r
+ {\r
+ return (STATUS_FAIL);\r
+ }\r
+\r
+ //Capture data from receive buffer after setting stop bit due to\r
+ //MSP430 I2C critical timing.\r
+ *txData = (HWREG8(baseAddress + OFS_UCBxRXBUF));\r
+\r
+ return (STATUS_SUCCESS);\r
+}\r
+\r
+void EUSCI_B_I2C_masterReceiveMultiByteStop(uint16_t baseAddress)\r
+{\r
+ //Send stop condition.\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP;\r
+}\r
+\r
+void EUSCI_B_I2C_enableMultiMasterMode(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMM;\r
+}\r
+\r
+void EUSCI_B_I2C_disableMultiMasterMode(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCMM;\r
+}\r
+\r
+uint8_t EUSCI_B_I2C_masterReceiveSingle(uint16_t baseAddress)\r
+{\r
+ //Polling RXIFG0 if RXIE is not enabled\r
+ if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCRXIE0))\r
+ {\r
+ while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG0))\r
+ {\r
+ ;\r
+ }\r
+ }\r
+\r
+ //Read a byte.\r
+ return (HWREG16(baseAddress + OFS_UCBxRXBUF));\r
+}\r
+\r
+uint32_t EUSCI_B_I2C_getReceiveBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCBxRXBUF);\r
+}\r
+\r
+uint32_t EUSCI_B_I2C_getTransmitBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCBxTXBUF);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for eusci_b_i2c_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_b_i2c.h - Driver for the EUSCI_B_I2C Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_EUSCI_B_I2C_H__\r
+#define __MSP430WARE_EUSCI_B_I2C_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Bx__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the EUSCI_B_I2C_initMaster() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct EUSCI_B_I2C_initMasterParam\r
+{\r
+ //! Is the clocksource.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_I2C_CLOCKSOURCE_ACLK\r
+ //! - \b EUSCI_B_I2C_CLOCKSOURCE_SMCLK\r
+ uint8_t selectClockSource;\r
+ //! Is the rate of the clock supplied to the I2C module (the frequency in\r
+ //! Hz of the clock source specified in selectClockSource).\r
+ uint32_t i2cClk;\r
+ //! Setup for selecting data transfer rate.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_I2C_SET_DATA_RATE_400KBPS\r
+ //! - \b EUSCI_B_I2C_SET_DATA_RATE_100KBPS\r
+ uint32_t dataRate;\r
+ //! Sets threshold for automatic STOP or UCSTPIFG\r
+ uint8_t byteCounterThreshold;\r
+ //! Sets up the STOP condition generation.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_I2C_NO_AUTO_STOP\r
+ //! - \b EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG\r
+ //! - \b EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD\r
+ uint8_t autoSTOPGeneration;\r
+} EUSCI_B_I2C_initMasterParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the EUSCI_B_I2C_initSlave() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct EUSCI_B_I2C_initSlaveParam\r
+{\r
+ //! 7-bit slave address\r
+ uint8_t slaveAddress;\r
+ //! Own address Offset referred to- 'x' value of UCBxI2COAx.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET0\r
+ //! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET1\r
+ //! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET2\r
+ //! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET3\r
+ uint8_t slaveAddressOffset;\r
+ //! Selects if the specified address is enabled or disabled.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_I2C_OWN_ADDRESS_DISABLE\r
+ //! - \b EUSCI_B_I2C_OWN_ADDRESS_ENABLE\r
+ uint32_t slaveOwnAddressEnable;\r
+} EUSCI_B_I2C_initSlaveParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_B_I2C_initMaster().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_NO_AUTO_STOP UCASTP_0\r
+#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG UCASTP_1\r
+#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD UCASTP_2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_B_I2C_initMaster().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_SET_DATA_RATE_400KBPS 400000\r
+#define EUSCI_B_I2C_SET_DATA_RATE_100KBPS 100000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_B_I2C_initMaster().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_CLOCKSOURCE_ACLK UCSSEL__ACLK\r
+#define EUSCI_B_I2C_CLOCKSOURCE_SMCLK UCSSEL__SMCLK\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_B_I2C_initSlave().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 0x00\r
+#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 0x02\r
+#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 0x04\r
+#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 0x06\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_B_I2C_initSlave().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_OWN_ADDRESS_DISABLE 0x00\r
+#define EUSCI_B_I2C_OWN_ADDRESS_ENABLE UCOAEN\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mode parameter for\r
+// functions: EUSCI_B_I2C_setMode() as well as returned by the\r
+// EUSCI_B_I2C_getMode() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_TRANSMIT_MODE UCTR\r
+#define EUSCI_B_I2C_RECEIVE_MODE 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: EUSCI_B_I2C_enableInterrupt(), EUSCI_B_I2C_disableInterrupt(),\r
+// EUSCI_B_I2C_clearInterrupt(), and EUSCI_B_I2C_getInterruptStatus() as well\r
+// as returned by the EUSCI_B_I2C_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_NAK_INTERRUPT UCNACKIE\r
+#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT UCALIE\r
+#define EUSCI_B_I2C_STOP_INTERRUPT UCSTPIE\r
+#define EUSCI_B_I2C_START_INTERRUPT UCSTTIE\r
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT0 UCTXIE0\r
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT1 UCTXIE1\r
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT2 UCTXIE2\r
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT3 UCTXIE3\r
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT0 UCRXIE0\r
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT1 UCRXIE1\r
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT2 UCRXIE2\r
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT3 UCRXIE3\r
+#define EUSCI_B_I2C_BIT9_POSITION_INTERRUPT UCBIT9IE\r
+#define EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT UCCLTOIE\r
+#define EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT UCBCNTIE\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the EUSCI_B_I2C_isBusBusy() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_BUS_BUSY UCBBUSY\r
+#define EUSCI_B_I2C_BUS_NOT_BUSY 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the EUSCI_B_I2C_masterIsStopSent() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_STOP_SEND_COMPLETE 0x00\r
+#define EUSCI_B_I2C_SENDING_STOP UCTXSTP\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the EUSCI_B_I2C_masterIsStartSent() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_I2C_START_SEND_COMPLETE 0x00\r
+#define EUSCI_B_I2C_SENDING_START UCTXSTT\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the I2C Master block.\r
+//!\r
+//! This function initializes operation of the I2C Master block. Upon\r
+//! successful initialization of the I2C block, this function will have set the\r
+//! bus speed for the master; however I2C module is still disabled till\r
+//! EUSCI_B_I2C_enable is invoked.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param param is the pointer to the struct for master initialization.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_initMaster(uint16_t baseAddress,\r
+ EUSCI_B_I2C_initMasterParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the I2C Slave block.\r
+//!\r
+//! This function initializes operation of the I2C as a Slave mode. Upon\r
+//! successful initialization of the I2C blocks, this function will have set\r
+//! the slave address but the I2C module is still disabled till\r
+//! EUSCI_B_I2C_enable is invoked.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Slave module.\r
+//! \param param is the pointer to the struct for slave initialization.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_initSlave(uint16_t baseAddress,\r
+ EUSCI_B_I2C_initSlaveParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the I2C block.\r
+//!\r
+//! This will enable operation of the I2C block.\r
+//!\r
+//! \param baseAddress is the base address of the USCI I2C module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_enable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the I2C block.\r
+//!\r
+//! This will disable operation of the I2C block.\r
+//!\r
+//! \param baseAddress is the base address of the USCI I2C module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_disable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the address that the I2C Master will place on the bus.\r
+//!\r
+//! This function will set the address that the I2C Master will place on the\r
+//! bus when initiating a transaction.\r
+//!\r
+//! \param baseAddress is the base address of the USCI I2C module.\r
+//! \param slaveAddress 7-bit slave address\r
+//!\r
+//! Modified bits of \b UCBxI2CSA register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_setSlaveAddress(uint16_t baseAddress,\r
+ uint8_t slaveAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the mode of the I2C device\r
+//!\r
+//! When the receive parameter is set to EUSCI_B_I2C_TRANSMIT_MODE, the address\r
+//! will indicate that the I2C module is in receive mode; otherwise, the I2C\r
+//! module is in send mode.\r
+//!\r
+//! \param baseAddress is the base address of the USCI I2C module.\r
+//! \param mode Mode for the EUSCI_B_I2C module\r
+//! Valid values are:\r
+//! - \b EUSCI_B_I2C_TRANSMIT_MODE [Default]\r
+//! - \b EUSCI_B_I2C_RECEIVE_MODE\r
+//!\r
+//! Modified bits are \b UCTR of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_setMode(uint16_t baseAddress,\r
+ uint8_t mode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the mode of the I2C device\r
+//!\r
+//! Current I2C transmit/receive mode.\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//!\r
+//! Modified bits are \b UCTR of \b UCBxCTLW0 register.\r
+//!\r
+//! \return One of the following:\r
+//! - \b EUSCI_B_I2C_TRANSMIT_MODE\r
+//! - \b EUSCI_B_I2C_RECEIVE_MODE\r
+//! \n indicating the current mode\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_B_I2C_getMode(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Transmits a byte from the I2C Module.\r
+//!\r
+//! This function will place the supplied data into I2C transmit data register\r
+//! to start transmission.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Slave module.\r
+//! \param transmitData data to be transmitted from the I2C module\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_slavePutData(uint16_t baseAddress,\r
+ uint8_t transmitData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Receives a byte that has been sent to the I2C Module.\r
+//!\r
+//! This function reads a byte of data from the I2C receive data Register.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Slave module.\r
+//!\r
+//! \return Returns the byte received from by the I2C module, cast as an\r
+//! uint8_t.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_B_I2C_slaveGetData(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Indicates whether or not the I2C bus is busy.\r
+//!\r
+//! This function returns an indication of whether or not the I2C bus is busy.\r
+//! This function checks the status of the bus via UCBBUSY bit in UCBxSTAT\r
+//! register.\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b EUSCI_B_I2C_BUS_BUSY\r
+//! - \b EUSCI_B_I2C_BUS_NOT_BUSY\r
+//! \n indicating whether the bus is busy\r
+//\r
+//*****************************************************************************\r
+extern uint16_t EUSCI_B_I2C_isBusBusy(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Indicates whether STOP got sent.\r
+//!\r
+//! This function returns an indication of whether or not STOP got sent This\r
+//! function checks the status of the bus via UCTXSTP bit in UCBxCTL1 register.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b EUSCI_B_I2C_STOP_SEND_COMPLETE\r
+//! - \b EUSCI_B_I2C_SENDING_STOP\r
+//! \n indicating whether the stop was sent\r
+//\r
+//*****************************************************************************\r
+extern uint16_t EUSCI_B_I2C_masterIsStopSent(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Indicates whether Start got sent.\r
+//!\r
+//! This function returns an indication of whether or not Start got sent This\r
+//! function checks the status of the bus via UCTXSTT bit in UCBxCTL1 register.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b EUSCI_B_I2C_START_SEND_COMPLETE\r
+//! - \b EUSCI_B_I2C_SENDING_START\r
+//! \n indicating whether the start was sent\r
+//\r
+//*****************************************************************************\r
+extern uint16_t EUSCI_B_I2C_masterIsStartSent(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables individual I2C interrupt sources.\r
+//!\r
+//! Enables the indicated I2C interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//! \param mask is the bit mask of the interrupt sources to be enabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt\r
+//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost\r
+//! interrupt\r
+//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt\r
+//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3\r
+//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt\r
+//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout\r
+//! interrupt enable\r
+//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt\r
+//! enable\r
+//!\r
+//! Modified bits of \b UCBxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_enableInterrupt(uint16_t baseAddress,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables individual I2C interrupt sources.\r
+//!\r
+//! Disables the indicated I2C interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//! \param mask is the bit mask of the interrupt sources to be disabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt\r
+//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost\r
+//! interrupt\r
+//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt\r
+//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3\r
+//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt\r
+//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout\r
+//! interrupt enable\r
+//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt\r
+//! enable\r
+//!\r
+//! Modified bits of \b UCBxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_disableInterrupt(uint16_t baseAddress,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears I2C interrupt sources.\r
+//!\r
+//! The I2C interrupt source is cleared, so that it no longer asserts. The\r
+//! highest interrupt flag is automatically cleared when an interrupt vector\r
+//! generator is used.\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//! \param mask is a bit mask of the interrupt sources to be cleared.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt\r
+//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost\r
+//! interrupt\r
+//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt\r
+//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3\r
+//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt\r
+//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout\r
+//! interrupt enable\r
+//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt\r
+//! enable\r
+//!\r
+//! Modified bits of \b UCBxIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_clearInterrupt(uint16_t baseAddress,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the current I2C interrupt status.\r
+//!\r
+//! This returns the interrupt status for the I2C module based on which flag is\r
+//! passed.\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//! \param mask is the masked interrupt flag status to be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt\r
+//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost\r
+//! interrupt\r
+//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt\r
+//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3\r
+//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt\r
+//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout\r
+//! interrupt enable\r
+//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt\r
+//! enable\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b EUSCI_B_I2C_NAK_INTERRUPT Not-acknowledge interrupt\r
+//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT Arbitration lost\r
+//! interrupt\r
+//! - \b EUSCI_B_I2C_STOP_INTERRUPT STOP condition interrupt\r
+//! - \b EUSCI_B_I2C_START_INTERRUPT START condition interrupt\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 Transmit interrupt0\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 Transmit interrupt1\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 Transmit interrupt2\r
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 Transmit interrupt3\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 Receive interrupt0\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 Receive interrupt1\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 Receive interrupt2\r
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 Receive interrupt3\r
+//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT Bit position 9 interrupt\r
+//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT Clock low timeout\r
+//! interrupt enable\r
+//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT Byte counter interrupt\r
+//! enable\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint16_t EUSCI_B_I2C_getInterruptStatus(uint16_t baseAddress,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Does single byte transmission from Master to Slave\r
+//!\r
+//! This function is used by the Master module to send a single byte. This\r
+//! function sends a start, then transmits the byte to the slave and then sends\r
+//! a stop.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param txData is the data byte to be transmitted\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits\r
+//! of \b UCBxIE register and bits of \b UCBxIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_masterSendSingleByte(uint16_t baseAddress,\r
+ uint8_t txData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Does single byte reception from Slave\r
+//!\r
+//! This function is used by the Master module to receive a single byte. This\r
+//! function sends start and stop, waits for data reception and then receives\r
+//! the data from the slave\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits\r
+//! of \b UCBxIE register and bits of \b UCBxIFG register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_B_I2C_masterReceiveSingleByte(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Does single byte transmission from Master to Slave with timeout\r
+//!\r
+//! This function is used by the Master module to send a single byte. This\r
+//! function sends a start, then transmits the byte to the slave and then sends\r
+//! a stop.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param txData is the data byte to be transmitted\r
+//! \param timeout is the amount of time to wait until giving up\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits\r
+//! of \b UCBxIE register and bits of \b UCBxIFG register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process.\r
+//\r
+//*****************************************************************************\r
+extern bool EUSCI_B_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress,\r
+ uint8_t txData,\r
+ uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts multi-byte transmission from Master to Slave\r
+//!\r
+//! This function is used by the master module to start a multi byte\r
+//! transaction.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param txData is the first data byte to be transmitted\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits\r
+//! of \b UCBxIE register and bits of \b UCBxIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_masterSendMultiByteStart(uint16_t baseAddress,\r
+ uint8_t txData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts multi-byte transmission from Master to Slave with timeout\r
+//!\r
+//! This function is used by the master module to start a multi byte\r
+//! transaction.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param txData is the first data byte to be transmitted\r
+//! \param timeout is the amount of time to wait until giving up\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits\r
+//! of \b UCBxIE register and bits of \b UCBxIFG register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process.\r
+//\r
+//*****************************************************************************\r
+extern bool EUSCI_B_I2C_masterSendMultiByteStartWithTimeout(\r
+ uint16_t baseAddress,\r
+ uint8_t txData,\r
+ uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Continues multi-byte transmission from Master to Slave\r
+//!\r
+//! This function is used by the Master module continue each byte of a multi-\r
+//! byte transmission. This function transmits each data byte of a multi-byte\r
+//! transmission to the slave.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param txData is the next data byte to be transmitted\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_masterSendMultiByteNext(uint16_t baseAddress,\r
+ uint8_t txData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Continues multi-byte transmission from Master to Slave with timeout\r
+//!\r
+//! This function is used by the Master module continue each byte of a multi-\r
+//! byte transmission. This function transmits each data byte of a multi-byte\r
+//! transmission to the slave.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param txData is the next data byte to be transmitted\r
+//! \param timeout is the amount of time to wait until giving up\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process.\r
+//\r
+//*****************************************************************************\r
+extern bool EUSCI_B_I2C_masterSendMultiByteNextWithTimeout(uint16_t baseAddress,\r
+ uint8_t txData,\r
+ uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Finishes multi-byte transmission from Master to Slave\r
+//!\r
+//! This function is used by the Master module to send the last byte and STOP.\r
+//! This function transmits the last data byte of a multi-byte transmission to\r
+//! the slave and then sends a stop.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param txData is the last data byte to be transmitted in a multi-byte\r
+//! transmission\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_masterSendMultiByteFinish(uint16_t baseAddress,\r
+ uint8_t txData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Finishes multi-byte transmission from Master to Slave with timeout\r
+//!\r
+//! This function is used by the Master module to send the last byte and STOP.\r
+//! This function transmits the last data byte of a multi-byte transmission to\r
+//! the slave and then sends a stop.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param txData is the last data byte to be transmitted in a multi-byte\r
+//! transmission\r
+//! \param timeout is the amount of time to wait until giving up\r
+//!\r
+//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTLW0 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process.\r
+//\r
+//*****************************************************************************\r
+extern bool EUSCI_B_I2C_masterSendMultiByteFinishWithTimeout(\r
+ uint16_t baseAddress,\r
+ uint8_t txData,\r
+ uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function is used by the Master module to initiate START\r
+//!\r
+//! This function is used by the Master module to initiate START\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! Modified bits are \b UCTXSTT of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_masterSendStart(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Send STOP byte at the end of a multi-byte transmission from Master\r
+//! to Slave\r
+//!\r
+//! This function is used by the Master module send STOP at the end of a multi-\r
+//! byte transmission. This function sends a stop after current transmission is\r
+//! complete.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_masterSendMultiByteStop(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Send STOP byte at the end of a multi-byte transmission from Master\r
+//! to Slave with timeout\r
+//!\r
+//! This function is used by the Master module send STOP at the end of a multi-\r
+//! byte transmission. This function sends a stop after current transmission is\r
+//! complete.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param timeout is the amount of time to wait until giving up\r
+//!\r
+//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process.\r
+//\r
+//*****************************************************************************\r
+extern bool EUSCI_B_I2C_masterSendMultiByteStopWithTimeout(uint16_t baseAddress,\r
+ uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts reception at the Master end\r
+//!\r
+//! This function is used by the Master module initiate reception of a single\r
+//! byte. This function sends a start.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! Modified bits are \b UCTXSTT of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_masterReceiveStart(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts multi-byte reception at the Master end one byte at a time\r
+//!\r
+//! This function is used by the Master module to receive each byte of a multi-\r
+//! byte reception. This function reads currently received byte.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! \return Received byte at Master end.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_B_I2C_masterReceiveMultiByteNext(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Finishes multi-byte reception at the Master end\r
+//!\r
+//! This function is used by the Master module to initiate completion of a\r
+//! multi-byte reception. This function receives the current byte and initiates\r
+//! the STOP from master to slave.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register.\r
+//!\r
+//! \return Received byte at Master end.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_B_I2C_masterReceiveMultiByteFinish(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Finishes multi-byte reception at the Master end with timeout\r
+//!\r
+//! This function is used by the Master module to initiate completion of a\r
+//! multi-byte reception. This function receives the current byte and initiates\r
+//! the STOP from master to slave.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//! \param txData is a pointer to the location to store the received byte at\r
+//! master end\r
+//! \param timeout is the amount of time to wait until giving up\r
+//!\r
+//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of the reception process\r
+//\r
+//*****************************************************************************\r
+extern bool EUSCI_B_I2C_masterReceiveMultiByteFinishWithTimeout(\r
+ uint16_t baseAddress,\r
+ uint8_t *txData,\r
+ uint32_t timeout);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sends the STOP at the end of a multi-byte reception at the Master\r
+//! end\r
+//!\r
+//! This function is used by the Master module to initiate STOP\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_masterReceiveMultiByteStop(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables Multi Master Mode\r
+//!\r
+//! At the end of this function, the I2C module is still disabled till\r
+//! EUSCI_B_I2C_enable is invoked\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//!\r
+//! Modified bits are \b UCSWRST and \b UCMM of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_enableMultiMasterMode(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables Multi Master Mode\r
+//!\r
+//! At the end of this function, the I2C module is still disabled till\r
+//! EUSCI_B_I2C_enable is invoked\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//!\r
+//! Modified bits are \b UCSWRST and \b UCMM of \b UCBxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_I2C_disableMultiMasterMode(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief receives a byte that has been sent to the I2C Master Module.\r
+//!\r
+//! This function reads a byte of data from the I2C receive data Register.\r
+//!\r
+//! \param baseAddress is the base address of the I2C Master module.\r
+//!\r
+//! \return Returns the byte received from by the I2C module, cast as an\r
+//! uint8_t.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_B_I2C_masterReceiveSingle(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the RX Buffer of the I2C for the DMA module.\r
+//!\r
+//! Returns the address of the I2C RX Buffer. This can be used in conjunction\r
+//! with the DMA to store the received data directly to memory.\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//!\r
+//! \return The address of the I2C RX Buffer\r
+//\r
+//*****************************************************************************\r
+extern uint32_t EUSCI_B_I2C_getReceiveBufferAddress(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the TX Buffer of the I2C for the DMA module.\r
+//!\r
+//! Returns the address of the I2C TX Buffer. This can be used in conjunction\r
+//! with the DMA to obtain transmitted data directly from memory.\r
+//!\r
+//! \param baseAddress is the base address of the I2C module.\r
+//!\r
+//! \return The address of the I2C TX Buffer\r
+//\r
+//*****************************************************************************\r
+extern uint32_t EUSCI_B_I2C_getTransmitBufferAddress(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_EUSCI_B_I2C_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_b_spi.c - Driver for the eusci_b_spi Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup eusci_b_spi_api eusci_b_spi\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Bx__\r
+#include "eusci_b_spi.h"\r
+\r
+#include <assert.h>\r
+\r
+void EUSCI_B_SPI_initMaster(uint16_t baseAddress,\r
+ EUSCI_B_SPI_initMasterParam *param)\r
+{\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+\r
+ //Reset OFS_UCBxCTLW0 values\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB +\r
+ UCMST + UCMODE_3 + UCSYNC);\r
+\r
+ //Reset OFS_UCBxCTLW0 values\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSSEL_3);\r
+\r
+ //Select Clock\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= param->selectClockSource;\r
+\r
+ HWREG16(baseAddress + OFS_UCBxBRW) =\r
+ (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);\r
+\r
+ /*\r
+ * Configure as SPI master mode.\r
+ * Clock phase select, polarity, msb\r
+ * UCMST = Master mode\r
+ * UCSYNC = Synchronous mode\r
+ * UCMODE_0 = 3-pin SPI\r
+ */\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= (\r
+ param->msbFirst +\r
+ param->clockPhase +\r
+ param->clockPolarity +\r
+ UCMST +\r
+ UCSYNC +\r
+ param->spiMode\r
+ );\r
+}\r
+\r
+void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress,\r
+ uint8_t select4PinFunctionality)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCSTEM;\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= select4PinFunctionality;\r
+}\r
+\r
+void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress,\r
+ EUSCI_B_SPI_changeMasterClockParam *param)\r
+{\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+\r
+ HWREG16(baseAddress + OFS_UCBxBRW) =\r
+ (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);\r
+\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_B_SPI_initSlave(uint16_t baseAddress,\r
+ EUSCI_B_SPI_initSlaveParam *param)\r
+{\r
+ //Disable USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+\r
+ //Reset OFS_UCBxCTLW0 register\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCMSB +\r
+ UC7BIT +\r
+ UCMST +\r
+ UCCKPL +\r
+ UCCKPH +\r
+ UCMODE_3\r
+ );\r
+\r
+ //Clock polarity, phase select, msbFirst, SYNC, Mode0\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= (param->clockPhase +\r
+ param->clockPolarity +\r
+ param->msbFirst +\r
+ UCSYNC +\r
+ param->spiMode\r
+ );\r
+}\r
+\r
+void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress,\r
+ uint16_t clockPhase,\r
+ uint16_t clockPolarity)\r
+{\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL);\r
+\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= (\r
+ clockPhase +\r
+ clockPolarity\r
+ );\r
+\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_B_SPI_transmitData(uint16_t baseAddress,\r
+ uint8_t transmitData)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData;\r
+}\r
+\r
+uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCBxRXBUF));\r
+}\r
+\r
+void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxIE) |= mask;\r
+}\r
+\r
+void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxIE) &= ~mask;\r
+}\r
+\r
+uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCBxIFG) & mask);\r
+}\r
+\r
+void EUSCI_B_SPI_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxIFG) &= ~mask;\r
+}\r
+\r
+void EUSCI_B_SPI_enable(uint16_t baseAddress)\r
+{\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_B_SPI_disable(uint16_t baseAddress)\r
+{\r
+ //Set the UCSWRST bit to disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+}\r
+\r
+uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCBxRXBUF);\r
+}\r
+\r
+uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCBxTXBUF);\r
+}\r
+\r
+uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress)\r
+{\r
+ //Return the bus busy status.\r
+ return (HWREG16(baseAddress + OFS_UCBxSTATW) & UCBUSY);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for eusci_b_spi_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_b_spi.h - Driver for the EUSCI_B_SPI Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_EUSCI_B_SPI_H__\r
+#define __MSP430WARE_EUSCI_B_SPI_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Bx__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the EUSCI_B_SPI_initMaster() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct EUSCI_B_SPI_initMasterParam\r
+{\r
+ //! Selects Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_SPI_CLOCKSOURCE_ACLK\r
+ //! - \b EUSCI_B_SPI_CLOCKSOURCE_SMCLK\r
+ uint8_t selectClockSource;\r
+ //! Is the frequency of the selected clock source\r
+ uint32_t clockSourceFrequency;\r
+ //! Is the desired clock rate for SPI communication\r
+ uint32_t desiredSpiClock;\r
+ //! Controls the direction of the receive and transmit shift register.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_SPI_MSB_FIRST\r
+ //! - \b EUSCI_B_SPI_LSB_FIRST [Default]\r
+ uint16_t msbFirst;\r
+ //! Is clock phase select.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default]\r
+ //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT\r
+ uint16_t clockPhase;\r
+ //! Is clock polarity select\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH\r
+ //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]\r
+ uint16_t clockPolarity;\r
+ //! Is SPI mode select\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_SPI_3PIN\r
+ //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH\r
+ //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW\r
+ uint16_t spiMode;\r
+} EUSCI_B_SPI_initMasterParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the EUSCI_B_SPI_initSlave() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct EUSCI_B_SPI_initSlaveParam\r
+{\r
+ //! Controls the direction of the receive and transmit shift register.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_SPI_MSB_FIRST\r
+ //! - \b EUSCI_B_SPI_LSB_FIRST [Default]\r
+ uint16_t msbFirst;\r
+ //! Is clock phase select.\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default]\r
+ //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT\r
+ uint16_t clockPhase;\r
+ //! Is clock polarity select\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH\r
+ //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]\r
+ uint16_t clockPolarity;\r
+ //! Is SPI mode select\r
+ //! \n Valid values are:\r
+ //! - \b EUSCI_B_SPI_3PIN\r
+ //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH\r
+ //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW\r
+ uint16_t spiMode;\r
+} EUSCI_B_SPI_initSlaveParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the EUSCI_B_SPI_changeMasterClock() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct EUSCI_B_SPI_changeMasterClockParam\r
+{\r
+ //! Is the frequency of the selected clock source\r
+ uint32_t clockSourceFrequency;\r
+ //! Is the desired clock rate for SPI communication\r
+ uint32_t desiredSpiClock;\r
+} EUSCI_B_SPI_changeMasterClockParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockPhase parameter for\r
+// functions: EUSCI_B_SPI_changeClockPhasePolarity(); the param parameter for\r
+// functions: EUSCI_B_SPI_initMaster(), and EUSCI_B_SPI_initSlave().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00\r
+#define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_B_SPI_initMaster(), and EUSCI_B_SPI_initSlave().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_SPI_MSB_FIRST UCMSB\r
+#define EUSCI_B_SPI_LSB_FIRST 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_B_SPI_initMaster(), and EUSCI_B_SPI_initSlave(); the\r
+// clockPolarity parameter for functions:\r
+// EUSCI_B_SPI_changeClockPhasePolarity().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL\r
+#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_B_SPI_initMaster().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK\r
+#define EUSCI_B_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: EUSCI_B_SPI_initMaster(), and EUSCI_B_SPI_initSlave().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_SPI_3PIN UCMODE_0\r
+#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1\r
+#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the select4PinFunctionality\r
+// parameter for functions: EUSCI_B_SPI_select4PinFunctionality().\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00\r
+#define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: EUSCI_B_SPI_enableInterrupt(), EUSCI_B_SPI_disableInterrupt(),\r
+// EUSCI_B_SPI_getInterruptStatus(), and EUSCI_B_SPI_clearInterrupt() as well\r
+// as returned by the EUSCI_B_SPI_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_SPI_TRANSMIT_INTERRUPT UCTXIE\r
+#define EUSCI_B_SPI_RECEIVE_INTERRUPT UCRXIE\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the EUSCI_B_SPI_isBusy() function.\r
+//\r
+//*****************************************************************************\r
+#define EUSCI_B_SPI_BUSY UCBUSY\r
+#define EUSCI_B_SPI_NOT_BUSY 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the SPI Master block.\r
+//!\r
+//! Upon successful initialization of the SPI master block, this function will\r
+//! have set the bus speed for the master, but the SPI Master block still\r
+//! remains disabled and must be enabled with EUSCI_B_SPI_enable()\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI Master module.\r
+//! \param param is the pointer to struct for master initialization.\r
+//!\r
+//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and\r
+//! \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return STATUS_SUCCESS\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_initMaster(uint16_t baseAddress,\r
+ EUSCI_B_SPI_initMasterParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects 4Pin Functionality\r
+//!\r
+//! This function should be invoked only in 4-wire mode. Invoking this function\r
+//! has no effect in 3-wire mode.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//! \param select4PinFunctionality selects 4 pin functionality\r
+//! Valid values are:\r
+//! - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS\r
+//! - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE\r
+//!\r
+//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress,\r
+ uint8_t select4PinFunctionality);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the SPI Master clock. At the end of this function call,\r
+//! SPI module is left enabled.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//! \param param is the pointer to struct for master clock setting.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress,\r
+ EUSCI_B_SPI_changeMasterClockParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the SPI Slave block.\r
+//!\r
+//! Upon successful initialization of the SPI slave block, this function will\r
+//! have initialized the slave block, but the SPI Slave block still remains\r
+//! disabled and must be enabled with EUSCI_B_SPI_enable()\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI Slave module.\r
+//! \param param is the pointer to struct for slave initialization.\r
+//!\r
+//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b\r
+//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return STATUS_SUCCESS\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_initSlave(uint16_t baseAddress,\r
+ EUSCI_B_SPI_initSlaveParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Changes the SPI clock phase and polarity. At the end of this\r
+//! function call, SPI module is left enabled.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//! \param clockPhase is clock phase select.\r
+//! Valid values are:\r
+//! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT\r
+//! [Default]\r
+//! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT\r
+//! \param clockPolarity is clock polarity select\r
+//! Valid values are:\r
+//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH\r
+//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]\r
+//!\r
+//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0\r
+//! register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress,\r
+ uint16_t clockPhase,\r
+ uint16_t clockPolarity);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Transmits a byte from the SPI Module.\r
+//!\r
+//! This function will place the supplied data into SPI transmit data register\r
+//! to start transmission.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//! \param transmitData data to be transmitted from the SPI module\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_transmitData(uint16_t baseAddress,\r
+ uint8_t transmitData);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Receives a byte that has been sent to the SPI Module.\r
+//!\r
+//! This function reads a byte of data from the SPI receive data Register.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//!\r
+//! \return Returns the byte received from by the SPI module, cast as an\r
+//! uint8_t.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables individual SPI interrupt sources.\r
+//!\r
+//! Enables the indicated SPI interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor. Does not clear interrupt flags.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//! \param mask is the bit mask of the interrupt sources to be enabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT\r
+//!\r
+//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables individual SPI interrupt sources.\r
+//!\r
+//! Disables the indicated SPI interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//! \param mask is the bit mask of the interrupt sources to be disabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT\r
+//!\r
+//! Modified bits of \b UCAxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the current SPI interrupt status.\r
+//!\r
+//! This returns the interrupt status for the SPI module based on which flag is\r
+//! passed.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//! \param mask is the masked interrupt flag status to be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the selected SPI interrupt status flag.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//! \param mask is the masked interrupt flag to be cleared.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT\r
+//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT\r
+//!\r
+//! Modified bits of \b UCAxIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the SPI block.\r
+//!\r
+//! This will enable operation of the SPI block.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_enable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the SPI block.\r
+//!\r
+//! This will disable operation of the SPI block.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void EUSCI_B_SPI_disable(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the RX Buffer of the SPI for the DMA module.\r
+//!\r
+//! Returns the address of the SPI RX Buffer. This can be used in conjunction\r
+//! with the DMA to store the received data directly to memory.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//!\r
+//! \return the address of the RX Buffer\r
+//\r
+//*****************************************************************************\r
+extern uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the TX Buffer of the SPI for the DMA module.\r
+//!\r
+//! Returns the address of the SPI TX Buffer. This can be used in conjunction\r
+//! with the DMA to obtain transmitted data directly from memory.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//!\r
+//! \return the address of the TX Buffer\r
+//\r
+//*****************************************************************************\r
+extern uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Indicates whether or not the SPI bus is busy.\r
+//!\r
+//! This function returns an indication of whether or not the SPI bus is\r
+//! busy.This function checks the status of the bus via UCBBUSY bit\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b EUSCI_B_SPI_BUSY\r
+//! - \b EUSCI_B_SPI_NOT_BUSY\r
+//! \n indicating if the EUSCI_B_SPI is busy\r
+//\r
+//*****************************************************************************\r
+extern uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_EUSCI_B_SPI_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// framctl.c - Driver for the framctl Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup framctl_api framctl\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_FRAM__\r
+#include "framctl.h"\r
+\r
+#include <assert.h>\r
+\r
+void FRAMCtl_write8(uint8_t *dataPtr,\r
+ uint8_t *framPtr,\r
+ uint16_t numberOfBytes)\r
+{\r
+ while(numberOfBytes > 0)\r
+ {\r
+ //Write to Fram\r
+ *framPtr++ = *dataPtr++;\r
+ numberOfBytes--;\r
+ }\r
+}\r
+\r
+void FRAMCtl_write16(uint16_t *dataPtr,\r
+ uint16_t *framPtr,\r
+ uint16_t numberOfWords)\r
+{\r
+ while(numberOfWords > 0)\r
+ {\r
+ //Write to Fram\r
+ *framPtr++ = *dataPtr++;\r
+ numberOfWords--;\r
+ }\r
+}\r
+\r
+void FRAMCtl_write32(uint32_t *dataPtr,\r
+ uint32_t *framPtr,\r
+ uint16_t count)\r
+{\r
+ while(count > 0)\r
+ {\r
+ //Write to Fram\r
+ *framPtr++ = *dataPtr++;\r
+ count--;\r
+ }\r
+}\r
+\r
+void FRAMCtl_fillMemory32(uint32_t value,\r
+ uint32_t *framPtr,\r
+ uint16_t count)\r
+{\r
+ while(count > 0)\r
+ {\r
+ //Write to Fram\r
+ *framPtr++ = value;\r
+ count--;\r
+ }\r
+}\r
+\r
+void FRAMCtl_enableInterrupt(uint8_t interruptMask)\r
+{\r
+ uint8_t waitSelection;\r
+\r
+ waitSelection = (HWREG8(FRAM_BASE + OFS_FRCTL0) & 0xFF);\r
+ // Clear lock in FRAM control registers\r
+ HWREG16(FRAM_BASE + OFS_FRCTL0) = FWPW | waitSelection;\r
+\r
+ // Enable user selected interrupt sources\r
+ HWREG16(FRAM_BASE + OFS_GCCTL0) |= interruptMask;\r
+}\r
+\r
+uint8_t FRAMCtl_getInterruptStatus(uint16_t interruptFlagMask)\r
+{\r
+ return (HWREG16(FRAM_BASE + OFS_GCCTL1) & interruptFlagMask);\r
+}\r
+\r
+void FRAMCtl_disableInterrupt(uint16_t interruptMask)\r
+{\r
+ uint8_t waitSelection;\r
+\r
+ waitSelection = (HWREG8(FRAM_BASE + OFS_FRCTL0) & 0xFF);\r
+ //Clear lock in FRAM control registers\r
+ HWREG16(FRAM_BASE + OFS_FRCTL0) = FWPW | waitSelection;\r
+\r
+ HWREG16(FRAM_BASE + OFS_GCCTL0) &= ~(interruptMask);\r
+}\r
+\r
+void FRAMCtl_configureWaitStateControl(uint8_t waitState)\r
+{\r
+ // Clear lock in FRAM control registers\r
+ HWREG16(FRAM_BASE + OFS_FRCTL0) = FWPW;\r
+\r
+ HWREG8(FRAM_BASE + OFS_FRCTL0_L) &= ~NWAITS_7;\r
+ HWREG8(FRAM_BASE + OFS_FRCTL0_L) |= (waitState);\r
+}\r
+\r
+void FRAMCtl_delayPowerUpFromLPM(uint8_t delayStatus)\r
+{\r
+ uint8_t waitSelection;\r
+\r
+ waitSelection = (HWREG8(FRAM_BASE + OFS_FRCTL0) & 0xFF);\r
+\r
+ // Clear lock in FRAM control registers\r
+ HWREG16(FRAM_BASE + OFS_FRCTL0) = FWPW | waitSelection;\r
+\r
+ HWREG8(FRAM_BASE + OFS_GCCTL0_L) &= ~0x02;\r
+ HWREG8(FRAM_BASE + OFS_GCCTL0_L) |= delayStatus;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for framctl_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// framctl.h - Driver for the FRAMCTL Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_FRAMCTL_H__\r
+#define __MSP430WARE_FRAMCTL_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_FRAM__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptMask parameter\r
+// for functions: FRAMCtl_enableInterrupt(), and FRAMCtl_disableInterrupt().\r
+//\r
+//*****************************************************************************\r
+#define FRAMCTL_PUC_ON_UNCORRECTABLE_BIT UBDRSTEN\r
+#define FRAMCTL_UNCORRECTABLE_BIT_INTERRUPT UBDIE\r
+#define FRAMCTL_CORRECTABLE_BIT_INTERRUPT CBDIE\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptFlagMask\r
+// parameter for functions: FRAMCtl_getInterruptStatus() as well as returned by\r
+// the FRAMCtl_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define FRAMCTL_ACCESS_TIME_ERROR_FLAG ACCTEIFG\r
+#define FRAMCTL_UNCORRECTABLE_BIT_FLAG UBDIFG\r
+#define FRAMCTL_CORRECTABLE_BIT_FLAG CBDIFG\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the waitState parameter for\r
+// functions: FRAMCtl_configureWaitStateControl().\r
+//\r
+//*****************************************************************************\r
+#define FRAMCTL_ACCESS_TIME_CYCLES_0 NWAITS_0\r
+#define FRAMCTL_ACCESS_TIME_CYCLES_1 NWAITS_1\r
+#define FRAMCTL_ACCESS_TIME_CYCLES_2 NWAITS_2\r
+#define FRAMCTL_ACCESS_TIME_CYCLES_3 NWAITS_3\r
+#define FRAMCTL_ACCESS_TIME_CYCLES_4 NWAITS_4\r
+#define FRAMCTL_ACCESS_TIME_CYCLES_5 NWAITS_5\r
+#define FRAMCTL_ACCESS_TIME_CYCLES_6 NWAITS_6\r
+#define FRAMCTL_ACCESS_TIME_CYCLES_7 NWAITS_7\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the delayStatus parameter for\r
+// functions: FRAMCtl_delayPowerUpFromLPM().\r
+//\r
+//*****************************************************************************\r
+#define FRAMCTL_DELAY_FROM_LPM_ENABLE 0x00\r
+#define FRAMCTL_DELAY_FROM_LPM_DISABLE 0x02\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Write data into the fram memory in byte format.\r
+//!\r
+//! \param dataPtr is the pointer to the data to be written\r
+//! \param framPtr is the pointer into which to write the data\r
+//! \param numberOfBytes is the number of bytes to be written\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void FRAMCtl_write8(uint8_t *dataPtr,\r
+ uint8_t *framPtr,\r
+ uint16_t numberOfBytes);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Write data into the fram memory in word format.\r
+//!\r
+//! \param dataPtr is the pointer to the data to be written\r
+//! \param framPtr is the pointer into which to write the data\r
+//! \param numberOfWords is the number of words to be written\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void FRAMCtl_write16(uint16_t *dataPtr,\r
+ uint16_t *framPtr,\r
+ uint16_t numberOfWords);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Write data into the fram memory in long format, pass by reference\r
+//!\r
+//! \param dataPtr is the pointer to the data to be written\r
+//! \param framPtr is the pointer into which to write the data\r
+//! \param count is the number of 32 bit words to be written\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void FRAMCtl_write32(uint32_t *dataPtr,\r
+ uint32_t *framPtr,\r
+ uint16_t count);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Write data into the fram memory in long format, pass by value\r
+//!\r
+//! \param value is the value to written to FRAMCTL memory\r
+//! \param framPtr is the pointer into which to write the data\r
+//! \param count is the number of 32 bit addresses to fill\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void FRAMCtl_fillMemory32(uint32_t value,\r
+ uint32_t *framPtr,\r
+ uint16_t count);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables selected FRAMCtl interrupt sources.\r
+//!\r
+//! Enables the indicated FRAMCtl interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor. Does not clear interrupt flags.\r
+//!\r
+//! \param interruptMask is the bit mask of the memory buffer interrupt sources\r
+//! to be disabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b FRAMCTL_PUC_ON_UNCORRECTABLE_BIT - Enable PUC reset if FRAMCtl\r
+//! uncorrectable bit error detected.\r
+//! - \b FRAMCTL_UNCORRECTABLE_BIT_INTERRUPT - Interrupts when an\r
+//! uncorrectable bit error is detected.\r
+//! - \b FRAMCTL_CORRECTABLE_BIT_INTERRUPT - Interrupts when a\r
+//! correctable bit error is detected.\r
+//!\r
+//! Modified bits of \b GCCTL0 register and bits of \b FRCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void FRAMCtl_enableInterrupt(uint8_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the status of the selected FRAMCtl interrupt flags.\r
+//!\r
+//! \param interruptFlagMask is a bit mask of the interrupt flags status to be\r
+//! returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b FRAMCTL_ACCESS_TIME_ERROR_FLAG - Interrupt flag is set if a\r
+//! wrong setting for NPRECHG and NACCESS is set and FRAMCtl access\r
+//! time is not hold.\r
+//! - \b FRAMCTL_UNCORRECTABLE_BIT_FLAG - Interrupt flag is set if an\r
+//! uncorrectable bit error has been detected in the FRAMCtl memory\r
+//! error detection logic.\r
+//! - \b FRAMCTL_CORRECTABLE_BIT_FLAG - Interrupt flag is set if a\r
+//! correctable bit error has been detected and corrected in the\r
+//! FRAMCtl memory error detection logic.\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b FRAMCtl_ACCESS_TIME_ERROR_FLAG Interrupt flag is set if a\r
+//! wrong setting for NPRECHG and NACCESS is set and FRAMCtl access\r
+//! time is not hold.\r
+//! - \b FRAMCtl_UNCORRECTABLE_BIT_FLAG Interrupt flag is set if an\r
+//! uncorrectable bit error has been detected in the FRAMCtl memory\r
+//! error detection logic.\r
+//! - \b FRAMCtl_CORRECTABLE_BIT_FLAG Interrupt flag is set if a\r
+//! correctable bit error has been detected and corrected in the\r
+//! FRAMCtl memory error detection logic.\r
+//! \n indicating the status of the masked flags\r
+//\r
+//*****************************************************************************\r
+extern uint8_t FRAMCtl_getInterruptStatus(uint16_t interruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables selected FRAMCtl interrupt sources.\r
+//!\r
+//! Disables the indicated FRAMCtl interrupt sources. Only the sources that\r
+//! are enabled can be reflected to the processor interrupt; disabled sources\r
+//! have no effect on the processor.\r
+//!\r
+//! \param interruptMask is the bit mask of the memory buffer interrupt sources\r
+//! to be disabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b FRAMCTL_PUC_ON_UNCORRECTABLE_BIT - Enable PUC reset if FRAMCtl\r
+//! uncorrectable bit error detected.\r
+//! - \b FRAMCTL_UNCORRECTABLE_BIT_INTERRUPT - Interrupts when an\r
+//! uncorrectable bit error is detected.\r
+//! - \b FRAMCTL_CORRECTABLE_BIT_INTERRUPT - Interrupts when a\r
+//! correctable bit error is detected.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void FRAMCtl_disableInterrupt(uint16_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures the access time of the FRAMCtl module\r
+//!\r
+//! Configures the access time of the FRAMCtl module.\r
+//!\r
+//! \param waitState defines the number of CPU cycles required for access time\r
+//! defined in the datasheet\r
+//! Valid values are:\r
+//! - \b FRAMCTL_ACCESS_TIME_CYCLES_0\r
+//! - \b FRAMCTL_ACCESS_TIME_CYCLES_1\r
+//! - \b FRAMCTL_ACCESS_TIME_CYCLES_2\r
+//! - \b FRAMCTL_ACCESS_TIME_CYCLES_3\r
+//! - \b FRAMCTL_ACCESS_TIME_CYCLES_4\r
+//! - \b FRAMCTL_ACCESS_TIME_CYCLES_5\r
+//! - \b FRAMCTL_ACCESS_TIME_CYCLES_6\r
+//! - \b FRAMCTL_ACCESS_TIME_CYCLES_7\r
+//!\r
+//! Modified bits are \b NWAITS of \b GCCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void FRAMCtl_configureWaitStateControl(uint8_t waitState);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures when the FRAMCtl module will power up after LPM exit\r
+//!\r
+//! Configures when the FRAMCtl module will power up after LPM exit. The module\r
+//! can either wait until the first FRAMCtl access to power up or power up\r
+//! immediately after leaving LPM. If FRAMCtl power is disabled, a memory\r
+//! access will automatically insert wait states to ensure sufficient timing\r
+//! for the FRAMCtl power-up and access.\r
+//!\r
+//! \param delayStatus chooses if FRAMCTL should power up instantly with LPM\r
+//! exit or to wait until first FRAMCTL access after LPM exit\r
+//! Valid values are:\r
+//! - \b FRAMCTL_DELAY_FROM_LPM_ENABLE\r
+//! - \b FRAMCTL_DELAY_FROM_LPM_DISABLE\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void FRAMCtl_delayPowerUpFromLPM(uint8_t delayStatus);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_FRAMCTL_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// gpio.c - Driver for the gpio Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup gpio_api gpio\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#if defined(__MSP430_HAS_PORT1_R__) || defined(__MSP430_HAS_PORT2_R__) || \\r
+ defined(__MSP430_HAS_PORTA_R__)\r
+#include "gpio.h"\r
+\r
+#include <assert.h>\r
+\r
+static const uint16_t GPIO_PORT_TO_BASE[] = {\r
+ 0x00,\r
+#if defined(__MSP430_HAS_PORT1_R__)\r
+ __MSP430_BASEADDRESS_PORT1_R__,\r
+#elif defined(__MSP430_HAS_PORT1__)\r
+ __MSP430_BASEADDRESS_PORT1__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT2_R__)\r
+ __MSP430_BASEADDRESS_PORT2_R__,\r
+#elif defined(__MSP430_HAS_PORT2__)\r
+ __MSP430_BASEADDRESS_PORT2__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT3_R__)\r
+ __MSP430_BASEADDRESS_PORT3_R__,\r
+#elif defined(__MSP430_HAS_PORT3__)\r
+ __MSP430_BASEADDRESS_PORT3__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT4_R__)\r
+ __MSP430_BASEADDRESS_PORT4_R__,\r
+#elif defined(__MSP430_HAS_PORT4__)\r
+ __MSP430_BASEADDRESS_PORT4__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT5_R__)\r
+ __MSP430_BASEADDRESS_PORT5_R__,\r
+#elif defined(__MSP430_HAS_PORT5__)\r
+ __MSP430_BASEADDRESS_PORT5__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT6_R__)\r
+ __MSP430_BASEADDRESS_PORT6_R__,\r
+#elif defined(__MSP430_HAS_PORT6__)\r
+ __MSP430_BASEADDRESS_PORT6__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT7_R__)\r
+ __MSP430_BASEADDRESS_PORT7_R__,\r
+#elif defined(__MSP430_HAS_PORT7__)\r
+ __MSP430_BASEADDRESS_PORT7__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT8_R__)\r
+ __MSP430_BASEADDRESS_PORT8_R__,\r
+#elif defined(__MSP430_HAS_PORT8__)\r
+ __MSP430_BASEADDRESS_PORT8__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT9_R__)\r
+ __MSP430_BASEADDRESS_PORT9_R__,\r
+#elif defined(__MSP430_HAS_PORT9__)\r
+ __MSP430_BASEADDRESS_PORT9__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT10_R__)\r
+ __MSP430_BASEADDRESS_PORT10_R__,\r
+#elif defined(__MSP430_HAS_PORT10__)\r
+ __MSP430_BASEADDRESS_PORT10__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+#if defined(__MSP430_HAS_PORT11_R__)\r
+ __MSP430_BASEADDRESS_PORT11_R__,\r
+#elif defined(__MSP430_HAS_PORT11__)\r
+ __MSP430_BASEADDRESS_PORT11__,\r
+#else\r
+ 0xFFFF,\r
+#endif\r
+ 0xFFFF,\r
+#if defined(__MSP430_HAS_PORTJ_R__)\r
+ __MSP430_BASEADDRESS_PORTJ_R__\r
+#elif defined(__MSP430_HAS_PORTJ__)\r
+ __MSP430_BASEADDRESS_PORTJ__\r
+#else\r
+ 0xFFFF\r
+#endif\r
+};\r
+\r
+void GPIO_setAsOutputPin(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PADIR) |= selectedPins;\r
+\r
+ return;\r
+}\r
+\r
+void GPIO_setAsInputPin(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PAREN) &= ~selectedPins;\r
+}\r
+\r
+void GPIO_setAsPeripheralModuleFunctionOutputPin(uint8_t selectedPort,\r
+ uint16_t selectedPins\r
+ ,\r
+ uint8_t mode) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PADIR) |= selectedPins;\r
+ switch(mode)\r
+ {\r
+ case GPIO_PRIMARY_MODULE_FUNCTION:\r
+ HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;\r
+ break;\r
+ case GPIO_SECONDARY_MODULE_FUNCTION:\r
+ HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;\r
+ break;\r
+ case GPIO_TERNARY_MODULE_FUNCTION:\r
+ HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;\r
+ break;\r
+ }\r
+}\r
+\r
+void GPIO_setAsPeripheralModuleFunctionInputPin(uint8_t selectedPort,\r
+ uint16_t selectedPins\r
+ ,\r
+ uint8_t mode) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;\r
+ switch(mode)\r
+ {\r
+ case GPIO_PRIMARY_MODULE_FUNCTION:\r
+ HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;\r
+ break;\r
+ case GPIO_SECONDARY_MODULE_FUNCTION:\r
+ HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;\r
+ break;\r
+ case GPIO_TERNARY_MODULE_FUNCTION:\r
+ HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;\r
+ break;\r
+ }\r
+}\r
+\r
+void GPIO_setOutputHighOnPin(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;\r
+}\r
+\r
+void GPIO_setOutputLowOnPin(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;\r
+}\r
+\r
+void GPIO_toggleOutputOnPin(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PAOUT) ^= selectedPins;\r
+}\r
+\r
+void GPIO_setAsInputPinWithPullDownResistor(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;\r
+\r
+ HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PAREN) |= selectedPins;\r
+ HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;\r
+}\r
+\r
+void GPIO_setAsInputPinWithPullUpResistor(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;\r
+ HWREG16(baseAddress + OFS_PAREN) |= selectedPins;\r
+ HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;\r
+}\r
+\r
+uint8_t GPIO_getInputPinValue(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ uint16_t inputPinValue = HWREG16(baseAddress + OFS_PAIN) & (selectedPins);\r
+\r
+ if(inputPinValue > 0)\r
+ {\r
+ return (GPIO_INPUT_PIN_HIGH);\r
+ }\r
+ return (GPIO_INPUT_PIN_LOW);\r
+}\r
+\r
+void GPIO_enableInterrupt(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PAIE) |= selectedPins;\r
+}\r
+\r
+void GPIO_disableInterrupt(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PAIE) &= ~selectedPins;\r
+}\r
+\r
+uint16_t GPIO_getInterruptStatus(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ return (HWREG16(baseAddress + OFS_PAIFG) & selectedPins);\r
+}\r
+\r
+void GPIO_clearInterrupt(uint8_t selectedPort,\r
+ uint16_t selectedPins) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_PAIFG) &= ~selectedPins;\r
+}\r
+\r
+void GPIO_selectInterruptEdge(uint8_t selectedPort,\r
+ uint16_t selectedPins,\r
+ uint8_t edgeSelect) {\r
+ uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];\r
+\r
+ #ifndef NDEBUG\r
+ if(baseAddress == 0xFFFF)\r
+ {\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ // Shift by 8 if port is even (upper 8-bits)\r
+ if((selectedPort & 1) ^ 1)\r
+ {\r
+ selectedPins <<= 8;\r
+ }\r
+\r
+ if(GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect)\r
+ {\r
+ HWREG16(baseAddress + OFS_PAIES) &= ~selectedPins;\r
+ }\r
+ else\r
+ {\r
+ HWREG16(baseAddress + OFS_PAIES) |= selectedPins;\r
+ }\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for gpio_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// gpio.h - Driver for the GPIO Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_GPIO_H__\r
+#define __MSP430WARE_GPIO_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#if defined(__MSP430_HAS_PORT1_R__) || defined(__MSP430_HAS_PORT2_R__) || \\r
+ defined(__MSP430_HAS_PORTA_R__)\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the selectedPort parameter\r
+// for functions: GPIO_setAsOutputPin(), GPIO_setAsInputPin(),\r
+// GPIO_setAsPeripheralModuleFunctionOutputPin(),\r
+// GPIO_setAsPeripheralModuleFunctionInputPin(), GPIO_setOutputHighOnPin(),\r
+// GPIO_setOutputLowOnPin(), GPIO_toggleOutputOnPin(),\r
+// GPIO_setAsInputPinWithPullDownResistor(),\r
+// GPIO_setAsInputPinWithPullUpResistor(), GPIO_getInputPinValue(),\r
+// GPIO_selectInterruptEdge(), GPIO_enableInterrupt(), GPIO_disableInterrupt(),\r
+// GPIO_getInterruptStatus(), and GPIO_clearInterrupt().\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PORT_P1 1\r
+#define GPIO_PORT_P2 2\r
+#define GPIO_PORT_P3 3\r
+#define GPIO_PORT_P4 4\r
+#define GPIO_PORT_P5 5\r
+#define GPIO_PORT_P6 6\r
+#define GPIO_PORT_P7 7\r
+#define GPIO_PORT_P8 8\r
+#define GPIO_PORT_P9 9\r
+#define GPIO_PORT_P10 10\r
+#define GPIO_PORT_P11 11\r
+#define GPIO_PORT_PA 1\r
+#define GPIO_PORT_PB 3\r
+#define GPIO_PORT_PC 5\r
+#define GPIO_PORT_PD 7\r
+#define GPIO_PORT_PE 9\r
+#define GPIO_PORT_PF 11\r
+#define GPIO_PORT_PJ 13\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the selectedPins parameter\r
+// for functions: GPIO_setAsOutputPin(), GPIO_setAsInputPin(),\r
+// GPIO_setAsPeripheralModuleFunctionOutputPin(),\r
+// GPIO_setAsPeripheralModuleFunctionInputPin(), GPIO_setOutputHighOnPin(),\r
+// GPIO_setOutputLowOnPin(), GPIO_toggleOutputOnPin(),\r
+// GPIO_setAsInputPinWithPullDownResistor(),\r
+// GPIO_setAsInputPinWithPullUpResistor(), GPIO_getInputPinValue(),\r
+// GPIO_enableInterrupt(), GPIO_disableInterrupt(), GPIO_getInterruptStatus(),\r
+// GPIO_clearInterrupt(), and GPIO_selectInterruptEdge() as well as returned by\r
+// the GPIO_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN0 (0x0001)\r
+#define GPIO_PIN1 (0x0002)\r
+#define GPIO_PIN2 (0x0004)\r
+#define GPIO_PIN3 (0x0008)\r
+#define GPIO_PIN4 (0x0010)\r
+#define GPIO_PIN5 (0x0020)\r
+#define GPIO_PIN6 (0x0040)\r
+#define GPIO_PIN7 (0x0080)\r
+#define GPIO_PIN8 (0x0100)\r
+#define GPIO_PIN9 (0x0200)\r
+#define GPIO_PIN10 (0x0400)\r
+#define GPIO_PIN11 (0x0800)\r
+#define GPIO_PIN12 (0x1000)\r
+#define GPIO_PIN13 (0x2000)\r
+#define GPIO_PIN14 (0x4000)\r
+#define GPIO_PIN15 (0x8000)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mode parameter for\r
+// functions: GPIO_setAsPeripheralModuleFunctionOutputPin(), and\r
+// GPIO_setAsPeripheralModuleFunctionInputPin().\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PRIMARY_MODULE_FUNCTION (0x01)\r
+#define GPIO_SECONDARY_MODULE_FUNCTION (0x02)\r
+#define GPIO_TERNARY_MODULE_FUNCTION (0x03)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the edgeSelect parameter for\r
+// functions: GPIO_selectInterruptEdge().\r
+//\r
+//*****************************************************************************\r
+#define GPIO_HIGH_TO_LOW_TRANSITION (0x01)\r
+#define GPIO_LOW_TO_HIGH_TRANSITION (0x00)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the GPIO_getInputPinValue() function.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_INPUT_PIN_HIGH (0x01)\r
+#define GPIO_INPUT_PIN_LOW (0x00)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function configures the selected Pin as output pin\r
+//!\r
+//! This function selected pins on a selected port as output pins.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxDIR register and bits of \b PxSEL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_setAsOutputPin(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function configures the selected Pin as input pin\r
+//!\r
+//! This function selected pins on a selected port as input pins.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxDIR register, bits of \b PxREN register and bits of\r
+//! \b PxSEL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_setAsInputPin(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function configures the peripheral module function in the\r
+//! output direction for the selected pin.\r
+//!\r
+//! This function configures the peripheral module function in the output\r
+//! direction for the selected pin for either primary, secondary or ternary\r
+//! module function modes. Note that MSP430F5xx/6xx family doesn't support\r
+//! these function modes.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//! \param mode is the specified mode that the pin should be configured for the\r
+//! module function.\r
+//! Valid values are:\r
+//! - \b GPIO_PRIMARY_MODULE_FUNCTION\r
+//! - \b GPIO_SECONDARY_MODULE_FUNCTION\r
+//! - \b GPIO_TERNARY_MODULE_FUNCTION\r
+//!\r
+//! Modified bits of \b PxDIR register and bits of \b PxSEL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_setAsPeripheralModuleFunctionOutputPin(uint8_t selectedPort,\r
+ uint16_t selectedPins,\r
+ uint8_t mode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function configures the peripheral module function in the input\r
+//! direction for the selected pin.\r
+//!\r
+//! This function configures the peripheral module function in the input\r
+//! direction for the selected pin for either primary, secondary or ternary\r
+//! module function modes. Note that MSP430F5xx/6xx family doesn't support\r
+//! these function modes.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//! \param mode is the specified mode that the pin should be configured for the\r
+//! module function.\r
+//! Valid values are:\r
+//! - \b GPIO_PRIMARY_MODULE_FUNCTION\r
+//! - \b GPIO_SECONDARY_MODULE_FUNCTION\r
+//! - \b GPIO_TERNARY_MODULE_FUNCTION\r
+//!\r
+//! Modified bits of \b PxDIR register and bits of \b PxSEL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_setAsPeripheralModuleFunctionInputPin(uint8_t selectedPort,\r
+ uint16_t selectedPins,\r
+ uint8_t mode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function sets output HIGH on the selected Pin\r
+//!\r
+//! This function sets output HIGH on the selected port's pin.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxOUT register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_setOutputHighOnPin(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function sets output LOW on the selected Pin\r
+//!\r
+//! This function sets output LOW on the selected port's pin.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxOUT register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_setOutputLowOnPin(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function toggles the output on the selected Pin\r
+//!\r
+//! This function toggles the output on the selected port's pin.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxOUT register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_toggleOutputOnPin(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function sets the selected Pin in input Mode with Pull Down\r
+//! resistor\r
+//!\r
+//! This function sets the selected Pin in input Mode with Pull Down resistor.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of\r
+//! \b PxREN register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_setAsInputPinWithPullDownResistor(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function sets the selected Pin in input Mode with Pull Up\r
+//! resistor\r
+//!\r
+//! This function sets the selected Pin in input Mode with Pull Up resistor.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of\r
+//! \b PxREN register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_setAsInputPinWithPullUpResistor(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function gets the input value on the selected pin\r
+//!\r
+//! This function gets the input value on the selected pin.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! \return One of the following:\r
+//! - \b GPIO_INPUT_PIN_HIGH\r
+//! - \b GPIO_INPUT_PIN_LOW\r
+//! \n indicating the status of the pin\r
+//\r
+//*****************************************************************************\r
+extern uint8_t GPIO_getInputPinValue(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function enables the port interrupt on the selected pin\r
+//!\r
+//! This function enables the port interrupt on the selected pin. Please refer\r
+//! to family user's guide for available ports with interrupt capability.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_enableInterrupt(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function disables the port interrupt on the selected pin\r
+//!\r
+//! This function disables the port interrupt on the selected pin. Please refer\r
+//! to family user's guide for available ports with interrupt capability.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_disableInterrupt(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function gets the interrupt status of the selected pin\r
+//!\r
+//! This function gets the interrupt status of the selected pin. Please refer\r
+//! to family user's guide for available ports with interrupt capability.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//! \n indicating the interrupt status of the selected pins [Default:\r
+//! 0]\r
+//\r
+//*****************************************************************************\r
+extern uint16_t GPIO_getInterruptStatus(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function clears the interrupt flag on the selected pin\r
+//!\r
+//! This function clears the interrupt flag on the selected pin. Please refer\r
+//! to family user's guide for available ports with interrupt capability.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//!\r
+//! Modified bits of \b PxIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_clearInterrupt(uint8_t selectedPort,\r
+ uint16_t selectedPins);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief This function selects on what edge the port interrupt flag should be\r
+//! set for a transition\r
+//!\r
+//! This function selects on what edge the port interrupt flag should be set\r
+//! for a transition. Values for edgeSelect should be\r
+//! GPIO_LOW_TO_HIGH_TRANSITION or GPIO_HIGH_TO_LOW_TRANSITION. Please refer to\r
+//! family user's guide for available ports with interrupt capability.\r
+//!\r
+//! \param selectedPort is the selected port.\r
+//! Valid values are:\r
+//! - \b GPIO_PORT_P1\r
+//! - \b GPIO_PORT_P2\r
+//! - \b GPIO_PORT_P3\r
+//! - \b GPIO_PORT_P4\r
+//! - \b GPIO_PORT_P5\r
+//! - \b GPIO_PORT_P6\r
+//! - \b GPIO_PORT_P7\r
+//! - \b GPIO_PORT_P8\r
+//! - \b GPIO_PORT_P9\r
+//! - \b GPIO_PORT_P10\r
+//! - \b GPIO_PORT_P11\r
+//! - \b GPIO_PORT_PA\r
+//! - \b GPIO_PORT_PB\r
+//! - \b GPIO_PORT_PC\r
+//! - \b GPIO_PORT_PD\r
+//! - \b GPIO_PORT_PE\r
+//! - \b GPIO_PORT_PF\r
+//! - \b GPIO_PORT_PJ\r
+//! \param selectedPins is the specified pin in the selected port.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b GPIO_PIN0\r
+//! - \b GPIO_PIN1\r
+//! - \b GPIO_PIN2\r
+//! - \b GPIO_PIN3\r
+//! - \b GPIO_PIN4\r
+//! - \b GPIO_PIN5\r
+//! - \b GPIO_PIN6\r
+//! - \b GPIO_PIN7\r
+//! - \b GPIO_PIN8\r
+//! - \b GPIO_PIN9\r
+//! - \b GPIO_PIN10\r
+//! - \b GPIO_PIN11\r
+//! - \b GPIO_PIN12\r
+//! - \b GPIO_PIN13\r
+//! - \b GPIO_PIN14\r
+//! - \b GPIO_PIN15\r
+//! \param edgeSelect specifies what transition sets the interrupt flag\r
+//! Valid values are:\r
+//! - \b GPIO_HIGH_TO_LOW_TRANSITION\r
+//! - \b GPIO_LOW_TO_HIGH_TRANSITION\r
+//!\r
+//! Modified bits of \b PxIES register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void GPIO_selectInterruptEdge(uint8_t selectedPort,\r
+ uint16_t selectedPins,\r
+ uint8_t edgeSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_GPIO_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+#ifndef __HW_MEMMAP__\r
+#define __HW_MEMMAP__\r
+\r
+#define __DRIVERLIB_MSP430FR5XX_6XX_FAMILY__\r
+//*****************************************************************************\r
+//\r
+// Include device specific header file\r
+//\r
+//*****************************************************************************\r
+#if defined (__MSP430FR6989__)\r
+ #include <msp430fr6989.h>\r
+#else\r
+ #include <msp430.h>\r
+#endif\r
+\r
+#if defined(__IAR_SYSTEMS_ICC__)\r
+#include "../deprecated/IAR/msp430fr5xx_6xxgeneric.h"\r
+#elif defined(__TI_COMPILER_VERSION__)\r
+#include "../deprecated/CCS/msp430fr5xx_6xxgeneric.h"\r
+#elif defined(__GNUC__)\r
+#include "msp430fr5xx_6xxgeneric.h"\r
+#else\r
+#include "msp430fr5xx_6xxgeneric.h"\r
+#endif\r
+\r
+#include "stdint.h"\r
+#include "stdbool.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// SUCCESS and FAILURE for API return value\r
+//\r
+//*****************************************************************************\r
+#define STATUS_SUCCESS 0x01\r
+#define STATUS_FAIL 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the base address of the peripherals.\r
+//\r
+//*****************************************************************************\r
+#ifdef __MSP430_HAS_ADC10_A__\r
+ #define \\r
+ ADC10_A_BASE __MSP430_BASEADDRESS_ADC10_A__\r
+#endif\r
+#ifdef __MSP430_HAS_ADC10_B__\r
+ #define \\r
+ ADC10_B_BASE __MSP430_BASEADDRESS_ADC10_B__\r
+#endif\r
+#ifdef __MSP430_HAS_ADC12_B__\r
+ #define \\r
+ ADC12_B_BASE __MSP430_BASEADDRESS_ADC12_B__\r
+#endif\r
+#ifdef __MSP430_HAS_ADC12_PLUS__\r
+ #define \\r
+ ADC12_A_BASE __MSP430_BASEADDRESS_ADC12_PLUS__\r
+#endif\r
+#ifdef __MSP430_HAS_AES256__\r
+ #define \\r
+ AES256_BASE __MSP430_BASEADDRESS_AES256__\r
+#endif\r
+#ifdef __MSP430_HAS_AES__\r
+ #define \\r
+ AES_BASE __MSP430_BASEADDRESS_AES__\r
+#endif\r
+#ifdef __MSP430_HAS_AUX_SUPPLY__\r
+ #define \\r
+ AUX_SUPPLY_BASE __MSP430_BASEADDRESS_AUX_SUPPLY__\r
+#endif\r
+#ifdef __MSP430_HAS_BACKUP_RAM__\r
+ #define \\r
+ BAK_RAM_BASE __MSP430_BASEADDRESS_BACKUP_RAM__\r
+#endif\r
+#ifdef __MSP430_HAS_BATTERY_CHARGER__\r
+ #define \\r
+ BAK_BATT_BASE __MSP430_BASEADDRESS_BATTERY_CHARGER__\r
+#endif\r
+#ifdef __MSP430_HAS_CAP_SENSE_IO_0__\r
+ #define \\r
+ CAP_TOUCH_0_BASE __MSP430_BASEADDRESS_CAP_SENSE_IO_0__\r
+#endif\r
+#ifdef __MSP430_HAS_CAP_SENSE_IO_1__\r
+ #define \\r
+ CAP_TOUCH_1_BASE __MSP430_BASEADDRESS_CAP_SENSE_IO_1__\r
+#endif\r
+#ifdef __MSP430_HAS_COMPB__\r
+ #define \\r
+ COMP_B_BASE __MSP430_BASEADDRESS_COMPB__\r
+#endif\r
+#ifdef __MSP430_HAS_COMPD__\r
+ #define \\r
+ COMP_D_BASE __MSP430_BASEADDRESS_COMPD__\r
+#endif\r
+#ifdef __MSP430_HAS_COMP_E__\r
+ #define \\r
+ COMP_E_BASE __MSP430_BASEADDRESS_COMP_E__\r
+#endif\r
+#ifdef __MSP430_HAS_COMPE__\r
+ #define \\r
+ __MSP430_BASEADDRESS_COMP_E__ __MSP430_BASEADDRESS_COMPE__\r
+#ifndef COMP_E_VECTOR\r
+#ifdef COMP_B_VECTOR\r
+#define COMP_E_VECTOR COMP_B_VECTOR\r
+#endif\r
+#endif\r
+\r
+#ifndef COMP_B_VECTOR\r
+#ifdef COMP_E_VECTOR\r
+#define COMP_B_VECTOR COMP_E_VECTOR\r
+#endif\r
+#endif\r
+#endif\r
+\r
+#ifdef __MSP430_HAS_COMP_E__\r
+ #define \\r
+ __MSP430_BASEADDRESS_COMPE__ __MSP430_BASEADDRESS_COMP_E__\r
+#ifndef COMP_B_VECTOR\r
+#ifdef COMP_E_VECTOR\r
+#define COMP_B_VECTOR COMP_E_VECTOR\r
+#endif\r
+#endif\r
+#ifndef COMP_E_VECTOR\r
+#ifdef COMP_B_VECTOR\r
+#define COMP_E_VECTOR COMP_B_VECTOR\r
+#endif\r
+#endif\r
+#endif\r
+#ifdef __MSP430_HAS_CRC__\r
+ #define \\r
+ CRC_BASE __MSP430_BASEADDRESS_CRC__\r
+#endif\r
+#ifdef __MSP430_HAS_CS__\r
+\r
+#ifndef __MSP430_BASEADDRESS_CS_A__\r
+#define __MSP430_BASEADDRESS_CS_A__ __MSP430_BASEADDRESS_CS__\r
+#endif\r
+#endif\r
+#ifdef __MSP430_HAS_CS_A__\r
+ #define \\r
+ CS_BASE __MSP430_BASEADDRESS_CS_A__\r
+#ifndef __MSP430_BASEADDRESS_CS__\r
+#define __MSP430_BASEADDRESS_CS__ __MSP430_BASEADDRESS_CS_A__\r
+#endif\r
+#endif\r
+#ifdef __MSP430_HAS_DAC12_2__\r
+ #define \\r
+ DAC12_A_BASE __MSP430_BASEADDRESS_DAC12_2__\r
+#endif\r
+#ifdef __MSP430_HAS_DMAX_3__\r
+ #define \\r
+ DMA_BASE __MSP430_BASEADDRESS_DMAX_3__\r
+#endif\r
+#ifdef __MSP430_HAS_DMAX_6__\r
+ #define \\r
+ DMA_BASE __MSP430_BASEADDRESS_DMAX_6__\r
+#endif\r
+#ifdef __MSP430_HAS_EUSCI_A0__\r
+ #define \\r
+ EUSCI_A0_BASE __MSP430_BASEADDRESS_EUSCI_A0__\r
+#endif\r
+#ifdef __MSP430_HAS_EUSCI_A1__\r
+ #define \\r
+ EUSCI_A1_BASE __MSP430_BASEADDRESS_EUSCI_A1__\r
+#endif\r
+#ifdef __MSP430_HAS_EUSCI_A2__\r
+ #define \\r
+ EUSCI_A2_BASE __MSP430_BASEADDRESS_EUSCI_A2__\r
+#endif\r
+#ifdef __MSP430_HAS_EUSCI_A3__\r
+ #define \\r
+ EUSCI_A3_BASE __MSP430_BASEADDRESS_EUSCI_A3__\r
+#endif\r
+#ifdef __MSP430_HAS_EUSCI_B0__\r
+ #define \\r
+ EUSCI_B0_BASE __MSP430_BASEADDRESS_EUSCI_B0__\r
+#endif\r
+#ifdef __MSP430_HAS_EUSCI_B1__\r
+ #define \\r
+ EUSCI_B1_BASE __MSP430_BASEADDRESS_EUSCI_B1__\r
+#endif\r
+#ifdef __MSP430_HAS_FLASH__\r
+ #define \\r
+ FLASH_BASE __MSP430_BASEADDRESS_FLASH__\r
+#endif\r
+#ifdef __MSP430_HAS_FRAM_FR5XX__\r
+ #define \\r
+ FRAM_BASE __MSP430_BASEADDRESS_FRAM_FR5XX__\r
+#endif\r
+#ifdef __MSP430_HAS_FRAM__\r
+ #define \\r
+ FRAM_BASE __MSP430_BASEADDRESS_FRAM__\r
+#endif\r
+#ifdef __MSP430_HAS_LCD_B__\r
+ #define \\r
+ LCD_B_BASE __MSP430_BASEADDRESS_LCD_B__\r
+#endif\r
+#ifdef __MSP430_HAS_LCD_C__\r
+ #define \\r
+ LCD_C_BASE __MSP430_BASEADDRESS_LCD_C__\r
+#endif\r
+#ifdef __MSP430_HAS_MPU_A__\r
+ #define \\r
+ MPU_BASE __MSP430_BASEADDRESS_MPU_A__\r
+#ifndef __MSP430_BASEADDRESS_MPU__\r
+#define __MSP430_BASEADDRESS_MPU__ __MSP430_BASEADDRESS_MPU_A__\r
+#endif\r
+#endif\r
+#ifdef __MSP430_HAS_MPU__\r
+\r
+#ifndef __MSP430_BASEADDRESS_MPU_A__\r
+#define __MSP430_BASEADDRESS_MPU_A__ __MSP430_BASEADDRESS_MPU__\r
+#endif\r
+#endif\r
+#ifdef __MSP430_HAS_MPY32__\r
+ #define \\r
+ MPY32_BASE __MSP430_BASEADDRESS_MPY32__\r
+#endif\r
+#ifdef __MSP430_HAS_PMM_FR5xx__\r
+ #define \\r
+ PMM_BASE __MSP430_BASEADDRESS_PMM_FR5xx__\r
+#endif\r
+#ifdef __MSP430_HAS_PMM_FRAM__\r
+ #define \\r
+ PMM_BASE __MSP430_BASEADDRESS_PMM_FRAM__\r
+#endif\r
+#ifdef __MSP430_HAS_PMM__\r
+ #define \\r
+ PMM_BASE __MSP430_BASEADDRESS_PMM__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT10_R__\r
+ #define \\r
+ P10_BASE __MSP430_BASEADDRESS_PORT10_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT11_R__\r
+ #define \\r
+ P11_BASE __MSP430_BASEADDRESS_PORT11_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT1_MAPPING__\r
+ #define \\r
+ P1MAP_BASE __MSP430_BASEADDRESS_PORT1_MAPPING__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT1_R__\r
+ #define \\r
+ P1_BASE __MSP430_BASEADDRESS_PORT1_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT2_MAPPING__\r
+ #define \\r
+ P2MAP_BASE __MSP430_BASEADDRESS_PORT2_MAPPING__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT2_R__\r
+ #define \\r
+ P2_BASE __MSP430_BASEADDRESS_PORT2_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT3_MAPPING__\r
+ #define \\r
+ P3MAP_BASE __MSP430_BASEADDRESS_PORT3_MAPPING__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT3_R__\r
+ #define \\r
+ P3_BASE __MSP430_BASEADDRESS_PORT3_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT4_MAPPING__\r
+ #define \\r
+ P4MAP_BASE __MSP430_BASEADDRESS_PORT4_MAPPING__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT4_R__\r
+ #define \\r
+ P4_BASE __MSP430_BASEADDRESS_PORT4_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT5_R__\r
+ #define \\r
+ P5_BASE __MSP430_BASEADDRESS_PORT5_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT6_R__\r
+ #define \\r
+ P6_BASE __MSP430_BASEADDRESS_PORT6_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT7_R__\r
+ #define \\r
+ P7_BASE __MSP430_BASEADDRESS_PORT7_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT8_R__\r
+ #define \\r
+ P8_BASE __MSP430_BASEADDRESS_PORT8_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT9_R__\r
+ #define \\r
+ P9_BASE __MSP430_BASEADDRESS_PORT9_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORTA_R__\r
+ #define \\r
+ PA_BASE __MSP430_BASEADDRESS_PORTA_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORTB_R__\r
+ #define \\r
+ PB_BASE __MSP430_BASEADDRESS_PORTB_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORTC_R__\r
+ #define \\r
+ PC_BASE __MSP430_BASEADDRESS_PORTC_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORTD_R__\r
+ #define \\r
+ PD_BASE __MSP430_BASEADDRESS_PORTD_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORTE_R__\r
+ #define \\r
+ PE_BASE __MSP430_BASEADDRESS_PORTE_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORTF_R__\r
+ #define \\r
+ PF_BASE __MSP430_BASEADDRESS_PORTF_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORTJ_R__\r
+ #define \\r
+ PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__\r
+#endif\r
+#ifdef __MSP430_HAS_PORT_MAPPING__\r
+ #define \\r
+ PMAP_CTRL_BASE __MSP430_BASEADDRESS_PORT_MAPPING__\r
+#endif\r
+#ifdef __MSP430_HAS_PU__\r
+ #define \\r
+ LDOPWR_BASE __MSP430_BASEADDRESS_PU__\r
+#endif\r
+#ifdef __MSP430_HAS_RC__\r
+ #define \\r
+ RAM_BASE __MSP430_BASEADDRESS_RC__\r
+#endif\r
+#ifdef __MSP430_HAS_REF_A__\r
+ #define \\r
+ REF_A_BASE __MSP430_BASEADDRESS_REF_A__\r
+#endif\r
+#ifdef __MSP430_HAS_REF__\r
+ #define \\r
+ REF_BASE __MSP430_BASEADDRESS_REF__\r
+#endif\r
+#ifdef __MSP430_HAS_RTC_B__\r
+ #define \\r
+ RTC_B_BASE __MSP430_BASEADDRESS_RTC_B__\r
+#endif\r
+#ifdef __MSP430_HAS_RTC_C__\r
+ #define \\r
+ RTC_C_BASE __MSP430_BASEADDRESS_RTC_C__\r
+#endif\r
+#ifdef __MSP430_HAS_RTC_D__\r
+ #define \\r
+ RTC_D_BASE __MSP430_BASEADDRESS_RTC_D__\r
+#endif\r
+#ifdef __MSP430_HAS_RTC__\r
+ #define \\r
+ RTC_A_BASE __MSP430_BASEADDRESS_RTC__\r
+#endif\r
+#ifdef __MSP430_HAS_SD24_B__\r
+ #define \\r
+ SD24_BASE __MSP430_BASEADDRESS_SD24_B__\r
+#endif\r
+#ifdef __MSP430_HAS_SFR__\r
+ #define \\r
+ SFR_BASE __MSP430_BASEADDRESS_SFR__\r
+#endif\r
+#ifdef __MSP430_HAS_SYS__\r
+ #define \\r
+ SYS_BASE __MSP430_BASEADDRESS_SYS__\r
+#endif\r
+#ifdef __MSP430_HAS_T0A3__\r
+ #define \\r
+ TIMER_A0_BASE __MSP430_BASEADDRESS_T0A3__\r
+#endif\r
+#ifdef __MSP430_HAS_T0A5__\r
+ #define \\r
+ TIMER_A0_BASE __MSP430_BASEADDRESS_T0A5__\r
+#endif\r
+#ifdef __MSP430_HAS_T0B3__\r
+ #define \\r
+ TIMER_B0_BASE __MSP430_BASEADDRESS_T0B3__\r
+#endif\r
+#ifdef __MSP430_HAS_T0B7__\r
+ #define \\r
+ TIMER_B0_BASE __MSP430_BASEADDRESS_T0B7__\r
+#endif\r
+#ifdef __MSP430_HAS_T0D3__\r
+ #define \\r
+ TIMER_D0_BASE __MSP430_BASEADDRESS_T0D3__\r
+#endif\r
+#ifdef __MSP430_HAS_T1A2__\r
+ #define \\r
+ TIMER_A1_BASE __MSP430_BASEADDRESS_T1A2__\r
+#endif\r
+#ifdef __MSP430_HAS_T1A3__\r
+ #define \\r
+ TIMER_A1_BASE __MSP430_BASEADDRESS_T1A3__\r
+#endif\r
+#ifdef __MSP430_HAS_T1B3__\r
+ #define \\r
+ TIMER_B1_BASE __MSP430_BASEADDRESS_T1B3__\r
+#endif\r
+#ifdef __MSP430_HAS_T1D3__\r
+ #define \\r
+ TIMER_D1_BASE __MSP430_BASEADDRESS_T1D3__\r
+#endif\r
+#ifdef __MSP430_HAS_T2A2__\r
+ #define \\r
+ TIMER_A2_BASE __MSP430_BASEADDRESS_T2A2__\r
+#endif\r
+#ifdef __MSP430_HAS_T2A3__\r
+ #define \\r
+ TIMER_A2_BASE __MSP430_BASEADDRESS_T2A3__\r
+#endif\r
+#ifdef __MSP430_HAS_T2B3__\r
+ #define \\r
+ TIMER_B2_BASE __MSP430_BASEADDRESS_T2B3__\r
+#endif\r
+#ifdef __MSP430_HAS_T3A2__\r
+ #define \\r
+ TIMER_A3_BASE __MSP430_BASEADDRESS_T3A2__\r
+#endif\r
+#ifdef __MSP430_HAS_TEV0__\r
+ #define \\r
+ TEC0_BASE __MSP430_BASEADDRESS_TEV0__\r
+#endif\r
+#ifdef __MSP430_HAS_TEV1__\r
+ #define \\r
+ TEC1_BASE __MSP430_BASEADDRESS_TEV1__\r
+#endif\r
+#ifdef __MSP430_HAS_UCS__\r
+ #define \\r
+ UCS_BASE __MSP430_BASEADDRESS_UCS__\r
+#endif\r
+#ifdef __MSP430_HAS_USB__\r
+ #define \\r
+ USB_BASE __MSP430_BASEADDRESS_USB__\r
+#endif\r
+#ifdef __MSP430_HAS_USCI_A0__\r
+ #define \\r
+ USCI_A0_BASE __MSP430_BASEADDRESS_USCI_A0__\r
+#endif\r
+#ifdef __MSP430_HAS_USCI_A1__\r
+ #define \\r
+ USCI_A1_BASE __MSP430_BASEADDRESS_USCI_A1__\r
+#endif\r
+#ifdef __MSP430_HAS_USCI_A2__\r
+ #define \\r
+ USCI_A2_BASE __MSP430_BASEADDRESS_USCI_A2__\r
+#endif\r
+#ifdef __MSP430_HAS_USCI_A3__\r
+ #define \\r
+ USCI_A3_BASE __MSP430_BASEADDRESS_USCI_A3__\r
+#endif\r
+#ifdef __MSP430_HAS_USCI_B0__\r
+ #define \\r
+ USCI_B0_BASE __MSP430_BASEADDRESS_USCI_B0__\r
+#endif\r
+#ifdef __MSP430_HAS_USCI_B1__\r
+ #define \\r
+ USCI_B1_BASE __MSP430_BASEADDRESS_USCI_B1__\r
+#endif\r
+#ifdef __MSP430_HAS_USCI_B2__\r
+ #define \\r
+ USCI_B2_BASE __MSP430_BASEADDRESS_USCI_B2__\r
+#endif\r
+#ifdef __MSP430_HAS_USCI_B3__\r
+ #define \\r
+ USCI_B3_BASE __MSP430_BASEADDRESS_USCI_B3__\r
+#endif\r
+#ifdef __MSP430_HAS_WDT_A__\r
+ #define \\r
+ WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__\r
+#endif\r
+\r
+#endif // #ifndef __HW_MEMMAP__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+#ifndef __HW_REGACCESS__\r
+#define __HW_REGACCESS__\r
+\r
+#include "stdint.h"\r
+#include "stdbool.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Macro for enabling assert statements for debugging\r
+//\r
+//*****************************************************************************\r
+#define NDEBUG\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access\r
+//\r
+//*****************************************************************************\r
+#define HWREG32(x) \\r
+ (*((volatile uint32_t *)((uint16_t)x)))\r
+#define HWREG16(x) \\r
+ (*((volatile uint16_t *)((uint16_t)x)))\r
+#define HWREG8(x) \\r
+ (*((volatile uint8_t *)((uint16_t)x)))\r
+\r
+//*****************************************************************************\r
+//\r
+// SUCCESS and FAILURE for API return value\r
+//\r
+//*****************************************************************************\r
+#define STATUS_SUCCESS 0x01\r
+#define STATUS_FAIL 0x00\r
+\r
+#endif // #ifndef __HW_REGACCESS__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+#ifndef __HW_TYPES__\r
+#define __HW_TYPES__\r
+\r
+//*****************************************************************************\r
+//\r
+// Macro for enabling assert statements for debugging\r
+//\r
+//*****************************************************************************\r
+#define NDEBUG\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned int *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+\r
+//*****************************************************************************\r
+//\r
+// SUCCESS and FAILURE for API return value\r
+//\r
+//*****************************************************************************\r
+#define STATUS_SUCCESS 0x01\r
+#define STATUS_FAIL 0x00\r
+\r
+#endif // #ifndef __HW_TYPES__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+#ifndef __DRIVERLIB_VERSION__\r
+ #define DRIVERLIB_VER_MAJOR 2\r
+ #define DRIVERLIB_VER_MINOR 00\r
+ #define DRIVERLIB_VER_PATCH 00\r
+ #define DRIVERLIB_VER_BUILD 16\r
+#endif\r
+\r
+#define getVersion() ((uint32_t)DRIVERLIB_VER_MAJOR << 24 | \\r
+ (uint32_t)DRIVERLIB_VER_MINOR << 16 | \\r
+ (uint32_t)DRIVERLIB_VER_PATCH << 8 | \\r
+ (uint32_t)DRIVERLIB_VER_BUILD)\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// lcd_c.c - Driver for the lcd_c Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup lcd_c_api lcd_c\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_LCD_C__\r
+#include "lcd_c.h"\r
+\r
+#include <assert.h>\r
+\r
+//*****************************************************************************\r
+//\r
+// Initialization parameter instance\r
+//\r
+//*****************************************************************************\r
+const LCD_C_initParam LCD_C_INIT_PARAM = {\r
+ LCD_C_CLOCKSOURCE_ACLK,\r
+ LCD_C_CLOCKDIVIDER_1,\r
+ LCD_C_CLOCKPRESCALAR_1,\r
+ LCD_C_STATIC,\r
+ LCD_C_STANDARD_WAVEFORMS,\r
+ LCD_C_SEGMENTS_DISABLED\r
+};\r
+\r
+static void setLCDFunction(uint16_t baseAddress,\r
+ uint8_t index,\r
+ uint16_t value)\r
+{\r
+ switch(index)\r
+ {\r
+ case 0:\r
+ HWREG16(baseAddress + OFS_LCDCPCTL0) |= value;\r
+ break;\r
+ case 1:\r
+ HWREG16(baseAddress + OFS_LCDCPCTL1) |= value;\r
+ break;\r
+ case 2:\r
+ HWREG16(baseAddress + OFS_LCDCPCTL2) |= value;\r
+ break;\r
+ case 3:\r
+ HWREG16(baseAddress + OFS_LCDCPCTL3) |= value;\r
+ break;\r
+ default: break;\r
+ }\r
+}\r
+\r
+void LCD_C_init(uint16_t baseAddress,\r
+ LCD_C_initParam *initParams)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~(LCDMX0 | LCDMX1 | LCDMX2 | LCDSSEL\r
+ | LCDLP | LCDSON | LCDDIV_31);\r
+\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->muxRate;\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->clockSource;\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->waveforms;\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->segments;\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->clockDivider;\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->clockPrescalar;\r
+}\r
+\r
+void LCD_C_on(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) |= LCDON;\r
+}\r
+\r
+void LCD_C_off(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+}\r
+\r
+void LCD_C_clearInterrupt(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ HWREG8(baseAddress + OFS_LCDCCTL1_L) &= ~(mask >> 8);\r
+}\r
+\r
+uint16_t LCD_C_getInterruptStatus(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ return (HWREG8(baseAddress + OFS_LCDCCTL1_L) & (mask >> 8));\r
+}\r
+\r
+void LCD_C_enableInterrupt(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL1) |= mask;\r
+}\r
+\r
+void LCD_C_disableInterrupt(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL1) &= ~mask;\r
+}\r
+\r
+void LCD_C_clearMemory(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCMEMCTL) |= LCDCLRM;\r
+}\r
+\r
+void LCD_C_clearBlinkingMemory(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCMEMCTL) |= LCDCLRBM;\r
+}\r
+\r
+void LCD_C_selectDisplayMemory(uint16_t baseAddress,\r
+ uint16_t displayMemory)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCMEMCTL) &= ~LCDDISP;\r
+ HWREG16(baseAddress + OFS_LCDCMEMCTL) |= displayMemory;\r
+}\r
+\r
+void LCD_C_setBlinkingControl(uint16_t baseAddress,\r
+ uint8_t clockDivider,\r
+ uint8_t clockPrescalar,\r
+ uint8_t mode)\r
+{\r
+ HWREG16(baseAddress +\r
+ OFS_LCDCBLKCTL) &= ~(LCDBLKDIV0 | LCDBLKDIV1 | LCDBLKDIV2 |\r
+ LCDBLKPRE0 | LCDBLKPRE1 |\r
+ LCDBLKPRE2 |\r
+ LCDBLKMOD0 | LCDBLKMOD1\r
+ );\r
+ HWREG16(baseAddress +\r
+ OFS_LCDCBLKCTL) |= clockDivider | clockPrescalar | mode;\r
+}\r
+\r
+void LCD_C_enableChargePump(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) |= LCDCPEN;\r
+}\r
+\r
+void LCD_C_disableChargePump(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) &= ~LCDCPEN;\r
+}\r
+\r
+void LCD_C_selectBias(uint16_t baseAddress,\r
+ uint16_t bias)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) &= ~LCD2B;\r
+\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) |= bias;\r
+}\r
+\r
+void LCD_C_selectChargePumpReference(uint16_t baseAddress,\r
+ uint16_t reference)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) &= ~VLCDREF_3;\r
+\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) |= reference;\r
+}\r
+\r
+void LCD_C_setVLCDSource(uint16_t baseAddress,\r
+ uint16_t vlcdSource,\r
+ uint16_t v2v3v4Source,\r
+ uint16_t v5Source)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) &= ~VLCDEXT;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) &= ~LCDREXT;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) &= ~LCDEXTBIAS;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) &= ~R03EXT;\r
+\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) |= vlcdSource;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) |= v2v3v4Source;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) |= v5Source;\r
+}\r
+\r
+void LCD_C_setVLCDVoltage(uint16_t baseAddress,\r
+ uint16_t voltage)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) &= ~VLCD_15;\r
+\r
+ HWREG16(baseAddress + OFS_LCDCVCTL) |= voltage;\r
+}\r
+\r
+void LCD_C_setPinAsLCDFunction(uint16_t baseAddress,\r
+ uint8_t pin)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+\r
+ uint8_t idx = pin >> 4;\r
+ uint16_t val = 1 << (pin & 0xF);\r
+\r
+ setLCDFunction(baseAddress, idx, val);\r
+}\r
+\r
+void LCD_C_setPinAsPortFunction(uint16_t baseAddress,\r
+ uint8_t pin)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+\r
+ uint8_t idx = pin >> 4;\r
+ uint16_t val = 1 << (pin & 0xF);\r
+\r
+ switch(idx)\r
+ {\r
+ case 0:\r
+ HWREG16(baseAddress + OFS_LCDCPCTL0) &= ~val;\r
+ break;\r
+ case 1:\r
+ HWREG16(baseAddress + OFS_LCDCPCTL1) &= ~val;\r
+ break;\r
+ case 2:\r
+ HWREG16(baseAddress + OFS_LCDCPCTL2) &= ~val;\r
+ break;\r
+ case 3:\r
+ HWREG16(baseAddress + OFS_LCDCPCTL3) &= ~val;\r
+ break;\r
+ default: break;\r
+ }\r
+}\r
+\r
+void LCD_C_setPinAsLCDFunctionEx(uint16_t baseAddress,\r
+ uint8_t startPin,\r
+ uint8_t endPin)\r
+{\r
+ uint8_t startIdx = startPin >> 4;\r
+ uint8_t endIdx = endPin >> 4;\r
+ uint8_t startPos = startPin & 0xF;\r
+ uint8_t endPos = endPin & 0xF;\r
+ uint16_t val = 0;\r
+ uint8_t i = 0;\r
+\r
+ HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON;\r
+\r
+ if(startIdx == endIdx)\r
+ {\r
+ val = (0xFFFF >> (15 - endPos)) & (0xFFFF << startPos);\r
+\r
+ setLCDFunction(baseAddress, startIdx, val);\r
+ }\r
+ else\r
+ {\r
+ val = 0xFFFF >> (15 - endPos);\r
+ setLCDFunction(baseAddress, endIdx, val);\r
+\r
+ for(i = endIdx - 1; i > startIdx; i--)\r
+ {\r
+ setLCDFunction(baseAddress, i, 0xFFFF);\r
+ }\r
+\r
+ val = 0xFFFF << startPos;\r
+ setLCDFunction(baseAddress, startIdx, val);\r
+ }\r
+}\r
+\r
+void LCD_C_setMemory(uint16_t baseAddress,\r
+ uint8_t pin,\r
+ uint8_t value)\r
+{\r
+ uint8_t muxRate = HWREG16(baseAddress + OFS_LCDCCTL0)\r
+ & (LCDMX2 | LCDMX1 | LCDMX0);\r
+\r
+ // static, 2-mux, 3-mux, 4-mux\r
+ if(muxRate <= (LCDMX1 | LCDMX0))\r
+ {\r
+ if(pin & 1)\r
+ {\r
+ HWREG8(baseAddress + OFS_LCDM1 + pin / 2) &= 0x0F;\r
+ HWREG8(baseAddress + OFS_LCDM1 + pin / 2) |= (value & 0xF) << 4;\r
+ }\r
+ else\r
+ {\r
+ HWREG8(baseAddress + OFS_LCDM1 + pin / 2) &= 0xF0;\r
+ HWREG8(baseAddress + OFS_LCDM1 + pin / 2) |= (value & 0xF);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ //5-mux, 6-mux, 7-mux, 8-mux\r
+ HWREG8(baseAddress + OFS_LCDM1 + pin) = value;\r
+ }\r
+}\r
+\r
+void LCD_C_setBlinkingMemory(uint16_t baseAddress,\r
+ uint8_t pin,\r
+ uint8_t value)\r
+{\r
+ uint8_t muxRate = HWREG16(baseAddress + OFS_LCDCCTL0)\r
+ & (LCDMX2 | LCDMX1 | LCDMX0);\r
+\r
+ // static, 2-mux, 3-mux, 4-mux\r
+ if(muxRate <= (LCDMX1 | LCDMX0))\r
+ {\r
+ if(pin & 1)\r
+ {\r
+ HWREG8(baseAddress + OFS_LCDBM1 + pin / 2) &= 0x0F;\r
+ HWREG8(baseAddress + OFS_LCDBM1 + pin / 2) |= (value & 0xF) << 4;\r
+ }\r
+ else\r
+ {\r
+ HWREG8(baseAddress + OFS_LCDBM1 + pin / 2) &= 0xF0;\r
+ HWREG8(baseAddress + OFS_LCDBM1 + pin / 2) |= (value & 0xF);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ //5-mux, 6-mux, 7-mux, 8-mux\r
+ HWREG8(baseAddress + OFS_LCDBM1 + pin) = value;\r
+ }\r
+}\r
+\r
+void LCD_C_configChargePump(uint16_t baseAddress,\r
+ uint16_t syncToClock,\r
+ uint16_t functionControl)\r
+{\r
+ HWREG16(baseAddress + OFS_LCDCCPCTL) &= ~(LCDCPCLKSYNC);\r
+ HWREG16(baseAddress + OFS_LCDCCPCTL) &= ~(LCDCPDIS7 | LCDCPDIS6 | LCDCPDIS5\r
+ | LCDCPDIS4 | LCDCPDIS3 |\r
+ LCDCPDIS2 | LCDCPDIS1 |\r
+ LCDCPDIS0);\r
+\r
+ HWREG16(baseAddress + OFS_LCDCCPCTL) |= syncToClock | functionControl;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for lcd_c_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// lcd_c.h - Driver for the LCD_C Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_LCD_C_H__\r
+#define __MSP430WARE_LCD_C_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_LCD_C__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the LCD_C_init() function as the initParams parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct LCD_C_initParam\r
+{\r
+ //! Selects the clock that will be used by the LCD.\r
+ //! \n Valid values are:\r
+ //! - \b LCD_C_CLOCKSOURCE_ACLK [Default]\r
+ //! - \b LCD_C_CLOCKSOURCE_VLOCLK\r
+ uint16_t clockSource;\r
+ //! Selects the divider for LCD_frequency.\r
+ //! \n Valid values are:\r
+ //! - \b LCD_C_CLOCKDIVIDER_1 [Default]\r
+ //! - \b LCD_C_CLOCKDIVIDER_2\r
+ //! - \b LCD_C_CLOCKDIVIDER_3\r
+ //! - \b LCD_C_CLOCKDIVIDER_4\r
+ //! - \b LCD_C_CLOCKDIVIDER_5\r
+ //! - \b LCD_C_CLOCKDIVIDER_6\r
+ //! - \b LCD_C_CLOCKDIVIDER_7\r
+ //! - \b LCD_C_CLOCKDIVIDER_8\r
+ //! - \b LCD_C_CLOCKDIVIDER_9\r
+ //! - \b LCD_C_CLOCKDIVIDER_10\r
+ //! - \b LCD_C_CLOCKDIVIDER_11\r
+ //! - \b LCD_C_CLOCKDIVIDER_12\r
+ //! - \b LCD_C_CLOCKDIVIDER_13\r
+ //! - \b LCD_C_CLOCKDIVIDER_14\r
+ //! - \b LCD_C_CLOCKDIVIDER_15\r
+ //! - \b LCD_C_CLOCKDIVIDER_16\r
+ //! - \b LCD_C_CLOCKDIVIDER_17\r
+ //! - \b LCD_C_CLOCKDIVIDER_18\r
+ //! - \b LCD_C_CLOCKDIVIDER_19\r
+ //! - \b LCD_C_CLOCKDIVIDER_20\r
+ //! - \b LCD_C_CLOCKDIVIDER_21\r
+ //! - \b LCD_C_CLOCKDIVIDER_22\r
+ //! - \b LCD_C_CLOCKDIVIDER_23\r
+ //! - \b LCD_C_CLOCKDIVIDER_24\r
+ //! - \b LCD_C_CLOCKDIVIDER_25\r
+ //! - \b LCD_C_CLOCKDIVIDER_26\r
+ //! - \b LCD_C_CLOCKDIVIDER_27\r
+ //! - \b LCD_C_CLOCKDIVIDER_28\r
+ //! - \b LCD_C_CLOCKDIVIDER_29\r
+ //! - \b LCD_C_CLOCKDIVIDER_30\r
+ //! - \b LCD_C_CLOCKDIVIDER_31\r
+ //! - \b LCD_C_CLOCKDIVIDER_32\r
+ uint16_t clockDivider;\r
+ //! Selects the prescalar for frequency.\r
+ //! \n Valid values are:\r
+ //! - \b LCD_C_CLOCKPRESCALAR_1 [Default]\r
+ //! - \b LCD_C_CLOCKPRESCALAR_2\r
+ //! - \b LCD_C_CLOCKPRESCALAR_4\r
+ //! - \b LCD_C_CLOCKPRESCALAR_8\r
+ //! - \b LCD_C_CLOCKPRESCALAR_16\r
+ //! - \b LCD_C_CLOCKPRESCALAR_32\r
+ uint16_t clockPrescalar;\r
+ //! Selects LCD mux rate.\r
+ //! \n Valid values are:\r
+ //! - \b LCD_C_STATIC [Default]\r
+ //! - \b LCD_C_2_MUX\r
+ //! - \b LCD_C_3_MUX\r
+ //! - \b LCD_C_4_MUX\r
+ //! - \b LCD_C_5_MUX\r
+ //! - \b LCD_C_6_MUX\r
+ //! - \b LCD_C_7_MUX\r
+ //! - \b LCD_C_8_MUX\r
+ uint16_t muxRate;\r
+ //! Selects LCD waveform mode.\r
+ //! \n Valid values are:\r
+ //! - \b LCD_C_STANDARD_WAVEFORMS [Default]\r
+ //! - \b LCD_C_LOW_POWER_WAVEFORMS\r
+ uint16_t waveforms;\r
+ //! Sets LCD segment on/off.\r
+ //! \n Valid values are:\r
+ //! - \b LCD_C_SEGMENTS_DISABLED [Default]\r
+ //! - \b LCD_C_SEGMENTS_ENABLED\r
+ uint16_t segments;\r
+} LCD_C_initParam;\r
+\r
+extern const LCD_C_initParam LCD_C_INIT_PARAM;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the initParams parameter for\r
+// functions: LCD_C_init().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_CLOCKSOURCE_ACLK (0x0)\r
+#define LCD_C_CLOCKSOURCE_VLOCLK (LCDSSEL)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the initParams parameter for\r
+// functions: LCD_C_init().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_CLOCKDIVIDER_1 (LCDDIV_0)\r
+#define LCD_C_CLOCKDIVIDER_2 (LCDDIV_1)\r
+#define LCD_C_CLOCKDIVIDER_3 (LCDDIV_2)\r
+#define LCD_C_CLOCKDIVIDER_4 (LCDDIV_3)\r
+#define LCD_C_CLOCKDIVIDER_5 (LCDDIV_4)\r
+#define LCD_C_CLOCKDIVIDER_6 (LCDDIV_5)\r
+#define LCD_C_CLOCKDIVIDER_7 (LCDDIV_6)\r
+#define LCD_C_CLOCKDIVIDER_8 (LCDDIV_7)\r
+#define LCD_C_CLOCKDIVIDER_9 (LCDDIV_8)\r
+#define LCD_C_CLOCKDIVIDER_10 (LCDDIV_9)\r
+#define LCD_C_CLOCKDIVIDER_11 (LCDDIV_10)\r
+#define LCD_C_CLOCKDIVIDER_12 (LCDDIV_11)\r
+#define LCD_C_CLOCKDIVIDER_13 (LCDDIV_12)\r
+#define LCD_C_CLOCKDIVIDER_14 (LCDDIV_13)\r
+#define LCD_C_CLOCKDIVIDER_15 (LCDDIV_14)\r
+#define LCD_C_CLOCKDIVIDER_16 (LCDDIV_15)\r
+#define LCD_C_CLOCKDIVIDER_17 (LCDDIV_16)\r
+#define LCD_C_CLOCKDIVIDER_18 (LCDDIV_17)\r
+#define LCD_C_CLOCKDIVIDER_19 (LCDDIV_18)\r
+#define LCD_C_CLOCKDIVIDER_20 (LCDDIV_19)\r
+#define LCD_C_CLOCKDIVIDER_21 (LCDDIV_20)\r
+#define LCD_C_CLOCKDIVIDER_22 (LCDDIV_21)\r
+#define LCD_C_CLOCKDIVIDER_23 (LCDDIV_22)\r
+#define LCD_C_CLOCKDIVIDER_24 (LCDDIV_23)\r
+#define LCD_C_CLOCKDIVIDER_25 (LCDDIV_24)\r
+#define LCD_C_CLOCKDIVIDER_26 (LCDDIV_25)\r
+#define LCD_C_CLOCKDIVIDER_27 (LCDDIV_26)\r
+#define LCD_C_CLOCKDIVIDER_28 (LCDDIV_27)\r
+#define LCD_C_CLOCKDIVIDER_29 (LCDDIV_28)\r
+#define LCD_C_CLOCKDIVIDER_30 (LCDDIV_29)\r
+#define LCD_C_CLOCKDIVIDER_31 (LCDDIV_30)\r
+#define LCD_C_CLOCKDIVIDER_32 (LCDDIV_31)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the initParams parameter for\r
+// functions: LCD_C_init().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_CLOCKPRESCALAR_1 (LCDPRE_0)\r
+#define LCD_C_CLOCKPRESCALAR_2 (LCDPRE_1)\r
+#define LCD_C_CLOCKPRESCALAR_4 (LCDPRE_2)\r
+#define LCD_C_CLOCKPRESCALAR_8 (LCDPRE_3)\r
+#define LCD_C_CLOCKPRESCALAR_16 (LCDPRE_4)\r
+#define LCD_C_CLOCKPRESCALAR_32 (LCDPRE_5)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the initParams parameter for\r
+// functions: LCD_C_init().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_STATIC (0x0)\r
+#define LCD_C_2_MUX (LCDMX0)\r
+#define LCD_C_3_MUX (LCDMX1)\r
+#define LCD_C_4_MUX (LCDMX1 | LCDMX0)\r
+#define LCD_C_5_MUX (LCDMX2)\r
+#define LCD_C_6_MUX (LCDMX2 | LCDMX0)\r
+#define LCD_C_7_MUX (LCDMX2 | LCDMX1)\r
+#define LCD_C_8_MUX (LCDMX2 | LCDMX1 | LCDMX0)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the initParams parameter for\r
+// functions: LCD_C_init().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_STANDARD_WAVEFORMS (0x0)\r
+#define LCD_C_LOW_POWER_WAVEFORMS (LCDLP)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the initParams parameter for\r
+// functions: LCD_C_init().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_SEGMENTS_DISABLED (0x0)\r
+#define LCD_C_SEGMENTS_ENABLED (LCDSON)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: LCD_C_clearInterrupt(), LCD_C_getInterruptStatus(),\r
+// LCD_C_enableInterrupt(), and LCD_C_disableInterrupt() as well as returned by\r
+// the LCD_C_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT (LCDNOCAPIE)\r
+#define LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT (LCDBLKONIE)\r
+#define LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT (LCDBLKOFFIE)\r
+#define LCD_C_FRAME_INTERRUPT (LCDFRMIE)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the displayMemory parameter\r
+// for functions: LCD_C_selectDisplayMemory().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_DISPLAYSOURCE_MEMORY (0x0)\r
+#define LCD_C_DISPLAYSOURCE_BLINKINGMEMORY (LCDDISP)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockDivider parameter\r
+// for functions: LCD_C_setBlinkingControl().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_1 (0x0)\r
+#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_2 (LCDBLKDIV0)\r
+#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_3 (LCDBLKDIV1)\r
+#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_4 (LCDBLKDIV0 | LCDBLKDIV1)\r
+#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_5 (LCDBLKDIV2)\r
+#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_6 (LCDBLKDIV2 | LCDBLKDIV0)\r
+#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_7 (LCDBLKDIV2 | LCDBLKDIV1)\r
+#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_8 (LCDBLKDIV2 | LCDBLKDIV1 | LCDBLKDIV0)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockPrescalar parameter\r
+// for functions: LCD_C_setBlinkingControl().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_512 (0x0)\r
+#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_1024 (LCDBLKPRE0)\r
+#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_2048 (LCDBLKPRE1)\r
+#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_4096 (LCDBLKPRE1 | LCDBLKPRE0)\r
+#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_8162 (LCDBLKPRE2)\r
+#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_16384 (LCDBLKPRE2 | LCDBLKPRE0)\r
+#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_32768 (LCDBLKPRE2 | LCDBLKPRE1)\r
+#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_65536 \\r
+ (LCDBLKPRE2 | LCDBLKPRE1 | LCDBLKPRE0)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the blinkingMode parameter\r
+// for functions: LCD_C_setBlinkingControl().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_BLINK_MODE_DISABLED (LCDBLKMOD_0)\r
+#define LCD_C_BLINK_MODE_INDIVIDUAL_SEGMENTS (LCDBLKMOD_1)\r
+#define LCD_C_BLINK_MODE_ALL_SEGMENTS (LCDBLKMOD_2)\r
+#define LCD_C_BLINK_MODE_SWITCHING_BETWEEN_DISPLAY_CONTENTS (LCDBLKMOD_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the bias parameter for\r
+// functions: LCD_C_selectBias().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_BIAS_1_3 (0x0)\r
+#define LCD_C_BIAS_1_2 (LCD2B)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the reference parameter for\r
+// functions: LCD_C_selectChargePumpReference().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_INTERNAL_REFERENCE_VOLTAGE (VLCDREF_0)\r
+#define LCD_C_EXTERNAL_REFERENCE_VOLTAGE (VLCDREF_1)\r
+#define LCD_C_INTERNAL_REFERENCE_VOLTAGE_SWITCHED_TO_EXTERNAL_PIN (VLCDREF_2)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the vlcdSource parameter for\r
+// functions: LCD_C_setVLCDSource().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_VLCD_GENERATED_INTERNALLY (0x0)\r
+#define LCD_C_VLCD_SOURCED_EXTERNALLY (VLCDEXT)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the v2v3v4Source parameter\r
+// for functions: LCD_C_setVLCDSource().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_V2V3V4_GENERATED_INTERNALLY_NOT_SWITCHED_TO_PINS (0x0)\r
+#define LCD_C_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS (LCDREXT)\r
+#define LCD_C_V2V3V4_SOURCED_EXTERNALLY (LCDEXTBIAS)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the v5Source parameter for\r
+// functions: LCD_C_setVLCDSource().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_V5_VSS (0x0)\r
+#define LCD_C_V5_SOURCED_FROM_R03 (R03EXT)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the voltage parameter for\r
+// functions: LCD_C_setVLCDVoltage().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_CHARGEPUMP_DISABLED (0x0)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_2_60V_OR_2_17VREF (VLCD0)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_2_66V_OR_2_22VREF (VLCD1)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_2_72V_OR_2_27VREF (VLCD1 | VLCD0)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_2_78V_OR_2_32VREF (VLCD2)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_2_84V_OR_2_37VREF (VLCD2 | VLCD0)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_2_90V_OR_2_42VREF (VLCD2 | VLCD1)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_2_96V_OR_2_47VREF (VLCD2 | VLCD1 | VLCD0)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_3_02V_OR_2_52VREF (VLCD3)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_3_08V_OR_2_57VREF (VLCD3 | VLCD0)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_3_14V_OR_2_62VREF (VLCD3 | VLCD1)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_3_20V_OR_2_67VREF (VLCD3 | VLCD1 | VLCD0)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_3_26V_OR_2_72VREF (VLCD3 | VLCD2)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_3_32V_OR_2_77VREF (VLCD3 | VLCD2 | VLCD0)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_3_38V_OR_2_82VREF (VLCD3 | VLCD2 | VLCD1)\r
+#define LCD_C_CHARGEPUMP_VOLTAGE_3_44V_OR_2_87VREF \\r
+ (VLCD3 | VLCD2 | VLCD1 | VLCD0)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the startPin parameter for\r
+// functions: LCD_C_setPinAsLCDFunctionEx(); the endPin parameter for\r
+// functions: LCD_C_setPinAsLCDFunctionEx(); the pin parameter for functions:\r
+// LCD_C_setPinAsLCDFunction(), LCD_C_setPinAsPortFunction(),\r
+// LCD_C_setMemory(), and LCD_C_setBlinkingMemory().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_SEGMENT_LINE_0 (0)\r
+#define LCD_C_SEGMENT_LINE_1 (1)\r
+#define LCD_C_SEGMENT_LINE_2 (2)\r
+#define LCD_C_SEGMENT_LINE_3 (3)\r
+#define LCD_C_SEGMENT_LINE_4 (4)\r
+#define LCD_C_SEGMENT_LINE_5 (5)\r
+#define LCD_C_SEGMENT_LINE_6 (6)\r
+#define LCD_C_SEGMENT_LINE_7 (7)\r
+#define LCD_C_SEGMENT_LINE_8 (8)\r
+#define LCD_C_SEGMENT_LINE_9 (9)\r
+#define LCD_C_SEGMENT_LINE_10 (10)\r
+#define LCD_C_SEGMENT_LINE_11 (11)\r
+#define LCD_C_SEGMENT_LINE_12 (12)\r
+#define LCD_C_SEGMENT_LINE_13 (13)\r
+#define LCD_C_SEGMENT_LINE_14 (14)\r
+#define LCD_C_SEGMENT_LINE_15 (15)\r
+#define LCD_C_SEGMENT_LINE_16 (16)\r
+#define LCD_C_SEGMENT_LINE_17 (17)\r
+#define LCD_C_SEGMENT_LINE_18 (18)\r
+#define LCD_C_SEGMENT_LINE_19 (19)\r
+#define LCD_C_SEGMENT_LINE_20 (20)\r
+#define LCD_C_SEGMENT_LINE_21 (21)\r
+#define LCD_C_SEGMENT_LINE_22 (22)\r
+#define LCD_C_SEGMENT_LINE_23 (23)\r
+#define LCD_C_SEGMENT_LINE_24 (24)\r
+#define LCD_C_SEGMENT_LINE_25 (25)\r
+#define LCD_C_SEGMENT_LINE_26 (26)\r
+#define LCD_C_SEGMENT_LINE_27 (27)\r
+#define LCD_C_SEGMENT_LINE_28 (28)\r
+#define LCD_C_SEGMENT_LINE_29 (29)\r
+#define LCD_C_SEGMENT_LINE_30 (30)\r
+#define LCD_C_SEGMENT_LINE_31 (31)\r
+#define LCD_C_SEGMENT_LINE_32 (32)\r
+#define LCD_C_SEGMENT_LINE_33 (33)\r
+#define LCD_C_SEGMENT_LINE_34 (34)\r
+#define LCD_C_SEGMENT_LINE_35 (35)\r
+#define LCD_C_SEGMENT_LINE_36 (36)\r
+#define LCD_C_SEGMENT_LINE_37 (37)\r
+#define LCD_C_SEGMENT_LINE_38 (38)\r
+#define LCD_C_SEGMENT_LINE_39 (39)\r
+#define LCD_C_SEGMENT_LINE_40 (40)\r
+#define LCD_C_SEGMENT_LINE_41 (41)\r
+#define LCD_C_SEGMENT_LINE_42 (42)\r
+#define LCD_C_SEGMENT_LINE_43 (43)\r
+#define LCD_C_SEGMENT_LINE_44 (44)\r
+#define LCD_C_SEGMENT_LINE_45 (45)\r
+#define LCD_C_SEGMENT_LINE_46 (46)\r
+#define LCD_C_SEGMENT_LINE_47 (47)\r
+#define LCD_C_SEGMENT_LINE_48 (48)\r
+#define LCD_C_SEGMENT_LINE_49 (49)\r
+#define LCD_C_SEGMENT_LINE_50 (50)\r
+#define LCD_C_SEGMENT_LINE_51 (51)\r
+#define LCD_C_SEGMENT_LINE_52 (52)\r
+#define LCD_C_SEGMENT_LINE_53 (53)\r
+#define LCD_C_SEGMENT_LINE_54 (54)\r
+#define LCD_C_SEGMENT_LINE_55 (55)\r
+#define LCD_C_SEGMENT_LINE_56 (56)\r
+#define LCD_C_SEGMENT_LINE_57 (57)\r
+#define LCD_C_SEGMENT_LINE_58 (58)\r
+#define LCD_C_SEGMENT_LINE_59 (59)\r
+#define LCD_C_SEGMENT_LINE_60 (60)\r
+#define LCD_C_SEGMENT_LINE_61 (61)\r
+#define LCD_C_SEGMENT_LINE_62 (62)\r
+#define LCD_C_SEGMENT_LINE_63 (63)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the syncToClock parameter for\r
+// functions: LCD_C_configChargePump().\r
+//\r
+//*****************************************************************************\r
+#define LCD_C_SYNCHRONIZATION_DISABLED (0x0)\r
+#define LCD_C_SYNCHRONIZATION_ENABLED (LCDCPCLKSYNC)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the LCD Module.\r
+//!\r
+//! his function initializes the LCD but without turning on. It bascially setup\r
+//! the clock source, clock divider, clock prescalar, mux rate, low-power\r
+//! waveform and segments on/off. After calling this function, user can config\r
+//! charge pump, internal reference voltage and voltage sources.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param initParams is the pointer to LCD_InitParam structure. See the\r
+//! following parameters for each field.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_init(uint16_t baseAddress,\r
+ LCD_C_initParam *initParams);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Turns on the LCD module.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//!\r
+//! Modified bits are \b LCDON of \b LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_on(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Turns off the LCD module.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//!\r
+//! Modified bits are \b LCDON of \b LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_off(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the LCD interrupt flags.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param mask is the masked interrupt flag to be cleared.\r
+//! Valid values are:\r
+//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT\r
+//! - \b LCD_C_FRAME_INTERRUPT\r
+//! \n Modified bits are \b LCDCAPIFG, \b LCDBLKONIFG, \b LCDBLKOFFIFG\r
+//! and \b LCDFRMIFG of \b LCDCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_clearInterrupt(uint16_t baseAddress,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the LCD interrupt status.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param mask is the masked interrupt flags.\r
+//! Valid values are:\r
+//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT\r
+//! - \b LCD_C_FRAME_INTERRUPT\r
+//!\r
+//! \return None\r
+//! Return Logical OR of any of the following:\r
+//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT\r
+//! - \b LCD_C_FRAME_INTERRUPT\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint16_t LCD_C_getInterruptStatus(uint16_t baseAddress,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables LCD interrupt sources.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param mask is the interrupts to be enabled.\r
+//! Valid values are:\r
+//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT\r
+//! - \b LCD_C_FRAME_INTERRUPT\r
+//! \n Modified bits are \b LCDCAPIE, \b LCDBLKONIE, \b LCDBLKOFFIE and\r
+//! \b LCDFRMIE of \b LCDCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_enableInterrupt(uint16_t baseAddress,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables LCD interrupt sources.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param mask is the interrupts to be disabled.\r
+//! Valid values are:\r
+//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT\r
+//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT\r
+//! - \b LCD_C_FRAME_INTERRUPT\r
+//! \n Modified bits are \b LCDCAPIE, \b LCDBLKONIE, \b LCDBLKOFFIE and\r
+//! \b LCDFRMIE of \b LCDCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_disableInterrupt(uint16_t baseAddress,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears all LCD memory registers.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//!\r
+//! Modified bits are \b LCDCLRM of \b LCDMEMCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_clearMemory(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears all LCD blinking memory registers.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//!\r
+//! Modified bits are \b LCDCLRBM of \b LCDMEMCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_clearBlinkingMemory(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects display memory.\r
+//!\r
+//! This function selects display memory either from memory or blinking memory.\r
+//! Please note if the blinking mode is selected as\r
+//! LCD_BLINKMODE_INDIVIDUALSEGMENTS or LCD_BLINKMODE_ALLSEGMENTS or mux rate\r
+//! >=5, display memory can not be changed. If\r
+//! LCD_BLINKMODE_SWITCHDISPLAYCONTENTS is selected, display memory bit\r
+//! reflects current displayed memory.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param displayMemory is the desired displayed memory.\r
+//! Valid values are:\r
+//! - \b LCD_C_DISPLAYSOURCE_MEMORY [Default]\r
+//! - \b LCD_C_DISPLAYSOURCE_BLINKINGMEMORY\r
+//! \n Modified bits are \b LCDDISP of \b LCDMEMCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_selectDisplayMemory(uint16_t baseAddress,\r
+ uint16_t displayMemory);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the blink settings.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param clockDivider is the clock divider for blinking frequency.\r
+//! Valid values are:\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_1 [Default]\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_2\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_3\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_4\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_5\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_6\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_7\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_8\r
+//! \n Modified bits are \b LCDBLKDIVx of \b LCDBLKCTL register.\r
+//! \param clockPrescalar is the clock pre-scalar for blinking frequency.\r
+//! Valid values are:\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_512 [Default]\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_1024\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_2048\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_4096\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_8162\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_16384\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_32768\r
+//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_65536\r
+//! \n Modified bits are \b LCDBLKPREx of \b LCDBLKCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_setBlinkingControl(uint16_t baseAddress,\r
+ uint8_t clockDivider,\r
+ uint8_t clockPrescalar,\r
+ uint8_t mode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the charge pump.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//!\r
+//! Modified bits are \b LCDCPEN of \b LCDVCTL register; bits \b LCDON of \b\r
+//! LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_enableChargePump(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the charge pump.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//!\r
+//! Modified bits are \b LCDCPEN of \b LCDVCTL register; bits \b LCDON of \b\r
+//! LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_disableChargePump(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects the bias level.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param bias is the select for bias level.\r
+//! Valid values are:\r
+//! - \b LCD_C_BIAS_1_3 [Default] - 1/3 bias\r
+//! - \b LCD_C_BIAS_1_2 - 1/2 bias\r
+//!\r
+//! Modified bits are \b LCD2B of \b LCDVCTL register; bits \b LCDON of \b\r
+//! LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_selectBias(uint16_t baseAddress,\r
+ uint16_t bias);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects the charge pump reference.\r
+//!\r
+//! The charge pump reference does not support\r
+//! LCD_C_EXTERNAL_REFERENCE_VOLTAGE,\r
+//! LCD_C_INTERNAL_REFERENCE_VOLTAGE_SWITCHED_TO_EXTERNAL_PIN when\r
+//! LCD_C_V2V3V4_SOURCED_EXTERNALLY or\r
+//! LCD_C_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS is selected.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param reference is the select for charge pump reference.\r
+//! Valid values are:\r
+//! - \b LCD_C_INTERNAL_REFERENCE_VOLTAGE [Default]\r
+//! - \b LCD_C_EXTERNAL_REFERENCE_VOLTAGE\r
+//! - \b LCD_C_INTERNAL_REFERENCE_VOLTAGE_SWITCHED_TO_EXTERNAL_PIN\r
+//!\r
+//! Modified bits are \b VLCDREFx of \b LCDVCTL register; bits \b LCDON of \b\r
+//! LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_selectChargePumpReference(uint16_t baseAddress,\r
+ uint16_t reference);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the voltage source for V2/V3/V4 and V5.\r
+//!\r
+//! The charge pump reference does not support\r
+//! LCD_C_EXTERNAL_REFERENCE_VOLTAGE,\r
+//! LCD_C_INTERNAL_REFERENCE_VOLTAGE_SWITCHED_TO_EXTERNAL_PIN when\r
+//! LCD_C_V2V3V4_SOURCED_EXTERNALLY or\r
+//! LCD_C_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS is selected.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param vlcdSource is the V(LCD) source select.\r
+//! Valid values are:\r
+//! - \b LCD_C_VLCD_GENERATED_INTERNALLY [Default]\r
+//! - \b LCD_C_VLCD_SOURCED_EXTERNALLY\r
+//! \param v2v3v4Source is the V2/V3/V4 source select.\r
+//! Valid values are:\r
+//! - \b LCD_C_V2V3V4_GENERATED_INTERNALLY_NOT_SWITCHED_TO_PINS\r
+//! [Default]\r
+//! - \b LCD_C_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS\r
+//! - \b LCD_C_V2V3V4_SOURCED_EXTERNALLY\r
+//! \param v5Source is the V5 source select.\r
+//! Valid values are:\r
+//! - \b LCD_C_V5_VSS [Default]\r
+//! - \b LCD_C_V5_SOURCED_FROM_R03\r
+//!\r
+//! Modified bits are \b VLCDEXT, \b LCDREXT, \b LCDEXTBIAS and \b R03EXT of \b\r
+//! LCDVCTL register; bits \b LCDON of \b LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_setVLCDSource(uint16_t baseAddress,\r
+ uint16_t vlcdSource,\r
+ uint16_t v2v3v4Source,\r
+ uint16_t v5Source);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects the charge pump reference.\r
+//!\r
+//! Sets LCD charge pump voltage.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param voltage is the charge pump select.\r
+//! Valid values are:\r
+//! - \b LCD_C_CHARGEPUMP_DISABLED [Default]\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_60V_OR_2_17VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_66V_OR_2_22VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_72V_OR_2_27VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_78V_OR_2_32VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_84V_OR_2_37VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_90V_OR_2_42VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_96V_OR_2_47VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_02V_OR_2_52VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_08V_OR_2_57VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_14V_OR_2_62VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_20V_OR_2_67VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_26V_OR_2_72VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_32V_OR_2_77VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_38V_OR_2_82VREF\r
+//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_44V_OR_2_87VREF\r
+//!\r
+//! Modified bits are \b VLCDx of \b LCDVCTL register; bits \b LCDON of \b\r
+//! LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_setVLCDVoltage(uint16_t baseAddress,\r
+ uint16_t voltage);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the LCD Pin as LCD functions.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param pin is the select pin set as LCD function.\r
+//! Valid values are:\r
+//! - \b LCD_C_SEGMENT_LINE_0\r
+//! - \b LCD_C_SEGMENT_LINE_1\r
+//! - \b LCD_C_SEGMENT_LINE_2\r
+//! - \b LCD_C_SEGMENT_LINE_3\r
+//! - \b LCD_C_SEGMENT_LINE_4\r
+//! - \b LCD_C_SEGMENT_LINE_5\r
+//! - \b LCD_C_SEGMENT_LINE_6\r
+//! - \b LCD_C_SEGMENT_LINE_7\r
+//! - \b LCD_C_SEGMENT_LINE_8\r
+//! - \b LCD_C_SEGMENT_LINE_9\r
+//! - \b LCD_C_SEGMENT_LINE_10\r
+//! - \b LCD_C_SEGMENT_LINE_11\r
+//! - \b LCD_C_SEGMENT_LINE_12\r
+//! - \b LCD_C_SEGMENT_LINE_13\r
+//! - \b LCD_C_SEGMENT_LINE_14\r
+//! - \b LCD_C_SEGMENT_LINE_15\r
+//! - \b LCD_C_SEGMENT_LINE_16\r
+//! - \b LCD_C_SEGMENT_LINE_17\r
+//! - \b LCD_C_SEGMENT_LINE_18\r
+//! - \b LCD_C_SEGMENT_LINE_19\r
+//! - \b LCD_C_SEGMENT_LINE_20\r
+//! - \b LCD_C_SEGMENT_LINE_21\r
+//! - \b LCD_C_SEGMENT_LINE_22\r
+//! - \b LCD_C_SEGMENT_LINE_23\r
+//! - \b LCD_C_SEGMENT_LINE_24\r
+//! - \b LCD_C_SEGMENT_LINE_25\r
+//! - \b LCD_C_SEGMENT_LINE_26\r
+//! - \b LCD_C_SEGMENT_LINE_27\r
+//! - \b LCD_C_SEGMENT_LINE_28\r
+//! - \b LCD_C_SEGMENT_LINE_29\r
+//! - \b LCD_C_SEGMENT_LINE_30\r
+//! - \b LCD_C_SEGMENT_LINE_31\r
+//! - \b LCD_C_SEGMENT_LINE_32\r
+//! - \b LCD_C_SEGMENT_LINE_33\r
+//! - \b LCD_C_SEGMENT_LINE_34\r
+//! - \b LCD_C_SEGMENT_LINE_35\r
+//! - \b LCD_C_SEGMENT_LINE_36\r
+//! - \b LCD_C_SEGMENT_LINE_37\r
+//! - \b LCD_C_SEGMENT_LINE_38\r
+//! - \b LCD_C_SEGMENT_LINE_39\r
+//! - \b LCD_C_SEGMENT_LINE_40\r
+//! - \b LCD_C_SEGMENT_LINE_41\r
+//! - \b LCD_C_SEGMENT_LINE_42\r
+//! - \b LCD_C_SEGMENT_LINE_43\r
+//! - \b LCD_C_SEGMENT_LINE_44\r
+//! - \b LCD_C_SEGMENT_LINE_45\r
+//! - \b LCD_C_SEGMENT_LINE_46\r
+//! - \b LCD_C_SEGMENT_LINE_47\r
+//! - \b LCD_C_SEGMENT_LINE_48\r
+//! - \b LCD_C_SEGMENT_LINE_49\r
+//! - \b LCD_C_SEGMENT_LINE_50\r
+//! - \b LCD_C_SEGMENT_LINE_51\r
+//! - \b LCD_C_SEGMENT_LINE_52\r
+//! - \b LCD_C_SEGMENT_LINE_53\r
+//! - \b LCD_C_SEGMENT_LINE_54\r
+//! - \b LCD_C_SEGMENT_LINE_55\r
+//! - \b LCD_C_SEGMENT_LINE_56\r
+//! - \b LCD_C_SEGMENT_LINE_57\r
+//! - \b LCD_C_SEGMENT_LINE_58\r
+//! - \b LCD_C_SEGMENT_LINE_59\r
+//! - \b LCD_C_SEGMENT_LINE_60\r
+//! - \b LCD_C_SEGMENT_LINE_61\r
+//! - \b LCD_C_SEGMENT_LINE_62\r
+//! - \b LCD_C_SEGMENT_LINE_63\r
+//!\r
+//! Modified bits are \b LCDSx of \b LCDPCTLx register; bits \b LCDON of \b\r
+//! LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_setPinAsLCDFunction(uint16_t baseAddress,\r
+ uint8_t pin);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the LCD Pin as Port functions.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param pin is the select pin set as Port function.\r
+//! Valid values are:\r
+//! - \b LCD_C_SEGMENT_LINE_0\r
+//! - \b LCD_C_SEGMENT_LINE_1\r
+//! - \b LCD_C_SEGMENT_LINE_2\r
+//! - \b LCD_C_SEGMENT_LINE_3\r
+//! - \b LCD_C_SEGMENT_LINE_4\r
+//! - \b LCD_C_SEGMENT_LINE_5\r
+//! - \b LCD_C_SEGMENT_LINE_6\r
+//! - \b LCD_C_SEGMENT_LINE_7\r
+//! - \b LCD_C_SEGMENT_LINE_8\r
+//! - \b LCD_C_SEGMENT_LINE_9\r
+//! - \b LCD_C_SEGMENT_LINE_10\r
+//! - \b LCD_C_SEGMENT_LINE_11\r
+//! - \b LCD_C_SEGMENT_LINE_12\r
+//! - \b LCD_C_SEGMENT_LINE_13\r
+//! - \b LCD_C_SEGMENT_LINE_14\r
+//! - \b LCD_C_SEGMENT_LINE_15\r
+//! - \b LCD_C_SEGMENT_LINE_16\r
+//! - \b LCD_C_SEGMENT_LINE_17\r
+//! - \b LCD_C_SEGMENT_LINE_18\r
+//! - \b LCD_C_SEGMENT_LINE_19\r
+//! - \b LCD_C_SEGMENT_LINE_20\r
+//! - \b LCD_C_SEGMENT_LINE_21\r
+//! - \b LCD_C_SEGMENT_LINE_22\r
+//! - \b LCD_C_SEGMENT_LINE_23\r
+//! - \b LCD_C_SEGMENT_LINE_24\r
+//! - \b LCD_C_SEGMENT_LINE_25\r
+//! - \b LCD_C_SEGMENT_LINE_26\r
+//! - \b LCD_C_SEGMENT_LINE_27\r
+//! - \b LCD_C_SEGMENT_LINE_28\r
+//! - \b LCD_C_SEGMENT_LINE_29\r
+//! - \b LCD_C_SEGMENT_LINE_30\r
+//! - \b LCD_C_SEGMENT_LINE_31\r
+//! - \b LCD_C_SEGMENT_LINE_32\r
+//! - \b LCD_C_SEGMENT_LINE_33\r
+//! - \b LCD_C_SEGMENT_LINE_34\r
+//! - \b LCD_C_SEGMENT_LINE_35\r
+//! - \b LCD_C_SEGMENT_LINE_36\r
+//! - \b LCD_C_SEGMENT_LINE_37\r
+//! - \b LCD_C_SEGMENT_LINE_38\r
+//! - \b LCD_C_SEGMENT_LINE_39\r
+//! - \b LCD_C_SEGMENT_LINE_40\r
+//! - \b LCD_C_SEGMENT_LINE_41\r
+//! - \b LCD_C_SEGMENT_LINE_42\r
+//! - \b LCD_C_SEGMENT_LINE_43\r
+//! - \b LCD_C_SEGMENT_LINE_44\r
+//! - \b LCD_C_SEGMENT_LINE_45\r
+//! - \b LCD_C_SEGMENT_LINE_46\r
+//! - \b LCD_C_SEGMENT_LINE_47\r
+//! - \b LCD_C_SEGMENT_LINE_48\r
+//! - \b LCD_C_SEGMENT_LINE_49\r
+//! - \b LCD_C_SEGMENT_LINE_50\r
+//! - \b LCD_C_SEGMENT_LINE_51\r
+//! - \b LCD_C_SEGMENT_LINE_52\r
+//! - \b LCD_C_SEGMENT_LINE_53\r
+//! - \b LCD_C_SEGMENT_LINE_54\r
+//! - \b LCD_C_SEGMENT_LINE_55\r
+//! - \b LCD_C_SEGMENT_LINE_56\r
+//! - \b LCD_C_SEGMENT_LINE_57\r
+//! - \b LCD_C_SEGMENT_LINE_58\r
+//! - \b LCD_C_SEGMENT_LINE_59\r
+//! - \b LCD_C_SEGMENT_LINE_60\r
+//! - \b LCD_C_SEGMENT_LINE_61\r
+//! - \b LCD_C_SEGMENT_LINE_62\r
+//! - \b LCD_C_SEGMENT_LINE_63\r
+//!\r
+//! Modified bits are \b LCDSx of \b LCDPCTLx register; bits \b LCDON of \b\r
+//! LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_setPinAsPortFunction(uint16_t baseAddress,\r
+ uint8_t pin);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the LCD pins as LCD function pin.\r
+//!\r
+//! This function sets the LCD pins as LCD function pin. Instead of passing the\r
+//! all the possible pins, it just requires the start pin and the end pin.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param startPin is the starting pin to be configed as LCD function pin.\r
+//! Valid values are:\r
+//! - \b LCD_C_SEGMENT_LINE_0\r
+//! - \b LCD_C_SEGMENT_LINE_1\r
+//! - \b LCD_C_SEGMENT_LINE_2\r
+//! - \b LCD_C_SEGMENT_LINE_3\r
+//! - \b LCD_C_SEGMENT_LINE_4\r
+//! - \b LCD_C_SEGMENT_LINE_5\r
+//! - \b LCD_C_SEGMENT_LINE_6\r
+//! - \b LCD_C_SEGMENT_LINE_7\r
+//! - \b LCD_C_SEGMENT_LINE_8\r
+//! - \b LCD_C_SEGMENT_LINE_9\r
+//! - \b LCD_C_SEGMENT_LINE_10\r
+//! - \b LCD_C_SEGMENT_LINE_11\r
+//! - \b LCD_C_SEGMENT_LINE_12\r
+//! - \b LCD_C_SEGMENT_LINE_13\r
+//! - \b LCD_C_SEGMENT_LINE_14\r
+//! - \b LCD_C_SEGMENT_LINE_15\r
+//! - \b LCD_C_SEGMENT_LINE_16\r
+//! - \b LCD_C_SEGMENT_LINE_17\r
+//! - \b LCD_C_SEGMENT_LINE_18\r
+//! - \b LCD_C_SEGMENT_LINE_19\r
+//! - \b LCD_C_SEGMENT_LINE_20\r
+//! - \b LCD_C_SEGMENT_LINE_21\r
+//! - \b LCD_C_SEGMENT_LINE_22\r
+//! - \b LCD_C_SEGMENT_LINE_23\r
+//! - \b LCD_C_SEGMENT_LINE_24\r
+//! - \b LCD_C_SEGMENT_LINE_25\r
+//! - \b LCD_C_SEGMENT_LINE_26\r
+//! - \b LCD_C_SEGMENT_LINE_27\r
+//! - \b LCD_C_SEGMENT_LINE_28\r
+//! - \b LCD_C_SEGMENT_LINE_29\r
+//! - \b LCD_C_SEGMENT_LINE_30\r
+//! - \b LCD_C_SEGMENT_LINE_31\r
+//! - \b LCD_C_SEGMENT_LINE_32\r
+//! - \b LCD_C_SEGMENT_LINE_33\r
+//! - \b LCD_C_SEGMENT_LINE_34\r
+//! - \b LCD_C_SEGMENT_LINE_35\r
+//! - \b LCD_C_SEGMENT_LINE_36\r
+//! - \b LCD_C_SEGMENT_LINE_37\r
+//! - \b LCD_C_SEGMENT_LINE_38\r
+//! - \b LCD_C_SEGMENT_LINE_39\r
+//! - \b LCD_C_SEGMENT_LINE_40\r
+//! - \b LCD_C_SEGMENT_LINE_41\r
+//! - \b LCD_C_SEGMENT_LINE_42\r
+//! - \b LCD_C_SEGMENT_LINE_43\r
+//! - \b LCD_C_SEGMENT_LINE_44\r
+//! - \b LCD_C_SEGMENT_LINE_45\r
+//! - \b LCD_C_SEGMENT_LINE_46\r
+//! - \b LCD_C_SEGMENT_LINE_47\r
+//! - \b LCD_C_SEGMENT_LINE_48\r
+//! - \b LCD_C_SEGMENT_LINE_49\r
+//! - \b LCD_C_SEGMENT_LINE_50\r
+//! - \b LCD_C_SEGMENT_LINE_51\r
+//! - \b LCD_C_SEGMENT_LINE_52\r
+//! - \b LCD_C_SEGMENT_LINE_53\r
+//! - \b LCD_C_SEGMENT_LINE_54\r
+//! - \b LCD_C_SEGMENT_LINE_55\r
+//! - \b LCD_C_SEGMENT_LINE_56\r
+//! - \b LCD_C_SEGMENT_LINE_57\r
+//! - \b LCD_C_SEGMENT_LINE_58\r
+//! - \b LCD_C_SEGMENT_LINE_59\r
+//! - \b LCD_C_SEGMENT_LINE_60\r
+//! - \b LCD_C_SEGMENT_LINE_61\r
+//! - \b LCD_C_SEGMENT_LINE_62\r
+//! - \b LCD_C_SEGMENT_LINE_63\r
+//! \param endPin is the ending pin to be configed as LCD function pin.\r
+//! Valid values are:\r
+//! - \b LCD_C_SEGMENT_LINE_0\r
+//! - \b LCD_C_SEGMENT_LINE_1\r
+//! - \b LCD_C_SEGMENT_LINE_2\r
+//! - \b LCD_C_SEGMENT_LINE_3\r
+//! - \b LCD_C_SEGMENT_LINE_4\r
+//! - \b LCD_C_SEGMENT_LINE_5\r
+//! - \b LCD_C_SEGMENT_LINE_6\r
+//! - \b LCD_C_SEGMENT_LINE_7\r
+//! - \b LCD_C_SEGMENT_LINE_8\r
+//! - \b LCD_C_SEGMENT_LINE_9\r
+//! - \b LCD_C_SEGMENT_LINE_10\r
+//! - \b LCD_C_SEGMENT_LINE_11\r
+//! - \b LCD_C_SEGMENT_LINE_12\r
+//! - \b LCD_C_SEGMENT_LINE_13\r
+//! - \b LCD_C_SEGMENT_LINE_14\r
+//! - \b LCD_C_SEGMENT_LINE_15\r
+//! - \b LCD_C_SEGMENT_LINE_16\r
+//! - \b LCD_C_SEGMENT_LINE_17\r
+//! - \b LCD_C_SEGMENT_LINE_18\r
+//! - \b LCD_C_SEGMENT_LINE_19\r
+//! - \b LCD_C_SEGMENT_LINE_20\r
+//! - \b LCD_C_SEGMENT_LINE_21\r
+//! - \b LCD_C_SEGMENT_LINE_22\r
+//! - \b LCD_C_SEGMENT_LINE_23\r
+//! - \b LCD_C_SEGMENT_LINE_24\r
+//! - \b LCD_C_SEGMENT_LINE_25\r
+//! - \b LCD_C_SEGMENT_LINE_26\r
+//! - \b LCD_C_SEGMENT_LINE_27\r
+//! - \b LCD_C_SEGMENT_LINE_28\r
+//! - \b LCD_C_SEGMENT_LINE_29\r
+//! - \b LCD_C_SEGMENT_LINE_30\r
+//! - \b LCD_C_SEGMENT_LINE_31\r
+//! - \b LCD_C_SEGMENT_LINE_32\r
+//! - \b LCD_C_SEGMENT_LINE_33\r
+//! - \b LCD_C_SEGMENT_LINE_34\r
+//! - \b LCD_C_SEGMENT_LINE_35\r
+//! - \b LCD_C_SEGMENT_LINE_36\r
+//! - \b LCD_C_SEGMENT_LINE_37\r
+//! - \b LCD_C_SEGMENT_LINE_38\r
+//! - \b LCD_C_SEGMENT_LINE_39\r
+//! - \b LCD_C_SEGMENT_LINE_40\r
+//! - \b LCD_C_SEGMENT_LINE_41\r
+//! - \b LCD_C_SEGMENT_LINE_42\r
+//! - \b LCD_C_SEGMENT_LINE_43\r
+//! - \b LCD_C_SEGMENT_LINE_44\r
+//! - \b LCD_C_SEGMENT_LINE_45\r
+//! - \b LCD_C_SEGMENT_LINE_46\r
+//! - \b LCD_C_SEGMENT_LINE_47\r
+//! - \b LCD_C_SEGMENT_LINE_48\r
+//! - \b LCD_C_SEGMENT_LINE_49\r
+//! - \b LCD_C_SEGMENT_LINE_50\r
+//! - \b LCD_C_SEGMENT_LINE_51\r
+//! - \b LCD_C_SEGMENT_LINE_52\r
+//! - \b LCD_C_SEGMENT_LINE_53\r
+//! - \b LCD_C_SEGMENT_LINE_54\r
+//! - \b LCD_C_SEGMENT_LINE_55\r
+//! - \b LCD_C_SEGMENT_LINE_56\r
+//! - \b LCD_C_SEGMENT_LINE_57\r
+//! - \b LCD_C_SEGMENT_LINE_58\r
+//! - \b LCD_C_SEGMENT_LINE_59\r
+//! - \b LCD_C_SEGMENT_LINE_60\r
+//! - \b LCD_C_SEGMENT_LINE_61\r
+//! - \b LCD_C_SEGMENT_LINE_62\r
+//! - \b LCD_C_SEGMENT_LINE_63\r
+//!\r
+//! Modified bits are \b LCDSx of \b LCDPCTLx register; bits \b LCDON of \b\r
+//! LCDCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_setPinAsLCDFunctionEx(uint16_t baseAddress,\r
+ uint8_t startPin,\r
+ uint8_t endPin);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the LCD memory register.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param pin is the select pin for setting value.\r
+//! Valid values are:\r
+//! - \b LCD_C_SEGMENT_LINE_0\r
+//! - \b LCD_C_SEGMENT_LINE_1\r
+//! - \b LCD_C_SEGMENT_LINE_2\r
+//! - \b LCD_C_SEGMENT_LINE_3\r
+//! - \b LCD_C_SEGMENT_LINE_4\r
+//! - \b LCD_C_SEGMENT_LINE_5\r
+//! - \b LCD_C_SEGMENT_LINE_6\r
+//! - \b LCD_C_SEGMENT_LINE_7\r
+//! - \b LCD_C_SEGMENT_LINE_8\r
+//! - \b LCD_C_SEGMENT_LINE_9\r
+//! - \b LCD_C_SEGMENT_LINE_10\r
+//! - \b LCD_C_SEGMENT_LINE_11\r
+//! - \b LCD_C_SEGMENT_LINE_12\r
+//! - \b LCD_C_SEGMENT_LINE_13\r
+//! - \b LCD_C_SEGMENT_LINE_14\r
+//! - \b LCD_C_SEGMENT_LINE_15\r
+//! - \b LCD_C_SEGMENT_LINE_16\r
+//! - \b LCD_C_SEGMENT_LINE_17\r
+//! - \b LCD_C_SEGMENT_LINE_18\r
+//! - \b LCD_C_SEGMENT_LINE_19\r
+//! - \b LCD_C_SEGMENT_LINE_20\r
+//! - \b LCD_C_SEGMENT_LINE_21\r
+//! - \b LCD_C_SEGMENT_LINE_22\r
+//! - \b LCD_C_SEGMENT_LINE_23\r
+//! - \b LCD_C_SEGMENT_LINE_24\r
+//! - \b LCD_C_SEGMENT_LINE_25\r
+//! - \b LCD_C_SEGMENT_LINE_26\r
+//! - \b LCD_C_SEGMENT_LINE_27\r
+//! - \b LCD_C_SEGMENT_LINE_28\r
+//! - \b LCD_C_SEGMENT_LINE_29\r
+//! - \b LCD_C_SEGMENT_LINE_30\r
+//! - \b LCD_C_SEGMENT_LINE_31\r
+//! - \b LCD_C_SEGMENT_LINE_32\r
+//! - \b LCD_C_SEGMENT_LINE_33\r
+//! - \b LCD_C_SEGMENT_LINE_34\r
+//! - \b LCD_C_SEGMENT_LINE_35\r
+//! - \b LCD_C_SEGMENT_LINE_36\r
+//! - \b LCD_C_SEGMENT_LINE_37\r
+//! - \b LCD_C_SEGMENT_LINE_38\r
+//! - \b LCD_C_SEGMENT_LINE_39\r
+//! - \b LCD_C_SEGMENT_LINE_40\r
+//! - \b LCD_C_SEGMENT_LINE_41\r
+//! - \b LCD_C_SEGMENT_LINE_42\r
+//! - \b LCD_C_SEGMENT_LINE_43\r
+//! - \b LCD_C_SEGMENT_LINE_44\r
+//! - \b LCD_C_SEGMENT_LINE_45\r
+//! - \b LCD_C_SEGMENT_LINE_46\r
+//! - \b LCD_C_SEGMENT_LINE_47\r
+//! - \b LCD_C_SEGMENT_LINE_48\r
+//! - \b LCD_C_SEGMENT_LINE_49\r
+//! - \b LCD_C_SEGMENT_LINE_50\r
+//! - \b LCD_C_SEGMENT_LINE_51\r
+//! - \b LCD_C_SEGMENT_LINE_52\r
+//! - \b LCD_C_SEGMENT_LINE_53\r
+//! - \b LCD_C_SEGMENT_LINE_54\r
+//! - \b LCD_C_SEGMENT_LINE_55\r
+//! - \b LCD_C_SEGMENT_LINE_56\r
+//! - \b LCD_C_SEGMENT_LINE_57\r
+//! - \b LCD_C_SEGMENT_LINE_58\r
+//! - \b LCD_C_SEGMENT_LINE_59\r
+//! - \b LCD_C_SEGMENT_LINE_60\r
+//! - \b LCD_C_SEGMENT_LINE_61\r
+//! - \b LCD_C_SEGMENT_LINE_62\r
+//! - \b LCD_C_SEGMENT_LINE_63\r
+//! \param value is the designated value for corresponding pin.\r
+//!\r
+//! Modified bits are \b MBITx of \b LCDMx register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_setMemory(uint16_t baseAddress,\r
+ uint8_t pin,\r
+ uint8_t value);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the LCD blink memory register.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param pin is the select pin for setting value.\r
+//! Valid values are:\r
+//! - \b LCD_C_SEGMENT_LINE_0\r
+//! - \b LCD_C_SEGMENT_LINE_1\r
+//! - \b LCD_C_SEGMENT_LINE_2\r
+//! - \b LCD_C_SEGMENT_LINE_3\r
+//! - \b LCD_C_SEGMENT_LINE_4\r
+//! - \b LCD_C_SEGMENT_LINE_5\r
+//! - \b LCD_C_SEGMENT_LINE_6\r
+//! - \b LCD_C_SEGMENT_LINE_7\r
+//! - \b LCD_C_SEGMENT_LINE_8\r
+//! - \b LCD_C_SEGMENT_LINE_9\r
+//! - \b LCD_C_SEGMENT_LINE_10\r
+//! - \b LCD_C_SEGMENT_LINE_11\r
+//! - \b LCD_C_SEGMENT_LINE_12\r
+//! - \b LCD_C_SEGMENT_LINE_13\r
+//! - \b LCD_C_SEGMENT_LINE_14\r
+//! - \b LCD_C_SEGMENT_LINE_15\r
+//! - \b LCD_C_SEGMENT_LINE_16\r
+//! - \b LCD_C_SEGMENT_LINE_17\r
+//! - \b LCD_C_SEGMENT_LINE_18\r
+//! - \b LCD_C_SEGMENT_LINE_19\r
+//! - \b LCD_C_SEGMENT_LINE_20\r
+//! - \b LCD_C_SEGMENT_LINE_21\r
+//! - \b LCD_C_SEGMENT_LINE_22\r
+//! - \b LCD_C_SEGMENT_LINE_23\r
+//! - \b LCD_C_SEGMENT_LINE_24\r
+//! - \b LCD_C_SEGMENT_LINE_25\r
+//! - \b LCD_C_SEGMENT_LINE_26\r
+//! - \b LCD_C_SEGMENT_LINE_27\r
+//! - \b LCD_C_SEGMENT_LINE_28\r
+//! - \b LCD_C_SEGMENT_LINE_29\r
+//! - \b LCD_C_SEGMENT_LINE_30\r
+//! - \b LCD_C_SEGMENT_LINE_31\r
+//! - \b LCD_C_SEGMENT_LINE_32\r
+//! - \b LCD_C_SEGMENT_LINE_33\r
+//! - \b LCD_C_SEGMENT_LINE_34\r
+//! - \b LCD_C_SEGMENT_LINE_35\r
+//! - \b LCD_C_SEGMENT_LINE_36\r
+//! - \b LCD_C_SEGMENT_LINE_37\r
+//! - \b LCD_C_SEGMENT_LINE_38\r
+//! - \b LCD_C_SEGMENT_LINE_39\r
+//! - \b LCD_C_SEGMENT_LINE_40\r
+//! - \b LCD_C_SEGMENT_LINE_41\r
+//! - \b LCD_C_SEGMENT_LINE_42\r
+//! - \b LCD_C_SEGMENT_LINE_43\r
+//! - \b LCD_C_SEGMENT_LINE_44\r
+//! - \b LCD_C_SEGMENT_LINE_45\r
+//! - \b LCD_C_SEGMENT_LINE_46\r
+//! - \b LCD_C_SEGMENT_LINE_47\r
+//! - \b LCD_C_SEGMENT_LINE_48\r
+//! - \b LCD_C_SEGMENT_LINE_49\r
+//! - \b LCD_C_SEGMENT_LINE_50\r
+//! - \b LCD_C_SEGMENT_LINE_51\r
+//! - \b LCD_C_SEGMENT_LINE_52\r
+//! - \b LCD_C_SEGMENT_LINE_53\r
+//! - \b LCD_C_SEGMENT_LINE_54\r
+//! - \b LCD_C_SEGMENT_LINE_55\r
+//! - \b LCD_C_SEGMENT_LINE_56\r
+//! - \b LCD_C_SEGMENT_LINE_57\r
+//! - \b LCD_C_SEGMENT_LINE_58\r
+//! - \b LCD_C_SEGMENT_LINE_59\r
+//! - \b LCD_C_SEGMENT_LINE_60\r
+//! - \b LCD_C_SEGMENT_LINE_61\r
+//! - \b LCD_C_SEGMENT_LINE_62\r
+//! - \b LCD_C_SEGMENT_LINE_63\r
+//! \param value is the designated value for corresponding blink pin.\r
+//!\r
+//! Modified bits are \b MBITx of \b LCDBMx register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_setBlinkingMemory(uint16_t baseAddress,\r
+ uint8_t pin,\r
+ uint8_t value);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configs the charge pump for synchronization and disabled capability.\r
+//!\r
+//! This function is device-specific. The charge pump clock can be synchronized\r
+//! to a device-specific clock, and also can be disabled by connected function.\r
+//!\r
+//! \param baseAddress is the base address of the LCD_C module.\r
+//! \param syncToClock is the synchronization select.\r
+//! Valid values are:\r
+//! - \b LCD_C_SYNCHRONIZATION_DISABLED [Default]\r
+//! - \b LCD_C_SYNCHRONIZATION_ENABLED\r
+//! \param functionControl is the connected function control select. Setting 0\r
+//! to make connected function not disable charge pump.\r
+//!\r
+//! Modified bits are \b MBITx of \b LCDBMx register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void LCD_C_configChargePump(uint16_t baseAddress,\r
+ uint16_t syncToClock,\r
+ uint16_t functionControl);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_LCD_C_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// mpu.c - Driver for the mpu Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup mpu_api mpu\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_MPU__\r
+#include "mpu.h"\r
+\r
+#include <assert.h>\r
+\r
+//*****************************************************************************\r
+//\r
+// The following value is used by createTwoSegments, createThreeSegments to\r
+// check the user has passed a valid segmentation value. This value was\r
+// obtained from the User's Guide.\r
+//\r
+//*****************************************************************************\r
+#define MPU_MAX_SEG_VALUE 0x13C1\r
+\r
+void MPU_initTwoSegments(uint16_t baseAddress,\r
+ uint16_t seg1boundary,\r
+ uint8_t seg1accmask,\r
+ uint8_t seg2accmask)\r
+{\r
+ // Write MPU password to allow MPU register configuration\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(\r
+ baseAddress + OFS_MPUCTL0);\r
+\r
+ // Create two memory segmentations\r
+ HWREG16(baseAddress + OFS_MPUSEGB1) = seg1boundary;\r
+ HWREG16(baseAddress + OFS_MPUSEGB2) = seg1boundary;\r
+\r
+ // Set access rights based on user's selection for segment1\r
+ switch(seg1accmask)\r
+ {\r
+ case MPU_EXEC | MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1WE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1XE + MPUSEG1RE;\r
+ break;\r
+ case MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1XE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE + MPUSEG1WE;\r
+ break;\r
+ case MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE);\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE;\r
+ break;\r
+ case MPU_EXEC | MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) |= (MPUSEG1XE + MPUSEG1WE + MPUSEG1RE);\r
+ break;\r
+ case MPU_NO_READ_WRITE_EXEC:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE + MPUSEG1RE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ // Set access rights based on user's selection for segment2\r
+ switch(seg2accmask)\r
+ {\r
+ case MPU_EXEC | MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3WE + MPUSEG2WE);\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3XE + MPUSEG3RE +\r
+ MPUSEG2XE + MPUSEG2RE;\r
+ break;\r
+ case MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG2XE);\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE + MPUSEG3WE +\r
+ MPUSEG2RE + MPUSEG2WE;\r
+ break;\r
+ case MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE +\r
+ MPUSEG2XE + MPUSEG2WE);\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE + MPUSEG2RE;\r
+ break;\r
+ case MPU_EXEC | MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= (MPUSEG3XE + MPUSEG3WE +\r
+ MPUSEG3RE + MPUSEG2XE +\r
+ MPUSEG2WE + MPUSEG2RE);\r
+ break;\r
+ case MPU_NO_READ_WRITE_EXEC:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE +\r
+ MPUSEG3RE + MPUSEG2XE +\r
+ MPUSEG2WE + MPUSEG2RE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+}\r
+\r
+void MPU_initThreeSegments(uint16_t baseAddress,\r
+ MPU_initThreeSegmentsParam *param)\r
+{\r
+ // Write MPU password to allow MPU register configuration\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(\r
+ baseAddress + OFS_MPUCTL0);\r
+\r
+ // Create two memory segmentations\r
+ HWREG16(baseAddress + OFS_MPUSEGB1) = param->seg1boundary;\r
+ HWREG16(baseAddress + OFS_MPUSEGB2) = param->seg2boundary;\r
+\r
+ // Set access rights based on user's selection for segment1\r
+ switch(param->seg1accmask)\r
+ {\r
+ case MPU_EXEC | MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1WE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1XE + MPUSEG1RE;\r
+ break;\r
+ case MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1XE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE + MPUSEG1WE;\r
+ break;\r
+ case MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE);\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE;\r
+ break;\r
+ case MPU_EXEC | MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) |= (MPUSEG1XE + MPUSEG1WE + MPUSEG1RE);\r
+ break;\r
+ case MPU_NO_READ_WRITE_EXEC:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE + MPUSEG1RE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ // Set access rights based on user's selection for segment2\r
+ switch(param->seg2accmask)\r
+ {\r
+ case MPU_EXEC | MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG2WE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG2XE + MPUSEG2RE;\r
+ break;\r
+ case MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG2XE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG2RE + MPUSEG2WE;\r
+ break;\r
+ case MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG2XE + MPUSEG2WE);\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG2RE;\r
+ break;\r
+ case MPU_EXEC | MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) |= (MPUSEG2XE + MPUSEG2WE + MPUSEG2RE);\r
+ break;\r
+ case MPU_NO_READ_WRITE_EXEC:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) &= ~(MPUSEG2XE + MPUSEG2WE + MPUSEG2RE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ // Set access rights based on user's selection for segment3\r
+ switch(param->seg3accmask)\r
+ {\r
+ case MPU_EXEC | MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG3WE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3XE + MPUSEG3RE;\r
+ break;\r
+ case MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG3XE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE + MPUSEG3WE;\r
+ break;\r
+ case MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE);\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE;\r
+ break;\r
+ case MPU_EXEC | MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) |= (MPUSEG3XE + MPUSEG3WE + MPUSEG3WE);\r
+ break;\r
+ case MPU_NO_READ_WRITE_EXEC:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE + MPUSEG3WE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+}\r
+\r
+void MPU_initInfoSegment(uint16_t baseAddress,\r
+ uint8_t accmask)\r
+{\r
+ // Write MPU password to allow MPU register configuration\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(\r
+ baseAddress + OFS_MPUCTL0);\r
+\r
+ // Set access rights based on user's selection for segment1\r
+ switch(accmask)\r
+ {\r
+ case MPU_EXEC | MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEGIWE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEGIXE + MPUSEGIRE;\r
+ break;\r
+ case MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEGIXE;\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEGIRE + MPUSEGIWE;\r
+ break;\r
+ case MPU_READ:\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEGIXE + MPUSEGIWE);\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEGIRE;\r
+ break;\r
+ case MPU_EXEC | MPU_READ | MPU_WRITE:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) |= (MPUSEGIXE + MPUSEGIWE + MPUSEGIRE);\r
+ break;\r
+ case MPU_NO_READ_WRITE_EXEC:\r
+ HWREG16(baseAddress +\r
+ OFS_MPUSAM) &= ~(MPUSEGIXE + MPUSEGIWE + MPUSEGIRE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+}\r
+\r
+void MPU_enableNMIevent(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | MPUSEGIE |\r
+ HWREG8(baseAddress + OFS_MPUCTL0);\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+}\r
+\r
+void MPU_start(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | MPUENA | HWREG8(\r
+ baseAddress + OFS_MPUCTL0);\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+}\r
+\r
+void MPU_enablePUCOnViolation(uint16_t baseAddress,\r
+ uint16_t segment)\r
+{\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(\r
+ baseAddress + OFS_MPUCTL0);\r
+ HWREG16(baseAddress + OFS_MPUSAM) |= segment;\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+}\r
+\r
+void MPU_disablePUCOnViolation(uint16_t baseAddress,\r
+ uint16_t segment)\r
+{\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(\r
+ baseAddress + OFS_MPUCTL0);\r
+ HWREG16(baseAddress + OFS_MPUSAM) &= ~segment;\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+}\r
+\r
+uint16_t MPU_getInterruptStatus(uint16_t baseAddress,\r
+ uint16_t memAccFlag)\r
+{\r
+ return (HWREG16(baseAddress + OFS_MPUCTL1) & memAccFlag);\r
+}\r
+\r
+uint16_t MPU_clearInterrupt(uint16_t baseAddress,\r
+ uint16_t memAccFlag)\r
+{\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(\r
+ baseAddress + OFS_MPUCTL0);\r
+ HWREG16(baseAddress + OFS_MPUCTL1) &= ~memAccFlag;\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+\r
+ return (HWREG16(baseAddress + OFS_MPUCTL1) & memAccFlag);\r
+}\r
+\r
+uint16_t MPU_clearAllInterrupts(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(\r
+ baseAddress + OFS_MPUCTL0);\r
+ HWREG16(baseAddress +\r
+ OFS_MPUCTL1) &= ~(MPUSEG1IFG + MPUSEG2IFG + MPUSEG3IFG);\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+\r
+ return (HWREG16(baseAddress +\r
+ OFS_MPUCTL1) & (MPUSEG1IFG + MPUSEG2IFG + MPUSEG3IFG));\r
+}\r
+\r
+void MPU_lockMPU(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | MPULOCK |\r
+ HWREG8(baseAddress + OFS_MPUCTL0);\r
+\r
+ //Lock MPU to disable writing to all registers\r
+ HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for mpu_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// mpu.h - Driver for the MPU Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_MPU_H__\r
+#define __MSP430WARE_MPU_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_MPU__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the MPU_initThreeSegments() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct MPU_initThreeSegmentsParam\r
+{\r
+ //! Valid values can be found in the Family User's Guide\r
+ uint16_t seg1boundary;\r
+ //! Valid values can be found in the Family User's Guide\r
+ uint16_t seg2boundary;\r
+ //! Is the bit mask of access right for memory segment 1.\r
+ //! \n Logical OR of any of the following:\r
+ //! - \b MPU_READ\r
+ //! - \b MPU_WRITE\r
+ //! - \b MPU_EXEC\r
+ //! - \b MPU_NO_READ_WRITE_EXEC\r
+ uint8_t seg1accmask;\r
+ //! Is the bit mask of access right for memory segment 2.\r
+ //! \n Logical OR of any of the following:\r
+ //! - \b MPU_READ\r
+ //! - \b MPU_WRITE\r
+ //! - \b MPU_EXEC\r
+ //! - \b MPU_NO_READ_WRITE_EXEC\r
+ uint8_t seg2accmask;\r
+ //! Is the bit mask of access right for memory segment 3.\r
+ //! \n Logical OR of any of the following:\r
+ //! - \b MPU_READ\r
+ //! - \b MPU_WRITE\r
+ //! - \b MPU_EXEC\r
+ //! - \b MPU_NO_READ_WRITE_EXEC\r
+ uint8_t seg3accmask;\r
+} MPU_initThreeSegmentsParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the accmask parameter for\r
+// functions: MPU_initInfoSegment(); the seg2accmask parameter for functions:\r
+// MPU_initTwoSegments(); the seg1accmask parameter for functions:\r
+// MPU_initTwoSegments(); the param parameter for functions:\r
+// MPU_initThreeSegments(), MPU_initThreeSegments(), and\r
+// MPU_initThreeSegments().\r
+//\r
+//*****************************************************************************\r
+#define MPU_READ MPUSEG1RE\r
+#define MPU_WRITE MPUSEG1WE\r
+#define MPU_EXEC MPUSEG1XE\r
+#define MPU_NO_READ_WRITE_EXEC (0x0000)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the segment parameter for\r
+// functions: MPU_enablePUCOnViolation(), and MPU_disablePUCOnViolation().\r
+//\r
+//*****************************************************************************\r
+#define MPU_FIRST_SEG MPUSEG1VS\r
+#define MPU_SECOND_SEG MPUSEG2VS\r
+#define MPU_THIRD_SEG MPUSEG3VS\r
+#define MPU_INFO_SEG MPUSEGIVS\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the memAccFlag parameter for\r
+// functions: MPU_getInterruptStatus(), and MPU_clearInterrupt() as well as\r
+// returned by the MPU_getInterruptStatus() function, the\r
+// MPU_clearAllInterrupts() function and the MPU_clearInterrupt() function.\r
+//\r
+//*****************************************************************************\r
+#define MPU_SEG_1_ACCESS_VIOLATION MPUSEG1IFG\r
+#define MPU_SEG_2_ACCESS_VIOLATION MPUSEG2IFG\r
+#define MPU_SEG_3_ACCESS_VIOLATION MPUSEG3IFG\r
+#define MPU_SEG_INFO_ACCESS_VIOLATION MPUSEGIIFG\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes MPU with two memory segments\r
+//!\r
+//! This function creates two memory segments in FRAM allowing the user to set\r
+//! access right to each segment. To set the correct value for seg1boundary,\r
+//! the user must consult the Device Family User's Guide and provide the MPUSBx\r
+//! value corresponding to the memory address where the user wants to create\r
+//! the partition. Consult the "Segment Border Setting" section in the User's\r
+//! Guide to find the options available for MPUSBx.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//! \param seg1boundary Valid values can be found in the Family User's Guide\r
+//! \param seg1accmask is the bit mask of access right for memory segment 1.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b MPU_READ - Read rights\r
+//! - \b MPU_WRITE - Write rights\r
+//! - \b MPU_EXEC - Execute rights\r
+//! - \b MPU_NO_READ_WRITE_EXEC - no read/write/execute rights\r
+//! \param seg2accmask is the bit mask of access right for memory segment 2\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b MPU_READ - Read rights\r
+//! - \b MPU_WRITE - Write rights\r
+//! - \b MPU_EXEC - Execute rights\r
+//! - \b MPU_NO_READ_WRITE_EXEC - no read/write/execute rights\r
+//!\r
+//! Modified bits of \b MPUSAM register, bits of \b MPUSEG register and bits of\r
+//! \b MPUCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPU_initTwoSegments(uint16_t baseAddress,\r
+ uint16_t seg1boundary,\r
+ uint8_t seg1accmask,\r
+ uint8_t seg2accmask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes MPU with three memory segments\r
+//!\r
+//! This function creates three memory segments in FRAM allowing the user to\r
+//! set access right to each segment. To set the correct value for\r
+//! seg1boundary, the user must consult the Device Family User's Guide and\r
+//! provide the MPUSBx value corresponding to the memory address where the user\r
+//! wants to create the partition. Consult the "Segment Border Setting" section\r
+//! in the User's Guide to find the options available for MPUSBx.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//! \param param is the pointer to struct for initializing three segments.\r
+//!\r
+//! Modified bits of \b MPUSAM register, bits of \b MPUSEG register and bits of\r
+//! \b MPUCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPU_initThreeSegments(uint16_t baseAddress,\r
+ MPU_initThreeSegmentsParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes user information memory segment\r
+//!\r
+//! This function initializes user information memory segment with specified\r
+//! access rights.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//! \param accmask is the bit mask of access right for user information memory\r
+//! segment.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b MPU_READ - Read rights\r
+//! - \b MPU_WRITE - Write rights\r
+//! - \b MPU_EXEC - Execute rights\r
+//! - \b MPU_NO_READ_WRITE_EXEC - no read/write/execute rights\r
+//!\r
+//! Modified bits of \b MPUSAM register and bits of \b MPUCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPU_initInfoSegment(uint16_t baseAddress,\r
+ uint8_t accmask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief The following function enables the NMI Event if a Segment violation\r
+//! has occurred.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//!\r
+//! Modified bits of \b MPUCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPU_enableNMIevent(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief The following function enables the MPU module in the device.\r
+//!\r
+//! This function needs to be called once all memory segmentation has been\r
+//! done. If this function is not called the MPU module will not be activated.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//!\r
+//! Modified bits of \b MPUCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPU_start(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief The following function enables PUC generation when an access\r
+//! violation has occurred on the memory segment selected by the user.\r
+//!\r
+//! Note that only specified segments for PUC generation are enabled. Other\r
+//! segments for PUC generation are left untouched. Users may call\r
+//! MPU_enablePUCOnViolation() and MPU_disablePUCOnViolation() to assure that\r
+//! all the bits will be set and/or cleared.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//! \param segment is the bit mask of memory segment that will generate a PUC\r
+//! when an access violation occurs.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b MPU_FIRST_SEG - PUC generation on first memory segment\r
+//! - \b MPU_SECOND_SEG - PUC generation on second memory segment\r
+//! - \b MPU_THIRD_SEG - PUC generation on third memory segment\r
+//! - \b MPU_INFO_SEG - PUC generation on user information memory\r
+//! segment\r
+//!\r
+//! Modified bits of \b MPUSAM register and bits of \b MPUCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPU_enablePUCOnViolation(uint16_t baseAddress,\r
+ uint16_t segment);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief The following function disables PUC generation when an access\r
+//! violation has occurred on the memory segment selected by the user.\r
+//!\r
+//! Note that only specified segments for PUC generation are disabled. Other\r
+//! segments for PUC generation are left untouched. Users may call\r
+//! MPU_enablePUCOnViolation() and MPU_disablePUCOnViolation() to assure that\r
+//! all the bits will be set and/or cleared.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//! \param segment is the bit mask of memory segment that will NOT generate a\r
+//! PUC when an access violation occurs.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b MPU_FIRST_SEG - PUC generation on first memory segment\r
+//! - \b MPU_SECOND_SEG - PUC generation on second memory segment\r
+//! - \b MPU_THIRD_SEG - PUC generation on third memory segment\r
+//! - \b MPU_INFO_SEG - PUC generation on user information memory\r
+//! segment\r
+//!\r
+//! Modified bits of \b MPUSAM register and bits of \b MPUCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPU_disablePUCOnViolation(uint16_t baseAddress,\r
+ uint16_t segment);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the memory segment violation flag status requested by the\r
+//! user.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//! \param memAccFlag is the is the memory access violation flag.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b MPU_SEG_1_ACCESS_VIOLATION - is set if an access violation in\r
+//! Main Memory Segment 1 is detected\r
+//! - \b MPU_SEG_2_ACCESS_VIOLATION - is set if an access violation in\r
+//! Main Memory Segment 2 is detected\r
+//! - \b MPU_SEG_3_ACCESS_VIOLATION - is set if an access violation in\r
+//! Main Memory Segment 3 is detected\r
+//! - \b MPU_SEG_INFO_ACCESS_VIOLATION - is set if an access violation\r
+//! in User Information Memory Segment is detected\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b MPU_SEG_1_ACCESS_VIOLATION is set if an access violation in\r
+//! Main Memory Segment 1 is detected\r
+//! - \b MPU_SEG_2_ACCESS_VIOLATION is set if an access violation in\r
+//! Main Memory Segment 2 is detected\r
+//! - \b MPU_SEG_3_ACCESS_VIOLATION is set if an access violation in\r
+//! Main Memory Segment 3 is detected\r
+//! - \b MPU_SEG_INFO_ACCESS_VIOLATION is set if an access violation in\r
+//! User Information Memory Segment is detected\r
+//! \n indicating the status of the masked flags.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t MPU_getInterruptStatus(uint16_t baseAddress,\r
+ uint16_t memAccFlag);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the masked interrupt flags\r
+//!\r
+//! Returns the memory segment violation flag status requested by the user or\r
+//! if user is providing a bit mask value, the function will return a value\r
+//! indicating if all flags were cleared.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//! \param memAccFlag is the is the memory access violation flag.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b MPU_SEG_1_ACCESS_VIOLATION - is set if an access violation in\r
+//! Main Memory Segment 1 is detected\r
+//! - \b MPU_SEG_2_ACCESS_VIOLATION - is set if an access violation in\r
+//! Main Memory Segment 2 is detected\r
+//! - \b MPU_SEG_3_ACCESS_VIOLATION - is set if an access violation in\r
+//! Main Memory Segment 3 is detected\r
+//! - \b MPU_SEG_INFO_ACCESS_VIOLATION - is set if an access violation\r
+//! in User Information Memory Segment is detected\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b MPU_SEG_1_ACCESS_VIOLATION is set if an access violation in\r
+//! Main Memory Segment 1 is detected\r
+//! - \b MPU_SEG_2_ACCESS_VIOLATION is set if an access violation in\r
+//! Main Memory Segment 2 is detected\r
+//! - \b MPU_SEG_3_ACCESS_VIOLATION is set if an access violation in\r
+//! Main Memory Segment 3 is detected\r
+//! - \b MPU_SEG_INFO_ACCESS_VIOLATION is set if an access violation in\r
+//! User Information Memory Segment is detected\r
+//! \n indicating the status of the masked flags.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t MPU_clearInterrupt(uint16_t baseAddress,\r
+ uint16_t memAccFlag);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears all Memory Segment Access Violation Interrupt Flags.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//!\r
+//! Modified bits of \b MPUCTL1 register.\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b MPU_SEG_1_ACCESS_VIOLATION is set if an access violation in\r
+//! Main Memory Segment 1 is detected\r
+//! - \b MPU_SEG_2_ACCESS_VIOLATION is set if an access violation in\r
+//! Main Memory Segment 2 is detected\r
+//! - \b MPU_SEG_3_ACCESS_VIOLATION is set if an access violation in\r
+//! Main Memory Segment 3 is detected\r
+//! - \b MPU_SEG_INFO_ACCESS_VIOLATION is set if an access violation in\r
+//! User Information Memory Segment is detected\r
+//! \n indicating the status of the interrupt flags.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t MPU_clearAllInterrupts(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Lock MPU to protect from write access.\r
+//!\r
+//! Sets MPULOCK to protect MPU from write access on all MPU registers except\r
+//! MPUCTL1, MPUIPC0 and MPUIPSEGBx until a BOR occurs. MPULOCK bit cannot be\r
+//! cleared manually. MPU_clearInterrupt() and MPU_clearAllInterrupts() still\r
+//! can be used after this API is called.\r
+//!\r
+//! \param baseAddress is the base address of the MPU module.\r
+//!\r
+//! Modified bits are \b MPULOCK of \b MPUCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPU_lockMPU(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_MPU_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// mpy32.c - Driver for the mpy32 Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup mpy32_api mpy32\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_MPY32__\r
+#include "mpy32.h"\r
+\r
+#include <assert.h>\r
+\r
+void MPY32_setWriteDelay(uint16_t writeDelaySelect)\r
+{\r
+ HWREG16(MPY32_BASE + OFS_MPY32CTL0) &= ~(MPYDLY32 + MPYDLYWRTEN);\r
+ HWREG16(MPY32_BASE + OFS_MPY32CTL0) |= writeDelaySelect;\r
+}\r
+\r
+void MPY32_enableSaturationMode(void)\r
+{\r
+ HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) |= MPYSAT;\r
+}\r
+\r
+void MPY32_disableSaturationMode(void)\r
+{\r
+ HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) &= ~(MPYSAT);\r
+}\r
+\r
+uint8_t MPY32_getSaturationMode(void)\r
+{\r
+ return (HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) & (MPYSAT));\r
+}\r
+\r
+void MPY32_enableFractionalMode(void)\r
+{\r
+ HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) |= MPYFRAC;\r
+}\r
+\r
+void MPY32_disableFractionalMode(void)\r
+{\r
+ HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) &= ~(MPYFRAC);\r
+}\r
+\r
+uint8_t MPY32_getFractionalMode(void)\r
+{\r
+ return (HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) & (MPYFRAC));\r
+}\r
+\r
+void MPY32_setOperandOne8Bit(uint8_t multiplicationType,\r
+ uint8_t operand)\r
+{\r
+ HWREG8(MPY32_BASE + OFS_MPY + multiplicationType) = operand;\r
+}\r
+\r
+void MPY32_setOperandOne16Bit(uint8_t multiplicationType,\r
+ uint16_t operand)\r
+{\r
+ HWREG16(MPY32_BASE + OFS_MPY + multiplicationType) = operand;\r
+}\r
+\r
+void MPY32_setOperandOne24Bit(uint8_t multiplicationType,\r
+ uint32_t operand)\r
+{\r
+ multiplicationType <<= 1;\r
+ HWREG16(MPY32_BASE + OFS_MPY32L + multiplicationType) = operand;\r
+ HWREG8(MPY32_BASE + OFS_MPY32H + multiplicationType) = (operand >> 16);\r
+}\r
+\r
+void MPY32_setOperandOne32Bit(uint8_t multiplicationType,\r
+ uint32_t operand)\r
+{\r
+ multiplicationType <<= 1;\r
+ HWREG16(MPY32_BASE + OFS_MPY32L + multiplicationType) = operand;\r
+ HWREG16(MPY32_BASE + OFS_MPY32H + multiplicationType) = (operand >> 16);\r
+}\r
+\r
+void MPY32_setOperandTwo8Bit(uint8_t operand)\r
+{\r
+ HWREG8(MPY32_BASE + OFS_OP2) = operand;\r
+}\r
+\r
+void MPY32_setOperandTwo16Bit(uint16_t operand)\r
+{\r
+ HWREG16(MPY32_BASE + OFS_OP2) = operand;\r
+}\r
+\r
+void MPY32_setOperandTwo24Bit(uint32_t operand)\r
+{\r
+ HWREG16(MPY32_BASE + OFS_OP2L) = operand;\r
+ HWREG8(MPY32_BASE + OFS_OP2H) = (operand >> 16);\r
+}\r
+\r
+void MPY32_setOperandTwo32Bit(uint32_t operand)\r
+{\r
+ HWREG16(MPY32_BASE + OFS_OP2L) = operand;\r
+ HWREG16(MPY32_BASE + OFS_OP2H) = (operand >> 16);\r
+}\r
+\r
+uint64_t MPY32_getResult(void)\r
+{\r
+ uint64_t result;\r
+\r
+ result = HWREG16(MPY32_BASE + OFS_RES0);\r
+ result += ((uint64_t)HWREG16(MPY32_BASE + OFS_RES1) << 16);\r
+ result += ((uint64_t)HWREG16(MPY32_BASE + OFS_RES2) << 32);\r
+ result += ((uint64_t)HWREG16(MPY32_BASE + OFS_RES3) << 48);\r
+ return (result);\r
+}\r
+\r
+uint16_t MPY32_getSumExtension(void)\r
+{\r
+ return (HWREG16(MPY32_BASE + OFS_SUMEXT));\r
+}\r
+\r
+uint16_t MPY32_getCarryBitValue(void)\r
+{\r
+ return (HWREG16(MPY32_BASE + OFS_MPY32CTL0) | MPYC);\r
+}\r
+\r
+void MPY32_clearCarryBitValue(void)\r
+{\r
+ HWREG16(MPY32_BASE + OFS_MPY32CTL0) &= ~MPYC;\r
+}\r
+\r
+void MPY32_preloadResult(uint64_t result)\r
+{\r
+ HWREG16(MPY32_BASE + OFS_RES0) = (result & 0xFFFF);\r
+ HWREG16(MPY32_BASE + OFS_RES1) = ((result >> 16) & 0xFFFF);\r
+ HWREG16(MPY32_BASE + OFS_RES2) = ((result >> 32) & 0xFFFF);\r
+ HWREG16(MPY32_BASE + OFS_RES3) = ((result >> 48) & 0xFFFF);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for mpy32_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// mpy32.h - Driver for the MPY32 Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_MPY32_H__\r
+#define __MSP430WARE_MPY32_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_MPY32__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the writeDelaySelect\r
+// parameter for functions: MPY32_setWriteDelay().\r
+//\r
+//*****************************************************************************\r
+#define MPY32_WRITEDELAY_OFF (!(MPYDLY32 + MPYDLYWRTEN))\r
+#define MPY32_WRITEDELAY_32BIT (MPYDLYWRTEN)\r
+#define MPY32_WRITEDELAY_64BIT (MPYDLY32 + MPYDLYWRTEN)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the multiplicationType\r
+// parameter for functions: MPY32_setOperandOne8Bit(),\r
+// MPY32_setOperandOne16Bit(), MPY32_setOperandOne24Bit(), and\r
+// MPY32_setOperandOne32Bit().\r
+//\r
+//*****************************************************************************\r
+#define MPY32_MULTIPLY_UNSIGNED (0x00)\r
+#define MPY32_MULTIPLY_SIGNED (0x02)\r
+#define MPY32_MULTIPLYACCUMULATE_UNSIGNED (0x04)\r
+#define MPY32_MULTIPLYACCUMULATE_SIGNED (0x06)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the MPY32_getSaturationMode() function.\r
+//\r
+//*****************************************************************************\r
+#define MPY32_SATURATION_MODE_DISABLED 0x00\r
+#define MPY32_SATURATION_MODE_ENABLED MPYSAT\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the MPY32_getFractionalMode() function.\r
+//\r
+//*****************************************************************************\r
+#define MPY32_FRACTIONAL_MODE_DISABLED 0x00\r
+#define MPY32_FRACTIONAL_MODE_ENABLED MPYFRAC\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the write delay setting for the MPY32 module.\r
+//!\r
+//! This function sets up a write delay to the MPY module's registers, which\r
+//! holds any writes to the registers until all calculations are complete.\r
+//! There are two different settings, one which waits for 32-bit results to be\r
+//! ready, and one which waits for 64-bit results to be ready. This prevents\r
+//! unpredicatble results if registers are changed before the results are\r
+//! ready.\r
+//!\r
+//! \param writeDelaySelect delays the write to any MPY32 register until the\r
+//! selected bit size of result has been written.\r
+//! Valid values are:\r
+//! - \b MPY32_WRITEDELAY_OFF [Default] - writes are not delayed\r
+//! - \b MPY32_WRITEDELAY_32BIT - writes are delayed until a 32-bit\r
+//! result is available in the result registers\r
+//! - \b MPY32_WRITEDELAY_64BIT - writes are delayed until a 64-bit\r
+//! result is available in the result registers\r
+//! \n Modified bits are \b MPYDLY32 and \b MPYDLYWRTEN of \b MPY32CTL0\r
+//! register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_setWriteDelay(uint16_t writeDelaySelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables Saturation Mode.\r
+//!\r
+//! This function enables saturation mode. When this is enabled, the result\r
+//! read out from the MPY result registers is converted to the most-positive\r
+//! number in the case of an overflow, or the most-negative number in the case\r
+//! of an underflow. Please note, that the raw value in the registers does not\r
+//! reflect the result returned, and if the saturation mode is disabled, then\r
+//! the raw value of the registers will be returned instead.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_enableSaturationMode(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables Saturation Mode.\r
+//!\r
+//! This function disables saturation mode, which allows the raw result of the\r
+//! MPY result registers to be returned.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_disableSaturationMode(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the Saturation Mode.\r
+//!\r
+//! This function gets the current saturation mode.\r
+//!\r
+//!\r
+//! \return Gets the Saturation Mode\r
+//! Return one of the following:\r
+//! - \b MPY32_SATURATION_MODE_DISABLED\r
+//! - \b MPY32_SATURATION_MODE_ENABLED\r
+//! \n Gets the Saturation Mode\r
+//\r
+//*****************************************************************************\r
+extern uint8_t MPY32_getSaturationMode(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables Fraction Mode.\r
+//!\r
+//! This function enables fraction mode.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_enableFractionalMode(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables Fraction Mode.\r
+//!\r
+//! This function disables fraction mode.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_disableFractionalMode(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the Fractional Mode.\r
+//!\r
+//! This function gets the current fractional mode.\r
+//!\r
+//!\r
+//! \return Gets the fractional mode\r
+//! Return one of the following:\r
+//! - \b MPY32_FRACTIONAL_MODE_DISABLED\r
+//! - \b MPY32_FRACTIONAL_MODE_ENABLED\r
+//! \n Gets the Fractional Mode\r
+//\r
+//*****************************************************************************\r
+extern uint8_t MPY32_getFractionalMode(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets an 8-bit value into operand 1.\r
+//!\r
+//! This function sets the first operand for multiplication and determines what\r
+//! type of operation should be performed. Once the second operand is set, then\r
+//! the operation will begin.\r
+//!\r
+//! \param multiplicationType is the type of multiplication to perform once the\r
+//! second operand is set.\r
+//! Valid values are:\r
+//! - \b MPY32_MULTIPLY_UNSIGNED\r
+//! - \b MPY32_MULTIPLY_SIGNED\r
+//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED\r
+//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED\r
+//! \param operand is the 8-bit value to load into the 1st operand.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_setOperandOne8Bit(uint8_t multiplicationType,\r
+ uint8_t operand);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets an 16-bit value into operand 1.\r
+//!\r
+//! This function sets the first operand for multiplication and determines what\r
+//! type of operation should be performed. Once the second operand is set, then\r
+//! the operation will begin.\r
+//!\r
+//! \param multiplicationType is the type of multiplication to perform once the\r
+//! second operand is set.\r
+//! Valid values are:\r
+//! - \b MPY32_MULTIPLY_UNSIGNED\r
+//! - \b MPY32_MULTIPLY_SIGNED\r
+//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED\r
+//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED\r
+//! \param operand is the 16-bit value to load into the 1st operand.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_setOperandOne16Bit(uint8_t multiplicationType,\r
+ uint16_t operand);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets an 24-bit value into operand 1.\r
+//!\r
+//! This function sets the first operand for multiplication and determines what\r
+//! type of operation should be performed. Once the second operand is set, then\r
+//! the operation will begin.\r
+//!\r
+//! \param multiplicationType is the type of multiplication to perform once the\r
+//! second operand is set.\r
+//! Valid values are:\r
+//! - \b MPY32_MULTIPLY_UNSIGNED\r
+//! - \b MPY32_MULTIPLY_SIGNED\r
+//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED\r
+//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED\r
+//! \param operand is the 24-bit value to load into the 1st operand.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_setOperandOne24Bit(uint8_t multiplicationType,\r
+ uint32_t operand);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets an 32-bit value into operand 1.\r
+//!\r
+//! This function sets the first operand for multiplication and determines what\r
+//! type of operation should be performed. Once the second operand is set, then\r
+//! the operation will begin.\r
+//!\r
+//! \param multiplicationType is the type of multiplication to perform once the\r
+//! second operand is set.\r
+//! Valid values are:\r
+//! - \b MPY32_MULTIPLY_UNSIGNED\r
+//! - \b MPY32_MULTIPLY_SIGNED\r
+//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED\r
+//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED\r
+//! \param operand is the 32-bit value to load into the 1st operand.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_setOperandOne32Bit(uint8_t multiplicationType,\r
+ uint32_t operand);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets an 8-bit value into operand 2, which starts the multiplication.\r
+//!\r
+//! This function sets the second operand of the multiplication operation and\r
+//! starts the operation.\r
+//!\r
+//! \param operand is the 8-bit value to load into the 2nd operand.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_setOperandTwo8Bit(uint8_t operand);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets an 16-bit value into operand 2, which starts the\r
+//! multiplication.\r
+//!\r
+//! This function sets the second operand of the multiplication operation and\r
+//! starts the operation.\r
+//!\r
+//! \param operand is the 16-bit value to load into the 2nd operand.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_setOperandTwo16Bit(uint16_t operand);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets an 24-bit value into operand 2, which starts the\r
+//! multiplication.\r
+//!\r
+//! This function sets the second operand of the multiplication operation and\r
+//! starts the operation.\r
+//!\r
+//! \param operand is the 24-bit value to load into the 2nd operand.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_setOperandTwo24Bit(uint32_t operand);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets an 32-bit value into operand 2, which starts the\r
+//! multiplication.\r
+//!\r
+//! This function sets the second operand of the multiplication operation and\r
+//! starts the operation.\r
+//!\r
+//! \param operand is the 32-bit value to load into the 2nd operand.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_setOperandTwo32Bit(uint32_t operand);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns an 64-bit result of the last multiplication operation.\r
+//!\r
+//! This function returns all 64 bits of the result registers\r
+//!\r
+//!\r
+//! \return The 64-bit result is returned as a uint64_t type\r
+//\r
+//*****************************************************************************\r
+extern uint64_t MPY32_getResult(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the Sum Extension of the last multiplication operation.\r
+//!\r
+//! This function returns the Sum Extension of the MPY module, which either\r
+//! gives the sign after a signed operation or shows a carry after a multiply-\r
+//! and-accumulate operation. The Sum Extension acts as a check for overflows\r
+//! or underflows.\r
+//!\r
+//!\r
+//! \return The value of the MPY32 module Sum Extension.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t MPY32_getSumExtension(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the Carry Bit of the last multiplication operation.\r
+//!\r
+//! This function returns the Carry Bit of the MPY module, which either gives\r
+//! the sign after a signed operation or shows a carry after a multiply- and-\r
+//! accumulate operation.\r
+//!\r
+//!\r
+//! \return The value of the MPY32 module Carry Bit 0x0 or 0x1.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t MPY32_getCarryBitValue(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the Carry Bit of the last multiplication operation.\r
+//!\r
+//! This function clears the Carry Bit of the MPY module\r
+//!\r
+//!\r
+//! \return The value of the MPY32 module Carry Bit 0x0 or 0x1.\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_clearCarryBitValue(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Preloads the result register\r
+//!\r
+//! This function Preloads the result register\r
+//!\r
+//! \param result value to preload the result register to\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void MPY32_preloadResult(uint64_t result);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_MPY32_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// pmm.c - Driver for the pmm Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup pmm_api pmm\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_PMM_FRAM__\r
+#include "pmm.h"\r
+\r
+#include <assert.h>\r
+\r
+void PMM_enableLowPowerReset(void)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0) |= PMMLPRST;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
+}\r
+\r
+void PMM_disableLowPowerReset(void)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0) &= ~PMMLPRST;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
+}\r
+\r
+void PMM_enableSVSH(void)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_L) |= SVSHE;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
+}\r
+\r
+void PMM_disableSVSH(void)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_L) &= ~SVSHE;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
+}\r
+\r
+void PMM_turnOnRegulator(void)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0) &= ~PMMREGOFF;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
+}\r
+\r
+void PMM_turnOffRegulator(void)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0) |= PMMREGOFF;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
+}\r
+\r
+void PMM_trigPOR(void)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0) |= PMMSWPOR;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
+}\r
+\r
+void PMM_trigBOR(void)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0) |= PMMSWBOR;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
+}\r
+\r
+void PMM_clearInterrupt(uint16_t mask)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H;\r
+ HWREG16(PMM_BASE + OFS_PMMIFG) &= ~mask;\r
+ HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
+}\r
+\r
+uint16_t PMM_getInterruptStatus(uint16_t mask)\r
+{\r
+ return ((HWREG16(PMM_BASE + OFS_PMMIFG)) & mask);\r
+}\r
+\r
+void PMM_unlockLPM5(void)\r
+{\r
+ HWREG8(PMM_BASE + OFS_PM5CTL0) &= ~LOCKLPM5;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for pmm_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// pmm.h - Driver for the PMM Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_PMM_H__\r
+#define __MSP430WARE_PMM_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_PMM_FRAM__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: PMM_clearInterrupt(), and PMM_getInterruptStatus() as well as\r
+// returned by the PMM_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define PMM_BOR_INTERRUPT PMMBORIFG\r
+#define PMM_RST_INTERRUPT PMMRSTIFG\r
+#define PMM_POR_INTERRUPT PMMPORIFG\r
+#define PMM_SVSH_INTERRUPT SVSHIFG\r
+#define PMM_LPM5_INTERRUPT PMMLPM5IFG\r
+#define PMM_ALL (0xA7)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the low power reset. SVSH does not reset device, but\r
+//! triggers a system NMI\r
+//!\r
+//!\r
+//! Modified bits of \b PMMCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_enableLowPowerReset(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the low power reset. SVSH resets device.\r
+//!\r
+//!\r
+//! Modified bits of \b PMMCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_disableLowPowerReset(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the high-side SVS circuitry\r
+//!\r
+//!\r
+//! Modified bits of \b PMMCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_enableSVSH(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the high-side SVS circuitry\r
+//!\r
+//!\r
+//! Modified bits of \b PMMCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_disableSVSH(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Makes the low-dropout voltage regulator (LDO) remain ON when going\r
+//! into LPM 3/4.\r
+//!\r
+//!\r
+//! Modified bits of \b PMMCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_turnOnRegulator(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Turns OFF the low-dropout voltage regulator (LDO) when going into\r
+//! LPM3/4, thus the system will enter LPM3.5 or LPM4.5 respectively\r
+//!\r
+//!\r
+//! Modified bits of \b PMMCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_turnOffRegulator(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Calling this function will trigger a software Power On Reset (POR).\r
+//!\r
+//!\r
+//! Modified bits of \b PMMCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_trigPOR(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Calling this function will trigger a software Brown Out Rest (BOR).\r
+//!\r
+//!\r
+//! Modified bits of \b PMMCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_trigBOR(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears interrupt flags for the PMM\r
+//!\r
+//! \param mask is the mask for specifying the required flag\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b PMM_BOR_INTERRUPT - Software BOR interrupt\r
+//! - \b PMM_RST_INTERRUPT - RESET pin interrupt\r
+//! - \b PMM_POR_INTERRUPT - Software POR interrupt\r
+//! - \b PMM_SVSH_INTERRUPT - SVS high side interrupt\r
+//! - \b PMM_LPM5_INTERRUPT - LPM5 indication\r
+//! - \b PMM_ALL - All interrupts\r
+//!\r
+//! Modified bits of \b PMMCTL0 register and bits of \b PMMIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_clearInterrupt(uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns interrupt status\r
+//!\r
+//! \param mask is the mask for specifying the required flag\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b PMM_BOR_INTERRUPT - Software BOR interrupt\r
+//! - \b PMM_RST_INTERRUPT - RESET pin interrupt\r
+//! - \b PMM_POR_INTERRUPT - Software POR interrupt\r
+//! - \b PMM_SVSH_INTERRUPT - SVS high side interrupt\r
+//! - \b PMM_LPM5_INTERRUPT - LPM5 indication\r
+//! - \b PMM_ALL - All interrupts\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b PMM_BOR_INTERRUPT Software BOR interrupt\r
+//! - \b PMM_RST_INTERRUPT RESET pin interrupt\r
+//! - \b PMM_POR_INTERRUPT Software POR interrupt\r
+//! - \b PMM_SVSH_INTERRUPT SVS high side interrupt\r
+//! - \b PMM_LPM5_INTERRUPT LPM5 indication\r
+//! - \b PMM_ALL All interrupts\r
+//! \n indicating the status of the selected interrupt flags\r
+//\r
+//*****************************************************************************\r
+extern uint16_t PMM_getInterruptStatus(uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Unlock LPM5\r
+//!\r
+//! LPMx.5 configuration is not locked and defaults to its reset condition.\r
+//! Disable the GPIO power-on default high-impedance mode to activate\r
+//! previously configured port settings.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void PMM_unlockLPM5(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_PMM_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// ram.c - Driver for the ram Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ram_api ram\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_RC_FRAM__\r
+#include "ram.h"\r
+\r
+#include <assert.h>\r
+\r
+void RAM_setSectorOff(uint8_t sector,\r
+ uint8_t mode)\r
+{\r
+ uint8_t sectorPos = sector << 1;\r
+ uint8_t val = HWREG8(RAM_BASE + OFS_RCCTL0_L) & ~(0x3 << sectorPos);\r
+\r
+ HWREG16(RAM_BASE + OFS_RCCTL0) = (RCKEY | val | (mode << sectorPos));\r
+}\r
+\r
+uint8_t RAM_getSectorState(uint8_t sector)\r
+{\r
+ uint8_t sectorPos = sector << 1;\r
+ return((HWREG8(RAM_BASE + OFS_RCCTL0_L) & (0x3 << sectorPos)) >> sectorPos);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for ram_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// ram.h - Driver for the RAM Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_RAM_H__\r
+#define __MSP430WARE_RAM_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_RC_FRAM__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the sector parameter for\r
+// functions: RAM_setSectorOff(), and RAM_getSectorState().\r
+//\r
+//*****************************************************************************\r
+#define RAM_SECTOR0 (0x00)\r
+#define RAM_SECTOR1 (0x01)\r
+#define RAM_SECTOR2 (0x02)\r
+#define RAM_SECTOR3 (0x03)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mode parameter for\r
+// functions: RAM_setSectorOff() as well as returned by the\r
+// RAM_getSectorState() function.\r
+//\r
+//*****************************************************************************\r
+#define RAM_RETENTION_MODE (0x00)\r
+#define RAM_OFF_WAKEUP_MODE (RCRS0OFF0)\r
+#define RAM_OFF_NON_WAKEUP_MODE (RCRS0OFF1)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Set specified RAM sector off\r
+//!\r
+//! \param sector is specified sector to be set off.\r
+//! Valid values are:\r
+//! - \b RAM_SECTOR0\r
+//! - \b RAM_SECTOR1\r
+//! - \b RAM_SECTOR2\r
+//! - \b RAM_SECTOR3\r
+//! \param mode is sector off mode\r
+//! Valid values are:\r
+//! - \b RAM_RETENTION_MODE\r
+//! - \b RAM_OFF_WAKEUP_MODE\r
+//! - \b RAM_OFF_NON_WAKEUP_MODE\r
+//!\r
+//! Modified bits of \b RCCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RAM_setSectorOff(uint8_t sector,\r
+ uint8_t mode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get RAM sector ON/OFF status\r
+//!\r
+//! \param sector is specified sector\r
+//! Valid values are:\r
+//! - \b RAM_SECTOR0\r
+//! - \b RAM_SECTOR1\r
+//! - \b RAM_SECTOR2\r
+//! - \b RAM_SECTOR3\r
+//!\r
+//! \return One of the following:\r
+//! - \b RAM_RETENTION_MODE\r
+//! - \b RAM_OFF_WAKEUP_MODE\r
+//! - \b RAM_OFF_NON_WAKEUP_MODE\r
+//! \n indicating the status of the masked sectors\r
+//\r
+//*****************************************************************************\r
+extern uint8_t RAM_getSectorState(uint8_t sector);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_RAM_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// ref_a.c - Driver for the ref_a Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ref_a_api ref_a\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_REF_A__\r
+#include "ref_a.h"\r
+\r
+#include <assert.h>\r
+\r
+void Ref_A_setReferenceVoltage(uint16_t baseAddress,\r
+ uint8_t referenceVoltageSelect)\r
+{\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFVSEL_3);\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) |= referenceVoltageSelect;\r
+}\r
+\r
+void Ref_A_disableTempSensor(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) |= REFTCOFF;\r
+}\r
+\r
+void Ref_A_enableTempSensor(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFTCOFF);\r
+}\r
+\r
+void Ref_A_enableReferenceVoltageOutput(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) |= REFOUT;\r
+}\r
+\r
+void Ref_A_disableReferenceVoltageOutput(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFOUT);\r
+}\r
+\r
+void Ref_A_enableReferenceVoltage(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) |= REFON;\r
+}\r
+\r
+void Ref_A_disableReferenceVoltage(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFON);\r
+}\r
+\r
+uint16_t Ref_A_getBandgapMode(uint16_t baseAddress)\r
+{\r
+ return (HWREG16((baseAddress) + OFS_REFCTL0) & BGMODE);\r
+}\r
+\r
+bool Ref_A_isBandgapActive(uint16_t baseAddress)\r
+{\r
+ if(HWREG16((baseAddress) + OFS_REFCTL0) & REFBGACT)\r
+ {\r
+ return (REF_A_ACTIVE);\r
+ }\r
+ else\r
+ {\r
+ return (REF_A_INACTIVE);\r
+ }\r
+}\r
+\r
+uint16_t Ref_A_isRefGenBusy(uint16_t baseAddress)\r
+{\r
+ return (HWREG16((baseAddress) + OFS_REFCTL0) & REFGENBUSY);\r
+}\r
+\r
+bool Ref_A_isRefGenActive(uint16_t baseAddress)\r
+{\r
+ if(HWREG16((baseAddress) + OFS_REFCTL0) & REFGENACT)\r
+ {\r
+ return (REF_A_ACTIVE);\r
+ }\r
+ else\r
+ {\r
+ return (REF_A_INACTIVE);\r
+ }\r
+}\r
+\r
+bool Ref_A_isBufferedBandgapVoltageReady(uint16_t baseAddress)\r
+{\r
+ if(HWREG16((baseAddress) + OFS_REFCTL0) & REFBGRDY)\r
+ {\r
+ return (REF_A_READY);\r
+ }\r
+ else\r
+ {\r
+ return (REF_A_NOTREADY);\r
+ }\r
+}\r
+\r
+bool Ref_A_isVariableReferenceVoltageOutputReady(uint16_t baseAddress)\r
+{\r
+ if(HWREG16((baseAddress) + OFS_REFCTL0) & REFGENRDY)\r
+ {\r
+ return (REF_A_READY);\r
+ }\r
+ else\r
+ {\r
+ return (REF_A_NOTREADY);\r
+ }\r
+}\r
+\r
+void Ref_A_setReferenceVoltageOneTimeTrigger(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) |= REFGENOT;\r
+}\r
+\r
+void Ref_A_setBufferedBandgapVoltageOneTimeTrigger(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_REFCTL0_L) |= REFBGOT;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for ref_a_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// ref_a.h - Driver for the REF_A Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_REF_A_H__\r
+#define __MSP430WARE_REF_A_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_REF_A__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the referenceVoltageSelect\r
+// parameter for functions: Ref_A_setReferenceVoltage().\r
+//\r
+//*****************************************************************************\r
+#define REF_A_VREF1_2V (REFVSEL_0)\r
+#define REF_A_VREF2_0V (REFVSEL_1)\r
+#define REF_A_VREF2_5V (REFVSEL_2)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the Ref_A_isBandgapActive() function and the\r
+// Ref_A_isRefGenActive() function.\r
+//\r
+//*****************************************************************************\r
+#define REF_A_ACTIVE true\r
+#define REF_A_INACTIVE false\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the Ref_A_getBandgapMode() function.\r
+//\r
+//*****************************************************************************\r
+#define REF_A_STATICMODE 0x00\r
+#define REF_A_SAMPLEMODE BGMODE\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the Ref_A_isRefGenBusy() function.\r
+//\r
+//*****************************************************************************\r
+#define REF_A_NOTBUSY 0x00\r
+#define REF_A_BUSY REFGENBUSY\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the Ref_A_isVariableReferenceVoltageOutputReady()\r
+// function and the Ref_A_isBufferedBandgapVoltageReady() function.\r
+//\r
+//*****************************************************************************\r
+#define REF_A_NOTREADY false\r
+#define REF_A_READY true\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the reference voltage for the voltage generator.\r
+//!\r
+//! This function sets the reference voltage generated by the voltage generator\r
+//! to be used by other peripherals. This reference voltage will only be valid\r
+//! while the Ref_A module is in control. Please note, if the\r
+//! Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function will have no effect.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//! \param referenceVoltageSelect is the desired voltage to generate for a\r
+//! reference voltage.\r
+//! Valid values are:\r
+//! - \b REF_A_VREF1_2V [Default]\r
+//! - \b REF_A_VREF2_0V\r
+//! - \b REF_A_VREF2_5V\r
+//! \n Modified bits are \b REFVSEL of \b REFCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Ref_A_setReferenceVoltage(uint16_t baseAddress,\r
+ uint8_t referenceVoltageSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the internal temperature sensor to save power consumption.\r
+//!\r
+//! This function is used to turn off the internal temperature sensor to save\r
+//! on power consumption. The temperature sensor is enabled by default. Please\r
+//! note, that giving ADC12 module control over the Ref_A module, the state of\r
+//! the temperature sensor is dependent on the controls of the ADC12 module.\r
+//! Please note, if the Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function\r
+//! will have no effect.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! Modified bits are \b REFTCOFF of \b REFCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Ref_A_disableTempSensor(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the internal temperature sensor.\r
+//!\r
+//! This function is used to turn on the internal temperature sensor to use by\r
+//! other peripherals. The temperature sensor is enabled by default. Please\r
+//! note, if the Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function will\r
+//! have no effect.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! Modified bits are \b REFTCOFF of \b REFCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Ref_A_enableTempSensor(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Outputs the reference voltage to an output pin.\r
+//!\r
+//! This function is used to output the reference voltage being generated to an\r
+//! output pin. Please note, the output pin is device specific. Please note,\r
+//! that giving ADC12 module control over the Ref_A module, the state of the\r
+//! reference voltage as an output to a pin is dependent on the controls of the\r
+//! ADC12 module. Please note, if the Ref_A_isRefGenBusy() returns Ref_A_BUSY,\r
+//! this function will have no effect.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! Modified bits are \b REFOUT of \b REFCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Ref_A_enableReferenceVoltageOutput(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the reference voltage as an output to a pin.\r
+//!\r
+//! This function is used to disables the reference voltage being generated to\r
+//! be given to an output pin. Please note, if the Ref_A_isRefGenBusy() returns\r
+//! Ref_A_BUSY, this function will have no effect.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! Modified bits are \b REFOUT of \b REFCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Ref_A_disableReferenceVoltageOutput(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the reference voltage to be used by peripherals.\r
+//!\r
+//! This function is used to enable the generated reference voltage to be used\r
+//! other peripherals or by an output pin, if enabled. Please note, that giving\r
+//! ADC12 module control over the Ref_A module, the state of the reference\r
+//! voltage is dependent on the controls of the ADC12 module. Please note, if\r
+//! the Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function will have no\r
+//! effect.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! Modified bits are \b REFON of \b REFCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Ref_A_enableReferenceVoltage(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the reference voltage.\r
+//!\r
+//! This function is used to disable the generated reference voltage. Please\r
+//! note, if the Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function will\r
+//! have no effect.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! Modified bits are \b REFON of \b REFCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Ref_A_disableReferenceVoltage(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the bandgap mode of the Ref_A module.\r
+//!\r
+//! This function is used to return the bandgap mode of the Ref_A module,\r
+//! requested by the peripherals using the bandgap. If a peripheral requests\r
+//! static mode, then the bandgap mode will be static for all modules, whereas\r
+//! if all of the peripherals using the bandgap request sample mode, then that\r
+//! will be the mode returned. Sample mode allows the bandgap to be active only\r
+//! when necessary to save on power consumption, static mode requires the\r
+//! bandgap to be active until no peripherals are using it anymore.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b Ref_A_STATICMODE if the bandgap is operating in static mode\r
+//! - \b Ref_A_SAMPLEMODE if the bandgap is operating in sample mode\r
+//! \n indicating the bandgap mode of the module\r
+//\r
+//*****************************************************************************\r
+extern uint16_t Ref_A_getBandgapMode(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the active status of the bandgap in the Ref_A module.\r
+//!\r
+//! This function is used to return the active status of the bandgap in the\r
+//! Ref_A module. If the bandgap is in use by a peripheral, then the status\r
+//! will be seen as active.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b Ref_A_ACTIVE if active\r
+//! - \b Ref_A_INACTIVE if not active\r
+//! \n indicating the bandgap active status of the module\r
+//\r
+//*****************************************************************************\r
+extern bool Ref_A_isBandgapActive(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the busy status of the reference generator in the Ref_A\r
+//! module.\r
+//!\r
+//! This function is used to return the busy status of the reference generator\r
+//! in the Ref_A module. If the ref generator is in use by a peripheral, then\r
+//! the status will be seen as busy.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b Ref_A_NOTBUSY if the reference generator is not being used\r
+//! - \b Ref_A_BUSY if the reference generator is being used,\r
+//! disallowing changes to be made to the Ref_A module controls\r
+//! \n indicating the reference generator busy status of the module\r
+//\r
+//*****************************************************************************\r
+extern uint16_t Ref_A_isRefGenBusy(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the active status of the reference generator in the Ref_A\r
+//! module.\r
+//!\r
+//! This function is used to return the active status of the reference\r
+//! generator in the Ref_A module. If the ref generator is on and ready to use,\r
+//! then the status will be seen as active.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b Ref_A_ACTIVE if active\r
+//! - \b Ref_A_INACTIVE if not active\r
+//! \n indicating the reference generator active status of the module\r
+//\r
+//*****************************************************************************\r
+extern bool Ref_A_isRefGenActive(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the busy status of the reference generator in the Ref_A\r
+//! module.\r
+//!\r
+//! This function is used to return the buys status of the buffered bandgap\r
+//! voltage in the Ref_A module. If the ref generator is on and ready to use,\r
+//! then the status will be seen as active.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b Ref_A_NOTREADY if NOT ready to be used\r
+//! - \b Ref_A_READY if ready to be used\r
+//! \n indicating the the busy status of the reference generator in the\r
+//! module\r
+//\r
+//*****************************************************************************\r
+extern bool Ref_A_isBufferedBandgapVoltageReady(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the busy status of the variable reference voltage in the\r
+//! Ref_A module.\r
+//!\r
+//! This function is used to return the busy status of the variable reference\r
+//! voltage in the Ref_A module. If the ref generator is on and ready to use,\r
+//! then the status will be seen as active.\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b Ref_A_NOTREADY if NOT ready to be used\r
+//! - \b Ref_A_READY if ready to be used\r
+//! \n indicating the the busy status of the variable reference voltage\r
+//! in the module\r
+//\r
+//*****************************************************************************\r
+extern bool Ref_A_isVariableReferenceVoltageOutputReady(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the one-time trigger of the reference voltage.\r
+//!\r
+//! Triggers the one-time generation of the variable reference voltage. Once\r
+//! the reference voltage request is set, this bit is cleared by hardware\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! Modified bits are \b REFGENOT of \b REFCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Ref_A_setReferenceVoltageOneTimeTrigger(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the one-time trigger of the buffered bandgap voltage.\r
+//!\r
+//! Triggers the one-time generation of the buffered bandgap voltage. Once the\r
+//! buffered bandgap voltage request is set, this bit is cleared by hardware\r
+//!\r
+//! \param baseAddress is the base address of the REF_A module.\r
+//!\r
+//! Modified bits are \b REFBGOT of \b REFCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Ref_A_setBufferedBandgapVoltageOneTimeTrigger(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_REF_A_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// rtc_b.c - Driver for the rtc_b Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup rtc_b_api rtc_b\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_RTC_B__\r
+#include "rtc_b.h"\r
+\r
+#include <assert.h>\r
+\r
+void RTC_B_startClock(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL01_H) &= ~(RTCHOLD_H);\r
+}\r
+\r
+void RTC_B_holdClock(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCHOLD_H;\r
+}\r
+\r
+void RTC_B_setCalibrationFrequency(uint16_t baseAddress,\r
+ uint16_t frequencySelect)\r
+{\r
+ HWREG16(baseAddress + OFS_RTCCTL23) &= ~(RTCCALF_3);\r
+ HWREG16(baseAddress + OFS_RTCCTL23) |= frequencySelect;\r
+}\r
+\r
+void RTC_B_setCalibrationData(uint16_t baseAddress,\r
+ uint8_t offsetDirection,\r
+ uint8_t offsetValue)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL23_L) = offsetValue + offsetDirection;\r
+}\r
+\r
+void RTC_B_initCalendar(uint16_t baseAddress,\r
+ Calendar *CalendarTime,\r
+ uint16_t formatSelect)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCHOLD_H;\r
+\r
+ HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCBCD);\r
+ HWREG16(baseAddress + OFS_RTCCTL01) |= formatSelect;\r
+\r
+ HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime->Seconds;\r
+ HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime->Minutes;\r
+ HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime->Hours;\r
+ HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime->DayOfWeek;\r
+ HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime->DayOfMonth;\r
+ HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime->Month;\r
+ HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime->Year;\r
+}\r
+\r
+Calendar RTC_B_getCalendarTime(uint16_t baseAddress)\r
+{\r
+ Calendar tempCal;\r
+\r
+ while(!(HWREG16(baseAddress + OFS_RTCCTL01) & RTCRDY))\r
+ {\r
+ ;\r
+ }\r
+\r
+ tempCal.Seconds = HWREG8(baseAddress + OFS_RTCTIM0_L);\r
+ tempCal.Minutes = HWREG8(baseAddress + OFS_RTCTIM0_H);\r
+ tempCal.Hours = HWREG8(baseAddress + OFS_RTCTIM1_L);\r
+ tempCal.DayOfWeek = HWREG8(baseAddress + OFS_RTCTIM1_H);\r
+ tempCal.DayOfMonth = HWREG8(baseAddress + OFS_RTCDATE_L);\r
+ tempCal.Month = HWREG8(baseAddress + OFS_RTCDATE_H);\r
+ tempCal.Year = HWREG16(baseAddress + OFS_RTCYEAR);\r
+\r
+ return (tempCal);\r
+}\r
+\r
+void RTC_B_configureCalendarAlarm(uint16_t baseAddress,\r
+ RTC_B_configureCalendarAlarmParam *param)\r
+{\r
+ //Each of these is XORed with 0x80 to turn on if an integer is passed,\r
+ //or turn OFF if RTC_B_ALARM_OFF (0x80) is passed.\r
+ HWREG8(baseAddress + OFS_RTCAMINHR_L) = (param->minutesAlarm ^ 0x80);\r
+ HWREG8(baseAddress + OFS_RTCAMINHR_H) = (param->hoursAlarm ^ 0x80);\r
+ HWREG8(baseAddress + OFS_RTCADOWDAY_L) = (param->dayOfWeekAlarm ^ 0x80);\r
+ HWREG8(baseAddress + OFS_RTCADOWDAY_H) = (param->dayOfMonthAlarm ^ 0x80);\r
+}\r
+\r
+void RTC_B_setCalendarEvent(uint16_t baseAddress,\r
+ uint16_t eventSelect)\r
+{\r
+ HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCTEV_3); //Reset bits\r
+ HWREG16(baseAddress + OFS_RTCCTL01) |= eventSelect;\r
+}\r
+\r
+void RTC_B_definePrescaleEvent(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint8_t prescaleEventDivider)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL_L + prescaleSelect) &= ~(RT0IP_7);\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL_L +\r
+ prescaleSelect) |= prescaleEventDivider;\r
+}\r
+\r
+uint8_t RTC_B_getPrescaleValue(uint16_t baseAddress,\r
+ uint8_t prescaleSelect)\r
+{\r
+ if(RTC_B_PRESCALE_0 == prescaleSelect)\r
+ {\r
+ return (HWREG8(baseAddress + OFS_RTCPS_L));\r
+ }\r
+ else if(RTC_B_PRESCALE_1 == prescaleSelect)\r
+ {\r
+ return (HWREG8(baseAddress + OFS_RTCPS_H));\r
+ }\r
+ else\r
+ {\r
+ return (0);\r
+ }\r
+}\r
+\r
+void RTC_B_setPrescaleValue(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint8_t prescaleCounterValue)\r
+{\r
+ if(RTC_B_PRESCALE_0 == prescaleSelect)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS_L) = prescaleCounterValue;\r
+ }\r
+ else if(RTC_B_PRESCALE_1 == prescaleSelect)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS_H) = prescaleCounterValue;\r
+ }\r
+}\r
+\r
+void RTC_B_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptMask)\r
+{\r
+ if(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCCTL01_L) |=\r
+ (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE));\r
+ }\r
+\r
+ if(interruptMask & RTC_B_PRESCALE_TIMER0_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL) |= RT0PSIE;\r
+ }\r
+\r
+ if(interruptMask & RTC_B_PRESCALE_TIMER1_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS1CTL) |= RT1PSIE;\r
+ }\r
+}\r
+\r
+void RTC_B_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptMask)\r
+{\r
+ if(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCCTL01_L) &=\r
+ ~(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE));\r
+ }\r
+\r
+ if(interruptMask & RTC_B_PRESCALE_TIMER0_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL) &= ~(RT0PSIE);\r
+ }\r
+\r
+ if(interruptMask & RTC_B_PRESCALE_TIMER1_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS1CTL) &= ~(RT1PSIE);\r
+ }\r
+}\r
+\r
+uint8_t RTC_B_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t interruptFlagMask)\r
+{\r
+ uint8_t tempInterruptFlagMask = 0x0000;\r
+\r
+ tempInterruptFlagMask |= (HWREG8(baseAddress + OFS_RTCCTL01_L)\r
+ & ((interruptFlagMask >> 4)\r
+ & (RTCOFIFG +\r
+ RTCTEVIFG +\r
+ RTCAIFG +\r
+ RTCRDYIFG)));\r
+\r
+ tempInterruptFlagMask = tempInterruptFlagMask << 4;\r
+\r
+ if(interruptFlagMask & RTC_B_PRESCALE_TIMER0_INTERRUPT)\r
+ {\r
+ if(HWREG8(baseAddress + OFS_RTCPS0CTL) & RT0PSIFG)\r
+ {\r
+ tempInterruptFlagMask |= RTC_B_PRESCALE_TIMER0_INTERRUPT;\r
+ }\r
+ }\r
+\r
+ if(interruptFlagMask & RTC_B_PRESCALE_TIMER1_INTERRUPT)\r
+ {\r
+ if(HWREG8(baseAddress + OFS_RTCPS1CTL) & RT1PSIFG)\r
+ {\r
+ tempInterruptFlagMask |= RTC_B_PRESCALE_TIMER1_INTERRUPT;\r
+ }\r
+ }\r
+\r
+ return (tempInterruptFlagMask);\r
+}\r
+\r
+void RTC_B_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptFlagMask)\r
+{\r
+ if(interruptFlagMask & (RTC_B_TIME_EVENT_INTERRUPT +\r
+ RTC_B_CLOCK_ALARM_INTERRUPT +\r
+ RTC_B_CLOCK_READ_READY_INTERRUPT +\r
+ RTC_B_OSCILLATOR_FAULT_INTERRUPT))\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCCTL01_L) &=\r
+ ~((interruptFlagMask >> 4) & (RTCOFIFG +\r
+ RTCTEVIFG +\r
+ RTCAIFG +\r
+ RTCRDYIFG));\r
+ }\r
+\r
+ if(interruptFlagMask & RTC_B_PRESCALE_TIMER0_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL) &= ~(RT0PSIFG);\r
+ }\r
+\r
+ if(interruptFlagMask & RTC_B_PRESCALE_TIMER1_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS1CTL) &= ~(RT1PSIFG);\r
+ }\r
+}\r
+\r
+uint16_t RTC_B_convertBCDToBinary(uint16_t baseAddress,\r
+ uint16_t valueToConvert)\r
+{\r
+ HWREG16(baseAddress + OFS_BCD2BIN) = valueToConvert;\r
+ return (HWREG16(baseAddress + OFS_BCD2BIN));\r
+}\r
+\r
+uint16_t RTC_B_convertBinaryToBCD(uint16_t baseAddress,\r
+ uint16_t valueToConvert)\r
+{\r
+ HWREG16(baseAddress + OFS_BIN2BCD) = valueToConvert;\r
+ return (HWREG16(baseAddress + OFS_BIN2BCD));\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for rtc_b_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// rtc_b.h - Driver for the RTC_B Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_RTC_B_H__\r
+#define __MSP430WARE_RTC_B_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_RTC_B__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the RTC_B_initCalendar() function as the CalendarTime\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Calendar\r
+{\r
+ //! Seconds of minute between 0-59\r
+ uint8_t Seconds;\r
+ //! Minutes of hour between 0-59\r
+ uint8_t Minutes;\r
+ //! Hour of day between 0-23\r
+ uint8_t Hours;\r
+ //! Day of week between 0-6\r
+ uint8_t DayOfWeek;\r
+ //! Day of month between 1-31\r
+ uint8_t DayOfMonth;\r
+ //! Month between 0-11\r
+ uint8_t Month;\r
+ //! Year between 0-4095\r
+ uint16_t Year;\r
+} Calendar;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the RTC_B_configureCalendarAlarm() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct RTC_B_configureCalendarAlarmParam\r
+{\r
+ //! Is the alarm condition for the minutes.\r
+ //! \n Valid values are:\r
+ //! - \b RTC_B_ALARMCONDITION_OFF [Default]\r
+ uint8_t minutesAlarm;\r
+ //! Is the alarm condition for the hours.\r
+ //! \n Valid values are:\r
+ //! - \b RTC_B_ALARMCONDITION_OFF [Default]\r
+ uint8_t hoursAlarm;\r
+ //! Is the alarm condition for the day of week.\r
+ //! \n Valid values are:\r
+ //! - \b RTC_B_ALARMCONDITION_OFF [Default]\r
+ uint8_t dayOfWeekAlarm;\r
+ //! Is the alarm condition for the day of the month.\r
+ //! \n Valid values are:\r
+ //! - \b RTC_B_ALARMCONDITION_OFF [Default]\r
+ uint8_t dayOfMonthAlarm;\r
+} RTC_B_configureCalendarAlarmParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the frequencySelect parameter\r
+// for functions: RTC_B_setCalibrationFrequency().\r
+//\r
+//*****************************************************************************\r
+#define RTC_B_CALIBRATIONFREQ_OFF (RTCCALF_0)\r
+#define RTC_B_CALIBRATIONFREQ_512HZ (RTCCALF_1)\r
+#define RTC_B_CALIBRATIONFREQ_256HZ (RTCCALF_2)\r
+#define RTC_B_CALIBRATIONFREQ_1HZ (RTCCALF_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the offsetDirection parameter\r
+// for functions: RTC_B_setCalibrationData().\r
+//\r
+//*****************************************************************************\r
+#define RTC_B_CALIBRATION_DOWN2PPM (!(RTCCALS))\r
+#define RTC_B_CALIBRATION_UP4PPM (RTCCALS)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the formatSelect parameter\r
+// for functions: RTC_B_initCalendar().\r
+//\r
+//*****************************************************************************\r
+#define RTC_B_FORMAT_BINARY (!(RTCBCD))\r
+#define RTC_B_FORMAT_BCD (RTCBCD)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: RTC_B_configureCalendarAlarm(), RTC_B_configureCalendarAlarm(),\r
+// RTC_B_configureCalendarAlarm(), and RTC_B_configureCalendarAlarm().\r
+//\r
+//*****************************************************************************\r
+#define RTC_B_ALARMCONDITION_OFF (0x80)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the eventSelect parameter for\r
+// functions: RTC_B_setCalendarEvent().\r
+//\r
+//*****************************************************************************\r
+#define RTC_B_CALENDAREVENT_MINUTECHANGE (RTCTEV_0)\r
+#define RTC_B_CALENDAREVENT_HOURCHANGE (RTCTEV_1)\r
+#define RTC_B_CALENDAREVENT_NOON (RTCTEV_2)\r
+#define RTC_B_CALENDAREVENT_MIDNIGHT (RTCTEV_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the prescaleEventDivider\r
+// parameter for functions: RTC_B_definePrescaleEvent().\r
+//\r
+//*****************************************************************************\r
+#define RTC_B_PSEVENTDIVIDER_2 (RT0IP_0)\r
+#define RTC_B_PSEVENTDIVIDER_4 (RT0IP_1)\r
+#define RTC_B_PSEVENTDIVIDER_8 (RT0IP_2)\r
+#define RTC_B_PSEVENTDIVIDER_16 (RT0IP_3)\r
+#define RTC_B_PSEVENTDIVIDER_32 (RT0IP_4)\r
+#define RTC_B_PSEVENTDIVIDER_64 (RT0IP_5)\r
+#define RTC_B_PSEVENTDIVIDER_128 (RT0IP_6)\r
+#define RTC_B_PSEVENTDIVIDER_256 (RT0IP_7)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the prescaleSelect parameter\r
+// for functions: RTC_B_definePrescaleEvent(), RTC_B_getPrescaleValue(), and\r
+// RTC_B_setPrescaleValue().\r
+//\r
+//*****************************************************************************\r
+#define RTC_B_PRESCALE_0 (0x0)\r
+#define RTC_B_PRESCALE_1 (0x2)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptMask parameter\r
+// for functions: RTC_B_enableInterrupt(), and RTC_B_disableInterrupt(); the\r
+// interruptFlagMask parameter for functions: RTC_B_getInterruptStatus(), and\r
+// RTC_B_clearInterrupt() as well as returned by the RTC_B_getInterruptStatus()\r
+// function.\r
+//\r
+//*****************************************************************************\r
+#define RTC_B_TIME_EVENT_INTERRUPT RTCTEVIE\r
+#define RTC_B_CLOCK_ALARM_INTERRUPT RTCAIE\r
+#define RTC_B_CLOCK_READ_READY_INTERRUPT RTCRDYIE\r
+#define RTC_B_PRESCALE_TIMER0_INTERRUPT 0x02\r
+#define RTC_B_PRESCALE_TIMER1_INTERRUPT 0x01\r
+#define RTC_B_OSCILLATOR_FAULT_INTERRUPT RTCOFIE\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts the RTC.\r
+//!\r
+//! This function clears the RTC main hold bit to allow the RTC to function.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_startClock(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Holds the RTC.\r
+//!\r
+//! This function sets the RTC main hold bit to disable RTC functionality.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_holdClock(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Allows and Sets the frequency output to RTCCLK pin for calibration\r
+//! measurement.\r
+//!\r
+//! This function sets a frequency to measure at the RTCCLK output pin. After\r
+//! testing the set frequency, the calibration could be set accordingly.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param frequencySelect is the frequency output to RTCCLK.\r
+//! Valid values are:\r
+//! - \b RTC_B_CALIBRATIONFREQ_OFF [Default] - turn off calibration\r
+//! output\r
+//! - \b RTC_B_CALIBRATIONFREQ_512HZ - output signal at 512Hz for\r
+//! calibration\r
+//! - \b RTC_B_CALIBRATIONFREQ_256HZ - output signal at 256Hz for\r
+//! calibration\r
+//! - \b RTC_B_CALIBRATIONFREQ_1HZ - output signal at 1Hz for\r
+//! calibration\r
+//! \n Modified bits are \b RTCCALF of \b RTCCTL3 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_setCalibrationFrequency(uint16_t baseAddress,\r
+ uint16_t frequencySelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the specified calibration for the RTC.\r
+//!\r
+//! This function sets the calibration offset to make the RTC as accurate as\r
+//! possible. The offsetDirection can be either +4-ppm or -2-ppm, and the\r
+//! offsetValue should be from 1-63 and is multiplied by the direction setting\r
+//! (i.e. +4-ppm * 8 (offsetValue) = +32-ppm). Please note, when measuring the\r
+//! frequency after setting the calibration, you will only see a change on the\r
+//! 1Hz frequency.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param offsetDirection is the direction that the calibration offset will\r
+//! go.\r
+//! Valid values are:\r
+//! - \b RTC_B_CALIBRATION_DOWN2PPM - calibrate at steps of -2\r
+//! - \b RTC_B_CALIBRATION_UP4PPM - calibrate at steps of +4\r
+//! \n Modified bits are \b RTCCALS of \b RTCCTL2 register.\r
+//! \param offsetValue is the value that the offset will be a factor of; a\r
+//! valid value is any integer from 1-63.\r
+//! \n Modified bits are \b RTCCAL of \b RTCCTL2 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_setCalibrationData(uint16_t baseAddress,\r
+ uint8_t offsetDirection,\r
+ uint8_t offsetValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the settings to operate the RTC in calendar mode\r
+//!\r
+//! This function initializes the Calendar mode of the RTC module. To prevent\r
+//! potential erroneous alarm conditions from occurring, the alarm should be\r
+//! disabled by clearing the RTCAIE, RTCAIFG and AE bits with APIs:\r
+//! RTC_B_disableInterrupt(), RTC_B_clearInterrupt() and\r
+//! RTC_B_configureCalendarAlarm() before calendar initialization.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param CalendarTime is the pointer to the structure containing the values\r
+//! for the Calendar to be initialized to. Valid values should be of\r
+//! type pointer to Calendar and should contain the following members\r
+//! and corresponding values: \b Seconds between 0-59 \b Minutes between\r
+//! 0-59 \b Hours between 0-23 \b DayOfWeek between 0-6 \b DayOfMonth\r
+//! between 1-31 \b Year between 0-4095 NOTE: Values beyond the ones\r
+//! specified may result in erratic behavior.\r
+//! \param formatSelect is the format for the Calendar registers to use.\r
+//! Valid values are:\r
+//! - \b RTC_B_FORMAT_BINARY [Default]\r
+//! - \b RTC_B_FORMAT_BCD\r
+//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_initCalendar(uint16_t baseAddress,\r
+ Calendar *CalendarTime,\r
+ uint16_t formatSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the Calendar Time stored in the Calendar registers of the\r
+//! RTC.\r
+//!\r
+//! This function returns the current Calendar time in the form of a Calendar\r
+//! structure. The RTCRDY polling is used in this function to prevent reading\r
+//! invalid time.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//!\r
+//! \return A Calendar structure containing the current time.\r
+//\r
+//*****************************************************************************\r
+extern Calendar RTC_B_getCalendarTime(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets and Enables the desired Calendar Alarm settings.\r
+//!\r
+//! This function sets a Calendar interrupt condition to assert the RTCAIFG\r
+//! interrupt flag. The condition is a logical and of all of the parameters.\r
+//! For example if the minutes and hours alarm is set, then the interrupt will\r
+//! only assert when the minutes AND the hours change to the specified setting.\r
+//! Use the RTC_B_ALARM_OFF for any alarm settings that should not be apart of\r
+//! the alarm condition.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param param is the pointer to struct for calendar alarm configuration.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_configureCalendarAlarm(uint16_t baseAddress,\r
+ RTC_B_configureCalendarAlarmParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets a single specified Calendar interrupt condition\r
+//!\r
+//! This function sets a specified event to assert the RTCTEVIFG interrupt.\r
+//! This interrupt is independent from the Calendar alarm interrupt.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param eventSelect is the condition selected.\r
+//! Valid values are:\r
+//! - \b RTC_B_CALENDAREVENT_MINUTECHANGE - assert interrupt on every\r
+//! minute\r
+//! - \b RTC_B_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour\r
+//! - \b RTC_B_CALENDAREVENT_NOON - assert interrupt when hour is 12\r
+//! - \b RTC_B_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0\r
+//! \n Modified bits are \b RTCTEV of \b RTCCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_setCalendarEvent(uint16_t baseAddress,\r
+ uint16_t eventSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets up an interrupt condition for the selected Prescaler.\r
+//!\r
+//! This function sets the condition for an interrupt to assert based on the\r
+//! individual prescalers.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param prescaleSelect is the prescaler to define an interrupt for.\r
+//! Valid values are:\r
+//! - \b RTC_B_PRESCALE_0\r
+//! - \b RTC_B_PRESCALE_1\r
+//! \param prescaleEventDivider is a divider to specify when an interrupt can\r
+//! occur based on the clock source of the selected prescaler. (Does not\r
+//! affect timer of the selected prescaler).\r
+//! Valid values are:\r
+//! - \b RTC_B_PSEVENTDIVIDER_2 [Default]\r
+//! - \b RTC_B_PSEVENTDIVIDER_4\r
+//! - \b RTC_B_PSEVENTDIVIDER_8\r
+//! - \b RTC_B_PSEVENTDIVIDER_16\r
+//! - \b RTC_B_PSEVENTDIVIDER_32\r
+//! - \b RTC_B_PSEVENTDIVIDER_64\r
+//! - \b RTC_B_PSEVENTDIVIDER_128\r
+//! - \b RTC_B_PSEVENTDIVIDER_256\r
+//! \n Modified bits are \b RTxIP of \b RTCPSxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_definePrescaleEvent(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint8_t prescaleEventDivider);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the selected prescaler value.\r
+//!\r
+//! This function returns the value of the selected prescale counter register.\r
+//! Note that the counter value should be held by calling RTC_B_holdClock()\r
+//! before calling this API.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param prescaleSelect is the prescaler to obtain the value of.\r
+//! Valid values are:\r
+//! - \b RTC_B_PRESCALE_0\r
+//! - \b RTC_B_PRESCALE_1\r
+//!\r
+//! \return The value of the specified prescaler count register\r
+//\r
+//*****************************************************************************\r
+extern uint8_t RTC_B_getPrescaleValue(uint16_t baseAddress,\r
+ uint8_t prescaleSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the selected prescaler value.\r
+//!\r
+//! This function sets the prescale counter value. Before setting the prescale\r
+//! counter, it should be held by calling RTC_B_holdClock().\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param prescaleSelect is the prescaler to set the value for.\r
+//! Valid values are:\r
+//! - \b RTC_B_PRESCALE_0\r
+//! - \b RTC_B_PRESCALE_1\r
+//! \param prescaleCounterValue is the specified value to set the prescaler to.\r
+//! Valid values are any integer between 0-255\r
+//! \n Modified bits are \b RTxPS of \b RTxPS register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_setPrescaleValue(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint8_t prescaleCounterValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables selected RTC interrupt sources.\r
+//!\r
+//! This function enables the selected RTC interrupt source. Only the sources\r
+//! that are enabled can be reflected to the processor interrupt; disabled\r
+//! sources have no effect on the processor. Does not clear interrupt flags.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param interruptMask is a bit mask of the interrupts to enable.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0\r
+//! event condition is met.\r
+//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1\r
+//! event condition is met.\r
+//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a\r
+//! problem with the 32kHz oscillator, while the RTC is running.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables selected RTC interrupt sources.\r
+//!\r
+//! This function disables the selected RTC interrupt source. Only the sources\r
+//! that are enabled can be reflected to the processor interrupt; disabled\r
+//! sources have no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param interruptMask is a bit mask of the interrupts to disable.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0\r
+//! event condition is met.\r
+//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1\r
+//! event condition is met.\r
+//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a\r
+//! problem with the 32kHz oscillator, while the RTC is running.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the status of the selected interrupts flags.\r
+//!\r
+//! This function returns the status of the interrupt flag for the selected\r
+//! channel.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param interruptFlagMask is a bit mask of the interrupt flags to return the\r
+//! status of.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0\r
+//! event condition is met.\r
+//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1\r
+//! event condition is met.\r
+//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a\r
+//! problem with the 32kHz oscillator, while the RTC is running.\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b RTC_B_TIME_EVENT_INTERRUPT asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_B_CLOCK_ALARM_INTERRUPT asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT asserts when Prescaler 0 event\r
+//! condition is met.\r
+//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT asserts when Prescaler 1 event\r
+//! condition is met.\r
+//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT asserts if there is a problem\r
+//! with the 32kHz oscillator, while the RTC is running.\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint8_t RTC_B_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t interruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears selected RTC interrupt flags.\r
+//!\r
+//! This function clears the RTC interrupt flag is cleared, so that it no\r
+//! longer asserts.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param interruptFlagMask is a bit mask of the interrupt flags to be\r
+//! cleared.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0\r
+//! event condition is met.\r
+//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1\r
+//! event condition is met.\r
+//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a\r
+//! problem with the 32kHz oscillator, while the RTC is running.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_B_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Convert the given BCD value to binary format\r
+//!\r
+//! This function converts BCD values to binary format. This API uses the\r
+//! hardware registers to perform the conversion rather than a software method.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param valueToConvert is the raw value in BCD format to convert to Binary.\r
+//! \n Modified bits are \b BCD2BIN of \b BCD2BIN register.\r
+//!\r
+//! \return The binary version of the input parameter\r
+//\r
+//*****************************************************************************\r
+extern uint16_t RTC_B_convertBCDToBinary(uint16_t baseAddress,\r
+ uint16_t valueToConvert);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Convert the given binary value to BCD format\r
+//!\r
+//! This function converts binary values to BCD format. This API uses the\r
+//! hardware registers to perform the conversion rather than a software method.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_B module.\r
+//! \param valueToConvert is the raw value in Binary format to convert to BCD.\r
+//! \n Modified bits are \b BIN2BCD of \b BIN2BCD register.\r
+//!\r
+//! \return The BCD version of the valueToConvert parameter\r
+//\r
+//*****************************************************************************\r
+extern uint16_t RTC_B_convertBinaryToBCD(uint16_t baseAddress,\r
+ uint16_t valueToConvert);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_RTC_B_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// rtc_c.c - Driver for the rtc_c Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup rtc_c_api rtc_c\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_RTC_C__\r
+#include "rtc_c.h"\r
+\r
+#include <assert.h>\r
+\r
+void RTC_C_startClock(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+ HWREG8(baseAddress + OFS_RTCCTL13_L) &= ~(RTCHOLD);\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+}\r
+\r
+void RTC_C_holdClock(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+ HWREG8(baseAddress + OFS_RTCCTL13_L) |= RTCHOLD;\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+}\r
+\r
+void RTC_C_setCalibrationFrequency(uint16_t baseAddress,\r
+ uint16_t frequencySelect)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+ HWREG16(baseAddress + OFS_RTCCTL13) &= ~(RTCCALF_3);\r
+ HWREG16(baseAddress + OFS_RTCCTL13) |= frequencySelect;\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+}\r
+\r
+void RTC_C_setCalibrationData(uint16_t baseAddress,\r
+ uint8_t offsetDirection,\r
+ uint8_t offsetValue)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+ HWREG16(baseAddress + OFS_RTCOCAL) = offsetValue + offsetDirection;\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+}\r
+\r
+void RTC_C_initCounter(uint16_t baseAddress,\r
+ uint16_t clockSelect,\r
+ uint16_t counterSizeSelect)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL13) |= RTCHOLD;\r
+ HWREG8(baseAddress + OFS_RTCCTL13) &= ~(RTCMODE);\r
+\r
+ HWREG16(baseAddress + OFS_RTCCTL13) &= ~(RTCSSEL_3 | RTCTEV_3);\r
+ HWREG16(baseAddress + OFS_RTCCTL13) |= clockSelect + counterSizeSelect;\r
+}\r
+\r
+bool RTC_C_setTemperatureCompensation(uint16_t baseAddress,\r
+ uint16_t offsetDirection,\r
+ uint8_t offsetValue)\r
+{\r
+ while(!(HWREG8(baseAddress + OFS_RTCTCMP_H) & RTCTCRDY_H))\r
+ {\r
+ ;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_RTCTCMP) = offsetValue + offsetDirection;\r
+\r
+ if(HWREG8(baseAddress + OFS_RTCTCMP_H) & RTCTCOK_H)\r
+ {\r
+ return(STATUS_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ return(STATUS_FAIL);\r
+ }\r
+}\r
+\r
+void RTC_C_initCalendar(uint16_t baseAddress,\r
+ Calendar *CalendarTime,\r
+ uint16_t formatSelect)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+\r
+ HWREG8(baseAddress + OFS_RTCCTL13_L) |= RTCHOLD;\r
+\r
+ HWREG16(baseAddress + OFS_RTCCTL13_L) &= ~(RTCBCD);\r
+ HWREG16(baseAddress + OFS_RTCCTL13_L) |= formatSelect;\r
+\r
+ HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime->Seconds;\r
+ HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime->Minutes;\r
+ HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime->Hours;\r
+ HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime->DayOfWeek;\r
+ HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime->DayOfMonth;\r
+ HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime->Month;\r
+ HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime->Year;\r
+\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+}\r
+\r
+Calendar RTC_C_getCalendarTime(uint16_t baseAddress)\r
+{\r
+ Calendar tempCal;\r
+\r
+ while(!(HWREG8(baseAddress + OFS_RTCCTL13_L) & RTCRDY))\r
+ {\r
+ ;\r
+ }\r
+\r
+ tempCal.Seconds = HWREG8(baseAddress + OFS_RTCTIM0_L);\r
+ tempCal.Minutes = HWREG8(baseAddress + OFS_RTCTIM0_H);\r
+ tempCal.Hours = HWREG8(baseAddress + OFS_RTCTIM1_L);\r
+ tempCal.DayOfWeek = HWREG8(baseAddress + OFS_RTCTIM1_H);\r
+ tempCal.DayOfMonth = HWREG8(baseAddress + OFS_RTCDATE_L);\r
+ tempCal.Month = HWREG8(baseAddress + OFS_RTCDATE_H);\r
+ tempCal.Year = HWREG16(baseAddress + OFS_RTCYEAR);\r
+\r
+ return (tempCal);\r
+}\r
+\r
+void RTC_C_configureCalendarAlarm(uint16_t baseAddress,\r
+ RTC_C_configureCalendarAlarmParam *param)\r
+{\r
+ //Each of these is XORed with 0x80 to turn on if an integer is passed,\r
+ //or turn OFF if RTC_C_ALARM_OFF (0x80) is passed.\r
+ HWREG8(baseAddress + OFS_RTCAMINHR_L) = (param->minutesAlarm ^ 0x80);\r
+ HWREG8(baseAddress + OFS_RTCAMINHR_H) = (param->hoursAlarm ^ 0x80);\r
+ HWREG8(baseAddress + OFS_RTCADOWDAY_L) = (param->dayOfWeekAlarm ^ 0x80);\r
+ HWREG8(baseAddress + OFS_RTCADOWDAY_H) = (param->dayOfMonthAlarm ^ 0x80);\r
+}\r
+\r
+void RTC_C_setCalendarEvent(uint16_t baseAddress,\r
+ uint16_t eventSelect)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+ HWREG8(baseAddress + OFS_RTCCTL13_L) &= ~(RTCTEV_3); //Reset bits\r
+ HWREG8(baseAddress + OFS_RTCCTL13_L) |= eventSelect;\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+}\r
+\r
+uint32_t RTC_C_getCounterValue(uint16_t baseAddress)\r
+{\r
+ if((HWREG8(baseAddress + OFS_RTCCTL13) & RTCHOLD)\r
+ || (HWREG8(baseAddress + OFS_RTCPS1CTL) & RT1PSHOLD))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ uint32_t counterValue_L = HWREG16(baseAddress + OFS_RTCTIM0);\r
+ uint32_t counterValue_H = HWREG16(baseAddress + OFS_RTCTIM1);\r
+ return ((counterValue_H << 16) + counterValue_L);\r
+}\r
+\r
+void RTC_C_setCounterValue(uint16_t baseAddress,\r
+ uint32_t counterValue)\r
+{\r
+ uint16_t mode = HWREG16(baseAddress + OFS_RTCCTL13) & RTCTEV_3;\r
+\r
+ if(mode == RTC_C_COUNTERSIZE_8BIT && counterValue > 0xF)\r
+ {\r
+ counterValue = 0xF;\r
+ }\r
+ else if(mode == RTC_C_COUNTERSIZE_16BIT && counterValue > 0xFF)\r
+ {\r
+ counterValue = 0xFF;\r
+ }\r
+ else if(mode == RTC_C_COUNTERSIZE_24BIT && counterValue > 0xFFFFFF)\r
+ {\r
+ counterValue = 0xFFFFFF;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_RTCTIM0) = counterValue;\r
+ HWREG16(baseAddress + OFS_RTCTIM1) = (counterValue >> 16);\r
+}\r
+\r
+void RTC_C_initCounterPrescale(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint16_t prescaleClockSelect,\r
+ uint16_t prescaleDivider)\r
+{\r
+ //Reset bits and set clock select\r
+ HWREG16(baseAddress + OFS_RTCPS0CTL + prescaleSelect) =\r
+ prescaleClockSelect + prescaleDivider;\r
+}\r
+\r
+void RTC_C_holdCounterPrescale(uint16_t baseAddress,\r
+ uint8_t prescaleSelect)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL_H + prescaleSelect) |= RT0PSHOLD_H;\r
+}\r
+\r
+void RTC_C_startCounterPrescale(uint16_t baseAddress,\r
+ uint8_t prescaleSelect)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL_H + prescaleSelect) &= ~(RT0PSHOLD_H);\r
+}\r
+\r
+void RTC_C_definePrescaleEvent(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint8_t prescaleEventDivider)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL_L + prescaleSelect) &= ~(RT0IP_7);\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL_L +\r
+ prescaleSelect) |= prescaleEventDivider;\r
+}\r
+\r
+uint8_t RTC_C_getPrescaleValue(uint16_t baseAddress,\r
+ uint8_t prescaleSelect)\r
+{\r
+ if(RTC_C_PRESCALE_0 == prescaleSelect)\r
+ {\r
+ return (HWREG8(baseAddress + OFS_RTCPS_L));\r
+ }\r
+ else if(RTC_C_PRESCALE_1 == prescaleSelect)\r
+ {\r
+ return (HWREG8(baseAddress + OFS_RTCPS_H));\r
+ }\r
+ else\r
+ {\r
+ return (0);\r
+ }\r
+}\r
+\r
+void RTC_C_setPrescaleValue(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint8_t prescaleCounterValue)\r
+{\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+ if(RTC_C_PRESCALE_0 == prescaleSelect)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS_L) = prescaleCounterValue;\r
+ }\r
+ else if(RTC_C_PRESCALE_1 == prescaleSelect)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS_H) = prescaleCounterValue;\r
+ }\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+}\r
+\r
+void RTC_C_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptMask)\r
+{\r
+ if(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+ HWREG8(baseAddress + OFS_RTCCTL0_L) |=\r
+ (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE));\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+ }\r
+\r
+ if(interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL_L) |= RT0PSIE;\r
+ }\r
+\r
+ if(interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS1CTL_L) |= RT1PSIE;\r
+ }\r
+}\r
+\r
+void RTC_C_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptMask)\r
+{\r
+ if(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+ HWREG8(baseAddress + OFS_RTCCTL0_L) &=\r
+ ~(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE));\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+ }\r
+\r
+ if(interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL_L) &= ~(RT0PSIE);\r
+ }\r
+\r
+ if(interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS1CTL_L) &= ~(RT1PSIE);\r
+ }\r
+}\r
+\r
+uint8_t RTC_C_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t interruptFlagMask)\r
+{\r
+ uint8_t tempInterruptFlagMask = 0x0000;\r
+\r
+ tempInterruptFlagMask |= (HWREG8(baseAddress + OFS_RTCCTL0_L)\r
+ & ((interruptFlagMask >> 4)\r
+ & (RTCOFIFG +\r
+ RTCTEVIFG +\r
+ RTCAIFG +\r
+ RTCRDYIFG)));\r
+\r
+ tempInterruptFlagMask = tempInterruptFlagMask << 4;\r
+\r
+ if(interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)\r
+ {\r
+ if(HWREG8(baseAddress + OFS_RTCPS0CTL_L) & RT0PSIFG)\r
+ {\r
+ tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT;\r
+ }\r
+ }\r
+\r
+ if(interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)\r
+ {\r
+ if(HWREG8(baseAddress + OFS_RTCPS1CTL_L) & RT1PSIFG)\r
+ {\r
+ tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT;\r
+ }\r
+ }\r
+\r
+ return (tempInterruptFlagMask);\r
+}\r
+\r
+void RTC_C_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptFlagMask)\r
+{\r
+ if(interruptFlagMask & (RTC_C_TIME_EVENT_INTERRUPT +\r
+ RTC_C_CLOCK_ALARM_INTERRUPT +\r
+ RTC_C_CLOCK_READ_READY_INTERRUPT +\r
+ RTC_C_OSCILLATOR_FAULT_INTERRUPT))\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H;\r
+ HWREG8(baseAddress + OFS_RTCCTL0_L) &=\r
+ ~((interruptFlagMask >> 4) & (RTCOFIFG +\r
+ RTCTEVIFG +\r
+ RTCAIFG +\r
+ RTCRDYIFG));\r
+ HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00;\r
+ }\r
+\r
+ if(interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS0CTL_L) &= ~(RT0PSIFG);\r
+ }\r
+\r
+ if(interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)\r
+ {\r
+ HWREG8(baseAddress + OFS_RTCPS1CTL_L) &= ~(RT1PSIFG);\r
+ }\r
+}\r
+\r
+uint16_t RTC_C_convertBCDToBinary(uint16_t baseAddress,\r
+ uint16_t valueToConvert)\r
+{\r
+ HWREG16(baseAddress + OFS_BCD2BIN) = valueToConvert;\r
+ return (HWREG16(baseAddress + OFS_BCD2BIN));\r
+}\r
+\r
+uint16_t RTC_C_convertBinaryToBCD(uint16_t baseAddress,\r
+ uint16_t valueToConvert)\r
+{\r
+ HWREG16(baseAddress + OFS_BIN2BCD) = valueToConvert;\r
+ return (HWREG16(baseAddress + OFS_BIN2BCD));\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for rtc_c_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// rtc_c.h - Driver for the RTC_C Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_RTC_C_H__\r
+#define __MSP430WARE_RTC_C_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_RTC_C__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the RTC_C_initCalendar() function as the CalendarTime\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Calendar\r
+{\r
+ //! Seconds of minute between 0-59\r
+ uint8_t Seconds;\r
+ //! Minutes of hour between 0-59\r
+ uint8_t Minutes;\r
+ //! Hour of day between 0-23\r
+ uint8_t Hours;\r
+ //! Day of week between 0-6\r
+ uint8_t DayOfWeek;\r
+ //! Day of month between 1-31\r
+ uint8_t DayOfMonth;\r
+ //! Month between 0-11\r
+ uint8_t Month;\r
+ //! Year between 0-4095\r
+ uint16_t Year;\r
+} Calendar;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the RTC_C_configureCalendarAlarm() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct RTC_C_configureCalendarAlarmParam\r
+{\r
+ //! Is the alarm condition for the minutes.\r
+ //! \n Valid values are:\r
+ //! - \b RTC_C_ALARMCONDITION_OFF [Default]\r
+ uint8_t minutesAlarm;\r
+ //! Is the alarm condition for the hours.\r
+ //! \n Valid values are:\r
+ //! - \b RTC_C_ALARMCONDITION_OFF [Default]\r
+ uint8_t hoursAlarm;\r
+ //! Is the alarm condition for the day of week.\r
+ //! \n Valid values are:\r
+ //! - \b RTC_C_ALARMCONDITION_OFF [Default]\r
+ uint8_t dayOfWeekAlarm;\r
+ //! Is the alarm condition for the day of the month.\r
+ //! \n Valid values are:\r
+ //! - \b RTC_C_ALARMCONDITION_OFF [Default]\r
+ uint8_t dayOfMonthAlarm;\r
+} RTC_C_configureCalendarAlarmParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the frequencySelect parameter\r
+// for functions: RTC_C_setCalibrationFrequency().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_CALIBRATIONFREQ_OFF (RTCCALF_0)\r
+#define RTC_C_CALIBRATIONFREQ_512HZ (RTCCALF_1)\r
+#define RTC_C_CALIBRATIONFREQ_256HZ (RTCCALF_2)\r
+#define RTC_C_CALIBRATIONFREQ_1HZ (RTCCALF_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the offsetDirection parameter\r
+// for functions: RTC_C_setCalibrationData().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_CALIBRATION_DOWN1PPM (!(RTCCALS))\r
+#define RTC_C_CALIBRATION_UP1PPM (RTCCALS)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the offsetDirection parameter\r
+// for functions: RTC_C_setTemperatureCompensation().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_COMPENSATION_DOWN1PPM (!(RTCTCMPS))\r
+#define RTC_C_COMPENSATION_UP1PPM (RTCTCMPS)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockSelect parameter for\r
+// functions: RTC_C_initCounter().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_CLOCKSELECT_32KHZ_OSC (RTCSSEL_0)\r
+#define RTC_C_CLOCKSELECT_RT1PS (RTCSSEL_2)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the counterSizeSelect\r
+// parameter for functions: RTC_C_initCounter().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_COUNTERSIZE_8BIT (RTCTEV_0)\r
+#define RTC_C_COUNTERSIZE_16BIT (RTCTEV_1)\r
+#define RTC_C_COUNTERSIZE_24BIT (RTCTEV_2)\r
+#define RTC_C_COUNTERSIZE_32BIT (RTCTEV_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the formatSelect parameter\r
+// for functions: RTC_C_initCalendar().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_FORMAT_BINARY (!(RTCBCD))\r
+#define RTC_C_FORMAT_BCD (RTCBCD)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: RTC_C_configureCalendarAlarm(), RTC_C_configureCalendarAlarm(),\r
+// RTC_C_configureCalendarAlarm(), and RTC_C_configureCalendarAlarm().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_ALARMCONDITION_OFF (0x80)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the eventSelect parameter for\r
+// functions: RTC_C_setCalendarEvent().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_CALENDAREVENT_MINUTECHANGE (RTCTEV_0)\r
+#define RTC_C_CALENDAREVENT_HOURCHANGE (RTCTEV_1)\r
+#define RTC_C_CALENDAREVENT_NOON (RTCTEV_2)\r
+#define RTC_C_CALENDAREVENT_MIDNIGHT (RTCTEV_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the prescaleDivider parameter\r
+// for functions: RTC_C_initCounterPrescale().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_PSDIVIDER_2 (RT0PSDIV_0)\r
+#define RTC_C_PSDIVIDER_4 (RT0PSDIV_1)\r
+#define RTC_C_PSDIVIDER_8 (RT0PSDIV_2)\r
+#define RTC_C_PSDIVIDER_16 (RT0PSDIV_3)\r
+#define RTC_C_PSDIVIDER_32 (RT0PSDIV_4)\r
+#define RTC_C_PSDIVIDER_64 (RT0PSDIV_5)\r
+#define RTC_C_PSDIVIDER_128 (RT0PSDIV_6)\r
+#define RTC_C_PSDIVIDER_256 (RT0PSDIV_7)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the prescaleClockSelect\r
+// parameter for functions: RTC_C_initCounterPrescale().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_PSCLOCKSELECT_ACLK (RT1SSEL_0)\r
+#define RTC_C_PSCLOCKSELECT_SMCLK (RT1SSEL_1)\r
+#define RTC_C_PSCLOCKSELECT_RT0PS (RT1SSEL_2)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the prescaleEventDivider\r
+// parameter for functions: RTC_C_definePrescaleEvent().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_PSEVENTDIVIDER_2 (RT0IP_0)\r
+#define RTC_C_PSEVENTDIVIDER_4 (RT0IP_1)\r
+#define RTC_C_PSEVENTDIVIDER_8 (RT0IP_2)\r
+#define RTC_C_PSEVENTDIVIDER_16 (RT0IP_3)\r
+#define RTC_C_PSEVENTDIVIDER_32 (RT0IP_4)\r
+#define RTC_C_PSEVENTDIVIDER_64 (RT0IP_5)\r
+#define RTC_C_PSEVENTDIVIDER_128 (RT0IP_6)\r
+#define RTC_C_PSEVENTDIVIDER_256 (RT0IP_7)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the prescaleSelect parameter\r
+// for functions: RTC_C_initCounterPrescale(), RTC_C_holdCounterPrescale(),\r
+// RTC_C_startCounterPrescale(), RTC_C_definePrescaleEvent(),\r
+// RTC_C_getPrescaleValue(), and RTC_C_setPrescaleValue().\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_PRESCALE_0 (0x0)\r
+#define RTC_C_PRESCALE_1 (0x2)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptMask parameter\r
+// for functions: RTC_C_enableInterrupt(), and RTC_C_disableInterrupt(); the\r
+// interruptFlagMask parameter for functions: RTC_C_getInterruptStatus(), and\r
+// RTC_C_clearInterrupt() as well as returned by the RTC_C_getInterruptStatus()\r
+// function.\r
+//\r
+//*****************************************************************************\r
+#define RTC_C_TIME_EVENT_INTERRUPT RTCTEVIE\r
+#define RTC_C_CLOCK_ALARM_INTERRUPT RTCAIE\r
+#define RTC_C_CLOCK_READ_READY_INTERRUPT RTCRDYIE\r
+#define RTC_C_PRESCALE_TIMER0_INTERRUPT 0x02\r
+#define RTC_C_PRESCALE_TIMER1_INTERRUPT 0x01\r
+#define RTC_C_OSCILLATOR_FAULT_INTERRUPT RTCOFIE\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts the RTC.\r
+//!\r
+//! This function clears the RTC main hold bit to allow the RTC to function.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_startClock(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Holds the RTC.\r
+//!\r
+//! This function sets the RTC main hold bit to disable RTC functionality.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_holdClock(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Allows and Sets the frequency output to RTCCLK pin for calibration\r
+//! measurement.\r
+//!\r
+//! This function sets a frequency to measure at the RTCCLK output pin. After\r
+//! testing the set frequency, the calibration could be set accordingly.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param frequencySelect is the frequency output to RTCCLK.\r
+//! Valid values are:\r
+//! - \b RTC_C_CALIBRATIONFREQ_OFF [Default] - turn off calibration\r
+//! output\r
+//! - \b RTC_C_CALIBRATIONFREQ_512HZ - output signal at 512Hz for\r
+//! calibration\r
+//! - \b RTC_C_CALIBRATIONFREQ_256HZ - output signal at 256Hz for\r
+//! calibration\r
+//! - \b RTC_C_CALIBRATIONFREQ_1HZ - output signal at 1Hz for\r
+//! calibration\r
+//! \n Modified bits are \b RTCCALF of \b RTCCTL3 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_setCalibrationFrequency(uint16_t baseAddress,\r
+ uint16_t frequencySelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the specified calibration for the RTC.\r
+//!\r
+//! This function sets the calibration offset to make the RTC as accurate as\r
+//! possible. The offsetDirection can be either +4-ppm or -2-ppm, and the\r
+//! offsetValue should be from 1-63 and is multiplied by the direction setting\r
+//! (i.e. +4-ppm * 8 (offsetValue) = +32-ppm).\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param offsetDirection is the direction that the calibration offset will\r
+//! go.\r
+//! Valid values are:\r
+//! - \b RTC_C_CALIBRATION_DOWN1PPM - calibrate at steps of -1\r
+//! - \b RTC_C_CALIBRATION_UP1PPM - calibrate at steps of +1\r
+//! \n Modified bits are \b RTC0CALS of \b RTC0CAL register.\r
+//! \param offsetValue is the value that the offset will be a factor of; a\r
+//! valid value is any integer from 1-240.\r
+//! \n Modified bits are \b RTC0CALx of \b RTC0CAL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_setCalibrationData(uint16_t baseAddress,\r
+ uint8_t offsetDirection,\r
+ uint8_t offsetValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the settings to operate the RTC in Counter mode.\r
+//!\r
+//! This function initializes the Counter mode of the RTC_C. Setting the clock\r
+//! source and counter size will allow an interrupt from the RTCTEVIFG once an\r
+//! overflow to the counter register occurs.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param clockSelect is the selected clock for the counter mode to use.\r
+//! Valid values are:\r
+//! - \b RTC_C_CLOCKSELECT_32KHZ_OSC\r
+//! - \b RTC_C_CLOCKSELECT_RT1PS\r
+//! \n Modified bits are \b RTCSSEL of \b RTCCTL1 register.\r
+//! \param counterSizeSelect is the size of the counter.\r
+//! Valid values are:\r
+//! - \b RTC_C_COUNTERSIZE_8BIT [Default]\r
+//! - \b RTC_C_COUNTERSIZE_16BIT\r
+//! - \b RTC_C_COUNTERSIZE_24BIT\r
+//! - \b RTC_C_COUNTERSIZE_32BIT\r
+//! \n Modified bits are \b RTCTEV of \b RTCCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_initCounter(uint16_t baseAddress,\r
+ uint16_t clockSelect,\r
+ uint16_t counterSizeSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the specified temperature compensation for the RTC.\r
+//!\r
+//! This function sets the calibration offset to make the RTC as accurate as\r
+//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the\r
+//! offsetValue should be from 1-240 and is multiplied by the direction setting\r
+//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm).\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param offsetDirection is the direction that the calibration offset wil go\r
+//! Valid values are:\r
+//! - \b RTC_C_COMPENSATION_DOWN1PPM\r
+//! - \b RTC_C_COMPENSATION_UP1PPM\r
+//! \n Modified bits are \b RTCTCMPS of \b RTCTCMP register.\r
+//! \param offsetValue is the value that the offset will be a factor of; a\r
+//! valid value is any integer from 1-240.\r
+//! \n Modified bits are \b RTCTCMPx of \b RTCTCMP register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAILURE of setting the temperature\r
+//! compensation\r
+//\r
+//*****************************************************************************\r
+extern bool RTC_C_setTemperatureCompensation(uint16_t baseAddress,\r
+ uint16_t offsetDirection,\r
+ uint8_t offsetValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the settings to operate the RTC in calendar mode\r
+//!\r
+//! This function initializes the Calendar mode of the RTC module. To prevent\r
+//! potential erroneous alarm conditions from occurring, the alarm should be\r
+//! disabled by clearing the RTCAIE, RTCAIFG and AE bits with APIs:\r
+//! RTC_C_disableInterrupt(), RTC_C_clearInterrupt() and\r
+//! RTC_C_configureCalendarAlarm() before calendar initialization.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param CalendarTime is the pointer to the structure containing the values\r
+//! for the Calendar to be initialized to. Valid values should be of\r
+//! type pointer to Calendar and should contain the following members\r
+//! and corresponding values: \b Seconds between 0-59 \b Minutes between\r
+//! 0-59 \b Hours between 0-23 \b DayOfWeek between 0-6 \b DayOfMonth\r
+//! between 1-31 \b Year between 0-4095 NOTE: Values beyond the ones\r
+//! specified may result in erratic behavior.\r
+//! \param formatSelect is the format for the Calendar registers to use.\r
+//! Valid values are:\r
+//! - \b RTC_C_FORMAT_BINARY [Default]\r
+//! - \b RTC_C_FORMAT_BCD\r
+//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_initCalendar(uint16_t baseAddress,\r
+ Calendar *CalendarTime,\r
+ uint16_t formatSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the Calendar Time stored in the Calendar registers of the\r
+//! RTC.\r
+//!\r
+//! This function returns the current Calendar time in the form of a Calendar\r
+//! structure. The RTCRDY polling is used in this function to prevent reading\r
+//! invalid time.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//!\r
+//! \return A Calendar structure containing the current time.\r
+//\r
+//*****************************************************************************\r
+extern Calendar RTC_C_getCalendarTime(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets and Enables the desired Calendar Alarm settings.\r
+//!\r
+//! This function sets a Calendar interrupt condition to assert the RTCAIFG\r
+//! interrupt flag. The condition is a logical and of all of the parameters.\r
+//! For example if the minutes and hours alarm is set, then the interrupt will\r
+//! only assert when the minutes AND the hours change to the specified setting.\r
+//! Use the RTC_C_ALARM_OFF for any alarm settings that should not be apart of\r
+//! the alarm condition.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param param is the pointer to struct for calendar alarm configuration.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_configureCalendarAlarm(uint16_t baseAddress,\r
+ RTC_C_configureCalendarAlarmParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets a single specified Calendar interrupt condition\r
+//!\r
+//! This function sets a specified event to assert the RTCTEVIFG interrupt.\r
+//! This interrupt is independent from the Calendar alarm interrupt.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param eventSelect is the condition selected.\r
+//! Valid values are:\r
+//! - \b RTC_C_CALENDAREVENT_MINUTECHANGE - assert interrupt on every\r
+//! minute\r
+//! - \b RTC_C_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour\r
+//! - \b RTC_C_CALENDAREVENT_NOON - assert interrupt when hour is 12\r
+//! - \b RTC_C_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0\r
+//! \n Modified bits are \b RTCTEV of \b RTCCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_setCalendarEvent(uint16_t baseAddress,\r
+ uint16_t eventSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the value of the Counter register.\r
+//!\r
+//! This function returns the value of the counter register for the RTC_C\r
+//! module. It will return the 32-bit value no matter the size set during\r
+//! initialization. The RTC should be held before trying to use this function.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//!\r
+//! \return The raw value of the full 32-bit Counter Register.\r
+//\r
+//*****************************************************************************\r
+extern uint32_t RTC_C_getCounterValue(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the value of the Counter register\r
+//!\r
+//! This function sets the counter register of the RTC_C module.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param counterValue is the value to set the Counter register to; a valid\r
+//! value may be any 32-bit integer.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_setCounterValue(uint16_t baseAddress,\r
+ uint32_t counterValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes the Prescaler for Counter mode.\r
+//!\r
+//! This function initializes the selected prescaler for the counter mode in\r
+//! the RTC_C module. If the RTC is initialized in Calendar mode, then these\r
+//! are automatically initialized. The Prescalers can be used to divide a clock\r
+//! source additionally before it gets to the main RTC clock.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param prescaleSelect is the prescaler to initialize.\r
+//! Valid values are:\r
+//! - \b RTC_C_PRESCALE_0\r
+//! - \b RTC_C_PRESCALE_1\r
+//! \param prescaleClockSelect is the clock to drive the selected prescaler.\r
+//! Valid values are:\r
+//! - \b RTC_C_PSCLOCKSELECT_ACLK\r
+//! - \b RTC_C_PSCLOCKSELECT_SMCLK\r
+//! - \b RTC_C_PSCLOCKSELECT_RT0PS - use Prescaler 0 as source to\r
+//! Prescaler 1 (May only be used if prescaleSelect is\r
+//! RTC_C_PRESCALE_1)\r
+//! \n Modified bits are \b RTxSSEL of \b RTCPSxCTL register.\r
+//! \param prescaleDivider is the divider for the selected clock source.\r
+//! Valid values are:\r
+//! - \b RTC_C_PSDIVIDER_2 [Default]\r
+//! - \b RTC_C_PSDIVIDER_4\r
+//! - \b RTC_C_PSDIVIDER_8\r
+//! - \b RTC_C_PSDIVIDER_16\r
+//! - \b RTC_C_PSDIVIDER_32\r
+//! - \b RTC_C_PSDIVIDER_64\r
+//! - \b RTC_C_PSDIVIDER_128\r
+//! - \b RTC_C_PSDIVIDER_256\r
+//! \n Modified bits are \b RTxPSDIV of \b RTCPSxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_initCounterPrescale(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint16_t prescaleClockSelect,\r
+ uint16_t prescaleDivider);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Holds the selected Prescaler.\r
+//!\r
+//! This function holds the prescale counter from continuing. This will only\r
+//! work in counter mode, in Calendar mode, the RTC_C_holdClock() must be used.\r
+//! In counter mode, if using both prescalers in conjunction with the main RTC\r
+//! counter, then stopping RT0PS will stop RT1PS, but stopping RT1PS will not\r
+//! stop RT0PS.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param prescaleSelect is the prescaler to hold.\r
+//! Valid values are:\r
+//! - \b RTC_C_PRESCALE_0\r
+//! - \b RTC_C_PRESCALE_1\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_holdCounterPrescale(uint16_t baseAddress,\r
+ uint8_t prescaleSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts the selected Prescaler.\r
+//!\r
+//! This function starts the selected prescale counter. This function will only\r
+//! work if the RTC is in counter mode.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param prescaleSelect is the prescaler to start.\r
+//! Valid values are:\r
+//! - \b RTC_C_PRESCALE_0\r
+//! - \b RTC_C_PRESCALE_1\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_startCounterPrescale(uint16_t baseAddress,\r
+ uint8_t prescaleSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets up an interrupt condition for the selected Prescaler.\r
+//!\r
+//! This function sets the condition for an interrupt to assert based on the\r
+//! individual prescalers.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param prescaleSelect is the prescaler to define an interrupt for.\r
+//! Valid values are:\r
+//! - \b RTC_C_PRESCALE_0\r
+//! - \b RTC_C_PRESCALE_1\r
+//! \param prescaleEventDivider is a divider to specify when an interrupt can\r
+//! occur based on the clock source of the selected prescaler. (Does not\r
+//! affect timer of the selected prescaler).\r
+//! Valid values are:\r
+//! - \b RTC_C_PSEVENTDIVIDER_2 [Default]\r
+//! - \b RTC_C_PSEVENTDIVIDER_4\r
+//! - \b RTC_C_PSEVENTDIVIDER_8\r
+//! - \b RTC_C_PSEVENTDIVIDER_16\r
+//! - \b RTC_C_PSEVENTDIVIDER_32\r
+//! - \b RTC_C_PSEVENTDIVIDER_64\r
+//! - \b RTC_C_PSEVENTDIVIDER_128\r
+//! - \b RTC_C_PSEVENTDIVIDER_256\r
+//! \n Modified bits are \b RTxIP of \b RTCPSxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_definePrescaleEvent(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint8_t prescaleEventDivider);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the selected prescaler value.\r
+//!\r
+//! This function returns the value of the selected prescale counter register.\r
+//! Note that the counter value should be held by calling RTC_C_holdClock()\r
+//! before calling this API.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param prescaleSelect is the prescaler to obtain the value of.\r
+//! Valid values are:\r
+//! - \b RTC_C_PRESCALE_0\r
+//! - \b RTC_C_PRESCALE_1\r
+//!\r
+//! \return The value of the specified prescaler count register\r
+//\r
+//*****************************************************************************\r
+extern uint8_t RTC_C_getPrescaleValue(uint16_t baseAddress,\r
+ uint8_t prescaleSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the selected Prescaler value.\r
+//!\r
+//! This function sets the prescale counter value. Before setting the prescale\r
+//! counter, it should be held by calling RTC_C_holdClock().\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param prescaleSelect is the prescaler to set the value for.\r
+//! Valid values are:\r
+//! - \b RTC_C_PRESCALE_0\r
+//! - \b RTC_C_PRESCALE_1\r
+//! \param prescaleCounterValue is the specified value to set the prescaler to.\r
+//! Valid values are any integer between 0-255\r
+//! \n Modified bits are \b RTxPS of \b RTxPS register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_setPrescaleValue(uint16_t baseAddress,\r
+ uint8_t prescaleSelect,\r
+ uint8_t prescaleCounterValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables selected RTC interrupt sources.\r
+//!\r
+//! This function enables the selected RTC interrupt source. Only the sources\r
+//! that are enabled can be reflected to the processor interrupt; disabled\r
+//! sources have no effect on the processor. Does not clear interrupt flags.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param interruptMask is a bit mask of the interrupts to enable.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0\r
+//! event condition is met.\r
+//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1\r
+//! event condition is met.\r
+//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a\r
+//! problem with the 32kHz oscillator, while the RTC is running.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables selected RTC interrupt sources.\r
+//!\r
+//! This function disables the selected RTC interrupt source. Only the sources\r
+//! that are enabled can be reflected to the processor interrupt; disabled\r
+//! sources have no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param interruptMask is a bit mask of the interrupts to disable.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0\r
+//! event condition is met.\r
+//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1\r
+//! event condition is met.\r
+//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a\r
+//! problem with the 32kHz oscillator, while the RTC is running.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the status of the selected interrupts flags.\r
+//!\r
+//! This function returns the status of the interrupt flag for the selected\r
+//! channel.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param interruptFlagMask is a bit mask of the interrupt flags to return the\r
+//! status of.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0\r
+//! event condition is met.\r
+//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1\r
+//! event condition is met.\r
+//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a\r
+//! problem with the 32kHz oscillator, while the RTC is running.\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b RTC_C_TIME_EVENT_INTERRUPT asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_C_CLOCK_ALARM_INTERRUPT asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT asserts when Prescaler 0 event\r
+//! condition is met.\r
+//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT asserts when Prescaler 1 event\r
+//! condition is met.\r
+//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT asserts if there is a problem\r
+//! with the 32kHz oscillator, while the RTC is running.\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint8_t RTC_C_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t interruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears selected RTC interrupt flags.\r
+//!\r
+//! This function clears the RTC interrupt flag is cleared, so that it no\r
+//! longer asserts.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param interruptFlagMask is a bit mask of the interrupt flags to be\r
+//! cleared.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in\r
+//! counter mode or when Calendar event condition defined by\r
+//! defineCalendarEvent() is met.\r
+//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in\r
+//! Calendar mode is met.\r
+//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar\r
+//! registers are settled.\r
+//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0\r
+//! event condition is met.\r
+//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1\r
+//! event condition is met.\r
+//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a\r
+//! problem with the 32kHz oscillator, while the RTC is running.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void RTC_C_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t interruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Convert the given BCD value to binary format\r
+//!\r
+//! This function converts BCD values to binary format. This API uses the\r
+//! hardware registers to perform the conversion rather than a software method.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param valueToConvert is the raw value in BCD format to convert to Binary.\r
+//! \n Modified bits are \b BCD2BIN of \b BCD2BIN register.\r
+//!\r
+//! \return The binary version of the input parameter\r
+//\r
+//*****************************************************************************\r
+extern uint16_t RTC_C_convertBCDToBinary(uint16_t baseAddress,\r
+ uint16_t valueToConvert);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Convert the given binary value to BCD format\r
+//!\r
+//! This function converts binary values to BCD format. This API uses the\r
+//! hardware registers to perform the conversion rather than a software method.\r
+//!\r
+//! \param baseAddress is the base address of the RTC_C module.\r
+//! \param valueToConvert is the raw value in Binary format to convert to BCD.\r
+//! \n Modified bits are \b BIN2BCD of \b BIN2BCD register.\r
+//!\r
+//! \return The BCD version of the valueToConvert parameter\r
+//\r
+//*****************************************************************************\r
+extern uint16_t RTC_C_convertBinaryToBCD(uint16_t baseAddress,\r
+ uint16_t valueToConvert);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_RTC_C_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// sfr.c - Driver for the sfr Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup sfr_api sfr\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_SFR__\r
+#include "sfr.h"\r
+\r
+#include <assert.h>\r
+\r
+void SFR_enableInterrupt(uint8_t interruptMask)\r
+{\r
+ HWREG8(SFR_BASE + OFS_SFRIE1_L) |= interruptMask;\r
+}\r
+\r
+void SFR_disableInterrupt(uint8_t interruptMask)\r
+{\r
+ HWREG8(SFR_BASE + OFS_SFRIE1_L) &= ~(interruptMask);\r
+}\r
+\r
+uint8_t SFR_getInterruptStatus(uint8_t interruptFlagMask)\r
+{\r
+ return (HWREG8(SFR_BASE + OFS_SFRIFG1_L) & interruptFlagMask);\r
+}\r
+\r
+void SFR_clearInterrupt(uint8_t interruptFlagMask)\r
+{\r
+ HWREG8(SFR_BASE + OFS_SFRIFG1_L) &= ~(interruptFlagMask);\r
+}\r
+\r
+void SFR_setResetPinPullResistor(uint16_t pullResistorSetup)\r
+{\r
+ HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSRSTRE + SYSRSTUP);\r
+ HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= pullResistorSetup;\r
+}\r
+\r
+void SFR_setNMIEdge(uint16_t edgeDirection)\r
+{\r
+ HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSNMIIES);\r
+ HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= edgeDirection;\r
+}\r
+\r
+void SFR_setResetNMIPinFunction(uint8_t resetPinFunction)\r
+{\r
+ HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSNMI);\r
+ HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= resetPinFunction;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for sfr_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// sfr.h - Driver for the SFR Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_SFR_H__\r
+#define __MSP430WARE_SFR_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_SFR__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the interruptMask parameter\r
+// for functions: SFR_enableInterrupt(), and SFR_disableInterrupt(); the\r
+// interruptFlagMask parameter for functions: SFR_getInterruptStatus(), and\r
+// SFR_clearInterrupt() as well as returned by the SFR_getInterruptStatus()\r
+// function.\r
+//\r
+//*****************************************************************************\r
+#define SFR_JTAG_OUTBOX_INTERRUPT JMBOUTIE\r
+#define SFR_JTAG_INBOX_INTERRUPT JMBINIE\r
+#define SFR_NMI_PIN_INTERRUPT NMIIE\r
+#define SFR_VACANT_MEMORY_ACCESS_INTERRUPT VMAIE\r
+#define SFR_OSCILLATOR_FAULT_INTERRUPT OFIE\r
+#define SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT WDTIE\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the pullResistorSetup\r
+// parameter for functions: SFR_setResetPinPullResistor().\r
+//\r
+//*****************************************************************************\r
+#define SFR_RESISTORDISABLE (!(SYSRSTRE + SYSRSTUP))\r
+#define SFR_RESISTORENABLE_PULLUP (SYSRSTRE + SYSRSTUP)\r
+#define SFR_RESISTORENABLE_PULLDOWN (SYSRSTRE)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the edgeDirection parameter\r
+// for functions: SFR_setNMIEdge().\r
+//\r
+//*****************************************************************************\r
+#define SFR_NMI_RISINGEDGE (!(SYSNMIIES))\r
+#define SFR_NMI_FALLINGEDGE (SYSNMIIES)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the resetPinFunction\r
+// parameter for functions: SFR_setResetNMIPinFunction().\r
+//\r
+//*****************************************************************************\r
+#define SFR_RESETPINFUNC_RESET (!(SYSNMI))\r
+#define SFR_RESETPINFUNC_NMI (SYSNMI)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables selected SFR interrupt sources.\r
+//!\r
+//! This function enables the selected SFR interrupt sources. Only the sources\r
+//! that are enabled can be reflected to the processor interrupt; disabled\r
+//! sources have no effect on the processor. Does not clear interrupt flags.\r
+//!\r
+//! \param interruptMask is the bit mask of interrupts that will be enabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt\r
+//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt\r
+//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt, if NMI function is\r
+//! chosen\r
+//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access\r
+//! interrupt\r
+//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt\r
+//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer\r
+//! interrupt\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SFR_enableInterrupt(uint8_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables selected SFR interrupt sources.\r
+//!\r
+//! This function disables the selected SFR interrupt sources. Only the sources\r
+//! that are enabled can be reflected to the processor interrupt; disabled\r
+//! sources have no effect on the processor.\r
+//!\r
+//! \param interruptMask is the bit mask of interrupts that will be disabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt\r
+//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt\r
+//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt, if NMI function is\r
+//! chosen\r
+//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access\r
+//! interrupt\r
+//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt\r
+//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer\r
+//! interrupt\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SFR_disableInterrupt(uint8_t interruptMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the status of the selected SFR interrupt flags.\r
+//!\r
+//! This function returns the status of the selected SFR interrupt flags in a\r
+//! bit mask format matching that passed into the interruptFlagMask parameter.\r
+//!\r
+//! \param interruptFlagMask is the bit mask of interrupt flags that the status\r
+//! of should be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt\r
+//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt\r
+//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt, if NMI function is\r
+//! chosen\r
+//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access\r
+//! interrupt\r
+//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt\r
+//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer\r
+//! interrupt\r
+//!\r
+//! \return A bit mask of the status of the selected interrupt flags.\r
+//! Return Logical OR of any of the following:\r
+//! - \b SFR_JTAG_OUTBOX_INTERRUPT JTAG outbox interrupt\r
+//! - \b SFR_JTAG_INBOX_INTERRUPT JTAG inbox interrupt\r
+//! - \b SFR_NMI_PIN_INTERRUPT NMI pin interrupt, if NMI function is\r
+//! chosen\r
+//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT Vacant memory access\r
+//! interrupt\r
+//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT Oscillator fault interrupt\r
+//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT Watchdog interval timer\r
+//! interrupt\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint8_t SFR_getInterruptStatus(uint8_t interruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the selected SFR interrupt flags.\r
+//!\r
+//! This function clears the status of the selected SFR interrupt flags.\r
+//!\r
+//! \param interruptFlagMask is the bit mask of interrupt flags that will be\r
+//! cleared.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt\r
+//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt\r
+//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt, if NMI function is\r
+//! chosen\r
+//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access\r
+//! interrupt\r
+//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt\r
+//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer\r
+//! interrupt\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SFR_clearInterrupt(uint8_t interruptFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the pull-up/down resistor on the ~RST/NMI pin.\r
+//!\r
+//! This function sets the pull-up/down resistors on the ~RST/NMI pin to the\r
+//! settings from the pullResistorSetup parameter.\r
+//!\r
+//! \param pullResistorSetup is the selection of how the pull-up/down resistor\r
+//! on the ~RST/NMI pin should be setup or disabled.\r
+//! Valid values are:\r
+//! - \b SFR_RESISTORDISABLE\r
+//! - \b SFR_RESISTORENABLE_PULLUP [Default]\r
+//! - \b SFR_RESISTORENABLE_PULLDOWN\r
+//! \n Modified bits are \b SYSRSTUP and \b SYSRSTRE of \b SFRRPCR\r
+//! register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SFR_setResetPinPullResistor(uint16_t pullResistorSetup);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the edge direction that will assert an NMI from a signal on the\r
+//! ~RST/NMI pin if NMI function is active.\r
+//!\r
+//! This function sets the edge direction that will assert an NMI from a signal\r
+//! on the ~RST/NMI pin if the NMI function is active. To activate the NMI\r
+//! function of the ~RST/NMI use the SFR_setResetNMIPinFunction() passing\r
+//! SFR_RESETPINFUNC_NMI into the resetPinFunction parameter.\r
+//!\r
+//! \param edgeDirection is the direction that the signal on the ~RST/NMI pin\r
+//! should go to signal an interrupt, if enabled.\r
+//! Valid values are:\r
+//! - \b SFR_NMI_RISINGEDGE [Default]\r
+//! - \b SFR_NMI_FALLINGEDGE\r
+//! \n Modified bits are \b SYSNMIIES of \b SFRRPCR register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SFR_setNMIEdge(uint16_t edgeDirection);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the function of the ~RST/NMI pin.\r
+//!\r
+//! This function sets the functionality of the ~RST/NMI pin, whether in reset\r
+//! mode which will assert a reset if a low signal is observed on that pin, or\r
+//! an NMI which will assert an interrupt from an edge of the signal dependent\r
+//! on the setting of the edgeDirection parameter in SFR_setNMIEdge().\r
+//!\r
+//! \param resetPinFunction is the function that the ~RST/NMI pin should take\r
+//! on.\r
+//! Valid values are:\r
+//! - \b SFR_RESETPINFUNC_RESET [Default]\r
+//! - \b SFR_RESETPINFUNC_NMI\r
+//! \n Modified bits are \b SYSNMI of \b SFRRPCR register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SFR_setResetNMIPinFunction(uint8_t resetPinFunction);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_SFR_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// sysctl.c - Driver for the sysctl Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup sysctl_api sysctl\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_SYS__\r
+#include "sysctl.h"\r
+\r
+#include <assert.h>\r
+\r
+void SysCtl_enableDedicatedJTAGPins(void)\r
+{\r
+ HWREG8(SYS_BASE + OFS_SYSCTL_L) |= SYSJTAGPIN;\r
+}\r
+\r
+uint8_t SysCtl_getBSLEntryIndication(void)\r
+{\r
+ if(HWREG8(SYS_BASE + OFS_SYSCTL_L) & SYSBSLIND)\r
+ {\r
+ return (SYSCTL_BSLENTRY_INDICATED);\r
+ }\r
+ else\r
+ {\r
+ return (SYSCTL_BSLENTRY_NOTINDICATED);\r
+ }\r
+}\r
+\r
+void SysCtl_enablePMMAccessProtect(void)\r
+{\r
+ HWREG8(SYS_BASE + OFS_SYSCTL_L) |= SYSPMMPE;\r
+}\r
+\r
+void SysCtl_enableRAMBasedInterruptVectors(void)\r
+{\r
+ HWREG8(SYS_BASE + OFS_SYSCTL_L) |= SYSRIVECT;\r
+}\r
+\r
+void SysCtl_disableRAMBasedInterruptVectors(void)\r
+{\r
+ HWREG8(SYS_BASE + OFS_SYSCTL_L) &= ~(SYSRIVECT);\r
+}\r
+\r
+void SysCtl_initJTAGMailbox(uint8_t mailboxSizeSelect,\r
+ uint8_t autoClearInboxFlagSelect)\r
+{\r
+ HWREG8(SYS_BASE + OFS_SYSJMBC_L) &= ~(JMBCLR1OFF + JMBCLR0OFF + JMBMODE);\r
+ HWREG8(SYS_BASE + OFS_SYSJMBC_L) |=\r
+ mailboxSizeSelect + autoClearInboxFlagSelect;\r
+}\r
+\r
+uint8_t SysCtl_getJTAGMailboxFlagStatus(uint8_t mailboxFlagMask)\r
+{\r
+ return (HWREG8(SYS_BASE + OFS_SYSJMBC_L) & mailboxFlagMask);\r
+}\r
+\r
+void SysCtl_clearJTAGMailboxFlagStatus(uint8_t mailboxFlagMask)\r
+{\r
+ HWREG8(SYS_BASE + OFS_SYSJMBC_L) &= ~(mailboxFlagMask);\r
+}\r
+\r
+uint16_t SysCtl_getJTAGInboxMessage16Bit(uint8_t inboxSelect)\r
+{\r
+ return (HWREG16(SYS_BASE + OFS_SYSJMBI0 + inboxSelect));\r
+}\r
+\r
+uint32_t SysCtl_getJTAGInboxMessage32Bit(void)\r
+{\r
+ uint32_t JTAGInboxMessageLow = HWREG16(SYS_BASE + OFS_SYSJMBI0);\r
+ uint32_t JTAGInboxMessageHigh = HWREG16(SYS_BASE + OFS_SYSJMBI1);\r
+\r
+ return ((JTAGInboxMessageHigh << 16) + JTAGInboxMessageLow);\r
+}\r
+\r
+void SysCtl_setJTAGOutgoingMessage16Bit(uint8_t outboxSelect,\r
+ uint16_t outgoingMessage)\r
+{\r
+ HWREG16(SYS_BASE + OFS_SYSJMBO0 + outboxSelect) = outgoingMessage;\r
+}\r
+\r
+void SysCtl_setJTAGOutgoingMessage32Bit(uint32_t outgoingMessage)\r
+{\r
+ HWREG16(SYS_BASE + OFS_SYSJMBO0) = (outgoingMessage);\r
+ HWREG16(SYS_BASE + OFS_SYSJMBO1) = (outgoingMessage >> 16);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for sysctl_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// sysctl.h - Driver for the SYSCTL Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_SYSCTL_H__\r
+#define __MSP430WARE_SYSCTL_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_SYS__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mailboxSizeSelect\r
+// parameter for functions: SysCtl_initJTAGMailbox().\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_JTAGMBSIZE_16BIT (!(JMBMODE))\r
+#define SYSCTL_JTAGMBSIZE_32BIT (JMBMODE)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the autoClearInboxFlagSelect\r
+// parameter for functions: SysCtl_initJTAGMailbox().\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_JTAGINBOX0AUTO_JTAGINBOX1AUTO (!(JMBCLR0OFF + JMBCLR1OFF))\r
+#define SYSCTL_JTAGINBOX0AUTO_JTAGINBOX1SW (JMBCLR1OFF)\r
+#define SYSCTL_JTAGINBOX0SW_JTAGINBOX1AUTO (JMBCLR0OFF)\r
+#define SYSCTL_JTAGINBOX0SW_JTAGINBOX1SW (JMBCLR0OFF + JMBCLR1OFF)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mailboxFlagMask parameter\r
+// for functions: SysCtl_getJTAGMailboxFlagStatus(), and\r
+// SysCtl_clearJTAGMailboxFlagStatus().\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_JTAGOUTBOX_FLAG0 (JMBOUT0FG)\r
+#define SYSCTL_JTAGOUTBOX_FLAG1 (JMBOUT1FG)\r
+#define SYSCTL_JTAGINBOX_FLAG0 (JMBIN0FG)\r
+#define SYSCTL_JTAGINBOX_FLAG1 (JMBIN1FG)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the inboxSelect parameter for\r
+// functions: SysCtl_getJTAGInboxMessage16Bit().\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_JTAGINBOX_0 (0x0)\r
+#define SYSCTL_JTAGINBOX_1 (0x2)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the outboxSelect parameter\r
+// for functions: SysCtl_setJTAGOutgoingMessage16Bit().\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_JTAGOUTBOX_0 (0x0)\r
+#define SYSCTL_JTAGOUTBOX_1 (0x2)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the SysCtl_getBSLEntryIndication() function.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BSLENTRY_INDICATED (0x1)\r
+#define SYSCTL_BSLENTRY_NOTINDICATED (0x0)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the JTAG pins to be exclusively for JTAG until a BOR occurs.\r
+//!\r
+//! This function sets the JTAG pins to be exclusively used for the JTAG, and\r
+//! not to be shared with the GPIO pins. This setting can only be cleared when\r
+//! a BOR occurs.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SysCtl_enableDedicatedJTAGPins(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the indication of a BSL entry sequence from the Spy-Bi-Wire.\r
+//!\r
+//! This function returns the indication of a BSL entry sequence from the Spy-\r
+//! Bi-Wire.\r
+//!\r
+//!\r
+//! \return One of the following:\r
+//! - \b SysCtl_BSLENTRY_INDICATED\r
+//! - \b SysCtl_BSLENTRY_NOTINDICATED\r
+//! \n indicating if a BSL entry sequence was detected\r
+//\r
+//*****************************************************************************\r
+extern uint8_t SysCtl_getBSLEntryIndication(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables PMM Access Protection.\r
+//!\r
+//! This function enables the PMM Access Protection, which will lock any\r
+//! changes on the PMM control registers until a BOR occurs.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SysCtl_enablePMMAccessProtect(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables RAM-based Interrupt Vectors.\r
+//!\r
+//! This function enables RAM-base Interrupt Vectors, which means that\r
+//! interrupt vectors are generated with the end address at the top of RAM,\r
+//! instead of the top of the lower 64kB of flash.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SysCtl_enableRAMBasedInterruptVectors(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables RAM-based Interrupt Vectors.\r
+//!\r
+//! This function disables the interrupt vectors from being generated at the\r
+//! top of the RAM.\r
+//!\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SysCtl_disableRAMBasedInterruptVectors(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes JTAG Mailbox with selected properties.\r
+//!\r
+//! This function sets the specified settings for the JTAG Mailbox system. The\r
+//! settings that can be set are the size of the JTAG messages, and the auto-\r
+//! clearing of the inbox flags. If the inbox flags are set to auto-clear, then\r
+//! the inbox flags will be cleared upon reading of the inbox message buffer,\r
+//! otherwise they will have to be reset by software using the\r
+//! SYS_clearJTAGMailboxFlagStatus() function.\r
+//!\r
+//! \param mailboxSizeSelect is the size of the JTAG Mailboxes, whether 16- or\r
+//! 32-bits.\r
+//! Valid values are:\r
+//! - \b SYSCTL_JTAGMBSIZE_16BIT [Default] - the JTAG messages will take\r
+//! up only one JTAG mailbox (i. e. an outgoing message will take up\r
+//! only 1 outbox of the JTAG mailboxes)\r
+//! - \b SYSCTL_JTAGMBSIZE_32BIT - the JTAG messages will be contained\r
+//! within both JTAG mailboxes (i. e. an outgoing message will take\r
+//! up both Outboxes of the JTAG mailboxes)\r
+//! \n Modified bits are \b JMBMODE of \b SYSJMBC register.\r
+//! \param autoClearInboxFlagSelect decides how the JTAG inbox flags should be\r
+//! cleared, whether automatically after the corresponding outbox has\r
+//! been written to, or manually by software.\r
+//! Valid values are:\r
+//! - \b SYSCTL_JTAGINBOX0AUTO_JTAGINBOX1AUTO [Default] - both JTAG\r
+//! inbox flags will be reset automatically when the corresponding\r
+//! inbox is read from.\r
+//! - \b SYSCTL_JTAGINBOX0AUTO_JTAGINBOX1SW - only JTAG inbox 0 flag is\r
+//! reset automatically, while JTAG inbox 1 is reset with the\r
+//! - \b SYSCTL_JTAGINBOX0SW_JTAGINBOX1AUTO - only JTAG inbox 1 flag is\r
+//! reset automatically, while JTAG inbox 0 is reset with the\r
+//! - \b SYSCTL_JTAGINBOX0SW_JTAGINBOX1SW - both JTAG inbox flags will\r
+//! need to be reset manually by the\r
+//! \n Modified bits are \b JMBCLR0OFF and \b JMBCLR1OFF of \b SYSJMBC\r
+//! register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SysCtl_initJTAGMailbox(uint8_t mailboxSizeSelect,\r
+ uint8_t autoClearInboxFlagSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the status of the selected JTAG Mailbox flags.\r
+//!\r
+//! This function will return the status of the selected JTAG Mailbox flags in\r
+//! bit mask format matching that passed into the mailboxFlagMask parameter.\r
+//!\r
+//! \param mailboxFlagMask is the bit mask of JTAG mailbox flags that the\r
+//! status of should be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b SYSCTL_JTAGOUTBOX_FLAG0 - flag for JTAG outbox 0\r
+//! - \b SYSCTL_JTAGOUTBOX_FLAG1 - flag for JTAG outbox 1\r
+//! - \b SYSCTL_JTAGINBOX_FLAG0 - flag for JTAG inbox 0\r
+//! - \b SYSCTL_JTAGINBOX_FLAG1 - flag for JTAG inbox 1\r
+//!\r
+//! \return A bit mask of the status of the selected mailbox flags.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t SysCtl_getJTAGMailboxFlagStatus(uint8_t mailboxFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the status of the selected JTAG Mailbox flags.\r
+//!\r
+//! This function clears the selected JTAG Mailbox flags.\r
+//!\r
+//! \param mailboxFlagMask is the bit mask of JTAG mailbox flags that the\r
+//! status of should be cleared.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b SYSCTL_JTAGOUTBOX_FLAG0 - flag for JTAG outbox 0\r
+//! - \b SYSCTL_JTAGOUTBOX_FLAG1 - flag for JTAG outbox 1\r
+//! - \b SYSCTL_JTAGINBOX_FLAG0 - flag for JTAG inbox 0\r
+//! - \b SYSCTL_JTAGINBOX_FLAG1 - flag for JTAG inbox 1\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SysCtl_clearJTAGMailboxFlagStatus(uint8_t mailboxFlagMask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the contents of the selected JTAG Inbox in a 16 bit format.\r
+//!\r
+//! This function returns the message contents of the selected JTAG inbox. If\r
+//! the auto clear settings for the Inbox flags were set, then using this\r
+//! function will automatically clear the corresponding JTAG inbox flag.\r
+//!\r
+//! \param inboxSelect is the chosen JTAG inbox that the contents of should be\r
+//! returned\r
+//! Valid values are:\r
+//! - \b SYSCTL_JTAGINBOX_0 - return contents of JTAG inbox 0\r
+//! - \b SYSCTL_JTAGINBOX_1 - return contents of JTAG inbox 1\r
+//!\r
+//! \return The contents of the selected JTAG inbox in a 16 bit format.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t SysCtl_getJTAGInboxMessage16Bit(uint8_t inboxSelect);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the contents of JTAG Inboxes in a 32 bit format.\r
+//!\r
+//! This function returns the message contents of both JTAG inboxes in a 32 bit\r
+//! format. This function should be used if 32-bit messaging has been set in\r
+//! the SYS_initJTAGMailbox() function. If the auto clear settings for the\r
+//! Inbox flags were set, then using this function will automatically clear\r
+//! both JTAG inbox flags.\r
+//!\r
+//!\r
+//! \return The contents of both JTAG messages in a 32 bit format.\r
+//\r
+//*****************************************************************************\r
+extern uint32_t SysCtl_getJTAGInboxMessage32Bit(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets a 16 bit outgoing message in to the selected JTAG Outbox.\r
+//!\r
+//! This function sets the outgoing message in the selected JTAG outbox. The\r
+//! corresponding JTAG outbox flag is cleared after this function, and set\r
+//! after the JTAG has read the message.\r
+//!\r
+//! \param outboxSelect is the chosen JTAG outbox that the message should be\r
+//! set it.\r
+//! Valid values are:\r
+//! - \b SYSCTL_JTAGOUTBOX_0 - set the contents of JTAG outbox 0\r
+//! - \b SYSCTL_JTAGOUTBOX_1 - set the contents of JTAG outbox 1\r
+//! \param outgoingMessage is the message to send to the JTAG.\r
+//! \n Modified bits are \b MSGHI and \b MSGLO of \b SYSJMBOx register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SysCtl_setJTAGOutgoingMessage16Bit(uint8_t outboxSelect,\r
+ uint16_t outgoingMessage);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets a 32 bit message in to both JTAG Outboxes.\r
+//!\r
+//! This function sets the 32-bit outgoing message in both JTAG outboxes. The\r
+//! JTAG outbox flags are cleared after this function, and set after the JTAG\r
+//! has read the message.\r
+//!\r
+//! \param outgoingMessage is the message to send to the JTAG.\r
+//! \n Modified bits are \b MSGHI and \b MSGLO of \b SYSJMBOx register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void SysCtl_setJTAGOutgoingMessage32Bit(uint32_t outgoingMessage);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_SYSCTL_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// timer_a.c - Driver for the timer_a Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup timer_a_api timer_a\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_TxA7__\r
+#include "timer_a.h"\r
+\r
+#include <assert.h>\r
+\r
+void Timer_A_startCounter(uint16_t baseAddress,\r
+ uint16_t timerMode)\r
+{\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= timerMode;\r
+}\r
+\r
+void Timer_A_initContinuousMode(uint16_t baseAddress,\r
+ Timer_A_initContinuousModeParam *param)\r
+{\r
+ HWREG16(baseAddress +\r
+ OFS_TAxCTL) &= ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +\r
+ TIMER_A_UPDOWN_MODE +\r
+ TIMER_A_DO_CLEAR +\r
+ TIMER_A_TAIE_INTERRUPT_ENABLE +\r
+ ID__8\r
+ );\r
+ HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7;\r
+\r
+ HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7;\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource +\r
+ param->timerClear +\r
+ param->timerInterruptEnable_TAIE +\r
+ ((param->clockSourceDivider >>\r
+ 3) << 6));\r
+\r
+ if(param->startTimer)\r
+ {\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= TIMER_A_CONTINUOUS_MODE;\r
+ }\r
+}\r
+\r
+void Timer_A_initUpMode(uint16_t baseAddress,\r
+ Timer_A_initUpModeParam *param)\r
+{\r
+ HWREG16(baseAddress + OFS_TAxCTL) &=\r
+ ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +\r
+ TIMER_A_UPDOWN_MODE +\r
+ TIMER_A_DO_CLEAR +\r
+ TIMER_A_TAIE_INTERRUPT_ENABLE +\r
+ ID__8\r
+ );\r
+ HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7;\r
+\r
+ HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7;\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource +\r
+ param->timerClear +\r
+ param->timerInterruptEnable_TAIE +\r
+ ((param->clockSourceDivider >>\r
+ 3) << 6));\r
+\r
+ if(param->startTimer)\r
+ {\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= TIMER_A_UP_MODE;\r
+ }\r
+\r
+ if(TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE ==\r
+ param->captureCompareInterruptEnable_CCR0_CCIE)\r
+ {\r
+ HWREG16(baseAddress +\r
+ OFS_TAxCCTL0) |= TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ HWREG16(baseAddress +\r
+ OFS_TAxCCTL0) &= ~TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_TAxCCR0) = param->timerPeriod;\r
+}\r
+\r
+void Timer_A_initUpDownMode(uint16_t baseAddress,\r
+ Timer_A_initUpDownModeParam *param)\r
+{\r
+ HWREG16(baseAddress + OFS_TAxCTL) &=\r
+ ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +\r
+ TIMER_A_UPDOWN_MODE +\r
+ TIMER_A_DO_CLEAR +\r
+ TIMER_A_TAIE_INTERRUPT_ENABLE +\r
+ ID__8\r
+ );\r
+ HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7;\r
+\r
+ HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7;\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource +\r
+ param->timerClear +\r
+ param->timerInterruptEnable_TAIE +\r
+ ((param->clockSourceDivider >>\r
+ 3) << 6));\r
+\r
+ if(param->startTimer)\r
+ {\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= TIMER_A_UPDOWN_MODE;\r
+ }\r
+\r
+ if(TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE ==\r
+ param->captureCompareInterruptEnable_CCR0_CCIE)\r
+ {\r
+ HWREG16(baseAddress +\r
+ OFS_TAxCCTL0) |= TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ HWREG16(baseAddress +\r
+ OFS_TAxCCTL0) &= ~TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_TAxCCR0) = param->timerPeriod;\r
+}\r
+\r
+void Timer_A_initCaptureMode(uint16_t baseAddress,\r
+ Timer_A_initCaptureModeParam *param)\r
+{\r
+ HWREG16(baseAddress + param->captureRegister) |= CAP;\r
+\r
+ HWREG16(baseAddress + param->captureRegister) &=\r
+ ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE +\r
+ TIMER_A_CAPTURE_INPUTSELECT_Vcc +\r
+ TIMER_A_CAPTURE_SYNCHRONOUS +\r
+ TIMER_A_DO_CLEAR +\r
+ TIMER_A_TAIE_INTERRUPT_ENABLE +\r
+ CM_3\r
+ );\r
+\r
+ HWREG16(baseAddress + param->captureRegister) |= (param->captureMode +\r
+ param->captureInputSelect\r
+ +\r
+ param->\r
+ synchronizeCaptureSource +\r
+ param->\r
+ captureInterruptEnable +\r
+ param->captureOutputMode\r
+ );\r
+}\r
+\r
+void Timer_A_initCompareMode(uint16_t baseAddress,\r
+ Timer_A_initCompareModeParam *param)\r
+{\r
+ HWREG16(baseAddress + param->compareRegister) &= ~CAP;\r
+\r
+ HWREG16(baseAddress + param->compareRegister) &=\r
+ ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE +\r
+ TIMER_A_OUTPUTMODE_RESET_SET\r
+ );\r
+\r
+ HWREG16(baseAddress +\r
+ param->compareRegister) |= (param->compareInterruptEnable +\r
+ param->compareOutputMode\r
+ );\r
+\r
+ HWREG16(baseAddress + param->compareRegister +\r
+ OFS_TAxR) = param->compareValue;\r
+}\r
+\r
+void Timer_A_enableInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= TAIE;\r
+}\r
+\r
+void Timer_A_disableInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TAxCTL) &= ~TAIE;\r
+}\r
+\r
+uint32_t Timer_A_getInterruptStatus(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_TAxCTL) & TAIFG);\r
+}\r
+\r
+void Timer_A_enableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ HWREG16(baseAddress + captureCompareRegister) |= CCIE;\r
+}\r
+\r
+void Timer_A_disableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ HWREG16(baseAddress + captureCompareRegister) &= ~CCIE;\r
+}\r
+\r
+uint32_t Timer_A_getCaptureCompareInterruptStatus(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t mask)\r
+{\r
+ return (HWREG16(baseAddress + captureCompareRegister) & mask);\r
+}\r
+\r
+void Timer_A_clear(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= TACLR;\r
+}\r
+\r
+uint8_t Timer_A_getSynchronizedCaptureCompareInput(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t synchronized)\r
+{\r
+ if(HWREG16(baseAddress + captureCompareRegister) & synchronized)\r
+ {\r
+ return (TIMER_A_CAPTURECOMPARE_INPUT_HIGH);\r
+ }\r
+ else\r
+ {\r
+ return (TIMER_A_CAPTURECOMPARE_INPUT_LOW);\r
+ }\r
+}\r
+\r
+uint8_t Timer_A_getOutputForOutputModeOutBitValue(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ if(HWREG16(baseAddress + captureCompareRegister) & OUT)\r
+ {\r
+ return (TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH);\r
+ }\r
+ else\r
+ {\r
+ return (TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW);\r
+ }\r
+}\r
+\r
+uint16_t Timer_A_getCaptureCompareCount(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ return (HWREG16(baseAddress + OFS_TAxR + captureCompareRegister));\r
+}\r
+\r
+void Timer_A_setOutputForOutputModeOutBitValue(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint8_t outputModeOutBitValue)\r
+{\r
+ HWREG16(baseAddress + captureCompareRegister) &= ~OUT;\r
+ HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue;\r
+}\r
+\r
+void Timer_A_outputPWM(uint16_t baseAddress,\r
+ Timer_A_outputPWMParam *param)\r
+{\r
+ HWREG16(baseAddress + OFS_TAxCTL) &=\r
+ ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +\r
+ TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR +\r
+ TIMER_A_TAIE_INTERRUPT_ENABLE +\r
+ ID__8\r
+ );\r
+ HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7;\r
+\r
+ HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7;\r
+ HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource +\r
+ TIMER_A_UP_MODE +\r
+ TIMER_A_DO_CLEAR +\r
+ ((param->clockSourceDivider >>\r
+ 3) << 6));\r
+\r
+ HWREG16(baseAddress + OFS_TAxCCR0) = param->timerPeriod;\r
+\r
+ HWREG16(baseAddress + OFS_TAxCCTL0) &=\r
+ ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE +\r
+ TIMER_A_OUTPUTMODE_RESET_SET);\r
+\r
+ HWREG16(baseAddress + param->compareRegister) |= param->compareOutputMode;\r
+\r
+ HWREG16(baseAddress + param->compareRegister + OFS_TAxR) = param->dutyCycle;\r
+}\r
+\r
+void Timer_A_stop(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TAxCTL) &= ~MC_3;\r
+}\r
+\r
+void Timer_A_setCompareValue(uint16_t baseAddress,\r
+ uint16_t compareRegister,\r
+ uint16_t compareValue)\r
+{\r
+ HWREG16(baseAddress + compareRegister + OFS_TAxR) = compareValue;\r
+}\r
+\r
+void Timer_A_clearTimerInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TAxCTL) &= ~TAIFG;\r
+}\r
+\r
+void Timer_A_clearCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG;\r
+}\r
+\r
+uint16_t Timer_A_getCounterValue(uint16_t baseAddress)\r
+{\r
+ uint16_t voteOne, voteTwo, res;\r
+\r
+ voteTwo = HWREG16(baseAddress + OFS_TAxR);\r
+\r
+ do\r
+ {\r
+ voteOne = voteTwo;\r
+ voteTwo = HWREG16(baseAddress + OFS_TAxR);\r
+\r
+ if(voteTwo > voteOne)\r
+ {\r
+ res = voteTwo - voteOne;\r
+ }\r
+ else if(voteOne > voteTwo)\r
+ {\r
+ res = voteOne - voteTwo;\r
+ }\r
+ else\r
+ {\r
+ res = 0;\r
+ }\r
+ }\r
+ while(res > TIMER_A_THRESHOLD);\r
+\r
+ return(voteTwo);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for timer_a_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// timer_a.h - Driver for the TIMER_A Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_TIMER_A_H__\r
+#define __MSP430WARE_TIMER_A_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_TxA7__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+// The following is a parameter used for Timer_A_getCounterValue that\r
+// determines the maximum difference in counts of the TAxR register for a\r
+// majority vote.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_THRESHOLD 50\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_A_initContinuousMode() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_A_initContinuousModeParam\r
+{\r
+ //! Selects Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default]\r
+ //! - \b TIMER_A_CLOCKSOURCE_ACLK\r
+ //! - \b TIMER_A_CLOCKSOURCE_SMCLK\r
+ //! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK\r
+ uint16_t clockSource;\r
+ //! Is the desired divider for the clock source\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default]\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64\r
+ uint16_t clockSourceDivider;\r
+ //! Is to enable or disable Timer_A interrupt\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_TAIE_INTERRUPT_ENABLE\r
+ //! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default]\r
+ uint16_t timerInterruptEnable_TAIE;\r
+ //! Decides if Timer_A clock divider, count direction, count need to be\r
+ //! reset.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_DO_CLEAR\r
+ //! - \b TIMER_A_SKIP_CLEAR [Default]\r
+ uint16_t timerClear;\r
+ //! Whether to start the timer immediately\r
+ bool startTimer;\r
+} Timer_A_initContinuousModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_A_initCaptureMode() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_A_initCaptureModeParam\r
+{\r
+ //! Selects the Capture register being used. Refer to datasheet to ensure\r
+ //! the device has the capture compare register being used.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+ uint16_t captureRegister;\r
+ //! Is the capture mode selected.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CAPTUREMODE_NO_CAPTURE [Default]\r
+ //! - \b TIMER_A_CAPTUREMODE_RISING_EDGE\r
+ //! - \b TIMER_A_CAPTUREMODE_FALLING_EDGE\r
+ //! - \b TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE\r
+ uint16_t captureMode;\r
+ //! Decides the Input Select\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxA\r
+ //! - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxB\r
+ //! - \b TIMER_A_CAPTURE_INPUTSELECT_GND\r
+ //! - \b TIMER_A_CAPTURE_INPUTSELECT_Vcc\r
+ uint16_t captureInputSelect;\r
+ //! Decides if capture source should be synchronized with timer clock\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CAPTURE_ASYNCHRONOUS [Default]\r
+ //! - \b TIMER_A_CAPTURE_SYNCHRONOUS\r
+ uint16_t synchronizeCaptureSource;\r
+ //! Is to enable or disable timer captureComapre interrupt.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default]\r
+ //! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE\r
+ uint16_t captureInterruptEnable;\r
+ //! Specifies the output mode.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default]\r
+ //! - \b TIMER_A_OUTPUTMODE_SET\r
+ //! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET\r
+ //! - \b TIMER_A_OUTPUTMODE_SET_RESET\r
+ //! - \b TIMER_A_OUTPUTMODE_TOGGLE\r
+ //! - \b TIMER_A_OUTPUTMODE_RESET\r
+ //! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET\r
+ //! - \b TIMER_A_OUTPUTMODE_RESET_SET\r
+ uint16_t captureOutputMode;\r
+} Timer_A_initCaptureModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_A_initUpDownMode() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_A_initUpDownModeParam\r
+{\r
+ //! Selects Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default]\r
+ //! - \b TIMER_A_CLOCKSOURCE_ACLK\r
+ //! - \b TIMER_A_CLOCKSOURCE_SMCLK\r
+ //! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK\r
+ uint16_t clockSource;\r
+ //! Is the desired divider for the clock source\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default]\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64\r
+ uint16_t clockSourceDivider;\r
+ //! Is the specified Timer_A period\r
+ uint16_t timerPeriod;\r
+ //! Is to enable or disable Timer_A interrupt\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_TAIE_INTERRUPT_ENABLE\r
+ //! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default]\r
+ uint16_t timerInterruptEnable_TAIE;\r
+ //! Is to enable or disable Timer_A CCR0 captureComapre interrupt.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE\r
+ //! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default]\r
+ uint16_t captureCompareInterruptEnable_CCR0_CCIE;\r
+ //! Decides if Timer_A clock divider, count direction, count need to be\r
+ //! reset.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_DO_CLEAR\r
+ //! - \b TIMER_A_SKIP_CLEAR [Default]\r
+ uint16_t timerClear;\r
+ //! Whether to start the timer immediately\r
+ bool startTimer;\r
+} Timer_A_initUpDownModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_A_outputPWM() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_A_outputPWMParam\r
+{\r
+ //! Selects Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default]\r
+ //! - \b TIMER_A_CLOCKSOURCE_ACLK\r
+ //! - \b TIMER_A_CLOCKSOURCE_SMCLK\r
+ //! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK\r
+ uint16_t clockSource;\r
+ //! Is the desired divider for the clock source\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default]\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64\r
+ uint16_t clockSourceDivider;\r
+ //! Selects the desired timer period\r
+ uint16_t timerPeriod;\r
+ //! Selects the compare register being used. Refer to datasheet to ensure\r
+ //! the device has the capture compare register being used.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+ uint16_t compareRegister;\r
+ //! Specifies the output mode.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default]\r
+ //! - \b TIMER_A_OUTPUTMODE_SET\r
+ //! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET\r
+ //! - \b TIMER_A_OUTPUTMODE_SET_RESET\r
+ //! - \b TIMER_A_OUTPUTMODE_TOGGLE\r
+ //! - \b TIMER_A_OUTPUTMODE_RESET\r
+ //! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET\r
+ //! - \b TIMER_A_OUTPUTMODE_RESET_SET\r
+ uint16_t compareOutputMode;\r
+ //! Specifies the dutycycle for the generated waveform\r
+ uint16_t dutyCycle;\r
+} Timer_A_outputPWMParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_A_initUpMode() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_A_initUpModeParam\r
+{\r
+ //! Selects Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default]\r
+ //! - \b TIMER_A_CLOCKSOURCE_ACLK\r
+ //! - \b TIMER_A_CLOCKSOURCE_SMCLK\r
+ //! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK\r
+ uint16_t clockSource;\r
+ //! Is the desired divider for the clock source\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default]\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56\r
+ //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64\r
+ uint16_t clockSourceDivider;\r
+ //! Is the specified Timer_A period. This is the value that gets written\r
+ //! into the CCR0. Limited to 16 bits[uint16_t]\r
+ uint16_t timerPeriod;\r
+ //! Is to enable or disable Timer_A interrupt\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_TAIE_INTERRUPT_ENABLE\r
+ //! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default]\r
+ uint16_t timerInterruptEnable_TAIE;\r
+ //! Is to enable or disable Timer_A CCR0 captureComapre interrupt.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE\r
+ //! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default]\r
+ uint16_t captureCompareInterruptEnable_CCR0_CCIE;\r
+ //! Decides if Timer_A clock divider, count direction, count need to be\r
+ //! reset.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_DO_CLEAR\r
+ //! - \b TIMER_A_SKIP_CLEAR [Default]\r
+ uint16_t timerClear;\r
+ //! Whether to start the timer immediately\r
+ bool startTimer;\r
+} Timer_A_initUpModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_A_initCompareMode() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_A_initCompareModeParam\r
+{\r
+ //! Selects the Capture register being used. Refer to datasheet to ensure\r
+ //! the device has the capture compare register being used.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+ //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+ uint16_t compareRegister;\r
+ //! Is to enable or disable timer captureComapre interrupt.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default]\r
+ //! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE\r
+ uint16_t compareInterruptEnable;\r
+ //! Specifies the output mode.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default]\r
+ //! - \b TIMER_A_OUTPUTMODE_SET\r
+ //! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET\r
+ //! - \b TIMER_A_OUTPUTMODE_SET_RESET\r
+ //! - \b TIMER_A_OUTPUTMODE_TOGGLE\r
+ //! - \b TIMER_A_OUTPUTMODE_RESET\r
+ //! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET\r
+ //! - \b TIMER_A_OUTPUTMODE_RESET_SET\r
+ uint16_t compareOutputMode;\r
+ //! Is the count to be compared with in compare mode\r
+ uint16_t compareValue;\r
+} Timer_A_initCompareModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initContinuousMode(), Timer_A_initUpMode(),\r
+// Timer_A_initUpDownMode(), and Timer_A_outputPWM().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_1 0x00\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_2 0x08\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_3 0x02\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_4 0x10\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_5 0x04\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_6 0x05\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_7 0x06\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_8 0x18\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_10 0x0C\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_12 0x0D\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_14 0x0E\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_16 0x0F\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_20 0x14\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_24 0x15\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_28 0x16\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_32 0x17\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_40 0x1C\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_48 0x1D\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_56 0x1E\r
+#define TIMER_A_CLOCKSOURCE_DIVIDER_64 0x1F\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the timerMode parameter for\r
+// functions: Timer_A_startCounter().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_STOP_MODE MC_0\r
+#define TIMER_A_UP_MODE MC_1\r
+#define TIMER_A_CONTINUOUS_MODE MC_2\r
+#define TIMER_A_UPDOWN_MODE MC_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initContinuousMode(), Timer_A_initUpMode(), and\r
+// Timer_A_initUpDownMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_DO_CLEAR TACLR\r
+#define TIMER_A_SKIP_CLEAR 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initContinuousMode(), Timer_A_initUpMode(),\r
+// Timer_A_initUpDownMode(), and Timer_A_outputPWM().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK TASSEL__TACLK\r
+#define TIMER_A_CLOCKSOURCE_ACLK TASSEL__ACLK\r
+#define TIMER_A_CLOCKSOURCE_SMCLK TASSEL__SMCLK\r
+#define TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TASSEL__INCLK\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initContinuousMode(), Timer_A_initUpMode(), and\r
+// Timer_A_initUpDownMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_TAIE_INTERRUPT_ENABLE TAIE\r
+#define TIMER_A_TAIE_INTERRUPT_DISABLE 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initUpMode(), and Timer_A_initUpDownMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE CCIE\r
+#define TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initCaptureMode(), and Timer_A_initCompareMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00\r
+#define TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE CCIE\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initCaptureMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CAPTURE_INPUTSELECT_CCIxA CCIS_0\r
+#define TIMER_A_CAPTURE_INPUTSELECT_CCIxB CCIS_1\r
+#define TIMER_A_CAPTURE_INPUTSELECT_GND CCIS_2\r
+#define TIMER_A_CAPTURE_INPUTSELECT_Vcc CCIS_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initCaptureMode(), Timer_A_initCompareMode(), and\r
+// Timer_A_outputPWM().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_OUTPUTMODE_OUTBITVALUE OUTMOD_0\r
+#define TIMER_A_OUTPUTMODE_SET OUTMOD_1\r
+#define TIMER_A_OUTPUTMODE_TOGGLE_RESET OUTMOD_2\r
+#define TIMER_A_OUTPUTMODE_SET_RESET OUTMOD_3\r
+#define TIMER_A_OUTPUTMODE_TOGGLE OUTMOD_4\r
+#define TIMER_A_OUTPUTMODE_RESET OUTMOD_5\r
+#define TIMER_A_OUTPUTMODE_TOGGLE_SET OUTMOD_6\r
+#define TIMER_A_OUTPUTMODE_RESET_SET OUTMOD_7\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the compareRegister parameter\r
+// for functions: Timer_A_setCompareValue(); the captureCompareRegister\r
+// parameter for functions: Timer_A_enableCaptureCompareInterrupt(),\r
+// Timer_A_disableCaptureCompareInterrupt(),\r
+// Timer_A_getCaptureCompareInterruptStatus(),\r
+// Timer_A_getSynchronizedCaptureCompareInput(),\r
+// Timer_A_getOutputForOutputModeOutBitValue(),\r
+// Timer_A_getCaptureCompareCount(),\r
+// Timer_A_setOutputForOutputModeOutBitValue(), and\r
+// Timer_A_clearCaptureCompareInterrupt(); the param parameter for functions:\r
+// Timer_A_initCaptureMode(), Timer_A_initCompareMode(), and\r
+// Timer_A_outputPWM().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CAPTURECOMPARE_REGISTER_0 0x02\r
+#define TIMER_A_CAPTURECOMPARE_REGISTER_1 0x04\r
+#define TIMER_A_CAPTURECOMPARE_REGISTER_2 0x06\r
+#define TIMER_A_CAPTURECOMPARE_REGISTER_3 0x08\r
+#define TIMER_A_CAPTURECOMPARE_REGISTER_4 0x0A\r
+#define TIMER_A_CAPTURECOMPARE_REGISTER_5 0x0C\r
+#define TIMER_A_CAPTURECOMPARE_REGISTER_6 0x0E\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initCaptureMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CAPTUREMODE_NO_CAPTURE CM_0\r
+#define TIMER_A_CAPTUREMODE_RISING_EDGE CM_1\r
+#define TIMER_A_CAPTUREMODE_FALLING_EDGE CM_2\r
+#define TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE CM_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_A_initCaptureMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CAPTURE_ASYNCHRONOUS 0x00\r
+#define TIMER_A_CAPTURE_SYNCHRONOUS SCS\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: Timer_A_getCaptureCompareInterruptStatus() as well as returned by\r
+// the Timer_A_getCaptureCompareInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CAPTURE_OVERFLOW COV\r
+#define TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG CCIFG\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the synchronized parameter\r
+// for functions: Timer_A_getSynchronizedCaptureCompareInput().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT SCCI\r
+#define TIMER_A_READ_CAPTURE_COMPARE_INPUT CCI\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the Timer_A_getSynchronizedCaptureCompareInput()\r
+// function.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_CAPTURECOMPARE_INPUT_HIGH 0x01\r
+#define TIMER_A_CAPTURECOMPARE_INPUT_LOW 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the outputModeOutBitValue\r
+// parameter for functions: Timer_A_setOutputForOutputModeOutBitValue() as well\r
+// as returned by the Timer_A_getOutputForOutputModeOutBitValue() function.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH OUT\r
+#define TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the Timer_A_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A_INTERRUPT_NOT_PENDING 0x00\r
+#define TIMER_A_INTERRUPT_PENDING 0x01\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts Timer_A counter\r
+//!\r
+//! This function assumes that the timer has been previously configured using\r
+//! Timer_A_configureContinuousMode, Timer_A_configureUpMode or\r
+//! Timer_A_configureUpDownMode.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param timerMode mode to put the timer in\r
+//! Valid values are:\r
+//! - \b TIMER_A_STOP_MODE\r
+//! - \b TIMER_A_UP_MODE\r
+//! - \b TIMER_A_CONTINUOUS_MODE [Default]\r
+//! - \b TIMER_A_UPDOWN_MODE\r
+//!\r
+//! Modified bits of \b TAxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_startCounter(uint16_t baseAddress,\r
+ uint16_t timerMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures Timer_A in continuous mode.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param param is the pointer to struct for continuous mode initialization.\r
+//!\r
+//! Modified bits of \b TAxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_initContinuousMode(uint16_t baseAddress,\r
+ Timer_A_initContinuousModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures Timer_A in up mode.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param param is the pointer to struct for up mode initialization.\r
+//!\r
+//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits\r
+//! of \b TAxCCR0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_initUpMode(uint16_t baseAddress,\r
+ Timer_A_initUpModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures Timer_A in up down mode.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param param is the pointer to struct for up-down mode initialization.\r
+//!\r
+//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits\r
+//! of \b TAxCCR0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_initUpDownMode(uint16_t baseAddress,\r
+ Timer_A_initUpDownModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes Capture Mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param param is the pointer to struct for capture mode initialization.\r
+//!\r
+//! Modified bits of \b TAxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_initCaptureMode(uint16_t baseAddress,\r
+ Timer_A_initCaptureModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes Compare Mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param param is the pointer to struct for compare mode initialization.\r
+//!\r
+//! Modified bits of \b TAxCCRn register and bits of \b TAxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_initCompareMode(uint16_t baseAddress,\r
+ Timer_A_initCompareModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable timer interrupt\r
+//!\r
+//! Does not clear interrupt flags\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//!\r
+//! Modified bits of \b TAxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_enableInterrupt(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable timer interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//!\r
+//! Modified bits of \b TAxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_disableInterrupt(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get timer interrupt status\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b Timer_A_INTERRUPT_NOT_PENDING\r
+//! - \b Timer_A_INTERRUPT_PENDING\r
+//! \n indicating the Timer_A interrupt status\r
+//\r
+//*****************************************************************************\r
+extern uint32_t Timer_A_getInterruptStatus(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable capture compare interrupt\r
+//!\r
+//! Does not clear interrupt flags\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param captureCompareRegister is the selected capture compare register\r
+//! Valid values are:\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! Modified bits of \b TAxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_enableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable capture compare interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param captureCompareRegister is the selected capture compare register\r
+//! Valid values are:\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! Modified bits of \b TAxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_disableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Return capture compare interrupt status\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param captureCompareRegister is the selected capture compare register\r
+//! Valid values are:\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+//! \param mask is the mask for the interrupt status\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b TIMER_A_CAPTURE_OVERFLOW\r
+//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b Timer_A_CAPTURE_OVERFLOW\r
+//! - \b Timer_A_CAPTURECOMPARE_INTERRUPT_FLAG\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint32_t Timer_A_getCaptureCompareInterruptStatus(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Reset/Clear the timer clock divider, count direction, count\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//!\r
+//! Modified bits of \b TAxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_clear(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get synchronized capturecompare input\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param captureCompareRegister\r
+//! Valid values are:\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+//! \param synchronized\r
+//! Valid values are:\r
+//! - \b TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT\r
+//! - \b TIMER_A_READ_CAPTURE_COMPARE_INPUT\r
+//!\r
+//! \return One of the following:\r
+//! - \b Timer_A_CAPTURECOMPARE_INPUT_HIGH\r
+//! - \b Timer_A_CAPTURECOMPARE_INPUT_LOW\r
+//\r
+//*****************************************************************************\r
+extern uint8_t Timer_A_getSynchronizedCaptureCompareInput(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t synchronized);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get output bit for output mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param captureCompareRegister\r
+//! Valid values are:\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! \return One of the following:\r
+//! - \b Timer_A_OUTPUTMODE_OUTBITVALUE_HIGH\r
+//! - \b Timer_A_OUTPUTMODE_OUTBITVALUE_LOW\r
+//\r
+//*****************************************************************************\r
+extern uint8_t Timer_A_getOutputForOutputModeOutBitValue(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get current capturecompare count\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param captureCompareRegister\r
+//! Valid values are:\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! \return Current count as an uint16_t\r
+//\r
+//*****************************************************************************\r
+extern uint16_t Timer_A_getCaptureCompareCount(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Set output bit for output mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param captureCompareRegister\r
+//! Valid values are:\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+//! \param outputModeOutBitValue is the value to be set for out bit\r
+//! Valid values are:\r
+//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH\r
+//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW\r
+//!\r
+//! Modified bits of \b TAxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_setOutputForOutputModeOutBitValue(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint8_t outputModeOutBitValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Generate a PWM with timer running in up mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param param is the pointer to struct for PWM configuration.\r
+//!\r
+//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register, bits of\r
+//! \b TAxCCR0 register and bits of \b TAxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_outputPWM(uint16_t baseAddress,\r
+ Timer_A_outputPWMParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Stops the timer\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//!\r
+//! Modified bits of \b TAxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_stop(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the value of the capture-compare register\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param compareRegister selects the Capture register being used. Refer to\r
+//! datasheet to ensure the device has the capture compare register\r
+//! being used.\r
+//! Valid values are:\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+//! \param compareValue is the count to be compared with in compare mode\r
+//!\r
+//! Modified bits of \b TAxCCRn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_setCompareValue(uint16_t baseAddress,\r
+ uint16_t compareRegister,\r
+ uint16_t compareValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the Timer TAIFG interrupt flag\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//!\r
+//! Modified bits are \b TAIFG of \b TAxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_clearTimerInterrupt(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the capture-compare interrupt flag\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//! \param captureCompareRegister selects the Capture-compare register being\r
+//! used.\r
+//! Valid values are:\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! Modified bits are \b CCIFG of \b TAxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_A_clearCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Reads the current timer count value\r
+//!\r
+//! Reads the current count value of the timer. There is a majority vote system\r
+//! in place to confirm an accurate value is returned. The TIMER_A_THRESHOLD\r
+//! #define in the corresponding header file can be modified so that the votes\r
+//! must be closer together for a consensus to occur.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_A module.\r
+//!\r
+//! \return Majority vote of timer count value\r
+//\r
+//*****************************************************************************\r
+extern uint16_t Timer_A_getCounterValue(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_TIMER_A_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// timer_b.c - Driver for the timer_b Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup timer_b_api timer_b\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_TxB7__\r
+#include "timer_b.h"\r
+\r
+#include <assert.h>\r
+\r
+void Timer_B_startCounter(uint16_t baseAddress,\r
+ uint16_t timerMode)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= timerMode;\r
+}\r
+\r
+void Timer_B_initContinuousMode(uint16_t baseAddress,\r
+ Timer_B_initContinuousModeParam *param)\r
+{\r
+ HWREG16(baseAddress +\r
+ OFS_TBxCTL) &= ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +\r
+ TIMER_B_UPDOWN_MODE +\r
+ TIMER_B_DO_CLEAR +\r
+ TIMER_B_TBIE_INTERRUPT_ENABLE +\r
+ CNTL_3 +\r
+ ID__8\r
+ );\r
+ HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7;\r
+\r
+ HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7;\r
+\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource +\r
+ param->timerClear +\r
+ param->timerInterruptEnable_TBIE +\r
+ ((param->clockSourceDivider >>\r
+ 3) << 6));\r
+\r
+ if(param->startTimer)\r
+ {\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= TIMER_B_CONTINUOUS_MODE;\r
+ }\r
+}\r
+\r
+void Timer_B_initUpMode(uint16_t baseAddress,\r
+ Timer_B_initUpModeParam *param)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) &=\r
+ ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +\r
+ TIMER_B_UPDOWN_MODE +\r
+ TIMER_B_DO_CLEAR +\r
+ TIMER_B_TBIE_INTERRUPT_ENABLE +\r
+ CNTL_3\r
+ );\r
+ HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7;\r
+\r
+ HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7;\r
+\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource +\r
+ param->timerClear +\r
+ param->timerInterruptEnable_TBIE +\r
+ ((param->clockSourceDivider >>\r
+ 3) << 6));\r
+\r
+ if(param->startTimer)\r
+ {\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= TIMER_B_UP_MODE;\r
+ }\r
+\r
+ if(TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE ==\r
+ param->captureCompareInterruptEnable_CCR0_CCIE)\r
+ {\r
+ HWREG16(baseAddress +\r
+ OFS_TBxCCTL0) |= TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ HWREG16(baseAddress +\r
+ OFS_TBxCCTL0) &= ~TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_TBxCCR0) = param->timerPeriod;\r
+}\r
+\r
+void Timer_B_initUpDownMode(uint16_t baseAddress,\r
+ Timer_B_initUpDownModeParam *param)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) &=\r
+ ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +\r
+ TIMER_B_UPDOWN_MODE +\r
+ TIMER_B_DO_CLEAR +\r
+ TIMER_B_TBIE_INTERRUPT_ENABLE +\r
+ CNTL_3\r
+ );\r
+ HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7;\r
+\r
+ HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7;\r
+\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource +\r
+ TIMER_B_STOP_MODE +\r
+ param->timerClear +\r
+ param->timerInterruptEnable_TBIE +\r
+ ((param->clockSourceDivider >>\r
+ 3) << 6));\r
+\r
+ if(param->startTimer)\r
+ {\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= TIMER_B_UPDOWN_MODE;\r
+ }\r
+\r
+ if(TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE ==\r
+ param->captureCompareInterruptEnable_CCR0_CCIE)\r
+ {\r
+ HWREG16(baseAddress +\r
+ OFS_TBxCCTL0) |= TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ HWREG16(baseAddress +\r
+ OFS_TBxCCTL0) &= ~TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ }\r
+\r
+ HWREG16(baseAddress + OFS_TBxCCR0) = param->timerPeriod;\r
+}\r
+\r
+void Timer_B_initCaptureMode(uint16_t baseAddress,\r
+ Timer_B_initCaptureModeParam *param)\r
+{\r
+ HWREG16(baseAddress + param->captureRegister) |= CAP;\r
+\r
+ HWREG16(baseAddress + param->captureRegister) &=\r
+ ~(TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE +\r
+ TIMER_B_CAPTURE_INPUTSELECT_Vcc +\r
+ TIMER_B_CAPTURE_SYNCHRONOUS +\r
+ TIMER_B_DO_CLEAR +\r
+ TIMER_B_TBIE_INTERRUPT_ENABLE +\r
+ CM_3\r
+ );\r
+\r
+ HWREG16(baseAddress + param->captureRegister) |= (param->captureMode +\r
+ param->captureInputSelect\r
+ +\r
+ param->\r
+ synchronizeCaptureSource +\r
+ param->\r
+ captureInterruptEnable +\r
+ param->captureOutputMode\r
+ );\r
+}\r
+\r
+void Timer_B_initCompareMode(uint16_t baseAddress,\r
+ Timer_B_initCompareModeParam *param)\r
+{\r
+ HWREG16(baseAddress + param->compareRegister) &= ~CAP;\r
+\r
+ HWREG16(baseAddress + param->compareRegister) &=\r
+ ~(TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE +\r
+ TIMER_B_OUTPUTMODE_RESET_SET\r
+ );\r
+\r
+ HWREG16(baseAddress +\r
+ param->compareRegister) |= (param->compareInterruptEnable +\r
+ param->compareOutputMode\r
+ );\r
+\r
+ HWREG16(baseAddress + param->compareRegister +\r
+ OFS_TBxR) = param->compareValue;\r
+}\r
+\r
+void Timer_B_enableInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= TBIE;\r
+}\r
+\r
+void Timer_B_disableInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) &= ~TBIE;\r
+}\r
+\r
+uint32_t Timer_B_getInterruptStatus(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_TBxCTL) & TBIFG);\r
+}\r
+\r
+void Timer_B_enableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ HWREG16(baseAddress + captureCompareRegister) |= CCIE;\r
+}\r
+\r
+void Timer_B_disableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ HWREG16(baseAddress + captureCompareRegister) &= ~CCIE;\r
+}\r
+\r
+uint32_t Timer_B_getCaptureCompareInterruptStatus(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t mask)\r
+{\r
+ return (HWREG16(baseAddress + captureCompareRegister) & mask);\r
+}\r
+\r
+void Timer_B_clear(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= TBCLR;\r
+}\r
+\r
+uint8_t Timer_B_getSynchronizedCaptureCompareInput(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t synchronized)\r
+{\r
+ if(HWREG16(baseAddress + captureCompareRegister) & synchronized)\r
+ {\r
+ return (TIMER_B_CAPTURECOMPARE_INPUT_HIGH);\r
+ }\r
+ else\r
+ {\r
+ return (TIMER_B_CAPTURECOMPARE_INPUT_LOW);\r
+ }\r
+}\r
+\r
+uint8_t Timer_B_getOutputForOutputModeOutBitValue(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ if(HWREG16(baseAddress + captureCompareRegister) & OUT)\r
+ {\r
+ return (TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH);\r
+ }\r
+ else\r
+ {\r
+ return (TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW);\r
+ }\r
+}\r
+\r
+uint16_t Timer_B_getCaptureCompareCount(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ return (HWREG16(baseAddress + OFS_TBxR + captureCompareRegister));\r
+}\r
+\r
+void Timer_B_setOutputForOutputModeOutBitValue(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint8_t outputModeOutBitValue)\r
+{\r
+ HWREG16(baseAddress + captureCompareRegister) &= ~OUT;\r
+ HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue;\r
+}\r
+\r
+void Timer_B_outputPWM(uint16_t baseAddress,\r
+ Timer_B_outputPWMParam *param)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) &=\r
+ ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +\r
+ TIMER_B_UPDOWN_MODE + TIMER_B_DO_CLEAR +\r
+ TIMER_B_TBIE_INTERRUPT_ENABLE\r
+ );\r
+ HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7;\r
+\r
+ HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7;\r
+\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource +\r
+ TIMER_B_UP_MODE +\r
+ TIMER_B_DO_CLEAR +\r
+ ((param->clockSourceDivider >>\r
+ 3) << 6));\r
+\r
+ HWREG16(baseAddress + OFS_TBxCCR0) = param->timerPeriod;\r
+\r
+ HWREG16(baseAddress + OFS_TBxCCTL0) &=\r
+ ~(TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE +\r
+ TIMER_B_OUTPUTMODE_RESET_SET\r
+ );\r
+\r
+ HWREG16(baseAddress + param->compareRegister) |= param->compareOutputMode;\r
+\r
+ HWREG16(baseAddress + param->compareRegister + OFS_TBxR) = param->dutyCycle;\r
+}\r
+\r
+void Timer_B_stop(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) &= ~MC_3;\r
+}\r
+\r
+void Timer_B_setCompareValue(uint16_t baseAddress,\r
+ uint16_t compareRegister,\r
+ uint16_t compareValue)\r
+{\r
+ HWREG16(baseAddress + compareRegister + OFS_TBxR) = compareValue;\r
+}\r
+\r
+void Timer_B_clearTimerInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) &= ~TBIFG;\r
+}\r
+\r
+void Timer_B_clearCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister)\r
+{\r
+ HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG;\r
+}\r
+\r
+void Timer_B_selectCounterLength(uint16_t baseAddress,\r
+ uint16_t counterLength)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) &= ~CNTL_3;\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= counterLength;\r
+}\r
+\r
+void Timer_B_selectLatchingGroup(uint16_t baseAddress,\r
+ uint16_t groupLatch)\r
+{\r
+ HWREG16(baseAddress + OFS_TBxCTL) &= ~TBCLGRP_3;\r
+ HWREG16(baseAddress + OFS_TBxCTL) |= groupLatch;\r
+}\r
+\r
+void Timer_B_initCompareLatchLoadEvent(uint16_t baseAddress,\r
+ uint16_t compareRegister,\r
+ uint16_t compareLatchLoadEvent)\r
+{\r
+ HWREG16(baseAddress + compareRegister) &= ~CLLD_3;\r
+ HWREG16(baseAddress + compareRegister) |= compareLatchLoadEvent;\r
+}\r
+\r
+uint16_t Timer_B_getCounterValue(uint16_t baseAddress)\r
+{\r
+ uint16_t voteOne, voteTwo, res;\r
+\r
+ voteTwo = HWREG16(baseAddress + OFS_TBxR);\r
+\r
+ do\r
+ {\r
+ voteOne = voteTwo;\r
+ voteTwo = HWREG16(baseAddress + OFS_TBxR);\r
+\r
+ if(voteTwo > voteOne)\r
+ {\r
+ res = voteTwo - voteOne;\r
+ }\r
+ else if(voteOne > voteTwo)\r
+ {\r
+ res = voteOne - voteTwo;\r
+ }\r
+ else\r
+ {\r
+ res = 0;\r
+ }\r
+ }\r
+ while(res > TIMER_B_THRESHOLD);\r
+\r
+ return(voteTwo);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for timer_b_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// timer_b.h - Driver for the TIMER_B Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_TIMER_B_H__\r
+#define __MSP430WARE_TIMER_B_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_TxB7__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//*****************************************************************************\r
+//\r
+// The following is a parameter used for Timer_B_getCounterValue that\r
+// determines the maximum difference in counts of the TAxR register for a\r
+// majority vote.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_THRESHOLD 50\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_B_outputPWM() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_B_outputPWMParam\r
+{\r
+ //! Selects the clock source\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default]\r
+ //! - \b TIMER_B_CLOCKSOURCE_ACLK\r
+ //! - \b TIMER_B_CLOCKSOURCE_SMCLK\r
+ //! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK\r
+ uint16_t clockSource;\r
+ //! Is the divider for Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default]\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64\r
+ uint16_t clockSourceDivider;\r
+ //! Selects the desired Timer_B period\r
+ uint16_t timerPeriod;\r
+ //! Selects the compare register being used. Refer to datasheet to ensure\r
+ //! the device has the compare register being used.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+ uint16_t compareRegister;\r
+ //! Specifies the output mode.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE [Default]\r
+ //! - \b TIMER_B_OUTPUTMODE_SET\r
+ //! - \b TIMER_B_OUTPUTMODE_TOGGLE_RESET\r
+ //! - \b TIMER_B_OUTPUTMODE_SET_RESET\r
+ //! - \b TIMER_B_OUTPUTMODE_TOGGLE\r
+ //! - \b TIMER_B_OUTPUTMODE_RESET\r
+ //! - \b TIMER_B_OUTPUTMODE_TOGGLE_SET\r
+ //! - \b TIMER_B_OUTPUTMODE_RESET_SET\r
+ uint16_t compareOutputMode;\r
+ //! Specifies the dutycycle for the generated waveform\r
+ uint16_t dutyCycle;\r
+} Timer_B_outputPWMParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_B_initUpMode() function as the param parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_B_initUpModeParam\r
+{\r
+ //! Selects the clock source\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default]\r
+ //! - \b TIMER_B_CLOCKSOURCE_ACLK\r
+ //! - \b TIMER_B_CLOCKSOURCE_SMCLK\r
+ //! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK\r
+ uint16_t clockSource;\r
+ //! Is the divider for Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default]\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64\r
+ uint16_t clockSourceDivider;\r
+ //! Is the specified Timer_B period. This is the value that gets written\r
+ //! into the CCR0. Limited to 16 bits[uint16_t]\r
+ uint16_t timerPeriod;\r
+ //! Is to enable or disable Timer_B interrupt\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_TBIE_INTERRUPT_ENABLE\r
+ //! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default]\r
+ uint16_t timerInterruptEnable_TBIE;\r
+ //! Is to enable or disable Timer_B CCR0 capture compare interrupt.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE\r
+ //! - \b TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE [Default]\r
+ uint16_t captureCompareInterruptEnable_CCR0_CCIE;\r
+ //! Decides if Timer_B clock divider, count direction, count need to be\r
+ //! reset.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_DO_CLEAR\r
+ //! - \b TIMER_B_SKIP_CLEAR [Default]\r
+ uint16_t timerClear;\r
+ //! Whether to start the timer immediately\r
+ bool startTimer;\r
+} Timer_B_initUpModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_B_initCaptureMode() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_B_initCaptureModeParam\r
+{\r
+ //! Selects the capture register being used. Refer to datasheet to ensure\r
+ //! the device has the capture register being used.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+ uint16_t captureRegister;\r
+ //! Is the capture mode selected.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CAPTUREMODE_NO_CAPTURE [Default]\r
+ //! - \b TIMER_B_CAPTUREMODE_RISING_EDGE\r
+ //! - \b TIMER_B_CAPTUREMODE_FALLING_EDGE\r
+ //! - \b TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE\r
+ uint16_t captureMode;\r
+ //! Decides the Input Select\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CAPTURE_INPUTSELECT_CCIxA [Default]\r
+ //! - \b TIMER_B_CAPTURE_INPUTSELECT_CCIxB\r
+ //! - \b TIMER_B_CAPTURE_INPUTSELECT_GND\r
+ //! - \b TIMER_B_CAPTURE_INPUTSELECT_Vcc\r
+ uint16_t captureInputSelect;\r
+ //! Decides if capture source should be synchronized with Timer_B clock\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CAPTURE_ASYNCHRONOUS [Default]\r
+ //! - \b TIMER_B_CAPTURE_SYNCHRONOUS\r
+ uint16_t synchronizeCaptureSource;\r
+ //! Is to enable or disable Timer_B capture compare interrupt.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE [Default]\r
+ //! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE\r
+ uint16_t captureInterruptEnable;\r
+ //! Specifies the output mode.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE [Default]\r
+ //! - \b TIMER_B_OUTPUTMODE_SET\r
+ //! - \b TIMER_B_OUTPUTMODE_TOGGLE_RESET\r
+ //! - \b TIMER_B_OUTPUTMODE_SET_RESET\r
+ //! - \b TIMER_B_OUTPUTMODE_TOGGLE\r
+ //! - \b TIMER_B_OUTPUTMODE_RESET\r
+ //! - \b TIMER_B_OUTPUTMODE_TOGGLE_SET\r
+ //! - \b TIMER_B_OUTPUTMODE_RESET_SET\r
+ uint16_t captureOutputMode;\r
+} Timer_B_initCaptureModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_B_initContinuousMode() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_B_initContinuousModeParam\r
+{\r
+ //! Selects the clock source\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default]\r
+ //! - \b TIMER_B_CLOCKSOURCE_ACLK\r
+ //! - \b TIMER_B_CLOCKSOURCE_SMCLK\r
+ //! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK\r
+ uint16_t clockSource;\r
+ //! Is the divider for Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default]\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64\r
+ uint16_t clockSourceDivider;\r
+ //! Is to enable or disable Timer_B interrupt\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_TBIE_INTERRUPT_ENABLE\r
+ //! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default]\r
+ uint16_t timerInterruptEnable_TBIE;\r
+ //! Decides if Timer_B clock divider, count direction, count need to be\r
+ //! reset.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_DO_CLEAR\r
+ //! - \b TIMER_B_SKIP_CLEAR [Default]\r
+ uint16_t timerClear;\r
+ //! Whether to start the timer immediately\r
+ bool startTimer;\r
+} Timer_B_initContinuousModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_B_initUpDownMode() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_B_initUpDownModeParam\r
+{\r
+ //! Selects the clock source\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default]\r
+ //! - \b TIMER_B_CLOCKSOURCE_ACLK\r
+ //! - \b TIMER_B_CLOCKSOURCE_SMCLK\r
+ //! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK\r
+ uint16_t clockSource;\r
+ //! Is the divider for Clock source.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default]\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56\r
+ //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64\r
+ uint16_t clockSourceDivider;\r
+ //! Is the specified Timer_B period\r
+ uint16_t timerPeriod;\r
+ //! Is to enable or disable Timer_B interrupt\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_TBIE_INTERRUPT_ENABLE\r
+ //! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default]\r
+ uint16_t timerInterruptEnable_TBIE;\r
+ //! Is to enable or disable Timer_B CCR0 capture compare interrupt.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE\r
+ //! - \b TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE [Default]\r
+ uint16_t captureCompareInterruptEnable_CCR0_CCIE;\r
+ //! Decides if Timer_B clock divider, count direction, count need to be\r
+ //! reset.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_DO_CLEAR\r
+ //! - \b TIMER_B_SKIP_CLEAR [Default]\r
+ uint16_t timerClear;\r
+ //! Whether to start the timer immediately\r
+ bool startTimer;\r
+} Timer_B_initUpDownModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Used in the Timer_B_initCompareMode() function as the param\r
+//! parameter.\r
+//\r
+//*****************************************************************************\r
+typedef struct Timer_B_initCompareModeParam\r
+{\r
+ //! Selects the compare register being used. Refer to datasheet to ensure\r
+ //! the device has the compare register being used.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+ //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+ uint16_t compareRegister;\r
+ //! Is to enable or disable Timer_B capture compare interrupt.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE [Default]\r
+ //! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE\r
+ uint16_t compareInterruptEnable;\r
+ //! Specifies the output mode.\r
+ //! \n Valid values are:\r
+ //! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE [Default]\r
+ //! - \b TIMER_B_OUTPUTMODE_SET\r
+ //! - \b TIMER_B_OUTPUTMODE_TOGGLE_RESET\r
+ //! - \b TIMER_B_OUTPUTMODE_SET_RESET\r
+ //! - \b TIMER_B_OUTPUTMODE_TOGGLE\r
+ //! - \b TIMER_B_OUTPUTMODE_RESET\r
+ //! - \b TIMER_B_OUTPUTMODE_TOGGLE_SET\r
+ //! - \b TIMER_B_OUTPUTMODE_RESET_SET\r
+ uint16_t compareOutputMode;\r
+ //! Is the count to be compared with in compare mode\r
+ uint16_t compareValue;\r
+} Timer_B_initCompareModeParam;\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initContinuousMode(), Timer_B_initUpMode(),\r
+// Timer_B_initUpDownMode(), and Timer_B_outputPWM().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_1 0x00\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_2 0x08\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_3 0x02\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_4 0x10\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_5 0x04\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_6 0x05\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_7 0x06\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_8 0x18\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_10 0x0C\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_12 0x0D\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_14 0x0E\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_16 0x0F\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_20 0x14\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_24 0x15\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_28 0x16\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_32 0x17\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_40 0x1C\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_48 0x1D\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_56 0x1E\r
+#define TIMER_B_CLOCKSOURCE_DIVIDER_64 0x1F\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the timerMode parameter for\r
+// functions: Timer_B_startCounter().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_STOP_MODE MC_0\r
+#define TIMER_B_UP_MODE MC_1\r
+#define TIMER_B_CONTINUOUS_MODE MC_2\r
+#define TIMER_B_UPDOWN_MODE MC_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initContinuousMode(), Timer_B_initUpMode(), and\r
+// Timer_B_initUpDownMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_DO_CLEAR TBCLR\r
+#define TIMER_B_SKIP_CLEAR 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initContinuousMode(), Timer_B_initUpMode(),\r
+// Timer_B_initUpDownMode(), and Timer_B_outputPWM().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK TBSSEL__TACLK\r
+#define TIMER_B_CLOCKSOURCE_ACLK TBSSEL__ACLK\r
+#define TIMER_B_CLOCKSOURCE_SMCLK TBSSEL__SMCLK\r
+#define TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TBSSEL__INCLK\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initContinuousMode(), Timer_B_initUpMode(), and\r
+// Timer_B_initUpDownMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_TBIE_INTERRUPT_ENABLE TBIE\r
+#define TIMER_B_TBIE_INTERRUPT_DISABLE 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initUpMode(), and Timer_B_initUpDownMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE CCIE\r
+#define TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initCaptureMode(), and Timer_B_initCompareMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00\r
+#define TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE CCIE\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initCaptureMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CAPTURE_INPUTSELECT_CCIxA CCIS_0\r
+#define TIMER_B_CAPTURE_INPUTSELECT_CCIxB CCIS_1\r
+#define TIMER_B_CAPTURE_INPUTSELECT_GND CCIS_2\r
+#define TIMER_B_CAPTURE_INPUTSELECT_Vcc CCIS_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initCaptureMode(), Timer_B_initCompareMode(), and\r
+// Timer_B_outputPWM().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_OUTPUTMODE_OUTBITVALUE OUTMOD_0\r
+#define TIMER_B_OUTPUTMODE_SET OUTMOD_1\r
+#define TIMER_B_OUTPUTMODE_TOGGLE_RESET OUTMOD_2\r
+#define TIMER_B_OUTPUTMODE_SET_RESET OUTMOD_3\r
+#define TIMER_B_OUTPUTMODE_TOGGLE OUTMOD_4\r
+#define TIMER_B_OUTPUTMODE_RESET OUTMOD_5\r
+#define TIMER_B_OUTPUTMODE_TOGGLE_SET OUTMOD_6\r
+#define TIMER_B_OUTPUTMODE_RESET_SET OUTMOD_7\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the compareRegister parameter\r
+// for functions: Timer_B_setCompareValue(), and\r
+// Timer_B_initCompareLatchLoadEvent(); the captureCompareRegister parameter\r
+// for functions: Timer_B_enableCaptureCompareInterrupt(),\r
+// Timer_B_disableCaptureCompareInterrupt(),\r
+// Timer_B_getCaptureCompareInterruptStatus(),\r
+// Timer_B_getSynchronizedCaptureCompareInput(),\r
+// Timer_B_getOutputForOutputModeOutBitValue(),\r
+// Timer_B_getCaptureCompareCount(),\r
+// Timer_B_setOutputForOutputModeOutBitValue(), and\r
+// Timer_B_clearCaptureCompareInterrupt(); the param parameter for functions:\r
+// Timer_B_initCaptureMode(), Timer_B_initCompareMode(), and\r
+// Timer_B_outputPWM().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CAPTURECOMPARE_REGISTER_0 0x02\r
+#define TIMER_B_CAPTURECOMPARE_REGISTER_1 0x04\r
+#define TIMER_B_CAPTURECOMPARE_REGISTER_2 0x06\r
+#define TIMER_B_CAPTURECOMPARE_REGISTER_3 0x08\r
+#define TIMER_B_CAPTURECOMPARE_REGISTER_4 0x0A\r
+#define TIMER_B_CAPTURECOMPARE_REGISTER_5 0x0C\r
+#define TIMER_B_CAPTURECOMPARE_REGISTER_6 0x0E\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initCaptureMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CAPTUREMODE_NO_CAPTURE CM_0\r
+#define TIMER_B_CAPTUREMODE_RISING_EDGE CM_1\r
+#define TIMER_B_CAPTUREMODE_FALLING_EDGE CM_2\r
+#define TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE CM_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the param parameter for\r
+// functions: Timer_B_initCaptureMode().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CAPTURE_ASYNCHRONOUS 0x00\r
+#define TIMER_B_CAPTURE_SYNCHRONOUS SCS\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the mask parameter for\r
+// functions: Timer_B_getCaptureCompareInterruptStatus() as well as returned by\r
+// the Timer_B_getCaptureCompareInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CAPTURE_OVERFLOW COV\r
+#define TIMER_B_CAPTURECOMPARE_INTERRUPT_FLAG CCIFG\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the synchronized parameter\r
+// for functions: Timer_B_getSynchronizedCaptureCompareInput().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT SCCI\r
+#define TIMER_B_READ_CAPTURE_COMPARE_INPUT CCI\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the Timer_B_getSynchronizedCaptureCompareInput()\r
+// function.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_CAPTURECOMPARE_INPUT_HIGH 0x01\r
+#define TIMER_B_CAPTURECOMPARE_INPUT_LOW 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the outputModeOutBitValue\r
+// parameter for functions: Timer_B_setOutputForOutputModeOutBitValue() as well\r
+// as returned by the Timer_B_getOutputForOutputModeOutBitValue() function.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH OUT\r
+#define TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the counterLength parameter\r
+// for functions: Timer_B_selectCounterLength().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_COUNTER_16BIT CNTL_3\r
+#define TIMER_B_COUNTER_12BIT CNTL_2\r
+#define TIMER_B_COUNTER_10BIT CNTL_1\r
+#define TIMER_B_COUNTER_8BIT CNTL_0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the groupLatch parameter for\r
+// functions: Timer_B_selectLatchingGroup().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_GROUP_NONE TBCLGRP_0\r
+#define TIMER_B_GROUP_CL12_CL23_CL56 TBCLGRP_1\r
+#define TIMER_B_GROUP_CL123_CL456 TBCLGRP_2\r
+#define TIMER_B_GROUP_ALL TBCLGRP_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the compareLatchLoadEvent\r
+// parameter for functions: Timer_B_initCompareLatchLoadEvent().\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_LATCH_ON_WRITE_TO_TBxCCRn_COMPARE_REGISTER CLLD_0\r
+#define TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE CLLD_1\r
+#define TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE CLLD_2\r
+#define TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE CLLD_3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed toThe following are values that\r
+// can be returned by the Timer_B_getInterruptStatus() function.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_B_INTERRUPT_NOT_PENDING 0x00\r
+#define TIMER_B_INTERRUPT_PENDING 0x01\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts Timer_B counter\r
+//!\r
+//! This function assumes that the timer has been previously configured using\r
+//! Timer_B_configureContinuousMode, Timer_B_configureUpMode or\r
+//! Timer_B_configureUpDownMode.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param timerMode selects the mode of the timer\r
+//! Valid values are:\r
+//! - \b TIMER_B_STOP_MODE\r
+//! - \b TIMER_B_UP_MODE\r
+//! - \b TIMER_B_CONTINUOUS_MODE [Default]\r
+//! - \b TIMER_B_UPDOWN_MODE\r
+//!\r
+//! Modified bits of \b TBxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_startCounter(uint16_t baseAddress,\r
+ uint16_t timerMode);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures Timer_B in continuous mode.\r
+//!\r
+//! This API does not start the timer. Timer needs to be started when required\r
+//! using the Timer_B_startCounter API.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param param is the pointer to struct for continuous mode initialization.\r
+//!\r
+//! Modified bits of \b TBxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_initContinuousMode(uint16_t baseAddress,\r
+ Timer_B_initContinuousModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures Timer_B in up mode.\r
+//!\r
+//! This API does not start the timer. Timer needs to be started when required\r
+//! using the Timer_B_startCounter API.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param param is the pointer to struct for up mode initialization.\r
+//!\r
+//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits\r
+//! of \b TBxCCR0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_initUpMode(uint16_t baseAddress,\r
+ Timer_B_initUpModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures Timer_B in up down mode.\r
+//!\r
+//! This API does not start the timer. Timer needs to be started when required\r
+//! using the Timer_B_startCounter API.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param param is the pointer to struct for up-down mode initialization.\r
+//!\r
+//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits\r
+//! of \b TBxCCR0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_initUpDownMode(uint16_t baseAddress,\r
+ Timer_B_initUpDownModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes Capture Mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param param is the pointer to struct for capture mode initialization.\r
+//!\r
+//! Modified bits of \b TBxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_initCaptureMode(uint16_t baseAddress,\r
+ Timer_B_initCaptureModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes Compare Mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param param is the pointer to struct for compare mode initialization.\r
+//!\r
+//! Modified bits of \b TBxCCTLn register and bits of \b TBxCCRn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_initCompareMode(uint16_t baseAddress,\r
+ Timer_B_initCompareModeParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable Timer_B interrupt\r
+//!\r
+//! Enables Timer_B interrupt. Does not clear interrupt flags.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//!\r
+//! Modified bits of \b TBxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_enableInterrupt(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable Timer_B interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//!\r
+//! Modified bits of \b TBxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_disableInterrupt(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get Timer_B interrupt status\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b Timer_B_INTERRUPT_NOT_PENDING\r
+//! - \b Timer_B_INTERRUPT_PENDING\r
+//! \n indicating the status of the Timer_B interrupt\r
+//\r
+//*****************************************************************************\r
+extern uint32_t Timer_B_getInterruptStatus(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable capture compare interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param captureCompareRegister selects the capture compare register being\r
+//! used. Refer to datasheet to ensure the device has the capture\r
+//! compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! Modified bits of \b TBxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_enableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable capture compare interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param captureCompareRegister selects the capture compare register being\r
+//! used. Refer to datasheet to ensure the device has the capture\r
+//! compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! Modified bits of \b TBxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_disableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Return capture compare interrupt status\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param captureCompareRegister selects the capture compare register being\r
+//! used. Refer to datasheet to ensure the device has the capture\r
+//! compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//! \param mask is the mask for the interrupt status\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b TIMER_B_CAPTURE_OVERFLOW\r
+//! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_FLAG\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b Timer_B_CAPTURE_OVERFLOW\r
+//! - \b Timer_B_CAPTURECOMPARE_INTERRUPT_FLAG\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+extern uint32_t Timer_B_getCaptureCompareInterruptStatus(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t mask);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Reset/Clear the Timer_B clock divider, count direction, count\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//!\r
+//! Modified bits of \b TBxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_clear(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get synchronized capturecompare input\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param captureCompareRegister selects the capture compare register being\r
+//! used. Refer to datasheet to ensure the device has the capture\r
+//! compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//! \param synchronized selects the type of capture compare input\r
+//! Valid values are:\r
+//! - \b TIMER_B_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT\r
+//! - \b TIMER_B_READ_CAPTURE_COMPARE_INPUT\r
+//!\r
+//! \return One of the following:\r
+//! - \b Timer_B_CAPTURECOMPARE_INPUT_HIGH\r
+//! - \b Timer_B_CAPTURECOMPARE_INPUT_LOW\r
+//\r
+//*****************************************************************************\r
+extern uint8_t Timer_B_getSynchronizedCaptureCompareInput(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t synchronized);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get output bit for output mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param captureCompareRegister selects the capture compare register being\r
+//! used. Refer to datasheet to ensure the device has the capture\r
+//! compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! \return One of the following:\r
+//! - \b Timer_B_OUTPUTMODE_OUTBITVALUE_HIGH\r
+//! - \b Timer_B_OUTPUTMODE_OUTBITVALUE_LOW\r
+//\r
+//*****************************************************************************\r
+extern uint8_t Timer_B_getOutputForOutputModeOutBitValue(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get current capturecompare count\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param captureCompareRegister selects the capture compare register being\r
+//! used. Refer to datasheet to ensure the device has the capture\r
+//! compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! \return Current count as uint16_t\r
+//\r
+//*****************************************************************************\r
+extern uint16_t Timer_B_getCaptureCompareCount(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Set output bit for output mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param captureCompareRegister selects the capture compare register being\r
+//! used. Refer to datasheet to ensure the device has the capture\r
+//! compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//! \param outputModeOutBitValue the value to be set for out bit\r
+//! Valid values are:\r
+//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH\r
+//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW\r
+//!\r
+//! Modified bits of \b TBxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_setOutputForOutputModeOutBitValue(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint8_t outputModeOutBitValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Generate a PWM with Timer_B running in up mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param param is the pointer to struct for PWM configuration.\r
+//!\r
+//! Modified bits of \b TBxCCTLn register, bits of \b TBxCTL register, bits of\r
+//! \b TBxCCTL0 register and bits of \b TBxCCR0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_outputPWM(uint16_t baseAddress,\r
+ Timer_B_outputPWMParam *param);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Stops the Timer_B\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//!\r
+//! Modified bits of \b TBxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_stop(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the value of the capture-compare register\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param compareRegister selects the compare register being used. Refer to\r
+//! datasheet to ensure the device has the compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//! \param compareValue is the count to be compared with in compare mode\r
+//!\r
+//! Modified bits of \b TBxCCRn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_setCompareValue(uint16_t baseAddress,\r
+ uint16_t compareRegister,\r
+ uint16_t compareValue);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the Timer_B TBIFG interrupt flag\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//!\r
+//! Modified bits are \b TBIFG of \b TBxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_clearTimerInterrupt(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the capture-compare interrupt flag\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param captureCompareRegister selects the capture compare register being\r
+//! used. Refer to datasheet to ensure the device has the capture\r
+//! compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! Modified bits are \b CCIFG of \b TBxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_clearCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects Timer_B counter length\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param counterLength selects the value of counter length.\r
+//! Valid values are:\r
+//! - \b TIMER_B_COUNTER_16BIT [Default]\r
+//! - \b TIMER_B_COUNTER_12BIT\r
+//! - \b TIMER_B_COUNTER_10BIT\r
+//! - \b TIMER_B_COUNTER_8BIT\r
+//!\r
+//! Modified bits are \b CNTL of \b TBxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_selectCounterLength(uint16_t baseAddress,\r
+ uint16_t counterLength);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects Timer_B Latching Group\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param groupLatch selects the latching group.\r
+//! Valid values are:\r
+//! - \b TIMER_B_GROUP_NONE [Default]\r
+//! - \b TIMER_B_GROUP_CL12_CL23_CL56\r
+//! - \b TIMER_B_GROUP_CL123_CL456\r
+//! - \b TIMER_B_GROUP_ALL\r
+//!\r
+//! Modified bits are \b TBCLGRP of \b TBxCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_selectLatchingGroup(uint16_t baseAddress,\r
+ uint16_t groupLatch);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects Compare Latch Load Event\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_B module.\r
+//! \param compareRegister selects the compare register being used. Refer to\r
+//! datasheet to ensure the device has the compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6\r
+//! \param compareLatchLoadEvent selects the latch load event\r
+//! Valid values are:\r
+//! - \b TIMER_B_LATCH_ON_WRITE_TO_TBxCCRn_COMPARE_REGISTER [Default]\r
+//! - \b TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE\r
+//! - \b TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE\r
+//! - \b\r
+//! TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE\r
+//!\r
+//! Modified bits are \b CLLD of \b TBxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void Timer_B_initCompareLatchLoadEvent(uint16_t baseAddress,\r
+ uint16_t compareRegister,\r
+ uint16_t compareLatchLoadEvent);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Reads the current timer count value\r
+//!\r
+//! Reads the current count value of the timer. There is a majority vote system\r
+//! in place to confirm an accurate value is returned. The Timer_B_THRESHOLD\r
+//! #define in the associated header file can be modified so that the votes\r
+//! must be closer together for a consensus to occur.\r
+//!\r
+//! \param baseAddress is the base address of the Timer module.\r
+//!\r
+//! \return Majority vote of timer count value\r
+//\r
+//*****************************************************************************\r
+extern uint16_t Timer_B_getCounterValue(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_TIMER_B_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// tlv.c - Driver for the tlv Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup tlv_api tlv\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_TLV__\r
+#include "tlv.h"\r
+\r
+#include <assert.h>\r
+\r
+void TLV_getInfo(uint8_t tag,\r
+ uint8_t instance,\r
+ uint8_t *length,\r
+ uint16_t **data_address)\r
+{\r
+ // TLV Structure Start Address\r
+ char *TLV_address = (char *)TLV_START;\r
+\r
+ while((TLV_address < (char *)TLV_END)\r
+ && ((*TLV_address != tag) || instance) // check for tag and instance\r
+ && (*TLV_address != TLV_TAGEND)) // do range check first\r
+ {\r
+ if(*TLV_address == tag)\r
+ {\r
+ // repeat till requested instance is reached\r
+ instance--;\r
+ }\r
+ // add (Current TAG address + LENGTH) + 2\r
+ TLV_address += *(TLV_address + 1) + 2;\r
+ }\r
+\r
+ // Check if Tag match happened..\r
+ if(*TLV_address == tag)\r
+ {\r
+ // Return length = Address + 1\r
+ *length = *(TLV_address + 1);\r
+ // Return address of first data/value info = Address + 2\r
+ *data_address = (uint16_t *)(TLV_address + 2);\r
+ }\r
+ // If there was no tag match and the end of TLV structure was reached..\r
+ else\r
+ {\r
+ // Return 0 for TAG not found\r
+ *length = 0;\r
+ // Return 0 for TAG not found\r
+ *data_address = 0;\r
+ }\r
+}\r
+\r
+uint16_t TLV_getDeviceType()\r
+{\r
+ uint16_t *pDeviceType = (uint16_t *)TLV_DEVICE_ID_0;\r
+ // Return Value from TLV Table\r
+ return(pDeviceType[0]);\r
+}\r
+\r
+uint16_t TLV_getMemory(uint8_t instance)\r
+{\r
+ uint8_t *pPDTAG;\r
+ uint8_t bPDTAG_bytes;\r
+ uint16_t count;\r
+\r
+ // set tag for word access comparison\r
+ instance *= 2;\r
+\r
+ // TLV access Function Call\r
+ // Get Peripheral data pointer\r
+ TLV_getInfo(TLV_PDTAG,\r
+ 0,\r
+ &bPDTAG_bytes,\r
+ (uint16_t **)&pPDTAG\r
+ );\r
+\r
+ for(count = 0; count <= instance; count += 2)\r
+ {\r
+ if(pPDTAG[count] == 0)\r
+ {\r
+ // Return 0 if end reached\r
+ return(0);\r
+ }\r
+ if(count == instance)\r
+ {\r
+ return (pPDTAG[count] | pPDTAG[count + 1] << 8);\r
+ }\r
+ }\r
+\r
+ // Return 0: not found\r
+ return(0);\r
+}\r
+\r
+uint16_t TLV_getPeripheral(uint8_t tag,\r
+ uint8_t instance)\r
+{\r
+ uint8_t *pPDTAG;\r
+ uint8_t bPDTAG_bytes;\r
+ uint16_t count = 0;\r
+ uint16_t pcount = 0;\r
+\r
+ // Get Peripheral data pointer\r
+ TLV_getInfo(TLV_PDTAG,\r
+ 0,\r
+ &bPDTAG_bytes,\r
+ (uint16_t **)&pPDTAG\r
+ );\r
+\r
+ // read memory configuration from TLV to get offset for Peripherals\r
+ while(TLV_getMemory(count))\r
+ {\r
+ count++;\r
+ }\r
+ // get number of Peripheral entries\r
+ pcount = pPDTAG[count * 2 + 1];\r
+ // inc count to first Periperal\r
+ count++;\r
+ // adjust point to first address of Peripheral\r
+ pPDTAG += count * 2;\r
+ // set counter back to 0\r
+ count = 0;\r
+ // align pcount for work comparision\r
+ pcount *= 2;\r
+\r
+ // TLV access Function Call\r
+ for(count = 0; count <= pcount; count += 2)\r
+ {\r
+ if(pPDTAG[count + 1] == tag)\r
+ {\r
+ // test if required Peripheral is found\r
+ if(instance > 0)\r
+ {\r
+ // test if required instance is found\r
+ instance--;\r
+ }\r
+ else\r
+ {\r
+ // Return found data\r
+ return (pPDTAG[count] | pPDTAG[count + 1] << 8);\r
+ }\r
+ }\r
+ }\r
+\r
+ // Return 0: not found\r
+ return(0);\r
+}\r
+\r
+uint8_t TLV_getInterrupt(uint8_t tag)\r
+{\r
+ uint8_t *pPDTAG;\r
+ uint8_t bPDTAG_bytes;\r
+ uint16_t count = 0;\r
+ uint16_t pcount = 0;\r
+\r
+ // Get Peripheral data pointer\r
+ TLV_getInfo(TLV_PDTAG,\r
+ 0,\r
+ &bPDTAG_bytes,\r
+ (uint16_t **)&pPDTAG\r
+ );\r
+\r
+ // read memory configuration from TLV to get offset for Peripherals\r
+ while(TLV_getMemory(count))\r
+ {\r
+ count++;\r
+ }\r
+\r
+ pcount = pPDTAG[count * 2 + 1];\r
+ // inc count to first Periperal\r
+ count++;\r
+ // adjust point to first address of Peripheral\r
+ pPDTAG += (pcount + count) * 2;\r
+ // set counter back to 0\r
+ count = 0;\r
+\r
+ // TLV access Function Call\r
+ for(count = 0; count <= tag; count += 2)\r
+ {\r
+ if(pPDTAG[count] == 0)\r
+ {\r
+ // Return 0: not found/end of table\r
+ return(0);\r
+ }\r
+ if(count == tag)\r
+ {\r
+ // Return found data\r
+ return (pPDTAG[count]);\r
+ }\r
+ }\r
+\r
+ // Return 0: not found\r
+ return(0);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for tlv_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// tlv.h - Driver for the TLV Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_TLV_H__\r
+#define __MSP430WARE_TLV_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_TLV__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include "inc/hw_regaccess.h"\r
+//******************************************************************************\r
+//\r
+// TLV Data Types\r
+//\r
+//******************************************************************************\r
+struct s_TLV_Die_Record\r
+{\r
+ uint32_t wafer_id;\r
+ uint16_t die_x_position;\r
+ uint16_t die_y_position;\r
+ uint16_t test_results;\r
+};\r
+\r
+struct s_TLV_ADC_Cal_Data\r
+{\r
+ uint16_t adc_gain_factor;\r
+ int16_t adc_offset;\r
+ uint16_t adc_ref15_30_temp;\r
+ uint16_t adc_ref15_85_temp;\r
+ uint16_t adc_ref20_30_temp;\r
+ uint16_t adc_ref20_85_temp;\r
+ uint16_t adc_ref25_30_temp;\r
+ uint16_t adc_ref25_85_temp;\r
+};\r
+\r
+struct s_TLV_Timer_D_Cal_Data\r
+{\r
+ uint16_t TDH0CTL1_64;\r
+ uint16_t TDH0CTL1_128;\r
+ uint16_t TDH0CTL1_200;\r
+ uint16_t TDH0CTL1_256;\r
+};\r
+\r
+struct s_TLV_REF_Cal_Data\r
+{\r
+ uint16_t ref_ref15;\r
+ uint16_t ref_ref20;\r
+ uint16_t ref_ref25;\r
+};\r
+\r
+struct s_Peripheral_Memory_Data\r
+{\r
+ uint16_t memory_1;\r
+ uint16_t memory_2;\r
+ uint16_t memory_3;\r
+ uint16_t memory_4;\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the tag parameter for\r
+// functions: TLV_getInfo().\r
+//\r
+//*****************************************************************************\r
+#define TLV_TAG_LDTAG TLV_LDTAG\r
+#define TLV_TAG_PDTAG TLV_PDTAG\r
+#define TLV_TAG_Reserved3 TLV_Reserved3\r
+#define TLV_TAG_Reserved4 TLV_Reserved4\r
+#define TLV_TAG_BLANK TLV_BLANK\r
+#define TLV_TAG_Reserved6 TLV_Reserved6\r
+#define TLV_TAG_Reserved7 TLV_Reserved7\r
+#define TLV_TAG_TAGEND TLV_TAGEND\r
+#define TLV_TAG_TAGEXT TLV_TAGEXT\r
+#define TLV_TAG_TIMER_D_CAL TLV_TIMERDCAL\r
+#define TLV_DEVICE_ID_0 0x1A04\r
+#define TLV_DEVICE_ID_1 0x1A05\r
+#define TLV_TAG_DIERECORD TLV_DIERECORD\r
+#define TLV_TAG_ADCCAL TLV_ADCCAL\r
+#define TLV_TAG_ADC12CAL TLV_ADC12CAL\r
+#define TLV_TAG_ADC10CAL TLV_ADC10CAL\r
+#define TLV_TAG_REFCAL TLV_REFCAL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the tag parameter for\r
+// functions: TLV_getPeripheral().\r
+//\r
+//*****************************************************************************\r
+#define TLV_PID_NO_MODULE (0x00)\r
+#define TLV_PID_PORTMAPPING (0x10)\r
+#define TLV_PID_MSP430CPUXV2 (0x23)\r
+#define TLV_PID_JTAG (0x09)\r
+#define TLV_PID_SBW (0x0F)\r
+#define TLV_PID_EEM_XS (0x02)\r
+#define TLV_PID_EEM_S (0x03)\r
+#define TLV_PID_EEM_M (0x04)\r
+#define TLV_PID_EEM_L (0x05)\r
+#define TLV_PID_PMM (0x30)\r
+#define TLV_PID_PMM_FR (0x32)\r
+#define TLV_PID_FCTL (0x39)\r
+#define TLV_PID_CRC16 (0x3C)\r
+#define TLV_PID_CRC16_RB (0x3D)\r
+#define TLV_PID_WDT_A (0x40)\r
+#define TLV_PID_SFR (0x41)\r
+#define TLV_PID_SYS (0x42)\r
+#define TLV_PID_RAMCTL (0x44)\r
+#define TLV_PID_DMA_1 (0x46)\r
+#define TLV_PID_DMA_3 (0x47)\r
+#define TLV_PID_UCS (0x48)\r
+#define TLV_PID_DMA_6 (0x4A)\r
+#define TLV_PID_DMA_2 (0x4B)\r
+#define TLV_PID_PORT1_2 (0x51)\r
+#define TLV_PID_PORT3_4 (0x52)\r
+#define TLV_PID_PORT5_6 (0x53)\r
+#define TLV_PID_PORT7_8 (0x54)\r
+#define TLV_PID_PORT9_10 (0x55)\r
+#define TLV_PID_PORT11_12 (0x56)\r
+#define TLV_PID_PORTU (0x5E)\r
+#define TLV_PID_PORTJ (0x5F)\r
+#define TLV_PID_TA2 (0x60)\r
+#define TLV_PID_TA3 (0x61)\r
+#define TLV_PID_TA5 (0x62)\r
+#define TLV_PID_TA7 (0x63)\r
+#define TLV_PID_TB3 (0x65)\r
+#define TLV_PID_TB5 (0x66)\r
+#define TLV_PID_TB7 (0x67)\r
+#define TLV_PID_RTC (0x68)\r
+#define TLV_PID_BT_RTC (0x69)\r
+#define TLV_PID_BBS (0x6A)\r
+#define TLV_PID_RTC_B (0x6B)\r
+#define TLV_PID_TD2 (0x6C)\r
+#define TLV_PID_TD3 (0x6D)\r
+#define TLV_PID_TD5 (0x6E)\r
+#define TLV_PID_TD7 (0x6F)\r
+#define TLV_PID_TEC (0x70)\r
+#define TLV_PID_RTC_C (0x71)\r
+#define TLV_PID_AES (0x80)\r
+#define TLV_PID_MPY16 (0x84)\r
+#define TLV_PID_MPY32 (0x85)\r
+#define TLV_PID_MPU (0x86)\r
+#define TLV_PID_USCI_AB (0x90)\r
+#define TLV_PID_USCI_A (0x91)\r
+#define TLV_PID_USCI_B (0x92)\r
+#define TLV_PID_EUSCI_A (0x94)\r
+#define TLV_PID_EUSCI_B (0x95)\r
+#define TLV_PID_REF (0xA0)\r
+#define TLV_PID_COMP_B (0xA8)\r
+#define TLV_PID_COMP_D (0xA9)\r
+#define TLV_PID_USB (0x98)\r
+#define TLV_PID_LCD_B (0xB1)\r
+#define TLV_PID_LCD_C (0xB2)\r
+#define TLV_PID_DAC12_A (0xC0)\r
+#define TLV_PID_SD16_B_1 (0xC8)\r
+#define TLV_PID_SD16_B_2 (0xC9)\r
+#define TLV_PID_SD16_B_3 (0xCA)\r
+#define TLV_PID_SD16_B_4 (0xCB)\r
+#define TLV_PID_SD16_B_5 (0xCC)\r
+#define TLV_PID_SD16_B_6 (0xCD)\r
+#define TLV_PID_SD16_B_7 (0xCE)\r
+#define TLV_PID_SD16_B_8 (0xCF)\r
+#define TLV_PID_ADC12_A (0xD1)\r
+#define TLV_PID_ADC10_A (0xD3)\r
+#define TLV_PID_ADC10_B (0xD4)\r
+#define TLV_PID_SD16_A (0xD8)\r
+#define TLV_PID_TI_BSL (0xFC)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets TLV Info\r
+//!\r
+//! The TLV structure uses a tag or base address to identify segments of the\r
+//! table where information is stored. Some examples of TLV tags are Peripheral\r
+//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves\r
+//! the value of a tag and the length of the tag.\r
+//!\r
+//! \param tag represents the tag for which the information needs to be\r
+//! retrieved.\r
+//! Valid values are:\r
+//! - \b TLV_TAG_LDTAG\r
+//! - \b TLV_TAG_PDTAG\r
+//! - \b TLV_TAG_Reserved3\r
+//! - \b TLV_TAG_Reserved4\r
+//! - \b TLV_TAG_BLANK\r
+//! - \b TLV_TAG_Reserved6\r
+//! - \b TLV_TAG_Reserved7\r
+//! - \b TLV_TAG_TAGEND\r
+//! - \b TLV_TAG_TAGEXT\r
+//! - \b TLV_TAG_TIMER_D_CAL\r
+//! - \b TLV_DEVICE_ID_0\r
+//! - \b TLV_DEVICE_ID_1\r
+//! - \b TLV_TAG_DIERECORD\r
+//! - \b TLV_TAG_ADCCAL\r
+//! - \b TLV_TAG_ADC12CAL\r
+//! - \b TLV_TAG_ADC10CAL\r
+//! - \b TLV_TAG_REFCAL\r
+//! \param instance In some cases a specific tag may have more than one\r
+//! instance. For example there may be multiple instances of timer\r
+//! calibration data present under a single Timer Cal tag. This variable\r
+//! specifies the instance for which information is to be retrieved (0,\r
+//! 1, etc.). When only one instance exists; 0 is passed.\r
+//! \param length Acts as a return through indirect reference. The function\r
+//! retrieves the value of the TLV tag length. This value is pointed to\r
+//! by *length and can be used by the application level once the\r
+//! function is called. If the specified tag is not found then the\r
+//! pointer is null 0.\r
+//! \param data_address acts as a return through indirect reference. Once the\r
+//! function is called data_address points to the pointer that holds the\r
+//! value retrieved from the specified TLV tag. If the specified tag is\r
+//! not found then the pointer is null 0.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void TLV_getInfo(uint8_t tag,\r
+ uint8_t instance,\r
+ uint8_t *length,\r
+ uint16_t **data_address);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Retrieves the unique device ID from the TLV structure.\r
+//!\r
+//!\r
+//! \return The device ID is returned as type uint16_t.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t TLV_getDeviceType(void);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets memory information\r
+//!\r
+//! The Peripheral Descriptor tag is split into two portions a list of the\r
+//! available flash memory blocks followed by a list of available peripherals.\r
+//! This function is used to parse through the first portion and calculate the\r
+//! total flash memory available in a device. The typical usage is to call the\r
+//! TLV_getMemory which returns a non-zero value until the entire memory list\r
+//! has been parsed. When a zero is returned, it indicates that all the memory\r
+//! blocks have been counted and the next address holds the beginning of the\r
+//! device peripheral list.\r
+//!\r
+//! \param instance In some cases a specific tag may have more than one\r
+//! instance. This variable specifies the instance for which information\r
+//! is to be retrieved (0, 1 etc). When only one instance exists; 0 is\r
+//! passed.\r
+//!\r
+//! \return The returned value is zero if the end of the memory list is\r
+//! reached.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t TLV_getMemory(uint8_t instance);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets peripheral information from the TLV\r
+//!\r
+//! he Peripheral Descriptor tag is split into two portions a list of the\r
+//! available flash memory blocks followed by a list of available peripherals.\r
+//! This function is used to parse through the second portion and can be used\r
+//! to check if a specific peripheral is present in a device. The function\r
+//! calls TLV_getPeripheral() recursively until the end of the memory list and\r
+//! consequently the beginning of the peripheral list is reached. <\r
+//!\r
+//! \param tag represents represents the tag for a specific peripheral for\r
+//! which the information needs to be retrieved. In the header file tlv.\r
+//! h specific peripheral tags are pre-defined, for example USCIA_B and\r
+//! TA0 are defined as TLV_PID_USCI_AB and TLV_PID_TA2 respectively.\r
+//! Valid values are:\r
+//! - \b TLV_PID_NO_MODULE - No Module\r
+//! - \b TLV_PID_PORTMAPPING - Port Mapping\r
+//! - \b TLV_PID_MSP430CPUXV2 - MSP430CPUXV2\r
+//! - \b TLV_PID_JTAG - JTAG\r
+//! - \b TLV_PID_SBW - SBW\r
+//! - \b TLV_PID_EEM_XS - EEM X-Small\r
+//! - \b TLV_PID_EEM_S - EEM Small\r
+//! - \b TLV_PID_EEM_M - EEM Medium\r
+//! - \b TLV_PID_EEM_L - EEM Large\r
+//! - \b TLV_PID_PMM - PMM\r
+//! - \b TLV_PID_PMM_FR - PMM FRAM\r
+//! - \b TLV_PID_FCTL - Flash\r
+//! - \b TLV_PID_CRC16 - CRC16\r
+//! - \b TLV_PID_CRC16_RB - CRC16 Reverse\r
+//! - \b TLV_PID_WDT_A - WDT_A\r
+//! - \b TLV_PID_SFR - SFR\r
+//! - \b TLV_PID_SYS - SYS\r
+//! - \b TLV_PID_RAMCTL - RAMCTL\r
+//! - \b TLV_PID_DMA_1 - DMA 1\r
+//! - \b TLV_PID_DMA_3 - DMA 3\r
+//! - \b TLV_PID_UCS - UCS\r
+//! - \b TLV_PID_DMA_6 - DMA 6\r
+//! - \b TLV_PID_DMA_2 - DMA 2\r
+//! - \b TLV_PID_PORT1_2 - Port 1 + 2 / A\r
+//! - \b TLV_PID_PORT3_4 - Port 3 + 4 / B\r
+//! - \b TLV_PID_PORT5_6 - Port 5 + 6 / C\r
+//! - \b TLV_PID_PORT7_8 - Port 7 + 8 / D\r
+//! - \b TLV_PID_PORT9_10 - Port 9 + 10 / E\r
+//! - \b TLV_PID_PORT11_12 - Port 11 + 12 / F\r
+//! - \b TLV_PID_PORTU - Port U\r
+//! - \b TLV_PID_PORTJ - Port J\r
+//! - \b TLV_PID_TA2 - Timer A2\r
+//! - \b TLV_PID_TA3 - Timer A1\r
+//! - \b TLV_PID_TA5 - Timer A5\r
+//! - \b TLV_PID_TA7 - Timer A7\r
+//! - \b TLV_PID_TB3 - Timer B3\r
+//! - \b TLV_PID_TB5 - Timer B5\r
+//! - \b TLV_PID_TB7 - Timer B7\r
+//! - \b TLV_PID_RTC - RTC\r
+//! - \b TLV_PID_BT_RTC - BT + RTC\r
+//! - \b TLV_PID_BBS - Battery Backup Switch\r
+//! - \b TLV_PID_RTC_B - RTC_B\r
+//! - \b TLV_PID_TD2 - Timer D2\r
+//! - \b TLV_PID_TD3 - Timer D1\r
+//! - \b TLV_PID_TD5 - Timer D5\r
+//! - \b TLV_PID_TD7 - Timer D7\r
+//! - \b TLV_PID_TEC - Timer Event Control\r
+//! - \b TLV_PID_RTC_C - RTC_C\r
+//! - \b TLV_PID_AES - AES\r
+//! - \b TLV_PID_MPY16 - MPY16\r
+//! - \b TLV_PID_MPY32 - MPY32\r
+//! - \b TLV_PID_MPU - MPU\r
+//! - \b TLV_PID_USCI_AB - USCI_AB\r
+//! - \b TLV_PID_USCI_A - USCI_A\r
+//! - \b TLV_PID_USCI_B - USCI_B\r
+//! - \b TLV_PID_EUSCI_A - eUSCI_A\r
+//! - \b TLV_PID_EUSCI_B - eUSCI_B\r
+//! - \b TLV_PID_REF - Shared Reference\r
+//! - \b TLV_PID_COMP_B - COMP_B\r
+//! - \b TLV_PID_COMP_D - COMP_D\r
+//! - \b TLV_PID_USB - USB\r
+//! - \b TLV_PID_LCD_B - LCD_B\r
+//! - \b TLV_PID_LCD_C - LCD_C\r
+//! - \b TLV_PID_DAC12_A - DAC12_A\r
+//! - \b TLV_PID_SD16_B_1 - SD16_B 1 Channel\r
+//! - \b TLV_PID_SD16_B_2 - SD16_B 2 Channel\r
+//! - \b TLV_PID_SD16_B_3 - SD16_B 3 Channel\r
+//! - \b TLV_PID_SD16_B_4 - SD16_B 4 Channel\r
+//! - \b TLV_PID_SD16_B_5 - SD16_B 5 Channel\r
+//! - \b TLV_PID_SD16_B_6 - SD16_B 6 Channel\r
+//! - \b TLV_PID_SD16_B_7 - SD16_B 7 Channel\r
+//! - \b TLV_PID_SD16_B_8 - SD16_B 8 Channel\r
+//! - \b TLV_PID_ADC12_A - ADC12_A\r
+//! - \b TLV_PID_ADC10_A - ADC10_A\r
+//! - \b TLV_PID_ADC10_B - ADC10_B\r
+//! - \b TLV_PID_SD16_A - SD16_A\r
+//! - \b TLV_PID_TI_BSL - BSL\r
+//! \param instance In some cases a specific tag may have more than one\r
+//! instance. For example a device may have more than a single USCI\r
+//! module, each of which is defined by an instance number 0, 1, 2, etc.\r
+//! When only one instance exists; 0 is passed.\r
+//!\r
+//! \return The returned value is zero if the specified tag value (peripheral)\r
+//! is not available in the device.\r
+//\r
+//*****************************************************************************\r
+extern uint16_t TLV_getPeripheral(uint8_t tag,\r
+ uint8_t instance);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Get interrupt information from the TLV\r
+//!\r
+//! This function is used to retrieve information on available interrupt\r
+//! vectors. It allows the user to check if a specific interrupt vector is\r
+//! defined in a given device.\r
+//!\r
+//! \param tag represents the tag for the interrupt vector. Interrupt vector\r
+//! tags number from 0 to N depending on the number of available\r
+//! interrupts. Refer to the device datasheet for a list of available\r
+//! interrupts.\r
+//!\r
+//! \return The returned value is zero is the specified interrupt vector is not\r
+//! defined.\r
+//\r
+//*****************************************************************************\r
+extern uint8_t TLV_getInterrupt(uint8_t tag);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_TLV_H__\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// wdt_a.c - Driver for the wdt_a Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup wdt_a_api wdt_a\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_WDT_A__\r
+#include "wdt_a.h"\r
+\r
+#include <assert.h>\r
+\r
+void WDT_A_hold(uint16_t baseAddress)\r
+{\r
+ // Set Hold bit\r
+ uint8_t newWDTStatus =\r
+ ((HWREG16(baseAddress + OFS_WDTCTL) & 0x00FF) | WDTHOLD);\r
+\r
+ HWREG16(baseAddress + OFS_WDTCTL) = WDTPW + newWDTStatus;\r
+}\r
+\r
+void WDT_A_start(uint16_t baseAddress)\r
+{\r
+ // Reset Hold bit\r
+ uint8_t newWDTStatus =\r
+ ((HWREG16(baseAddress + OFS_WDTCTL) & 0x00FF) & ~(WDTHOLD));\r
+\r
+ HWREG16(baseAddress + OFS_WDTCTL) = WDTPW + newWDTStatus;\r
+}\r
+\r
+void WDT_A_resetTimer(uint16_t baseAddress)\r
+{\r
+ // Set Counter Clear bit\r
+ uint8_t newWDTStatus =\r
+ ((HWREG16(baseAddress + OFS_WDTCTL) & 0x00FF) | WDTCNTCL);\r
+\r
+ HWREG16(baseAddress + OFS_WDTCTL) = WDTPW + newWDTStatus;\r
+}\r
+\r
+void WDT_A_initWatchdogTimer(uint16_t baseAddress,\r
+ uint8_t clockSelect,\r
+ uint8_t clockDivider)\r
+{\r
+ HWREG16(baseAddress + OFS_WDTCTL) =\r
+ WDTPW + WDTCNTCL + WDTHOLD + clockSelect + clockDivider;\r
+}\r
+\r
+void WDT_A_initIntervalTimer(uint16_t baseAddress,\r
+ uint8_t clockSelect,\r
+ uint8_t clockDivider)\r
+{\r
+ HWREG16(baseAddress + OFS_WDTCTL) =\r
+ WDTPW + WDTCNTCL + WDTHOLD + WDTTMSEL + clockSelect + clockDivider;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for wdt_a_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// wdt_a.h - Driver for the WDT_A Module.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MSP430WARE_WDT_A_H__\r
+#define __MSP430WARE_WDT_A_H__\r
+\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_WDT_A__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockSelect parameter for\r
+// functions: WDT_A_initWatchdogTimer(), and WDT_A_initIntervalTimer().\r
+//\r
+//*****************************************************************************\r
+#define WDT_A_CLOCKSOURCE_SMCLK (WDTSSEL_0)\r
+#define WDT_A_CLOCKSOURCE_ACLK (WDTSSEL_1)\r
+#define WDT_A_CLOCKSOURCE_VLOCLK (WDTSSEL_2)\r
+#define WDT_A_CLOCKSOURCE_XCLK (WDTSSEL_3)\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the clockDivider parameter\r
+// for functions: WDT_A_initWatchdogTimer(), and WDT_A_initIntervalTimer().\r
+//\r
+//*****************************************************************************\r
+#define WDT_A_CLOCKDIVIDER_2G (WDTIS_0)\r
+#define WDT_A_CLOCKDIVIDER_128M (WDTIS_1)\r
+#define WDT_A_CLOCKDIVIDER_8192K (WDTIS_2)\r
+#define WDT_A_CLOCKDIVIDER_512K (WDTIS_3)\r
+#define WDT_A_CLOCKDIVIDER_32K (WDTIS_4)\r
+#define WDT_A_CLOCKDIVIDER_8192 (WDTIS_5)\r
+#define WDT_A_CLOCKDIVIDER_512 (WDTIS_6)\r
+#define WDT_A_CLOCKDIVIDER_64 (WDTIS_7)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Holds the Watchdog Timer.\r
+//!\r
+//! This function stops the watchdog timer from running, that way no interrupt\r
+//! or PUC is asserted.\r
+//!\r
+//! \param baseAddress is the base address of the WDT_A module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void WDT_A_hold(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts the Watchdog Timer.\r
+//!\r
+//! This function starts the watchdog timer functionality to start counting\r
+//! again.\r
+//!\r
+//! \param baseAddress is the base address of the WDT_A module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void WDT_A_start(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Resets the timer counter of the Watchdog Timer.\r
+//!\r
+//! This function resets the watchdog timer to 0x0000h.\r
+//!\r
+//! \param baseAddress is the base address of the WDT_A module.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void WDT_A_resetTimer(uint16_t baseAddress);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the clock source for the Watchdog Timer in watchdog mode.\r
+//!\r
+//! This function sets the watchdog timer in watchdog mode, which will cause a\r
+//! PUC when the timer overflows. When in the mode, a PUC can be avoided with a\r
+//! call to WDT_A_resetTimer() before the timer runs out.\r
+//!\r
+//! \param baseAddress is the base address of the WDT_A module.\r
+//! \param clockSelect is the clock source that the watchdog timer will use.\r
+//! Valid values are:\r
+//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default]\r
+//! - \b WDT_A_CLOCKSOURCE_ACLK\r
+//! - \b WDT_A_CLOCKSOURCE_VLOCLK\r
+//! - \b WDT_A_CLOCKSOURCE_XCLK\r
+//! \n Modified bits are \b WDTSSEL of \b WDTCTL register.\r
+//! \param clockDivider is the divider of the clock source, in turn setting the\r
+//! watchdog timer interval.\r
+//! Valid values are:\r
+//! - \b WDT_A_CLOCKDIVIDER_2G\r
+//! - \b WDT_A_CLOCKDIVIDER_128M\r
+//! - \b WDT_A_CLOCKDIVIDER_8192K\r
+//! - \b WDT_A_CLOCKDIVIDER_512K\r
+//! - \b WDT_A_CLOCKDIVIDER_32K [Default]\r
+//! - \b WDT_A_CLOCKDIVIDER_8192\r
+//! - \b WDT_A_CLOCKDIVIDER_512\r
+//! - \b WDT_A_CLOCKDIVIDER_64\r
+//! \n Modified bits are \b WDTIS and \b WDTHOLD of \b WDTCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void WDT_A_initWatchdogTimer(uint16_t baseAddress,\r
+ uint8_t clockSelect,\r
+ uint8_t clockDivider);\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the clock source for the Watchdog Timer in timer interval mode.\r
+//!\r
+//! This function sets the watchdog timer as timer interval mode, which will\r
+//! assert an interrupt without causing a PUC.\r
+//!\r
+//! \param baseAddress is the base address of the WDT_A module.\r
+//! \param clockSelect is the clock source that the watchdog timer will use.\r
+//! Valid values are:\r
+//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default]\r
+//! - \b WDT_A_CLOCKSOURCE_ACLK\r
+//! - \b WDT_A_CLOCKSOURCE_VLOCLK\r
+//! - \b WDT_A_CLOCKSOURCE_XCLK\r
+//! \n Modified bits are \b WDTSSEL of \b WDTCTL register.\r
+//! \param clockDivider is the divider of the clock source, in turn setting the\r
+//! watchdog timer interval.\r
+//! Valid values are:\r
+//! - \b WDT_A_CLOCKDIVIDER_2G\r
+//! - \b WDT_A_CLOCKDIVIDER_128M\r
+//! - \b WDT_A_CLOCKDIVIDER_8192K\r
+//! - \b WDT_A_CLOCKDIVIDER_512K\r
+//! - \b WDT_A_CLOCKDIVIDER_32K [Default]\r
+//! - \b WDT_A_CLOCKDIVIDER_8192\r
+//! - \b WDT_A_CLOCKDIVIDER_512\r
+//! - \b WDT_A_CLOCKDIVIDER_64\r
+//! \n Modified bits are \b WDTIS and \b WDTHOLD of \b WDTCTL register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+extern void WDT_A_initIntervalTimer(uint16_t baseAddress,\r
+ uint8_t clockSelect,\r
+ uint8_t clockDivider);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+#endif // __MSP430WARE_WDT_A_H__\r
--- /dev/null
+/*******************************************************************************\r
+ *\r
+\r
+ * This is a template for early application low-level initialization.\r
+ *\r
+ * The following license agreement applies to linker command files,\r
+ * example projects (unless another license is explicitly stated), the\r
+ * cstartup code, low_level_init.c, and some other low-level runtime\r
+ * library files.\r
+ *\r
+ *\r
+ * Copyright 2013, IAR Systems AB.\r
+ *\r
+ * This source code is the property of IAR Systems. The source code may only\r
+ * be used together with the IAR Embedded Workbench. Redistribution and use\r
+ * in source and binary forms, with or without modification, is permitted\r
+ * provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code, in whole or in part, must retain the\r
+ * above copyright notice, this list of conditions and the disclaimer below.\r
+ *\r
+ * - IAR Systems name may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r
+ *\r
+ ******************************************************************************/\r
+\r
+/*\r
+ * The function __low_level_init it called by the start-up code before\r
+ * "main" is called, and before data segment initialization is\r
+ * performed.\r
+ *\r
+ * This is a template file, modify to perform any initialization that\r
+ * should take place early.\r
+ *\r
+ * The return value of this function controls if data segment\r
+ * initialization should take place. If 0 is returned, it is bypassed.\r
+ *\r
+ * For the MSP430 microcontroller family, please consider disabling\r
+ * the watchdog timer here, as it could time-out during the data\r
+ * segment initialization.\r
+ */\r
+\r
+#include <intrinsics.h>\r
+#include "msp430.h"\r
+\r
+int __low_level_init(void)\r
+{\r
+ /* Insert your low-level initializations here */\r
+ WDTCTL = WDTPW | WDTHOLD;\r
+ \r
+ /*\r
+ * Return value:\r
+ *\r
+ * 1 - Perform data segment initialization.\r
+ * 0 - Skip data segment initialization.\r
+ */\r
+\r
+ return 1;\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and standard FreeRTOS hook functions.\r
+ *\r
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "EventGroupsDemo.h"\r
+#include "IntSemTest.h"\r
+#include "TaskNotify.h"\r
+#include "ParTest.h" /* LEDs - a historic name for "Parallel Port". */\r
+\r
+/* TI includes. */\r
+#include "driverlib.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware as necessary to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ extern void main_blinky( void );\r
+#else\r
+ extern void main_full( void );\r
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/* The heap is allocated here so the __persistent qualifier can be used. This\r
+requires configAPPLICATION_ALLOCATED_HEAP to be set to 1 in FreeRTOSConfig.h.\r
+See http://www.freertos.org/a00111.html for more information. */\r
+__persistent uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the hardware ready to run the demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Set all GPIO pins to output and low. */\r
+ GPIO_setOutputLowOnPin( GPIO_PORT_P1, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 );\r
+ GPIO_setOutputLowOnPin( GPIO_PORT_P2, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 );\r
+ GPIO_setOutputLowOnPin( GPIO_PORT_P3, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 );\r
+ GPIO_setOutputLowOnPin( GPIO_PORT_P4, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 );\r
+ GPIO_setOutputLowOnPin( GPIO_PORT_PJ, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 | GPIO_PIN8 | GPIO_PIN9 | GPIO_PIN10 | GPIO_PIN11 | GPIO_PIN12 | GPIO_PIN13 | GPIO_PIN14 | GPIO_PIN15 );\r
+ GPIO_setAsOutputPin( GPIO_PORT_P1, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 );\r
+ GPIO_setAsOutputPin( GPIO_PORT_P2, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 );\r
+ GPIO_setAsOutputPin( GPIO_PORT_P3, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 );\r
+ GPIO_setAsOutputPin( GPIO_PORT_P4, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 );\r
+ GPIO_setAsOutputPin( GPIO_PORT_PJ, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 | GPIO_PIN8 | GPIO_PIN9 | GPIO_PIN10 | GPIO_PIN11 | GPIO_PIN12 | GPIO_PIN13 | GPIO_PIN14 | GPIO_PIN15 );\r
+\r
+ /* Configure P2.0 for UCA0TXD and P2.1 for UCA0RXD. */\r
+ GPIO_setOutputLowOnPin( GPIO_PORT_P2, GPIO_PIN0 );\r
+ GPIO_setAsOutputPin( GPIO_PORT_P2, GPIO_PIN0 );\r
+ GPIO_setAsPeripheralModuleFunctionInputPin( GPIO_PORT_P2, GPIO_PIN1, GPIO_SECONDARY_MODULE_FUNCTION );\r
+\r
+ /* Set PJ.4 and PJ.5 for LFXT. */\r
+ GPIO_setAsPeripheralModuleFunctionInputPin( GPIO_PORT_PJ, GPIO_PIN4 + GPIO_PIN5, GPIO_PRIMARY_MODULE_FUNCTION );\r
+\r
+ /* Set DCO frequency to 1 MHz. */\r
+ CS_setDCOFreq( CS_DCORSEL_0, CS_DCOFSEL_6 );\r
+\r
+ /* Set external clock frequency to 32.768 KHz. */\r
+ CS_setExternalClockSource( 32768, 0 );\r
+\r
+ /* Set ACLK = LFXT. */\r
+ CS_initClockSignal( CS_ACLK, CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1 );\r
+\r
+ /* Set SMCLK = DCO with frequency divider of 1. */\r
+ CS_initClockSignal( CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );\r
+\r
+ /* Set MCLK = DCO with frequency divider of 1. */\r
+ CS_initClockSignal( CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );\r
+\r
+ /* Start XT1 with no time out. */\r
+ CS_turnOnLFXT( CS_LFXT_DRIVE_0 );\r
+\r
+ /* Disable the GPIO power-on default high-impedance mode. */\r
+ PMM_unlockLPM5();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeHeapSpace;\r
+\r
+ /* This is just a trivial example of an idle hook. It is called on each\r
+ cycle of the idle task. It must *NOT* attempt to block. In this case the\r
+ idle task just queries the amount of FreeRTOS heap that remains. See the\r
+ memory management section on the http://www.FreeRTOS.org web site for memory\r
+ management options. If there is a lot of heap memory free then the\r
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
+ RAM. */\r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
+ ( void ) xFreeHeapSpace;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
+ {\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+\r
+ /* Call the periodic queue overwrite from ISR demo. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+\r
+ /* Call the periodic event group from ISR demo. */\r
+ vPeriodicEventGroupsProcessing();\r
+\r
+ /* Call the code that uses a mutex from an ISR. */\r
+ vInterruptSemaphorePeriodicTest();\r
+\r
+ /* Call the code that 'gives' a task notification from an ISR. */\r
+ xNotifyTaskFromISR();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The MSP430X port uses this callback function to configure its tick interrupt.\r
+This allows the application to choose the tick interrupt source.\r
+configTICK_VECTOR must also be set in FreeRTOSConfig.h to the correct\r
+interrupt vector for the chosen tick interrupt source. This implementation of\r
+vApplicationSetupTimerInterrupt() generates the tick from timer A0, so in this\r
+case configTICK_VECTOR is set to TIMER0_A0_VECTOR. */\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+const unsigned short usACLK_Frequency_Hz = 32768;\r
+\r
+ /* Ensure the timer is stopped. */\r
+ TA0CTL = 0;\r
+\r
+ /* Run the timer from the ACLK. */\r
+ TA0CTL = TASSEL_1;\r
+\r
+ /* Clear everything to start with. */\r
+ TA0CTL |= TACLR;\r
+\r
+ /* Set the compare match value according to the tick rate we want. */\r
+ TA0CCR0 = usACLK_Frequency_Hz / configTICK_RATE_HZ;\r
+\r
+ /* Enable the interrupts. */\r
+ TA0CCTL0 = CCIE;\r
+\r
+ /* Start up clean. */\r
+ TA0CTL |= TACLR;\r
+\r
+ /* Up mode. */\r
+ TA0CTL |= MC_1;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+/*******************************************************************************\r
+ *\r
+ * main.h\r
+ *\r
+ * Out of Box Demo for the MSP-EXP430FR5969\r
+ * Main loop, initialization, and interrupt service routines\r
+ *\r
+ * June 2014\r
+ * E. Chen\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef OUTOFBOX_FR5969_NEWD_MAIN_H_\r
+#define OUTOFBOX_FR5969_NEWD_MAIN_H_\r
+\r
+#define CAL_ADC_12T30_L *(int8_t *)(0x1A1E) // Temperature Sensor Calibration-30 C 2.0V ref\r
+#define CAL_ADC_12T30_H *(int8_t *)(0x1A1F)\r
+#define CAL_ADC_12T85_L *(int8_t *)(0x1A20) // Temperature Sensor Calibration-85 C 2.0V ref\r
+#define CAL_ADC_12T85_H *(int8_t *)(0x1A21)\r
+\r
+extern int mode;\r
+extern int pingHost;\r
+\r
+void Init_GPIO(void);\r
+void Init_Clock(void);\r
+void Init_UART(void);\r
+void Init_RTC(void);\r
+void sendCalibrationConstants(void);\r
+void sendTimeStamp(void);\r
+void sendAckToPC(void);\r
+void enterLPM35(void);\r
+\r
+#endif /* OUTOFBOX_FR5969_NEWD_MAIN_H_ */\r
projects / freertos / commitdiff