void after_reloc (ulong dest_addr)
{
DECLARE_GLOBAL_DATA_PTR;
-
+
/*
* Jump to the main U-Boot board init code
*/
ulong temp, i;
ulong reg_val;
volatile ulong *reg_ptr;
-
+
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
-
+
/*
* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
/* Make sure that OCN_BAR2 decoder is set (to allow following
* immediate read from SDRAM)
*/
-
+
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
__asm__ __volatile__ ("sync");
* and enable all HLP banks and not just HLP 0 as is being done for
* Taiga Rev. 2.
*/
-
+
env_init ();
#ifndef DISABLE_PBM
-
+
/*
* For IBM processors we have to set Address-Only commands generated
* by PBM that are different from ones set after reset.
for (i = 0; i < 32; i++) {
*reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
-
+
/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
- *reg_ptr++ = 0;
-
+ *reg_ptr++ = 0;
+
/* offset = 16MB, address translation is enabled to allow byte swapping */
reg_val += 0x01000000;
}
#endif /* !DISABLE_PBM */
-#ifdef ENABLE_PCI_CSR_BAR
+#ifdef ENABLE_PCI_CSR_BAR
/* open if required access to Tsi108 CSRs from the PCI/X bus */
/* enable BAR0 on the PCI/X bus */
reg_val = in32(CFG_TSI108_CSR_BASE +
/*
* Finally enable PCI/X Bus Master and Memory Space access
*/
-
+
reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
reg_val |= 0x06;
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
* Ensure that Machine Check exception is enabled
* We need it to support PCI Bus probing (configuration reads)
*/
-
+
reg_val = mfmsr ();
mtmsr(reg_val | MSR_ME);
* thing done with regards to enabling diabling the cache.
* So this seems like a good place to print all this information
*/
-
+
printf ("CACHE: ");
switch (get_cpu_type()) {
case CPU_7447A:
u32 *p;
ulong clock;
int len;
-
+
clock = bd->bi_busfreq;
-
+
p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32 (clock);
static void program_mode(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks,
- ddr_cas_id_t *selected_cas,
- int *write_recovery);
+ ddr_cas_id_t *selected_cas,
+ int *write_recovery);
static void program_tr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
static void program_initplr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks,
- ddr_cas_id_t selected_cas,
+ ddr_cas_id_t selected_cas,
int write_recovery);
static unsigned long is_ecc_enabled(void);
static void program_ecc(unsigned long *dimm_populated,
modt3 = 0x00000000;
}
}
- } else {
+ } else {
codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
modt0 = 0x00000000;
modt1 = 0x00000000;
static void program_initplr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks,
- ddr_cas_id_t selected_cas,
+ ddr_cas_id_t selected_cas,
int write_recovery)
{
u32 cas = 0;
#endif /* CONFIG_405EP */
#if defined(CONFIG_440)
-#define function_prolog(func_name) .text; \
+#define function_prolog(func_name) .text; \
.align 2; \
.globl func_name; \
func_name:
-#define function_epilog(func_name) .type func_name,@function; \
+#define function_epilog(func_name) .type func_name,@function; \
.size func_name,.-func_name
/*----------------------------------------------------------------------------+
/*----------------------------------------------------------------------------+
| dcbz_area.
+----------------------------------------------------------------------------*/
- function_prolog(dcbz_area)
- rlwinm. r5,r4,0,27,31
- rlwinm r5,r4,27,5,31
- beq ..d_ra2
- addi r5,r5,0x0001
-..d_ra2:mtctr r5
-..d_ag2:dcbz r0,r3
- addi r3,r3,32
- bdnz ..d_ag2
- sync
- blr
- function_epilog(dcbz_area)
+ function_prolog(dcbz_area)
+ rlwinm. r5,r4,0,27,31
+ rlwinm r5,r4,27,5,31
+ beq ..d_ra2
+ addi r5,r5,0x0001
+..d_ra2:mtctr r5
+..d_ag2:dcbz r0,r3
+ addi r3,r3,32
+ bdnz ..d_ag2
+ sync
+ blr
+ function_epilog(dcbz_area)
/*----------------------------------------------------------------------------+
| dflush. Assume 32K at vector address is cachable.
+----------------------------------------------------------------------------*/
- function_prolog(dflush)
- mfmsr r9
- rlwinm r8,r9,0,15,13
- rlwinm r8,r8,0,17,15
- mtmsr r8
- addi r3,r0,0x0000
- mtspr dvlim,r3
- mfspr r3,ivpr
- addi r4,r0,1024
- mtctr r4
+ function_prolog(dflush)
+ mfmsr r9
+ rlwinm r8,r9,0,15,13
+ rlwinm r8,r8,0,17,15
+ mtmsr r8
+ addi r3,r0,0x0000
+ mtspr dvlim,r3
+ mfspr r3,ivpr
+ addi r4,r0,1024
+ mtctr r4
..dflush_loop:
- lwz r6,0x0(r3)
- addi r3,r3,32
- bdnz ..dflush_loop
- addi r3,r3,-32
- mtctr r4
-..ag: dcbf r0,r3
- addi r3,r3,-32
- bdnz ..ag
- sync
- mtmsr r9
- blr
- function_epilog(dflush)
+ lwz r6,0x0(r3)
+ addi r3,r3,32
+ bdnz ..dflush_loop
+ addi r3,r3,-32
+ mtctr r4
+..ag: dcbf r0,r3
+ addi r3,r3,-32
+ bdnz ..ag
+ sync
+ mtmsr r9
+ blr
+ function_epilog(dflush)
#endif /* CONFIG_440 */
CPU Core Frequency (MHz)
Bus Frequency
123456 100 133 167 200 Ratio
-
+
------
SW2=101100 500 667 833 1000 5x
SW2=100100 550 733 917 1100 5.5x
SW2[7-8]: Bus Protocol and CPU Reset Option
- 7
+ 7
-
SW2=0 System bus uses MPX bus protocol
SW2=1 System bus uses 60x bus protocol
- 8
+ 8
-
SW2=0 TSI108 can cause CPU reset
SW2=1 TSI108 can not cause CPU reset
SW3[1-8] system options
- 123
+ 123
---
SW3=xxx Connected to GPIO[0:2] on TSI108
- 4
+ 4
-
SW3=0 CPU boots from low half of flash
SW3=1 CPU boots from high half of flash
- 5
+ 5
-
SW3=0 SATA and slot2 connected to PCI bus
SW3=1 Only slot1 connected to PCI bus
- 6
+ 6
-
SW3=0 USB connected to PCI bus
SW3=1 USB disconnected from PCI bus
- 7
+ 7
-
SW3=0 Flash is write protected
SW3=1 Flash is NOT write protected
- 8
+ 8
-
SW3=0 CPU will boot from flash
SW3=1 CPU will boot from PromJet
Bus Frequency (MHz)
---
SW4=000 external clock
- SW4=011 system clock
+ SW4=011 system clock
SW4=100 133
SW4=101 166
SW4=110 200
others reserved
SW4[7-8]: PCI/PCI-X frequency control
- 7
+ 7
-
SW4=0 PCI/PCI-X bus operates normally
SW4=1 PCI bus forced to PCI-33 mode
- 8
+ 8
-
SW4=0 PCI-X mode at 133 MHz allowed
SW4=1 PCI-X mode limited to 100 MHz
-
/* Wait until operation completed */
do {
/* Read I2C operation status */
- temp =
- *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset +
- I2C_CNTRL2);
-
- if (0 ==
- (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START)))
- {
- if (0 ==
- (temp &
+ temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
+
+ if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
+ if (0 == (temp &
(I2C_CNTRL2_I2C_CFGERR |
I2C_CNTRL2_I2C_TO_ERR))
) {
/* Check for valid I2C address */
if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
while (len--) {
- op_status =
- i2c_read_byte(i2c_if, chip_addr, byte_addr++,
- buffer++);
+ op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
if (TSI108_I2C_SUCCESS != op_status) {
DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
/* Check if I2C operation is in progress */
temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
- if (0 ==
- (temp &
- (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
- {
+ if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
/* Place data into the I2C Tx Register */
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_TX_DATA) = (u32) * buffer;
/* Issue the write command (at this moment all other parameters
* are 0 (size = 1 byte, lane = 0)
*/
-
+
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_CNTRL2) = (I2C_CNTRL2_START);
/* Wait until operation completed */
do {
/* Read I2C operation status */
- temp =
- *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
- I2C_CNTRL2);
-
- if (0 ==
- (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
- {
- if (0 ==
- (temp &
+ temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
+
+ if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
+ if (0 == (temp &
(I2C_CNTRL2_I2C_CFGERR |
I2C_CNTRL2_I2C_TO_ERR))) {
op_status = TSI108_I2C_SUCCESS;
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
-#define CFG_PCI_MEMORY_SIZE 0x80000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
/* PCI Memory Space */
#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)
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