]> git.sur5r.net Git - u-boot/commitdiff
rockchip: clk: rk3288: limit gpll and cpll init to SPL build
authorHeiko Stübner <heiko@sntech.de>
Sat, 18 Feb 2017 18:46:22 +0000 (19:46 +0100)
committerSimon Glass <sjg@chromium.org>
Thu, 16 Mar 2017 22:03:44 +0000 (16:03 -0600)
The gpll and cpll init values are only used in rk_clk_init in the SPL
and therefore produce compile time warnings in regular uboot builds.
Fix that with an #ifdef.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
drivers/clk/rockchip/clk_rk3288.c

index d15504c3aaebda86250b56233d7871a8249bc061..78356766a7816a30475a12ed0ec280100fdd0e15 100644 (file)
@@ -131,8 +131,10 @@ enum {
 
 /* Keep divisors as low as possible to reduce jitter and power usage */
 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
+#ifdef CONFIG_SPL_BUILD
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
+#endif
 
 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
                         const struct pll_div *div)