N: Dr. Wolfgang Grandegger
E: wg@denx.de
-D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
+D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
W: www.denx.de
N: Peter Figuli
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
-#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
+#if defined(CONFIG_MUSENKI)
/* Why is this here, you ask? Try, just try setting 0x8000
* in PCIACR with CONFIG_WRITE_HALFWORD()
* this one was a stumper, and we are annoyed
CONFIG_READ_WORD(PICR2, val);
val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
-#ifndef CONFIG_PN62
val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
-#endif
CONFIG_WRITE_WORD(PICR2, val);
CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
* should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
* its not set, we define it to zero in this file
*/
-#if defined(CONFIG_CU824) || defined(CONFIG_PN62)
+#if defined(CONFIG_CU824)
CONFIG_WRITE_WORD(MCCR4,
(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pn62.o cmd_pn62.o misc.o
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <command.h>
-#include "pn62.h"
-
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Command led: controls the various LEDs 0..11 on the PN62 card.
- */
-int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
-{
- unsigned int number, function;
-
- if (argc != 3)
- return cmd_usage(cmdtp);
-
- number = simple_strtoul(argv[1], NULL, 10);
- if (number > PN62_LED_MAX)
- return 1;
-
- function = simple_strtoul(argv[2], NULL, 16);
- set_led(number, function);
- return 0;
-}
-U_BOOT_CMD(
- led , 3, 1, do_led,
- "set LED 0..11 on the PN62 board",
- "i fun"
- " - set 'i'th LED to function 'fun'"
-);
-
-/*
- * Command loadpci: loads a image over PCI.
- */
-#define CMD_MOVE_WINDOW 0x1
-#define CMD_BOOT_IMAGE 0x2
-
-int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *s;
- ulong addr = 0, count = 0;
- u32 off;
- int cmd, rcode = 0;
-
- /* pre-set load_addr */
- if ((s = getenv("loadaddr")) != NULL) {
- addr = simple_strtoul(s, NULL, 16);
- }
-
- switch (argc) {
- case 1:
- break;
- case 2:
- addr = simple_strtoul(argv[1], NULL, 16);
- break;
- default:
- return cmd_usage(cmdtp);
- }
-
- printf ("## Ready for image download ...\n");
-
- show_startup_phase(12);
-
- while (1) {
- /* Alive indicator */
- i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY);
-
- /* Toggle status LEDs */
- cmd = (count / 200) % 4; /* downscale */
- set_led(4, cmd == 0 ? LED_1 : LED_0);
- set_led(5, cmd == 1 ? LED_1 : LED_0);
- set_led(6, cmd == 2 ? LED_1 : LED_0);
- set_led(7, cmd == 3 ? LED_1 : LED_0);
- udelay(1000);
- count++;
-
- cmd = i2155x_read_scrapad(BOOT_CMD);
-
- if (cmd == BOOT_CMD_MOVE) {
- off = i2155x_read_scrapad(BOOT_DATA);
- off += addr;
- i2155x_set_bar_base(3, off);
- printf ("## BAR3 Addr moved = 0x%08x\n", off);
- i2155x_write_scrapad(BOOT_CMD, ~cmd);
- show_startup_phase(13);
- }
- else if (cmd == BOOT_CMD_BOOT) {
- set_led(4, LED_1);
- set_led(5, LED_1);
- set_led(6, LED_1);
- set_led(7, LED_1);
-
- i2155x_write_scrapad(BOOT_CMD, ~cmd);
- show_startup_phase(14);
- break;
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- printf("\nAbort\n");
- return 0;
- }
-
- }
-
- /* Repoint to the default shared memory */
- i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
-
- load_addr = addr;
- printf ("## Start Addr = 0x%08lx\n", addr);
-
- show_startup_phase(15);
-
- /* Loading ok, check if we should attempt an auto-start */
- if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
- char *local_args[2];
- local_args[0] = argv[0];
- local_args[1] = NULL;
-
- printf ("Automatic boot of image at addr 0x%08lX ...\n",
- load_addr);
- rcode = do_bootm (cmdtp, 0, 1, local_args);
- }
-
- return rcode;
-}
-
-U_BOOT_CMD(
- loadpci, 2, 1, do_loadpci,
- "load binary file over PCI",
- "[addr]\n"
- " - load binary file over PCI to address 'addr'"
-);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#include "pn62.h"
-
-typedef struct {
- pci_dev_t devno;
- volatile u32 *csr;
-
-} i2155x_t;
-
-static i2155x_t i2155x = { 0, NULL };
-
-static struct pci_device_id i2155x_ids[] = {
- { 0x1011, 0x0046 }, /* i21554 */
- { 0x8086, 0xb555 } /* i21555 */
-};
-
-int i2155x_init(void)
-{
- pci_dev_t devno;
- u32 val;
- int i;
-
- /*
- * Find the Intel bridge.
- */
- if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) {
- printf("Error: Intel bridge 2155x not found!\n");
- return -1;
- }
- i2155x.devno = devno;
-
- /*
- * Get auto-configured base address for CSR access.
- */
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val);
- if (val & PCI_BASE_ADDRESS_SPACE_IO) {
- val &= PCI_BASE_ADDRESS_IO_MASK;
- i2155x.csr = (volatile u32 *)(_IO_BASE + val);
- } else {
- val &= PCI_BASE_ADDRESS_MEM_MASK;
- i2155x.csr = (volatile u32 *)val;
- }
-
- /*
- * Translate downstream memory 2 (bar3) to base of shared memory.
- */
- i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
-
- /*
- * Enable memory space, I/O space and bus master bits
- * in both Primary and Secondary command registers.
- */
- val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO;
- pci_write_config_word(devno, 0x44, val);
- pci_write_config_word(devno, 0x04, val);
-
- /*
- * Clear scratchpad registers.
- */
- for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) {
- i2155x_write_scrapad(i, 0x0);
- }
-
- /*
- * Set interrupt line for Linux.
- */
- pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3);
-
- return 0;
-}
-
-/*
- * Access the Scratchpad registers 0..7 of the Intel bridge.
- */
-void i2155x_write_scrapad(int idx, u32 val)
-{
- if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
- out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val);
- else
- printf("i2155x_write_scrapad: invalid index\n");
-}
-
-u32 i2155x_read_scrapad(int idx)
-{
- if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
- return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx);
- else
- printf("i2155x_read_scrapad: invalid index\n");
- return -1;
-}
-
-void i2155x_set_bar_base(int bar, u32 base)
-{
- if (bar >= 2 && bar <= 4) {
- pci_write_config_dword(i2155x.devno,
- I2155X_BAR2_BASE + (bar - 2) * 4,
- base);
- }
-}
-
-/*
- * Read Vital Product Data (VPD) from the Serial EPROM attached
- * to the Intel bridge.
- */
-int i2155x_read_vpd(int offset, int size, unsigned char *data)
-{
- int i, n;
- u16 val16;
-
- for (i = 0; i < size; i++) {
- pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR,
- offset + i - I2155X_VPD_START);
- for (n = 10000; n > 0; n--) {
- pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16);
- if ((val16 & 0x8000) != 0) /* wait for completion */
- break;
- udelay(100);
- }
- if (n == 0) {
- printf("i2155x_read_vpd: TIMEOUT\n");
- return -1;
- }
-
- pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]);
- }
-
- return i;
-}
-
-static struct pci_device_id am79c95x_ids [] = {
- { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
- { }
-};
-
-
-/*
- * Initialize the AMD ethernet controllers.
- */
-int am79c95x_init(void)
-{
- pci_dev_t devno;
- int i;
-
- /*
- * Set interrupt line for Linux.
- */
- for (i = 0; i < 2; i++) {
- if ((devno = pci_find_devices(am79c95x_ids, i)) < 0)
- break;
- pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i);
- }
- if (i < 2)
- printf("Error: Only %d AMD Ethernet Controller found!\n", i);
-
- return 0;
-}
-
-
-void set_led(unsigned int number, unsigned int function)
-{
- volatile u8 *addr;
-
- if ((number >= 0) && (number < PN62_LED_MAX) &&
- (function >= 0) && (function <= LED_LAST_FUNCTION)) {
- addr = (volatile u8 *)(PN62_LED_BASE + number * 8);
- out_8(addr, function&0xff);
- }
-}
-
-/*
- * Show fatal error indicated by Kinght Rider(tm) effect
- * in LEDS 0-7. LEDS 8-11 contain 4 bit error code.
- * Note: this function will not terminate.
- */
-void fatal_error(unsigned int error_code)
-{
- int i, d;
-
- for (i = 0; i < 12; i++) {
- set_led(i, LED_0);
- }
-
- /*
- * Write error code.
- */
- set_led(8, (error_code & 0x01) ? LED_1 : LED_0);
- set_led(9, (error_code & 0x02) ? LED_1 : LED_0);
- set_led(10, (error_code & 0x04) ? LED_1 : LED_0);
- set_led(11, (error_code & 0x08) ? LED_1 : LED_0);
-
- /*
- * Yay - Knight Rider effect!
- */
- while(1) {
- unsigned int delay = 2000;
-
- for (i = 0; i < 8; i++) {
- set_led(i, LED_1);
- for (d = 0; d < delay; d++);
- set_led(i, LED_0);
- }
-
- for (i = 7; i > 0; i--) {
- set_led(i, LED_1);
- for (d = 0; d < delay; d++);
- set_led(i, LED_0);
- }
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <net.h>
-#include <pci.h>
-#include <netdev.h>
-
-#include "pn62.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int get_serial_number (char *string, int size);
-static void get_mac_address(int id, u8 *mac);
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress (int phase)
-{
- /*
- * Show phases of the bootm command on the front panel
- * LEDs and the scratchpad register #3 as well. We use
- * blinking LEDs for logical "1".
- */
- if (phase > 0) {
- set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0);
- set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0);
- set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0);
- set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0);
- }
- i2155x_write_scrapad (BOOT_STATUS, phase);
- if (phase < 0)
- i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
-}
-#endif
-
-void show_startup_phase (int phase)
-{
- /*
- * Show the phase of U-Boot startup on the front panel
- * LEDs and the scratchpad register #3 as well.
- */
- if (phase > 0) {
- set_led (8, (phase & 0x1) ? LED_1 : LED_0);
- set_led (9, (phase & 0x2) ? LED_1 : LED_0);
- set_led (10, (phase & 0x4) ? LED_1 : LED_0);
- set_led (11, (phase & 0x8) ? LED_1 : LED_0);
- }
- i2155x_write_scrapad (BOOT_STATUS, phase);
- if (phase < 0)
- i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
-}
-
-int checkboard (void)
-{
- show_startup_phase (1);
- puts ("Board: PN62\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- show_startup_phase (2);
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg (MEAR1);
- emear1 = mpc824x_mpc107_getreg (EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg (MEAR1, mear1);
- mpc824x_mpc107_setreg (EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices. We rely on auto-configuration.
- */
-#ifndef CONFIG_PCI_PNP
-#error "CONFIG_PCI_PNP is not defined, please correct!"
-#endif
-
-struct pci_controller hose = {
-};
-
-void pci_init_board (void)
-{
- show_startup_phase (4);
- pci_mpc824x_init (&hose);
-
- show_startup_phase (5);
- i2155x_init ();
- show_startup_phase (6);
- am79c95x_init ();
- show_startup_phase (7);
-}
-
-int misc_init_r (void)
-{
- char str[20];
- u8 mac[6];
-
- show_startup_phase (8);
- /*
- * Get serial number and ethernet addresses if not already defined
- * and update the board info structure and the environment.
- */
- if (getenv ("serial#") == NULL &&
- get_serial_number (str, strlen (str)) > 0) {
- setenv ("serial#", str);
- }
- show_startup_phase (9);
-
- if (!eth_getenv_enetaddr("ethaddr", mac)) {
- get_mac_address(0, mac);
- eth_setenv_enetaddr("ethaddr", mac);
- }
- show_startup_phase (10);
-
-#ifdef CONFIG_HAS_ETH1
- if (!eth_getenv_enetaddr("eth1addr", mac)) {
- get_mac_address(1, mac);
- eth_setenv_enetaddr("eth1addr", mac);
- }
-#endif /* CONFIG_HAS_ETH1 */
- show_startup_phase (11);
-
- /* Tell everybody that U-Boot is up and runnig */
- i2155x_write_scrapad (0, 0x12345678);
- return (0);
-}
-
-static int get_serial_number (char *string, int size)
-{
- int i;
- char c;
-
- if (size < I2155X_VPD_SN_SIZE)
- size = I2155X_VPD_SN_SIZE;
- for (i = 0; i < (size - 1); i++) {
- i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c);
- if (c == '\0')
- break;
- string[i] = c;
- }
- string[i] = '\0'; /* make sure it's terminated */
-
- return i;
-}
-
-static void get_mac_address(int id, u8 *mac)
-{
- i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PN62_H_
-#define _PN62_H_
-
-/*
- * Definitions for the Intel Bridge 21554 or 21555.
- */
-#define I2155X_VPD_ADDR 0xe6
-#define I2155X_VPD_DATA 0xe8
-
-#define I2155X_VPD_START 0x80
-#define I2155X_VPD_SN_START 0x80
-#define I2155X_VPD_SN_SIZE 0x10
-#define I2155X_VPD_MAC0_START 0x90
-#define I2155X_VPD_MAC1_START 0x96
-
-#define I2155X_SCRAPAD_ADDR 0xa8
-#define I2155X_SCRAPAD_MAX 8
-
-#define I2155X_BAR2_BASE 0x98
-#define I2155X_BAR3_BASE 0x9c
-#define I2155X_BAR4_BASE 0xa0
-
-#define I2155X_BAR2_SETUP 0xb0
-#define I2155X_BAR3_SETUP 0xb4
-#define I2155X_BAR4_SETUP 0xb8
-
-/*
- * Interrupt request numbers
- */
-#define PN62_IRQ_HOST 0x0
-#define PN62_IRQ_PLX9054 0x1
-#define PN62_IRQ_ETH0 0x2
-#define PN62_IRQ_ETH1 0x3
-#define PN62_IRQ_COM1 0x4
-#define PN62_IRQ_COM2 0x4
-
-/*
- * Miscellaneous definitons.
- */
-#define PN62_SMEM_DEFAULT 0x1f00000
-
-/*
- * Definitions for boot protocol using Scratchpad registers.
- */
-#define BOOT_DONE 0
-#define BOOT_DONE_CLEAR 0x00dead00
-#define BOOT_DONE_ERROR 0xbad0dead
-#define BOOT_DONE_U_BOOT 0x12345678
-#define BOOT_DONE_LINUX 0x87654321
-#define BOOT_CMD 1
-#define BOOT_CMD_MOVE 0x1
-#define BOOT_CMD_BOOT 0x2
-#define BOOT_DATA 2
-#define BOOT_PROTO 3
-#define BOOT_PROTO_READY 0x23456789
-#define BOOT_PROTO_CLEAR 0x00000000
-#define BOOT_STATUS 4
-
-/*
- * LED Definitions:
- */
-#define PN62_LED_BASE 0xff800300
-#define PN62_LED_MAX 12
-
-/*
- * LED0 - 7 mounted on top of board, D1 - D8
- * LED8 - 11 upper four LEDs on the front panel of the board.
- */
-#define LED_0 0x00 /* OFF */
-#define LED_1 0x01 /* ON */
-#define LED_SLOW_CLOCK 0x02 /* SLOW 1Hz ish */
-#define LED_nSLOW_CLOCK 0x03 /* inverse of above */
-#define LED_WATCHDOG_OUT 0x06 /* Reset Watchdog level */
-#define LED_WATCHDOG_CLOCK 0x07 /* clock to watchdog */
-
-/*
- * LED's currently setup in AMD79C973 device as the following:
- * LED0 100Mbit
- * LED1 LNKSE
- * LED2 TX Activity
- * LED3 RX Activity
- */
-#define LED_E0_LED0 0x08 /* Ethernet Port 0 LED 0 */
-#define LED_E0_LED1 0x09 /* Ethernet Port 0 LED 1 */
-#define LED_E0_LED2 0x0A /* Ethernet Port 0 LED 2 */
-#define LED_E0_LED3 0x0B /* Ethernet Port 0 LED 3 */
-#define LED_E1_LED0 0x0C /* Ethernet Port 1 LED 0 */
-#define LED_E1_LED1 0x0D /* Ethernet Port 1 LED 1 */
-#define LED_E1_LED2 0x0E /* Ethernet Port 1 LED 2 */
-#define LED_E1_LED3 0x0F /* Ethernet Port 1 LED 3 */
-#define LED_STROBE0 0x10 /* Processor Strobe 0 */
-#define LED_STROBE1 0x11 /* Processor Strobe 1 */
-#define LED_STROBE2 0x12 /* Processor Strobe 2 */
-#define LED_STROBE3 0x13 /* Processor Strobe 3 */
-#define LED_STROBE4 0x14 /* Processor Strobe 4 */
-#define LED_STROBE5 0x15 /* Processor Strobe 5 */
-#define LED_STROBE6 0x16 /* Processor Strobe 6 */
-#define LED_STROBE7 0x17 /* Processor Strobe 7 */
-#define LED_HOST_STROBE0 0x18 /* Host strobe 0 */
-#define LED_HOST_STROBE1 0x19 /* Host strobe 1 */
-#define LED_HOST_STROBE2 0x1A /* Host strobe 2 */
-#define LED_HOST_STROBE3 0x1B /* Host strobe 3 */
-#define LED_HOST_STROBE4 0x1C /* Host strobe 4 */
-#define LED_HOST_STROBE5 0x1D /* Host strobe 5 */
-#define LED_HOST_STROBE6 0x1E /* Host strobe 6 */
-#define LED_HOST_STROBE7 0x1F /* Host strobe 7 */
-#define LED_MPC_INT0 0x20 /* MPC8240 INT 0 */
-#define LED_MPC_INT1 0x21 /* MPC8240 INT 1 */
-#define LED_MPC_INT2 0x22 /* MPC8240 INT 2 */
-#define LED_MPC_INT3 0x23 /* MPC8240 INT 3 */
-#define LED_MPC_INT4 0x24 /* MPC8240 INT 4 */
-#define LED_UART0_CS 0x25 /* UART 0 Chip Select */
-#define LED_UART1_CS 0x26 /* UART 1 Chip Select */
-#define LED_SRAM_CS 0x27 /* SRAM Chip Select */
-#define LED_SRAM_WR 0x28 /* SRAM WR Signal */
-#define LED_SRAM_RD 0x29 /* SRAM RD Signal */
-#define LED_MPC_RCS0 0x2A /* MPC8240 RCS0 Signal */
-#define LED_S_PCI_FRAME 0x2B /* Secondary PCI Frame Signal */
-#define LED_MPC_CS0 0x2C /* MPC8240 CS0 Signal */
-#define LED_HOST_INT 0x2D /* MPC8240 to Host Interrupt signal */
-#define LED_LAST_FUNCTION LED_HOST_INT /* last function */
-
-/*
- * Forward declarations
- */
-int i2155x_init (void);
-void i2155x_write_scrapad(int idx, u32 val);
-u32 i2155x_read_scrapad (int idx);
-void i2155x_set_bar_base (int bar, u32 addr);
-int i2155x_read_vpd (int offset, int size, unsigned char *data);
-
-int am79c95x_init (void);
-
-void set_led (unsigned int number, unsigned int function);
-void fatal_error (unsigned int error_code);
-void show_startup_phase (int phase);
-
-
-#endif /* _PN62_H_ */
Active powerpc mpc824x - - linkstation linkstation_HGLAN linkstation:HGLAN=1 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
Active powerpc mpc824x - - mvblue MVBLUE - -
-Active powerpc mpc824x - - pn62 PN62 - Wolfgang Grandegger <wg@denx.de>
Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
pdnb3 arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
scpu arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>
/* Switch pcnet to 32bit mode */
pcnet_write_bcr(dev, 20, 2);
-#ifdef CONFIG_PN62
- /* Setup LED registers */
- val = pcnet_read_bcr(dev, 2) | 0x1000;
- pcnet_write_bcr(dev, 2, val); /* enable LEDPE */
- pcnet_write_bcr(dev, 4, 0x5080); /* 100MBit */
- pcnet_write_bcr(dev, 5, 0x40c0); /* LNKSE */
- pcnet_write_bcr(dev, 6, 0x4090); /* TX Activity */
- pcnet_write_bcr(dev, 7, 0x4084); /* RX Activity */
-#endif
-
/* Set/reset autoselect bit */
val = pcnet_read_bcr(dev, 2) & ~2;
val |= 2;
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X 1
-#define CONFIG_MPC8240 1
-#define CONFIG_PN62 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_CONS_INDEX 1
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_BSP
-
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_SOURCE
-
-
-#define CONFIG_BAUDRATE 19200 /* console baudrate */
-
-#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_SERVERIP 10.0.0.201
-#define CONFIG_IPADDR 10.0.0.200
-#define CONFIG_ROOTPATH "/opt/eldk/ppc_82xx"
-#define CONFIG_NETMASK 255.255.255.0
-#undef CONFIG_BOOTARGS
-#if 0
-/* Boot Linux with NFS root filesystem */
-#define CONFIG_BOOTCOMMAND \
- "setenv verify y;" \
- "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
- "loadp 100000; bootm"
- /* "tftpboot 100000 uImage; bootm" */
-#else
-/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
-#define CONFIG_BOOTCOMMAND \
- "setenv verify n;" \
- "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
- "root=/dev/ram rw " \
- "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
- "loadp 200000; bootm"
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
-
-#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* we need Plug 'n Play */
-#if 0
-#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */
-#endif
-
-/*
- * Networking stuff
- */
-
-#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */
-#define CONFIG_PCNET_79C973
-
-#define _IO_BASE 0xfe000000 /* points to PCI I/O space */
-
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-#define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */
-
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
-
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */
-
-/*
- * Serial port configuration
- */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK 1843200
-
-#define CONFIG_SYS_NS16550_COM1 0xff800008
-#define CONFIG_SYS_NS16550_COM2 0xff800000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
-
-#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
-
-/* MCCR1 */
-#define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */
-
-/* MCCR2 */
-#define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */
-#define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */
-#define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */
-
-/* MCCR3 */
-#define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */
-#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 3 /* data latency from read command */
-
-/* MCCR4 */
-#define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-
-/* Memory bank settings:
- *
- * only bits 20-29 are actually used from these vales to set the
- * start/qend address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x00000000
-#define CONFIG_SYS_BANK1_END 0x00000000
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x00000000
-#define CONFIG_SYS_BANK2_END 0x00000000
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x00000000
-#define CONFIG_SYS_BANK3_END 0x00000000
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- * are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-/* PCI memory space */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#endif /* __CONFIG_H */
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