*/
/*
- * Designware ethernet IP driver for u-boot
+ * Designware ethernet IP driver for U-Boot
*/
#include <common.h>
+#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/compiler.h>
udelay(10);
};
- return -1;
+ return -ETIMEDOUT;
}
static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
struct eth_mac_regs *mac_p = bus->priv;
ulong start;
u16 miiaddr;
- int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
+ int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
writel(val, &mac_p->miidata);
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
return ret;
}
-static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p)
+static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
{
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate MDIO bus\n");
- return -1;
+ return -ENOMEM;
}
bus->read = dw_mdio_read;
bus->write = dw_mdio_write;
- sprintf(bus->name, name);
+ snprintf(bus->name, sizeof(bus->name), name);
bus->priv = (void *)mac_regs_p;
return mdio_register(bus);
}
-static void tx_descs_init(struct eth_device *dev)
+static void tx_descs_init(struct dw_eth_dev *priv)
{
- struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
char *txbuffs = &priv->txbuffs[0];
priv->tx_currdescnum = 0;
}
-static void rx_descs_init(struct eth_device *dev)
+static void rx_descs_init(struct dw_eth_dev *priv)
{
- struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
char *rxbuffs = &priv->rxbuffs[0];
priv->rx_currdescnum = 0;
}
-static int dw_write_hwaddr(struct eth_device *dev)
+static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
{
- struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 macid_lo, macid_hi;
- u8 *mac_id = &dev->enetaddr[0];
macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
(mac_id[3] << 24);
(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}
-static void dw_eth_halt(struct eth_device *dev)
+static void _dw_eth_halt(struct dw_eth_dev *priv)
{
- struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
phy_shutdown(priv->phydev);
}
-static int dw_eth_init(struct eth_device *dev, bd_t *bis)
+static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
{
- struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
unsigned int start;
+ int ret;
writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
while (readl(&dma_p->busmode) & DMAMAC_SRST) {
if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
printf("DMA reset timeout\n");
- return -1;
+ return -ETIMEDOUT;
}
mdelay(100);
/* Soft reset above clears HW address registers.
* So we have to set it here once again */
- dw_write_hwaddr(dev);
+ _dw_write_hwaddr(priv, enetaddr);
- rx_descs_init(dev);
- tx_descs_init(dev);
+ rx_descs_init(priv);
+ tx_descs_init(priv);
writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
#endif
/* Start up the PHY */
- if (phy_startup(priv->phydev)) {
+ ret = phy_startup(priv->phydev);
+ if (ret) {
printf("Could not initialize PHY %s\n",
priv->phydev->dev->name);
- return -1;
+ return ret;
}
dw_adjust_link(mac_p, priv->phydev);
if (!priv->phydev->link)
- return -1;
+ return -EIO;
writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
return 0;
}
-static int dw_eth_send(struct eth_device *dev, void *packet, int length)
+static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
{
- struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 desc_num = priv->tx_currdescnum;
struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
/* Check if the descriptor is owned by CPU */
if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
printf("CPU not owner of tx frame\n");
- return -1;
+ return -EPERM;
}
memcpy(desc_p->dmamac_addr, packet, length);
return 0;
}
-static int dw_eth_recv(struct eth_device *dev)
+static int _dw_eth_recv(struct dw_eth_dev *priv)
{
- struct dw_eth_dev *priv = dev->priv;
u32 status, desc_num = priv->rx_currdescnum;
struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
int length = 0;
return length;
}
-static int dw_phy_init(struct eth_device *dev)
+static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
- struct dw_eth_dev *priv = dev->priv;
struct phy_device *phydev;
int mask = 0xffffffff;
phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
if (!phydev)
- return -1;
+ return -ENODEV;
phy_connect_dev(phydev, dev);
priv->phydev = phydev;
phy_config(phydev);
- return 1;
+ return 0;
+}
+
+static int dw_eth_init(struct eth_device *dev, bd_t *bis)
+{
+ return _dw_eth_init(dev->priv, dev->enetaddr);
+}
+
+static int dw_eth_send(struct eth_device *dev, void *packet, int length)
+{
+ return _dw_eth_send(dev->priv, packet, length);
+}
+
+static int dw_eth_recv(struct eth_device *dev)
+{
+ return _dw_eth_recv(dev->priv);
+}
+
+static void dw_eth_halt(struct eth_device *dev)
+{
+ return _dw_eth_halt(dev->priv);
+}
+
+static int dw_write_hwaddr(struct eth_device *dev)
+{
+ return _dw_write_hwaddr(dev->priv, dev->enetaddr);
}
int designware_initialize(ulong base_addr, u32 interface)
dw_mdio_init(dev->name, priv->mac_regs_p);
priv->bus = miiphy_get_dev_by_name(dev->name);
- return dw_phy_init(dev);
+ return dw_phy_init(priv, dev);
}