]> git.sur5r.net Git - u-boot/commitdiff
x86: ivybridge: Move northbridge init into the probe() method
authorSimon Glass <sjg@chromium.org>
Sun, 17 Jan 2016 23:11:16 +0000 (16:11 -0700)
committerBin Meng <bmeng.cn@gmail.com>
Sun, 24 Jan 2016 04:08:16 +0000 (12:08 +0800)
Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
arch/x86/cpu/ivybridge/cpu.c
arch/x86/cpu/ivybridge/early_init.c

index 2a15fc02205c7562bc6138a6f077f2db2363bd1a..f32b4a18e12d730f0ebc1c2353e3132776066fe6 100644 (file)
@@ -243,6 +243,8 @@ int print_cpuinfo(void)
        }
 
        /* Early chipset init required before RAM init can work */
+       uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+
        ret = uclass_first_device(UCLASS_PCH, &dev);
        if (ret)
                return ret;
index 945ae2dfcd89604de78b5c5fdcc4917ca1ef9ac5..c629f5b9ca9ff35b38fe0b5639ce8d3bd5f5bad2 100644 (file)
@@ -123,20 +123,6 @@ void sandybridge_early_init(int chipset_type)
        pci_dev_t pch_dev = PCH_DEV;
        pci_dev_t video_dev = PCH_VIDEO_DEV;
        pci_dev_t lpc_dev = PCH_LPC_DEV;
-       u32 capid0_a;
-       u8 reg8;
-
-       /* Device ID Override Enable should be done very early */
-       capid0_a = x86_pci_read_config32(pch_dev, 0xe4);
-       if (capid0_a & (1 << 10)) {
-               reg8 = x86_pci_read_config8(pch_dev, 0xf3);
-               reg8 &= ~7; /* Clear 2:0 */
-
-               if (chipset_type == SANDYBRIDGE_MOBILE)
-                       reg8 |= 1; /* Set bit 0 */
-
-               x86_pci_write_config8(pch_dev, 0xf3, reg8);
-       }
 
        /* Setup all BARs required for early PCIe and raminit */
        sandybridge_setup_bars(pch_dev, lpc_dev);
@@ -149,6 +135,25 @@ void sandybridge_early_init(int chipset_type)
 
 static int bd82x6x_northbridge_probe(struct udevice *dev)
 {
+       const int chipset_type = SANDYBRIDGE_MOBILE;
+       u32 capid0_a;
+       u8 reg8;
+
+       if (gd->flags & GD_FLG_RELOC)
+               return 0;
+
+       /* Device ID Override Enable should be done very early */
+       dm_pci_read_config32(dev, 0xe4, &capid0_a);
+       if (capid0_a & (1 << 10)) {
+               dm_pci_read_config8(dev, 0xf3, &reg8);
+               reg8 &= ~7; /* Clear 2:0 */
+
+               if (chipset_type == SANDYBRIDGE_MOBILE)
+                       reg8 |= 1; /* Set bit 0 */
+
+               dm_pci_write_config8(dev, 0xf3, reg8);
+       }
+
        return 0;
 }