* Patch by Rune Torgersen, 17 Sep 2003:
- Fixes for MPC8266 default config
+ - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
* Patches by Jon Diekema, 17 Sep 2003:
- update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
sda10 = sdam + 2;
#else
- sdam = cols - 6;
+ sdam = cols + banks - 8;
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
sda10 = sdam;
#endif
printf("SDRAM configuration read from SPD\n");
printf("\tSize per side = %dMB\n", sdram_size >> 20);
printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
- printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency);
+ printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ printf(", Using Bank Based Interleave\n");
+#else
+ printf(", Using Page Based Interleave\n");
+#endif
printf("\tTotal size: ");
+ /* this delay only needed for original 16MB DIMM...
+ * Not needed for any other memory configuration */
+ if ((sdram_size * chipselects) == (16 *1024 *1024))
+ udelay (250000);
return (sdram_size * chipselects);
/*return (16 * 1024 * 1024);*/
}
pci_mpc8250_init(&hose);
}
#endif
+
/* 28.9 - (1-2): ioports have been set up already */
#if defined(CONFIG_HYMOD)
+ /*
+ * Attention: this is board-specific
+ * 0, FCC1
+ * 1, FCC2
+ * 2, FCC3
+ */
+# define FCC_START_LOOP 0
+# define FCC_END_LOOP 2
+
/*
* Attention: this is board-specific
* - FCC1 Rx-CLK is CLK10
immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
+#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng)
+ /*
+ * Attention: this is board-specific
+ * 1, FCC2
+ */
+# define FCC_START_LOOP 1
+# define FCC_END_LOOP 1
+
+ /*
+ * Attention: this is board-specific
+ * - FCC2 Rx-CLK is CLK13
+ * - FCC2 Tx-CLK is CLK14
+ */
+
+ /* 28.9 - (3): connect FCC's tx and rx clocks */
+ immr->im_cpmux.cmx_uar = 0;
+ immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
#else
#error "eth_loopback_test not supported on your board"
#endif
puts ("Initialise FCC channels:");
- for (c = 0; c < 3; c++) {
+ for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
elbt_chan *ecp = &elbt_chans[c];
volatile fcc_t *fcp = &immr->im_fcc[c];
volatile fcc_enet_t *fpp;
do {
nclosed = 0;
- for (c = 0; c < 3; c++) {
+ for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
volatile fcc_t *fcp = &immr->im_fcc[c];
elbt_chan *ecp = &elbt_chans[c];
int i;
}
}
- } while (nclosed < 3);
+ } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1));
runtime = get_timer (runtime);
if (runtime <= ELBT_CLSWAIT) {
* now print stats
*/
- for (c = 0; c < 3; c++) {
+ for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
elbt_chan *ecp = &elbt_chans[c];
uint rxpps, txpps, nerr;
}
puts ("Receive Error Counts:\n");
- for (c = 0; c < 3; c++)
+ for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
bases[c] = (uchar *)&elbt_chans[c].rxeacc;
print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
puts ("\nTransmit Error Counts:\n");
- for (c = 0; c < 3; c++)
+ for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
bases[c] = (uchar *)&elbt_chans[c].txeacc;
print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
puts ("\nRMON(-like) Counters:\n");
- for (c = 0; c < 3; c++)
+ for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
print_desc (epram_descs, epram_ndesc, bases, 3);
}
#define CFG_MPTPR 0x00001900
#define CFG_PSRT 0x00000021
-#define CFG_RESET_ADDRESS 0x04400000
+/* This address must not exist */
+#define CFG_RESET_ADDRESS 0xFCFFFF00
/* PCI Memory map (if different from default map */
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
/*----------------------------------------------------------------------------+
|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
+| This source code has been made available to you by IBM on an AS-IS
+| basis. Anyone receiving this source is licensed under IBM
+| copyrights to use it in any way he or she deems fit, including
+| copying it, modifying it, compiling it, and redistributing it either
+| with or without modifications. No license under IBM patents or
+| patent applications is to be implied by the copyright license.
|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
+| Any user of this software should understand that IBM cannot provide
+| technical support for this software and will not be responsible for
+| any consequences resulting from the use of this software.
|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
+| Any person who transfers this source code or any derivative work
+| must include the IBM copyright notice, this paragraph, and the
+| preceding two paragraphs in the transferred software.
|
-| COPYRIGHT I B M CORPORATION 1999
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+| COPYRIGHT I B M CORPORATION 1999
+| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
|
-| File Name: miiphy.h
+| File Name: miiphy.h
|
-| Function: Include file defining PHY registers.
+| Function: Include file defining PHY registers.
|
-| Author: Mark Wisner
+| Author: Mark Wisner
|
| Change Activity-
|
-| Date Description of Change BY
-| --------- --------------------- ---
-| 04-May-99 Created MKW
-| 07-Jul-99 Added full duplex support MKW
-| 08-Sep-01 Tweaks gvb
+| Date Description of Change BY
+| --------- --------------------- ---
+| 04-May-99 Created MKW
+| 07-Jul-99 Added full duplex support MKW
+| 08-Sep-01 Tweaks gvb
|
+----------------------------------------------------------------------------*/
#ifndef _miiphy_h_
/* phy seed setup */
-#define AUTO 99
-#define _100BASET 100
-#define _10BASET 10
-#define HALF 22
-#define FULL 44
+#define AUTO 99
+#define _100BASET 100
+#define _10BASET 10
+#define HALF 22
+#define FULL 44
/* phy register offsets */
-#define PHY_BMCR 0x00
+#define PHY_BMCR 0x00
#define PHY_BMSR 0x01
-#define PHY_PHYIDR1 0x02
-#define PHY_PHYIDR2 0x03
+#define PHY_PHYIDR1 0x02
+#define PHY_PHYIDR2 0x03
#define PHY_ANAR 0x04
-#define PHY_ANLPAR 0x05
+#define PHY_ANLPAR 0x05
#define PHY_ANER 0x06
-#define PHY_ANNPTR 0x07
-#define PHY_PHYSTS 0x10
-#define PHY_MIPSCR 0x11
-#define PHY_MIPGSR 0x12
-#define PHY_DCR 0x13
+#define PHY_ANNPTR 0x07
+#define PHY_PHYSTS 0x10
+#define PHY_MIPSCR 0x11
+#define PHY_MIPGSR 0x12
+#define PHY_DCR 0x13
#define PHY_FCSCR 0x14
#define PHY_RECR 0x15
#define PHY_PCSR 0x16
-#define PHY_LBR 0x17
-#define PHY_10BTSCR 0x18
-#define PHY_PHYCTRL 0x19
+#define PHY_LBR 0x17
+#define PHY_10BTSCR 0x18
+#define PHY_PHYCTRL 0x19
/* PHY BMCR */
-#define PHY_BMCR_RESET 0x8000
-#define PHY_BMCR_LOOP 0x4000
+#define PHY_BMCR_RESET 0x8000
+#define PHY_BMCR_LOOP 0x4000
#define PHY_BMCR_100MB 0x2000
#define PHY_BMCR_AUTON 0x1000
#define PHY_BMCR_POWD 0x0800
/*phy ANLPAR */
#define PHY_ANLPAR_NP 0x8000
#define PHY_ANLPAR_ACK 0x4000
-#define PHY_ANLPAR_RF 0x2000
-#define PHY_ANLPAR_T4 0x0200
-#define PHY_ANLPAR_TXFD 0x0100
-#define PHY_ANLPAR_TX 0x0080
+#define PHY_ANLPAR_RF 0x2000
+#define PHY_ANLPAR_T4 0x0200
+#define PHY_ANLPAR_TXFD 0x0100
+#define PHY_ANLPAR_TX 0x0080
#define PHY_ANLPAR_10FD 0x0040
-#define PHY_ANLPAR_10 0x0020
-#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
+#define PHY_ANLPAR_10 0x0020
+#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
#endif
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