out:
return pll_out;
}
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
- printf("Cores: ARM %d MHz",
- clk_get(DAVINCI_ARM_CLKID) / 1000000);
- printf("\nDDR: %d MHz\n",
- /* DDR PHY uses an x2 input clock */
- clk_get(0x10001) / 1000000);
- return 0;
-}
-#endif
#else /* CONFIG_SOC_DA8XX */
-#ifdef CONFIG_DISPLAY_CPUINFO
-
static unsigned pll_div(volatile void *pllbase, unsigned offset)
{
u32 div;
return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
}
-int print_cpuinfo(void)
-{
- /* REVISIT fetch and display CPU ID and revision information
- * too ... that will matter as more revisions appear.
- */
-#if defined(CONFIG_SOC_DM365)
- printf("Cores: ARM %d MHz",
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
-#else
- printf("Cores: ARM %d MHz",
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
-#endif
-
-#ifdef DSP_PLLDIV
- printf(", DSP %d MHz",
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
-#endif
-
- printf("\nDDR: %d MHz\n",
- /* DDR PHY uses an x2 input clock */
-#if defined(CONFIG_SOC_DM365)
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
- / 2);
-#else
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
- / 2);
-#endif
- return 0;
-}
-
#ifdef DAVINCI_DM6467EVM
unsigned int davinci_arm_clk_get()
{
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
}
#endif
-#endif /* CONFIG_DISPLAY_CPUINFO */
#endif /* !CONFIG_SOC_DA8XX */
/*
#define CONFIG_POST CONFIG_SYS_POST_MEMORY
#define _POST_WORD_ADDR 0x0
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
/* Spectrum Digital TMS320DM6467T EVM board */
#define DAVINCI_DM6467EVM
#define DAVINCI_DM6467TEVM
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_NAND_SMALLPAGE
/* Spectrum Digital TMS320DM6467 EVM board */
#define DAVINCI_DM6467EVM
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_NAND_SMALLPAGE
#define DV_EVM
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NAND
-#define CONFIG_DISPLAY_CPUINFO
/*===================*/
/* SoC Configuration */
/*===================*/
#define SCHMOOGIE
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
-#define CONFIG_DISPLAY_CPUINFO
#define MACH_TYPE_SCHMOOGIE 1255
#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
-#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define SONATA_BOARD
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NOR
-#define CONFIG_DISPLAY_CPUINFO
#define MACH_TYPE_SONATA 1254
#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
/*===================*/
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_HOSTNAME enbw_cmc
-#define CONFIG_DISPLAY_CPUINFO
#define MACH_TYPE_ENBW_CMC 3585
#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC