]> git.sur5r.net Git - u-boot/commitdiff
Nand boot: Add nand boot support for MPC8569mds board
authorLiu Yu <yu.liu@freescale.com>
Mon, 18 Jan 2010 11:03:28 +0000 (19:03 +0800)
committerScott Wood <scottwood@freescale.com>
Wed, 27 Jan 2010 20:22:40 +0000 (14:22 -0600)
This patch add nand boot support for MPC8569mds board.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
MAKEALL
Makefile
board/freescale/mpc8569mds/config.mk
board/freescale/mpc8569mds/tlb.c
include/configs/MPC8569MDS.h
nand_spl/board/freescale/mpc8569mds/Makefile [new file with mode: 0644]
nand_spl/board/freescale/mpc8569mds/nand_boot.c [new file with mode: 0644]

diff --git a/MAKEALL b/MAKEALL
index 15e93cf273d3c38042d30da089f372aad408d953..aac52bba2ea93d85c3478a8de1974c31281f8d5a 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -404,6 +404,7 @@ LIST_85xx="         \
        MPC8568MDS      \
        MPC8569MDS      \
        MPC8569MDS_ATM  \
+       MPC8569MDS_NAND \
        MPC8572DS       \
        MPC8572DS_36BIT \
        P2020DS         \
index 69b963f2b87dd7b5ef1813b1f0f36974a076d923..c4ef585d68d0920582dad8580cd336ac3dd077f7 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2490,6 +2490,7 @@ MPC8568MDS_config:        unconfig
        @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
 
 MPC8569MDS_ATM_config \
+MPC8569MDS_NAND_config \
 MPC8569MDS_config:     unconfig
        @$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale
 
index 962f79b747732abb8bbb9024e690dd78d85c107b..7de0f7cf7d6cb2382114debb911ff18f6afadc20 100644 (file)
 #
 # mpc8569mds board
 #
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+endif
+endif
+
+ifndef TEXT_BASE
 TEXT_BASE = 0xfff80000
+endif
index 3b8ee050da1c8ccfc6c51584b8043816bd43fb56..73dcc3e66c5b4ebb484dfc09264b50cca4c7cd2b 100644 (file)
@@ -90,6 +90,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 4, BOOKE_PAGESZ_64M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+       /* *I*G - L2SRAM */
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 5, BOOKE_PAGESZ_256K, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+                       CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
index ae2fc19f4b526059773f684017d8712581ce15cd..6cf807befa0676c0047ed50b89906cee2cdaf204 100644 (file)
@@ -62,6 +62,12 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_L2_CACHE                                /* toggle L2 cache      */
 #define CONFIG_BTB                             /* toggle branch predition */
 
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT             1
+#define CONFIG_RAMBOOT_NAND            1
+#define CONFIG_RAMBOOT_TEXT_BASE       0xf8f82000
+#endif
+
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
@@ -73,17 +79,30 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END         0x00400000
 
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR                0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS   CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE             (512 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS        CONFIG_SYS_CCSRBAR
                                                /* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR
                                                /* PQII uses CONFIG_SYS_IMMR */
 
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT     CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
+#endif
+
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 
@@ -152,8 +171,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BCSR_BASE_PHYS      CONFIG_SYS_BCSR_BASE
 
 /*Chip select 0 - Flash*/
-#define CONFIG_SYS_BR0_PRELIM          0xfe000801
-#define        CONFIG_SYS_OR0_PRELIM           0xfe000ff7
+#define CONFIG_FLASH_BR_PRELIM         0xfe000801
+#define        CONFIG_FLASH_OR_PRELIM          0xfe000ff7
 
 /*Chip select 1 - BCSR*/
 #define CONFIG_SYS_BR1_PRELIM          0xf8000801
@@ -175,12 +194,33 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_SYS_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* Chip select 3 - NAND */
+#ifndef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE           0xFC000000
+#else
+#define CONFIG_SYS_NAND_BASE           0xFFF00000
+#endif
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE       0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST     (CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+       (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    (0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC   (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP        ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
 #define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE, }
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
@@ -200,8 +240,18 @@ extern unsigned long get_clock_freq(void);
                                | OR_FCM_SCY_1 \
                                | OR_FCM_TRLX \
                                | OR_FCM_EHTR)
+
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM   /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM   /* NAND Options */
+#define CONFIG_SYS_BR3_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR3_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 #define CONFIG_SYS_BR3_PRELIM  CONFIG_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR3_PRELIM  CONFIG_NAND_OR_PRELIM /* NAND Options */
+#endif
 
 /*
  * SDRAM on the LocalBus
@@ -437,10 +487,18 @@ extern unsigned long get_clock_freq(void);
 /*
  * Environment
  */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND  1
+#define CONFIG_ENV_SIZE                CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET      ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#else
 #define CONFIG_ENV_IS_IN_FLASH 1
 #define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
+#endif
 
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile
new file mode 100644 (file)
index 0000000..7ed9d61
--- /dev/null
@@ -0,0 +1,133 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+TEXT_BASE := 0xfff00000
+PAD_TO := 0xfff01000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds
+LDFLAGS        = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS  = start.o resetvec.o
+COBJS  = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+         nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
+
+SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR  := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj        := $(OBJTREE)/nand_spl/
+
+ALL    = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:   $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+       $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:      $(nandobj)u-boot-spl
+       $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:  $(OBJS)
+       cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+               -Map $(nandobj)u-boot-spl.map \
+               -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+       @rm -f $(obj)cache.c
+       ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+       @rm -f $(obj)cpu_init_early.c
+       ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+       @rm -f $(obj)cpu_init_nand.c
+       ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+       @rm -f $(obj)fsl_law.c
+       ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+       @rm -f $(obj)law.c
+       ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+       @rm -f $(obj)nand_boot_fsl_elbc.c
+       ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+              $(obj)nand_boot_fsl_elbc.c
+
+$(obj)ns16550.c:
+       @rm -f $(obj)ns16550.c
+       ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)resetvec.S:
+       @rm -f $(obj)resetvec.S
+       ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+
+$(obj)fixed_ivor.S:
+       @rm -f $(obj)fixed_ivor.S
+       ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+       @rm -f $(obj)start.S
+       ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+
+$(obj)tlb.c:
+       @rm -f $(obj)tlb.c
+       ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+       @rm -f $(obj)tlb_table.c
+       ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_boot.c:
+       @rm -f $(obj)nand_boot.c
+       ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o:     $(obj)%.S
+       $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:     $(obj)%.c
+       $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/mpc8569mds/nand_boot.c b/nand_spl/board/freescale/mpc8569mds/nand_boot.c
new file mode 100644 (file)
index 0000000..e030656
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm-ppc/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+
+#define SYSCLK_66       66666666
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+       uint plat_ratio, bus_clk, sys_clk;
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+       sys_clk = SYSCLK_66;
+
+       plat_ratio = gur->porpllsr & 0x0000003e;
+       plat_ratio >>= 1;
+       bus_clk = plat_ratio * sys_clk;
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                       bus_clk / 16 / CONFIG_BAUDRATE);
+
+       puts("\nNAND boot... ");
+
+       /* copy code to DDR and jump to it - this should not return */
+       /* NOTE - code has to be copied out of NAND buffer before
+        * other blocks can be read.
+        */
+       relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+                       CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       nand_boot();
+}
+
+void putc(char c)
+{
+       if (c == '\n')
+               NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+       NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+       while (*str)
+               putc(*str++);
+}