]> git.sur5r.net Git - u-boot/commitdiff
mpc512x: use common code for CSx configuration
authorAnatolij Gustschin <agust@denx.de>
Fri, 8 Feb 2013 00:03:44 +0000 (00:03 +0000)
committerWolfgang Denk <wd@denx.de>
Sat, 9 Mar 2013 07:21:46 +0000 (08:21 +0100)
Remove CSx configurations from board code and only define
required CSx macros in the board config file to configure
chip select windows and parameters.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Wolfgang Denk <wd@denx.de>
board/davedenx/aria/aria.c
board/esd/mecp5123/mecp5123.c
board/freescale/mpc5121ads/mpc5121ads.c
board/pdm360ng/pdm360ng.c
include/configs/aria.h
include/configs/mecp5123.h
include/configs/mpc5121ads.h
include/configs/pdm360ng.h

index 31b079b1c38105d65a22ebb42df20d3fc576d6c8..04912b8d63b78462aadaa42cf8668d4b346d9b61 100644 (file)
@@ -55,37 +55,6 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_early_init_f(void)
 {
        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       u32 spridr;
-
-       /*
-        * Initialize Local Window for the On Board FPGA access
-        */
-       out_be32(&im->sysconf.lpcs2aw,
-               CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
-               CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
-       );
-       out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
-       sync_law(&im->sysconf.lpcs2aw);
-
-       /*
-        * Initialize Local Window for the On Board SRAM access
-        */
-       out_be32(&im->sysconf.lpcs6aw,
-               CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
-               CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
-       );
-       out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
-       sync_law(&im->sysconf.lpcs6aw);
-
-       /*
-        * Configure Flash Speed
-        */
-       out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-
-       spridr = in_be32(&im->sysconf.spridr);
-
-       if (SVR_MJREV(spridr) >= 2)
-               out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
 
        /*
         * Enable clocks
index 748ad7cec61c234472c8c07227c282b1264cb5c3..19e6e1f96b3e7dd071c7268afb5c912ce9bec9a6 100644 (file)
@@ -65,17 +65,8 @@ int eeprom_write_enable(unsigned dev_addr, int state)
 int board_early_init_f(void)
 {
        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       u32 spridr;
        int i;
 
-       /*
-        * Initialize Local Window for NOR FLASH access
-        */
-       out_be32(&im->sysconf.lpcs0aw,
-                CSAW_START(CONFIG_SYS_FLASH_BASE) |
-                CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
-       sync_law(&im->sysconf.lpcs0aw);
-
        /*
         * Initialize Local Window for boot access
         */
@@ -83,28 +74,6 @@ int board_early_init_f(void)
                 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
        sync_law(&im->sysconf.lpbaw);
 
-       /*
-        * Initialize Local Window for VPC3 access
-        */
-       out_be32(&im->sysconf.lpcs1aw,
-                CSAW_START(CONFIG_SYS_VPC3_BASE) |
-                CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE));
-       sync_law(&im->sysconf.lpcs1aw);
-
-       /*
-        * Configure Flash Speed
-        */
-       out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-
-       /*
-        * Configure VPC3 Speed
-        */
-       out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
-
-       spridr = in_be32(&im->sysconf.spridr);
-       if (SVR_MJREV(spridr) >= 2)
-               out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
-
        /*
         * Enable clocks
         */
index 97eeab3a23415ab34b0202e326532b11020eec1c..4b58dbcba931823f670c83b9b400336ea60e62eb 100644 (file)
@@ -84,18 +84,6 @@ void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
 int board_early_init_f(void)
 {
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-       u32 spridr;
-
-       /*
-        * Initialize Local Window for the CPLD registers access (CS2 selects
-        * the CPLD chip)
-        */
-       out_be32(&im->sysconf.lpcs2aw,
-               CSAW_START(CONFIG_SYS_CPLD_BASE) |
-               CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
-       );
-       out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
-       sync_law(&im->sysconf.lpcs2aw);
 
        /*
         * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
@@ -114,15 +102,6 @@ int board_early_init_f(void)
                out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
        }
 #endif
-       /*
-        * Configure Flash Speed
-        */
-       out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-
-       spridr = in_be32(&im->sysconf.spridr);
-
-       if (SVR_MJREV (spridr) >= 2)
-               out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
 
        /*
         * Enable clocks
index a2a132344f5771f70a9a51c87e87358bababdbd8..9a164eeff0a11d453805c2c8fde786be4bf5ce3d 100644 (file)
@@ -63,32 +63,6 @@ int board_early_init_f(void)
 {
        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
-       /*
-        * Initialize Local Window for FLASH-Bank1 access (CS1)
-        */
-       out_be32(&im->sysconf.lpcs1aw,
-               CSAW_START(CONFIG_SYS_FLASH1_BASE) |
-               CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE)
-       );
-       out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
-
-       /*
-        * Local Window for MRAM access (CS2)
-        */
-       out_be32(&im->sysconf.lpcs2aw,
-               CSAW_START(CONFIG_SYS_MRAM_BASE) |
-               CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE)
-       );
-       out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
-
-       sync_law(&im->sysconf.lpcs2aw);
-
-       /*
-        * Configure Flash Speed
-        */
-       out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-       out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
-
        /*
         * Enable clocks
         */
index 0b31c50daf4da0dde659700e502c8648fa86f486..6b6e400b5573b56f4a267447fff15281776efe60 100644 (file)
 #define CONFIG_SYS_ARIA_SRAM_BASE      (CONFIG_SYS_SRAM_BASE + \
                                         CONFIG_SYS_SRAM_SIZE)
 #define CONFIG_SYS_ARIA_SRAM_SIZE      0x00100000      /* reserve 1MB-window */
+#define CONFIG_SYS_CS6_START           CONFIG_SYS_ARIA_SRAM_BASE
+#define CONFIG_SYS_CS6_SIZE            CONFIG_SYS_ARIA_SRAM_SIZE
 
 #define CONFIG_SYS_ARIA_FPGA_BASE      (CONFIG_SYS_ARIA_SRAM_BASE + \
                                         CONFIG_SYS_ARIA_SRAM_SIZE)
 #define CONFIG_SYS_ARIA_FPGA_SIZE      0x20000         /* 128 KB */
 
+#define CONFIG_SYS_CS2_START           CONFIG_SYS_ARIA_FPGA_BASE
+#define CONFIG_SYS_CS2_SIZE            CONFIG_SYS_ARIA_FPGA_SIZE
+
 #define CONFIG_SYS_CS0_CFG             0x05059150
 #define CONFIG_SYS_CS2_CFG             (       (5 << 24) | \
                                                (5 << 16) | \
index cafc273c8c2c8c379311bde1e196c342508ec025..1e09ff2230b1565954ceb358038965a26994a223 100644 (file)
 #define CONFIG_SYS_SRAM_BASE           0x30000000
 #define CONFIG_SYS_SRAM_SIZE           0x00020000      /* 128 KB */
 
+/* Initialize Local Window for NOR FLASH access */
+#define CONFIG_SYS_CS0_START           CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE            CONFIG_SYS_FLASH_SIZE
+
 /* ALE active low, data size 4bytes */
 #define CONFIG_SYS_CS0_CFG             0x05051150
 
 #define CONFIG_SYS_CS1_CFG             0x1f1f3090
 #define CONFIG_SYS_VPC3_BASE           0x82000000      /* start of VPC3 space */
 #define CONFIG_SYS_VPC3_SIZE           0x00010000      /* max VPC3 size */
+/* Initialize Local Window for VPC3 access */
+#define CONFIG_SYS_CS1_START           CONFIG_SYS_VPC3_BASE
+#define CONFIG_SYS_CS1_SIZE            CONFIG_SYS_VPC3_SIZE
 
 /* Use SRAM for initial stack */
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_SRAM_BASE /* Init RAM addr */
index 3f55d354ef7d28b81a5d50bd6548ad026e29c91e..a64df61fe5c2f2fcecc30dc6af0c1728bad517b7 100644 (file)
  */
 #define CONFIG_SYS_CPLD_BASE           0x82000000
 #define CONFIG_SYS_CPLD_SIZE           0x00010000      /* 64 KB */
+#define CONFIG_SYS_CS2_START           CONFIG_SYS_CPLD_BASE
+#define CONFIG_SYS_CS2_SIZE            CONFIG_SYS_CPLD_SIZE
 
 #define CONFIG_SYS_SRAM_BASE           0x30000000
 #define CONFIG_SYS_SRAM_SIZE           0x00020000      /* 128 KB */
index 671e9eb1e5ef866dea43edf9718fc38f75643029..07731217bcb30dcea45f112e4035b1a37ccdc941 100644 (file)
 #define CONFIG_SYS_SRAM_BASE           0x50000000
 #define CONFIG_SYS_SRAM_SIZE           0x00020000      /* 128 KB */
 
+#define CONFIG_SYS_CS1_START           CONFIG_SYS_FLASH1_BASE
+#define CONFIG_SYS_CS1_SIZE            CONFIG_SYS_FLASH_SIZE
+
 /* ALE active low, data size 4 bytes */
 #define CONFIG_SYS_CS0_CFG             0x05059350
 /* ALE active low, data size 4 bytes */
 
 #define CONFIG_SYS_MRAM_BASE           0x50040000
 #define CONFIG_SYS_MRAM_SIZE           0x00020000
+#define CONFIG_SYS_CS2_START           CONFIG_SYS_MRAM_BASE
+#define CONFIG_SYS_CS2_SIZE            CONFIG_SYS_MRAM_SIZE
+
 /* ALE active low, data size 4 bytes */
 #define CONFIG_SYS_CS2_CFG             0x05059110