powerpc/85xx: Add support for Freescale P1023/P1017 Processors

Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
  (fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 628e1cf0c6ebda31a910b5d14679d04120a5f461..cc16db350dff208452550e1dd1e9bdfba4e46757 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -92,9 +92,11 @@ COBJS-$(CONFIG_P1011)        += p1021_serdes.o
 COBJS-$(CONFIG_P1012)  += p1021_serdes.o
 COBJS-$(CONFIG_P1013)  += p1022_serdes.o
 COBJS-$(CONFIG_P1014)  += p1010_serdes.o
+COBJS-$(CONFIG_P1017)  += p1023_serdes.o
 COBJS-$(CONFIG_P1020)  += p1021_serdes.o
 COBJS-$(CONFIG_P1021)  += p1021_serdes.o
 COBJS-$(CONFIG_P1022)  += p1022_serdes.o
+COBJS-$(CONFIG_P1023)  += p1023_serdes.o
 COBJS-$(CONFIG_P2010)  += p2020_serdes.o
 COBJS-$(CONFIG_P2020)  += p2020_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o

diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
new file mode 100644 (file)
index 0000000..c8ab5d6
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES                4
+
+static u32 serdes1_prtcl_map;
+
+static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+       [0x00] = {PCIE1, PCIE2, NONE, NONE},
+       [0x01] = {PCIE1, PCIE2, PCIE3, NONE},
+       [0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2},
+       [0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2},
+};
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+       int ret = (1 << device) & serdes1_prtcl_map;
+       return ret;
+}
+
+void fsl_serdes_init(void)
+{
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       u32 pordevsr = in_be32(&gur->pordevsr);
+       u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+                               MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+       int lane;
+
+       debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+               printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+               return;
+       }
+       for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+               enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+               serdes1_prtcl_map |= (1 << lane_prtcl);
+       }
+
+}

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 4335fb4f31ff1c879f1f380a5e90377bb6bf6592..d2baaf0c2daca407358d225694243076c7b3ef5e 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -71,15 +71,19 @@ struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(P1012, P1012, 1),
        CPU_TYPE_ENTRY(P1012, P1012_E, 1),
        CPU_TYPE_ENTRY(P1013, P1013, 1),
+       CPU_TYPE_ENTRY(P1013, P1013_E, 1),
        CPU_TYPE_ENTRY(P1014, P1014_E, 1),
        CPU_TYPE_ENTRY(P1014, P1014, 1),
-       CPU_TYPE_ENTRY(P1013, P1013_E, 1),
+       CPU_TYPE_ENTRY(P1017, P1017, 1),
+       CPU_TYPE_ENTRY(P1017, P1017, 1),
        CPU_TYPE_ENTRY(P1020, P1020, 2),
        CPU_TYPE_ENTRY(P1020, P1020_E, 2),
        CPU_TYPE_ENTRY(P1021, P1021, 2),
        CPU_TYPE_ENTRY(P1021, P1021_E, 2),
        CPU_TYPE_ENTRY(P1022, P1022, 2),
        CPU_TYPE_ENTRY(P1022, P1022_E, 2),
+       CPU_TYPE_ENTRY(P1023, P1023, 2),
+       CPU_TYPE_ENTRY(P1023, P1023_E, 2),
        CPU_TYPE_ENTRY(P2010, P2010, 1),
        CPU_TYPE_ENTRY(P2010, P2010_E, 1),
        CPU_TYPE_ENTRY(P2020, P2020, 2),

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index b014ec626e290b088b4edd6cac7f031dde444005..94373011ebb55b8650c48a0ea8dd5155249e02af 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -121,6 +121,16 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 
+#elif defined(CONFIG_P1017)
+#define CONFIG_MAX_CPUS                        1
+#define CONFIG_SYS_FSL_NUM_LAWS                12
+#define CONFIG_SYS_FSL_SEC_COMPAT      4
+#define CONFIG_SYS_NUM_FMAN            1
+#define CONFIG_SYS_NUM_FM1_DTSEC       2
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_SYS_QMAN_NUM_PORTALS    3
+#define CONFIG_SYS_BMAN_NUM_PORTALS    3
+
 #elif defined(CONFIG_P1020)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
@@ -144,6 +154,16 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
 
+#elif defined(CONFIG_P1023)
+#define CONFIG_MAX_CPUS                        2
+#define CONFIG_SYS_FSL_NUM_LAWS                12
+#define CONFIG_SYS_FSL_SEC_COMPAT      4
+#define CONFIG_SYS_NUM_FMAN            1
+#define CONFIG_SYS_NUM_FM1_DTSEC       2
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_SYS_QMAN_NUM_PORTALS    3
+#define CONFIG_SYS_BMAN_NUM_PORTALS    3
+
 #elif defined(CONFIG_P2010)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                12

diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index ae45f9b8d6e2d819e7c9f6e519328a8d52ac0847..13caffd96e27eee4a595af054f4dde576ca4f4d5 100644 (file)
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -83,6 +83,7 @@ enum law_trgt_if {
        LAW_TRGT_IF_DDR_INTRLV = 0x0b,
        LAW_TRGT_IF_RIO = 0x0c,
        LAW_TRGT_IF_RIO_2 = 0x0d,
+       LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
        LAW_TRGT_IF_DDR = 0x0f,
        LAW_TRGT_IF_DDR_2 = 0x16,       /* 2nd controller */
 };

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index f239e5932f84c975ad9bcbdd2a9320bf8888dc5c..ce27fece02e6a55a845090fa16703536eb7819cc 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1865,8 +1865,13 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORBMSR_HA_SHIFT       16
        u32     porimpscr;      /* POR I/O impedance status & control */
        u32     pordevsr;       /* POR I/O device status regsiter */
+#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_SGMII1_DIS    0x10000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS    0x08000000
+#else
 #define MPC85xx_PORDEVSR_SGMII1_DIS    0x20000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS    0x10000000
+#endif
 #define MPC85xx_PORDEVSR_SGMII3_DIS    0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS    0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL  0x38000000
@@ -1874,6 +1879,9 @@ typedef struct ccsr_gur {
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
 #define MPC85xx_PORDEVSR_IO_SEL                0x007c0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  18
+#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_IO_SEL                0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
 #else
 #if defined(CONFIG_P1010)
 #define MPC85xx_PORDEVSR_IO_SEL                0x00600000
@@ -2247,6 +2255,12 @@ typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET      0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET          0x80000
+#define CONFIG_SYS_FSL_QMAN_OFFSET             0x88000
+#define CONFIG_SYS_FSL_BMAN_OFFSET             0x8a000
+#define CONFIG_SYS_FSL_FM1_OFFSET              0x100000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET       0x188000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET       0x189000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET       0x1e0000
 #endif
 
 #define CONFIG_SYS_MPC85xx_PIC_OFFSET          0x40000

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fcee1a2428510045e7933a410da4717ea06b309a..d8b8f34017c9955e4f6e67fdfc46279857d273a4 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1048,12 +1048,16 @@
 #define SVR_P1013_E    0x80EF00
 #define SVR_P1014      0x80F101
 #define SVR_P1014_E    0x80F901
+#define SVR_P1017      0x80F700
+#define SVR_P1017_E    0x80FF00
 #define SVR_P1020      0x80E400
 #define SVR_P1020_E    0x80EC00
 #define SVR_P1021      0x80E401
 #define SVR_P1021_E    0x80EC01
 #define SVR_P1022      0x80E600
 #define SVR_P1022_E    0x80EE00
+#define SVR_P1023      0x80F600
+#define SVR_P1023_E    0x80FE00
 #define SVR_P2010      0x80E300
 #define SVR_P2010_E    0x80EB00
 #define SVR_P2020      0x80E200