Move these fields into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
                puts("CPU:   ");
        }
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
 
        puts(cpu->name);
        if (IS_E_PROCESSOR(svr))
 
                "bus-frequency", bd->bi_busfreq, 1);
 
        do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
-               "bus-frequency", gd->lbc_clk, 1);
+               "bus-frequency", gd->arch.lbc_clk, 1);
        do_fixup_by_compat_u32(blob, "fsl,elbc",
-               "bus-frequency", gd->lbc_clk, 1);
+               "bus-frequency", gd->arch.lbc_clk, 1);
 #ifdef CONFIG_QE
        ft_qe_setup(blob);
        ft_fixup_qe_snum(blob);
 
        gd->cpu_clk = sys_info.freqProcessor[0];
        gd->bus_clk = sys_info.freqSystemBus;
        gd->mem_clk = sys_info.freqDDRBus;
-       gd->lbc_clk = sys_info.freqLocalBus;
+       gd->arch.lbc_clk = sys_info.freqLocalBus;
 
 #ifdef CONFIG_QE
        gd->qe_clk = sys_info.freqQE;
 
        }
        puts("CPU:   ");
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
 
        puts(cpu->name);
 
 
 
 #if defined(CONFIG_MPC8641)
        do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus",
-                              "bus-frequency", gd->lbc_clk, 1);
+                              "bus-frequency", gd->arch.lbc_clk, 1);
 #endif
        do_fixup_by_compat_u32(blob, "fsl,elbc",
-                              "bus-frequency", gd->lbc_clk, 1);
+                              "bus-frequency", gd->arch.lbc_clk, 1);
 
        fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
 
        get_sys_info(&sys_info);
        gd->cpu_clk = sys_info.freqProcessor;
        gd->bus_clk = sys_info.freqSystemBus;
-       gd->lbc_clk = sys_info.freqLocalBus;
+       gd->arch.lbc_clk = sys_info.freqLocalBus;
 
        /*
         * The base clock for I2C depends on the actual SOC.  Unfortunately,
 
 u32 cpu_mask(void)
 {
        ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
 
        /* better to query feature reporting register than just assume 1 */
        if (cpu == &cpu_type_unknown)
  */
 int cpu_numcores(void)
 {
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
 
        /*
         * Report # of cores in terms of the cpu_mask if we haven't
        svr = get_svr();
        ver = SVR_SOC_VER(svr);
 
-       gd->cpu = identify_cpu(ver);
+       gd->arch.cpu = identify_cpu(ver);
 
        return 0;
 }
 /* Once in memory, compute mask & # cores once and save them off */
 int fixup_cpu(void)
 {
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
 
        if (cpu->num_cores == 0) {
                cpu->mask = cpu_mask();
 
        u32 mem_sec_clk;
 # endif /* CONFIG_MPC8360 */
 #endif
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+       u32 lbc_clk;
+       void *cpu;
+#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
 };
 
 /*
 #if defined(CONFIG_FSL_ESDHC)
        u32 sdhc_clk;
 #endif
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
-       u32 lbc_clk;
-       void *cpu;
-#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
 #if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
        u32 i2c1_clk;
        u32 i2c2_clk;
 
 
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
        /*
-        * The gd->cpu pointer is set to an address in flash before relocation.
-        * We need to update it to point to the same CPU entry in RAM.
+        * The gd->arch.cpu pointer is set to an address in flash before
+        * relocation.  We need to update it to point to the same CPU entry
+        * in RAM.
         */
-       gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
+       gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
 
        /*
         * If we didn't know the cpu mask & # cores, we can save them of
 
 {
        char buf[64];
        u8 sw;
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
        unsigned int i;
        static const char *const freq[] = {"100", "125", "156.25", "161.13",
 
 {
        struct cpu_type *cpu;
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
        printf("Board: %sRDB\n", cpu->name);
 
        return 0;
 
        struct cpu_type *cpu;
        u8 sw;
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
        printf("Board: %sQDS\n", cpu->name);
 
        printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
 
 int checkboard (void)
 {
        u8 sw;
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
        unsigned int i;
        static const char * const freq[] = {"100", "125", "156.25", "212.5" };
 
        struct cpu_type *cpu;
        phys_size_t ddr_size;
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
        /* P1014 and it's derivatives support max 16it DDR width */
        if (cpu->soc_ver == SVR_P1014)
                ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
                panic("Unsupported DDR data rate %s MT/s data rate\n",
                                        strmhz(buf, ddr_freq));
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
        /* P1014 and it's derivatives support max 16bit DDR width */
        if (cpu->soc_ver == SVR_P1014) {
                ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
        popts->trwt_override = 1;
        popts->trwt = 0;
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
        /* P1014 and it's derivatives support max 16it DDR width */
        if (cpu->soc_ver == SVR_P1014)
                popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
 
 {
        struct cpu_type *cpu;
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
        printf("Board: %sRDB\n", cpu->name);
 
        return 0;
        struct cpu_type *cpu;
        int num = 0;
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
 
 #ifdef CONFIG_TSEC1
        SET_STD_TSEC_INFO(tsec_info[num], 1);
        phys_size_t size;
        struct cpu_type *cpu;
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
 
        ft_cpu_setup(blob, bd);
 
 
        struct cpu_type *cpu;
        ulong ddr_freq, ddr_freq_mhz;
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
        /* P1020 and it's derivatives support max 32bit DDR width */
        if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
                ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
 
        else
                panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
        printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
 
        setbits_be32(&pgpio->gpdir, GPIO_DIR);
 
 int checkboard(void)
 {
        u8 sw;
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
        unsigned int i;
 
 
 {
        char buf[64];
        u8 sw;
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
        unsigned int i;