muas3001 MPC8270
municse MPC5200
sc3 PPC405GP
+ suen3 ARM926EJS (Kirkwood SoC)
uc101 MPC5200
-
Peter De Schrijver <p2@mind.be>
ML2 PPC4xx
spear310 \
spear320 \
spear600 \
+ suen3 \
trab \
VCMA9 \
versatile \
spear600_config : unconfig
@$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear
+suen3_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood
+
SX1_stdout_serial_config \
SX1_config: unconfig
@mkdir -p $(obj)include
#include <libfdt.h>
#endif
+#include "../common/common.h"
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
return ((val & SCL_BIT) == SCL_BIT);
}
-
#endif
#if !defined(CONFIG_KMETER1)
out_8 (&dev->cr, (I2C_CR_MEN));
#else
-#if defined(CONFIG_HARD_I2C)
+#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
}
#endif
+#if !defined(CONFIG_MACH_SUEN3)
int ethernet_present (void)
{
return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
}
+#endif
int board_eth_init (bd_t *bis)
{
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o ../common/common.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x004000000
+
+# Kirkwood Boot Image configuration file
+KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <nand.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int io_dev;
+extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
+
+/* Multi-Purpose Pins Functionality configuration */
+u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_PEX_RST_OUTn,
+#if defined(CONFIG_SOFT_I2C)
+ MPP8_GPIO, /* SDA */
+ MPP9_GPIO, /* SCL */
+#endif
+#if defined(CONFIG_HARD_I2C)
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+#endif
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* Reserved */
+ MPP13_UART1_TXD,
+ MPP14_UART1_RXD,
+ MPP15_GPIO, /* Not used */
+ MPP16_GPIO, /* Not used */
+ MPP17_GPIO, /* Reserved */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO, /* CDL1 (input) */
+ MPP35_GPIO, /* CDL2 (input) */
+ MPP36_GPIO, /* MAIN_IRQ (input) */
+ MPP37_GPIO, /* BOARD_LED */
+ MPP38_GPIO, /* Piggy3 LED[1] */
+ MPP39_GPIO, /* Piggy3 LED[2] */
+ MPP40_GPIO, /* Piggy3 LED[3] */
+ MPP41_GPIO, /* Piggy3 LED[4] */
+ MPP42_GPIO, /* Piggy3 LED[5] */
+ MPP43_GPIO, /* Piggy3 LED[6] */
+ MPP44_GPIO, /* Piggy3 LED[7] */
+ MPP45_GPIO, /* Piggy3 LED[8] */
+ MPP46_GPIO, /* Reserved */
+ MPP47_GPIO, /* Reserved */
+ MPP48_GPIO, /* Reserved */
+ MPP49_GPIO, /* SW_INTOUTn */
+ 0
+};
+
+int ethernet_present(void)
+{
+ uchar buf;
+ int ret = 0;
+
+ if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
+ printf ("%s: Error reading Boco\n", __FUNCTION__);
+ return -1;
+ }
+ if ((buf & 0x40) == 0x40) {
+ ret = 1;
+ }
+ return ret;
+}
+
+int misc_init_r(void)
+{
+ I2C_MUX_DEVICE *i2cdev;
+ char *str;
+ int mach_type;
+
+ /* add I2C Bus for I/O Expander */
+ i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
+ io_dev = i2cdev->busid;
+ puts("Piggy:");
+ if (ethernet_present() == 0)
+ puts (" not");
+ puts(" present\n");
+
+ str = getenv("mach_type");
+ if (str != NULL) {
+ mach_type = simple_strtoul(str, NULL, 10);
+ printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
+ gd->bd->bi_arch_number = mach_type;
+ }
+ return 0;
+}
+
+int board_init(void)
+{
+ u32 tmp;
+
+ kirkwood_mpp_conf(kwmpp_config);
+
+ /*
+ * The FLASH_GPIO_PIN switches between using a
+ * NAND or a SPI FLASH. Set this pin on start
+ * to NAND mode.
+ */
+ tmp = readl(KW_GPIO0_BASE);
+ writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+ tmp = readl(KW_GPIO0_BASE + 4);
+ writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
+ printf("KM: setting NAND mode\n");
+
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+#if defined(CONFIG_SOFT_I2C)
+ /* init the GPIO for I2C Bitbang driver */
+ kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
+ kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
+ kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
+ kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
+#endif
+#if defined(CONFIG_SYS_EEPROM_WREN)
+ kw_gpio_set_valid(SUEN3_ENV_WP, 38);
+ kw_gpio_direction_output(SUEN3_ENV_WP, 1);
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_CMD_SF)
+int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u32 tmp;
+ if (argc < 2) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ if ((strcmp(argv[1], "off") == 0)) {
+ printf("SPI FLASH disabled, NAND enabled\n");
+ /* Multi-Purpose Pins Functionality configuration */
+ kwmpp_config[0] = MPP0_NF_IO2;
+ kwmpp_config[1] = MPP1_NF_IO3;
+ kwmpp_config[2] = MPP2_NF_IO4;
+ kwmpp_config[3] = MPP3_NF_IO5;
+
+ kirkwood_mpp_conf(kwmpp_config);
+ tmp = readl(KW_GPIO0_BASE);
+ writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+ } else if ((strcmp(argv[1], "on") == 0)) {
+ printf("SPI FLASH enabled, NAND disabled\n");
+ /* Multi-Purpose Pins Functionality configuration */
+ kwmpp_config[0] = MPP0_SPI_SCn;
+ kwmpp_config[1] = MPP1_SPI_MOSI;
+ kwmpp_config[2] = MPP2_SPI_SCK;
+ kwmpp_config[3] = MPP3_SPI_MISO;
+
+ kirkwood_mpp_conf(kwmpp_config);
+ tmp = readl(KW_GPIO0_BASE);
+ writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
+ } else {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ spitoggle, 2, 0, do_spi_toggle,
+ "En-/disable SPI FLASH access",
+ "<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
+ );
+#endif
+
+int dram_init(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+ gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
+ kw_sdram_bs(i));
+ }
+ return 0;
+}
+
+/* Configure and enable MV88E1118 PHY */
+void reset_phy(void)
+{
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* reset the phy */
+ miiphy_reset(name, CONFIG_PHY_BASE_ADR);
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var (void)
+{
+ ivm_read_eeprom ();
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+void bootcount_store (ulong a)
+{
+ volatile ulong *save_addr;
+ volatile ulong size = 0;
+ int i;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ size += gd->bd->bi_dram[i].size;
+ }
+ save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
+ writel(a, save_addr);
+ writel(BOOTCOUNT_MAGIC, &save_addr[1]);
+}
+
+ulong bootcount_load (void)
+{
+ volatile ulong *save_addr;
+ volatile ulong size = 0;
+ int i;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ size += gd->bd->bi_dram[i].size;
+ }
+ save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
+ if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
+ return 0;
+ else
+ return readl(save_addr);
+}
+#endif
+
+#if defined(CONFIG_SOFT_I2C)
+void set_sda (int state)
+{
+ I2C_ACTIVE;
+ I2C_SDA(state);
+}
+
+void set_scl (int state)
+{
+ I2C_SCL(state);
+}
+
+int get_sda (void)
+{
+ I2C_TRISTATE;
+ return I2C_READ;
+}
+
+int get_scl (void)
+{
+ return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ kw_gpio_set_value(SUEN3_ENV_WP, !state);
+
+ return !kw_gpio_get_value(SUEN3_ENV_WP);
+}
+#endif
--- /dev/null
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+DATA 0xFFD10000 0x01111111 # MPP Control 0 Register
+# bit 3-0: MPPSel0 1, NF_IO[2]
+# bit 7-4: MPPSel1 1, NF_IO[3]
+# bit 12-8: MPPSel2 1, NF_IO[4]
+# bit 15-12: MPPSel3 1, NF_IO[5]
+# bit 19-16: MPPSel4 1, NF_IO[6]
+# bit 23-20: MPPSel5 1, NF_IO[7]
+# bit 27-24: MPPSel6 1, SYSRST_O
+# bit 31-28: MPPSel7 0, GPO[7]
+
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
+# bit 3-0: MPPSel16 0, GPIO[16]
+# bit 7-4: MPPSel17 0, GPIO[17]
+# bit 12-8: MPPSel18 1, NF_IO[0]
+# bit 15-12: MPPSel19 1, NF_IO[1]
+# bit 19-16: MPPSel20 0, GPIO[20]
+# bit 23-20: MPPSel21 0, GPIO[21]
+# bit 27-24: MPPSel22 0, GPIO[22]
+# bit 31-28: MPPSel23 0, GPIO[23]
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+DATA 0xFFD20134 0xBBBBBBBB # L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x00BBBBBB # L2 RAM Timing 1 Register
+DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
+DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
+DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
+
+#Dram initalization
+DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
+# bit13-0: 0x400 (DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x36343000 # DDR Controller Control Low
+ 0x38543000
+# bit 3-0: 0 reserved
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302544B # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000032 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000D # DDR Address Control
+# bit1-0: 01, Cs0width=x16
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000642 # DDR Mode
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 1, DDR ODT control lsd disabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 0 , no sample stage
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00000000 # DDR ODT Control (Low)
+# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 00, ODT1 controlled by register
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E90F # CPU ODT Control
+# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit9-8: 1, ODTEn, never active
+# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
+
+#ifndef _CONFIG_KM_ARM_H
+#define _CONFIG_KM_ARM_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL
+#define CONFIG_ARM926EJS /* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD /* SOC Family Name */
+#define CONFIG_KW88F6281 /* SOC Name */
+#define CONFIG_MACH_SUEN3 /* Machine type */
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+#undef CONFIG_CMD_DTT
+#undef CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#undef CONFIG_KIRKWOOD_PCIE_INIT /* Disable PCIE Port0 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /* Console on UART0 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+
+/*
+ * Without NOR FLASH we need this
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_NAND_BASE 0xd8000000
+
+#define BOOTFLASH_START 0x0
+
+#define CONFIG_KM_CONSOLE_TTY "ttyS0"
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
+
+/*
+ * UBI related stuff
+ */
+#define CONFIG_SYS_USE_UBI
+
+/*
+ * I2C related stuff
+ */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C /* I2C bit-banged */
+
+#if defined(CONFIG_HARD_I2C)
+#define CONFIG_I2C_KIRKWOOD
+#define CONFIG_I2C_KW_REG_BASE KW_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
+#if defined(CONFIG_SOFT_I2C)
+#ifndef __ASSEMBLY__
+#include <asm/arch-kirkwood/gpio.h>
+extern void __set_direction(unsigned pin, int high);
+void set_sda (int state);
+void set_scl (int state);
+int get_sda (void);
+int get_scl (void);
+#define SUEN3_SDA_PIN 8
+#define SUEN3_SCL_PIN 9
+#define SUEN3_ENV_WP 38
+
+#define I2C_ACTIVE __set_direction(SUEN3_SDA_PIN, 0)
+#define I2C_TRISTATE __set_direction(SUEN3_SDA_PIN, 1)
+#define I2C_READ (kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0)
+#define I2C_SDA(bit) kw_gpio_set_value(SUEN3_SDA_PIN, bit);
+#define I2C_SCL(bit) kw_gpio_set_value(SUEN3_SCL_PIN, bit);
+#endif
+
+#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
+#define I2C_SOFT_DECLARATIONS
+
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+#if defined(CONFIG_SYS_NO_FLASH)
+#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
+#undef CONFIG_FLASH_CFI_MTD
+#undef CONFIG_JFFS2_CMDLINE
+#endif
+
+#endif /* _CONFIG_KM_ARM_H */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
+
+#ifndef _CONFIG_SUEN3_H
+#define _CONFIG_SUEN3_H
+
+/* include common defines/options for all arm based Keymile boards */
+#include "km_arm.h"
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nKeymile SUEN3"
+
+#define CONFIG_HOSTNAME suen3
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
+#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
+#define CONFIG_ENV_EEPROM_IS_ON_I2C 1
+#define CONFIG_SYS_EEPROM_WREN 1
+#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
+#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
+
+/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#define CONFIG_CMD_SF
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_KIRKWOOD_SPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */
+
+#define FLASH_GPIO_PIN 0x00010000
+
+#define MTDIDS_DEFAULT "nand0=orion_nand"
+/* test-only: partitioning needs some tuning, this is just for tests */
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "orion_nand:" \
+ "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+
+#define CONFIG_KM_DEF_ENV_UPDATE \
+ "update=" \
+ "spi on;sf probe 0;sf erase 0 50000;" \
+ "sf write ${u-boot_addr_r} 0 ${filesize};" \
+ "spi off\0"
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ "memsize=0x8000000\0" \
+ "newenv=setenv addr 0x100000 && " \
+ "i2c dev 1; mw.b ${addr} 0 4 && " \
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
+ "rootpath=/opt/eldk/arm\0" \
+ "EEprom_ivm=pca9544a:70:9\0" \
+ ""
+
+#endif /* _CONFIG_SUEN3_H */
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