SPC1920: cleanup memory contoller setup

diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c
index 05dd8bd5cb2792225a68f233903ed58d94c65ca9..3c36f7911bc216b8ff18cb57939d93669bb3c9b3 100644 (file)
--- a/board/spc1920/hpi.c
+++ b/board/spc1920/hpi.c
@@ -148,8 +148,8 @@ int hpi_init(void)
        udelay(100);
 
        memctl->memc_mamr = CFG_MAMR;
-       memctl->memc_or3 = CFG_OR3_PRELIM;
-       memctl->memc_br3 = CFG_BR3_PRELIM;
+       memctl->memc_or3 = CFG_OR3;
+       memctl->memc_br3 = CFG_BR3;
 
        /* reset dsp */
        dsp_reset();

diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c
index 06ec60e2a75901a97971ff306f8a5e274a2d6af6..1f5dcb5d3e0e22760f0fa47c8f85296b14141f30 100644 (file)
--- a/board/spc1920/spc1920.c
+++ b/board/spc1920/spc1920.c
@@ -175,14 +175,9 @@ long int initdram (int board_type)
        /* initalize the DSP Host Port Interface */
        hpi_init();
 
-       /* PLD Setup */
-       memctl->memc_or4 = CFG_OR4_PRELIM;
-       memctl->memc_br4 = CFG_BR4_PRELIM;
-       udelay(1000);
-
-       /* PLD Setup */
-       memctl->memc_or5 = CFG_OR5_PRELIM;
-       memctl->memc_br5 = CFG_BR5_PRELIM;
+       /* FRAM Setup */
+       memctl->memc_or4 = CFG_OR4;
+       memctl->memc_br4 = CFG_BR4;
        udelay(1000);
 
        return (size_b0);

diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index fb7062400ba054552eadcdd326216ca937ad8505..09bbebdce899407d9e390c77092e05682cde7b15 100644 (file)
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -361,14 +361,14 @@
  * DSP Host Port Interface CS3
  */
 #define CFG_SPC1920_HPI_BASE   0x90000000
-#define CFG_PRELIM_OR3_AM      0xF0000000
+#define CFG_PRELIM_OR3_AM      0xF8000000
 
-#define CFG_OR3_PRELIM         (CFG_PRELIM_OR3_AM | \
+#define CFG_OR3         (CFG_PRELIM_OR3_AM | \
                                       OR_G5LS | \
                                       OR_SCY_0_CLK | \
                                       OR_BI)
 
-#define CFG_BR3_PRELIM ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
+#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
                                               BR_MS_UPMA | \
                                               BR_PS_16 | \
                                               BR_V);
@@ -396,13 +396,13 @@
  */
 #define CFG_SPC1920_FRAM_BASE  0x80100000
 #define CFG_PRELIM_OR4_AM      0xffff8000
-#define CFG_OR4_PRELIM         (CFG_PRELIM_OR4_AM | \
+#define CFG_OR4                (CFG_PRELIM_OR4_AM | \
                                        OR_ACS_DIV2 | \
                                        OR_BI | \
                                        OR_SCY_4_CLK | \
                                        OR_TRLX)
 
-#define CFG_BR4_PRELIM ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 
 /*
  * PLD CS5