struct gpmc *gpmc_cfg;
 
 #if defined(CONFIG_CMD_NAND)
-#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-       SMNAND_GPMC_CONFIG1,
-       SMNAND_GPMC_CONFIG2,
-       SMNAND_GPMC_CONFIG3,
-       SMNAND_GPMC_CONFIG4,
-       SMNAND_GPMC_CONFIG5,
-       SMNAND_GPMC_CONFIG6,
-       0,
-};
-#else
 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
        M_NAND_GPMC_CONFIG1,
        M_NAND_GPMC_CONFIG2,
        M_NAND_GPMC_CONFIG5,
        M_NAND_GPMC_CONFIG6, 0
 };
-#endif
 #endif /* CONFIG_CMD_NAND */
 
 #if defined(CONFIG_CMD_ONENAND)
 
 
 #define GPMC_CS_ENABLE         0x1
 
-#define SMNAND_GPMC_CONFIG1    0x00000800
-#define SMNAND_GPMC_CONFIG2    0x00141400
-#define SMNAND_GPMC_CONFIG3    0x00141400
-#define SMNAND_GPMC_CONFIG4    0x0F010F01
-#define SMNAND_GPMC_CONFIG5    0x010C1414
-#define SMNAND_GPMC_CONFIG6    0x1F0F0A80
-#define SMNAND_GPMC_CONFIG7    0x00000C44
-
 #define M_NAND_GPMC_CONFIG1    0x00001800
 #define M_NAND_GPMC_CONFIG2    0x00141400
 #define M_NAND_GPMC_CONFIG3    0x00141400
 
 };
 
 static u32 gpmc_nand_config[GPMC_MAX_REG] = {
-       SMNAND_GPMC_CONFIG1,
-       SMNAND_GPMC_CONFIG2,
-       SMNAND_GPMC_CONFIG3,
-       SMNAND_GPMC_CONFIG4,
-       SMNAND_GPMC_CONFIG5,
-       SMNAND_GPMC_CONFIG6,
+       M_NAND_GPMC_CONFIG1,
+       M_NAND_GPMC_CONFIG2,
+       M_NAND_GPMC_CONFIG3,
+       M_NAND_GPMC_CONFIG4,
+       M_NAND_GPMC_CONFIG5,
+       M_NAND_GPMC_CONFIG6,
        0,
 };
 
 
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x200000
 
 #define CONFIG_CMD_NAND
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
 #define MTDIDS_DEFAULT                 "nand0=nand"
 #define MTDPARTS_DEFAULT               "mtdparts=nand:2m(spl)," \
                                        "1m(u-boot),1m(u-boot-env)," \
 
                                                        /* CS0 */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND */
                                                        /* devices */
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
 
 /* Environment information */
 #define CONFIG_BOOTDELAY               3
 
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x80000
 
-#define GPMC_NAND_ECC_LP_x8_LAYOUT     1
 #define MTDIDS_DEFAULT                 "nand0=omap2-nand.0"
 #define MTDPARTS_DEFAULT               "mtdparts=omap2-nand.0:128k(SPL)," \
                                        "128k(SPL.backup1)," \
 
 #define CONFIG_SYS_NAND_BASE           NAND_BASE       /* physical address */
                                                        /* to access nand at */
                                                        /* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND */
                                                        /* devices */
 
 /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
 #define CONFIG_NAND_OMAP_ELM
 #define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
-#define GPMC_NAND_ECC_LP_x16_LAYOUT    1
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128*1024)
 #define CONFIG_SYS_NAND_PAGE_SIZE      2048