]> git.sur5r.net Git - u-boot/commitdiff
ARM: keystone: clock: add support for K2E SoCs
authorKhoronzhuk, Ivan <ivan.khoronzhuk@ti.com>
Fri, 17 Oct 2014 18:01:16 +0000 (21:01 +0300)
committerTom Rini <trini@ti.com>
Thu, 23 Oct 2014 15:27:29 +0000 (11:27 -0400)
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
arch/arm/cpu/armv7/keystone/clock.c
arch/arm/include/asm/arch-keystone/clock.h
board/ti/ks2_evm/board.c

index 47fc89398d44123441ade21d9bf017e7621bd4d6..d13fbc1a4bb99cb4e59bb62663644e7462e58cba 100644 (file)
@@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data)
                tmp &= ~(PLL_BWADJ_HI_MASK);
                tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
 
-               /* set PLL Select (bit 13) for PASS PLL */
-               if (data->pll == PASS_PLL)
-                       tmp |= PLLCTL_PAPLL;
-
                __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 
                /* Reset bit: bit 14 for both DDR3 & PASS PLL */
@@ -261,3 +257,16 @@ inline int get_max_arm_speed(void)
        return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
 }
 #endif
+
+void pass_pll_pa_clk_enable(void)
+{
+       u32 reg;
+
+       reg = readl(keystone_pll_regs[PASS_PLL].reg1);
+
+       reg |= PLLCTL_PAPLL;
+       writel(reg, keystone_pll_regs[PASS_PLL].reg1);
+
+       /* wait till clock is enabled */
+       sdelay(15000);
+}
index 7218230c412d72cca4f0639014742b9a79eeb646..9f6cfb265f4342f3b9e36b682cbb541462846397 100644 (file)
@@ -58,6 +58,7 @@ void init_pll(const struct pll_init_data *data);
 unsigned long clk_get_rate(unsigned int clk);
 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 int clk_set_rate(unsigned int clk, unsigned long hz);
+void pass_pll_pa_clk_enable(void);
 int get_max_dev_speed(void);
 int get_max_arm_speed(void);
 
index 279ec8e67b97aebe82f5cea0d884559e1507b392..899178606383da9d9b2038c20f853c945fdd15a8 100644 (file)
@@ -77,6 +77,7 @@ int board_eth_init(bd_t *bis)
                return -1;
        if (psc_enable_module(KS2_LPSC_CRYPTO))
                return -1;
+       pass_pll_pa_clk_enable();
 
        port_num = get_num_eth_ports();