Add tests of each API call using a sandbox clock device.
Signed-off-by: Simon Glass <sjg@chromium.org>
compatible = "denx,u-boot-fdt-test";
};
+ clk@0 {
+ compatible = "sandbox,clk";
+ };
+
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
+#define SANDBOX_CLK_RATE 32768
+
+enum {
+ PERIPH_ID_FIRST = 0,
+ PERIPH_ID_SPI = PERIPH_ID_FIRST,
+ PERIPH_ID_I2C,
+ PERIPH_ID_PCI,
+
+ PERIPH_ID_COUNT,
+};
+
/**
* sandbox_i2c_set_test_mode() - set test mode for running unit tests
*
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
+CONFIG_CLK=y
#
obj-$(CONFIG_CLK) += clk-uclass.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox.o
--- /dev/null
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/test.h>
+
+struct sandbox_clk_priv {
+ ulong rate;
+ ulong periph_rate[PERIPH_ID_COUNT];
+};
+
+static ulong sandbox_clk_get_rate(struct udevice *dev)
+{
+ struct sandbox_clk_priv *priv = dev_get_priv(dev);
+
+ return priv->rate;
+}
+
+static ulong sandbox_clk_set_rate(struct udevice *dev, ulong rate)
+{
+ struct sandbox_clk_priv *priv = dev_get_priv(dev);
+
+ if (!rate)
+ return -EINVAL;
+ priv->rate = rate;
+ return 0;
+}
+
+ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
+{
+ struct sandbox_clk_priv *priv = dev_get_priv(dev);
+
+ if (periph < PERIPH_ID_FIRST || periph >= PERIPH_ID_COUNT)
+ return -EINVAL;
+ return priv->periph_rate[periph];
+}
+
+ulong sandbox_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+{
+ struct sandbox_clk_priv *priv = dev_get_priv(dev);
+ ulong old_rate;
+
+ if (periph < PERIPH_ID_FIRST || periph >= PERIPH_ID_COUNT)
+ return -EINVAL;
+ old_rate = priv->periph_rate[periph];
+ priv->periph_rate[periph] = rate;
+
+ return old_rate;
+}
+
+static int sandbox_clk_probe(struct udevice *dev)
+{
+ struct sandbox_clk_priv *priv = dev_get_priv(dev);
+
+ priv->rate = SANDBOX_CLK_RATE;
+
+ return 0;
+}
+
+static struct clk_ops sandbox_clk_ops = {
+ .get_rate = sandbox_clk_get_rate,
+ .set_rate = sandbox_clk_set_rate,
+ .get_periph_rate = sandbox_get_periph_rate,
+ .set_periph_rate = sandbox_set_periph_rate,
+};
+
+static const struct udevice_id sandbox_clk_ids[] = {
+ { .compatible = "sandbox,clk" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sandbox) = {
+ .name = "clk_sandbox",
+ .id = UCLASS_CLK,
+ .of_match = sandbox_clk_ids,
+ .ops = &sandbox_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct sandbox_clk_priv),
+ .probe = sandbox_clk_probe,
+};
# subsystem you must add sandbox tests here.
obj-$(CONFIG_UT_DM) += core.o
ifneq ($(CONFIG_SANDBOX),)
+obj-$(CONFIG_CLK) += clk.o
obj-$(CONFIG_DM_ETH) += eth.o
obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_I2C) += i2c.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <linux/err.h>
+#include <test/ut.h>
+
+/* Test that we can find and adjust clocks */
+static int dm_test_clk_base(struct unit_test_state *uts)
+{
+ struct udevice *clk;
+ ulong rate;
+
+ ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk));
+ rate = clk_get_rate(clk);
+ ut_asserteq(SANDBOX_CLK_RATE, rate);
+ ut_asserteq(-EINVAL, clk_set_rate(clk, 0));
+ ut_assertok(clk_set_rate(clk, rate * 2));
+ ut_asserteq(SANDBOX_CLK_RATE * 2, clk_get_rate(clk));
+
+ return 0;
+}
+DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that peripheral clocks work as expected */
+static int dm_test_clk_periph(struct unit_test_state *uts)
+{
+ struct udevice *clk;
+ ulong rate;
+
+ ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk));
+ rate = clk_set_periph_rate(clk, PERIPH_ID_COUNT, 123);
+ ut_asserteq(-EINVAL, rate);
+ ut_asserteq(1, IS_ERR_VALUE(rate));
+
+ rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 123);
+ ut_asserteq(0, rate);
+ ut_asserteq(123, clk_get_periph_rate(clk, PERIPH_ID_SPI));
+
+ rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234);
+ ut_asserteq(123, rate);
+
+ rate = clk_set_periph_rate(clk, PERIPH_ID_I2C, 567);
+
+ rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234);
+ ut_asserteq(1234, rate);
+
+ ut_asserteq(567, clk_get_periph_rate(clk, PERIPH_ID_I2C));
+
+ return 0;
+}
+DM_TEST(dm_test_clk_periph, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);