]> git.sur5r.net Git - u-boot/commitdiff
ppc: xilinx-ppc4xx-generic: Update xparameters.h
authorRicardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Tue, 26 Jan 2016 10:24:15 +0000 (11:24 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 27 Jan 2016 14:55:32 +0000 (15:55 +0100)
-Remove UART address (It is now part of the dts).
-Include dummy ns16550 clock
-Fix address to last test

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
board/xilinx/ppc405-generic/xparameters.h
board/xilinx/ppc440-generic/xparameters.h
include/configs/xilinx-ppc.h

index e61040785937afd07319b21c57e7be8d290bf0f3..90fe969d339e8b60dc0734445f8f902bd7982ce6 100644 (file)
 #define XPAR_IIC_EEPROM_BASEADDR       0x81600000
 #define XPAR_INTC_0_BASEADDR           0x81800000
 #define XPAR_SPI_0_BASEADDR             0x83400000
-#define XPAR_UARTLITE_0_BASEADDR       0x84000000
 #define XPAR_FLASH_MEM0_BASEADDR       0xFE000000
 #define XPAR_PLB_CLOCK_FREQ_HZ         100000000
 #define XPAR_CORE_CLOCK_FREQ_HZ                400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS  13
-#define XPAR_UARTLITE_0_BAUDRATE       9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS  32
 #define XPAR_SPI_0_NUM_TRANSFER_BITS   8
+#define XPAR_UARTNS550_0_BASEADDR      0xdeadbeef
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
 
 #endif
index 3c135ec42b3745af61add6c622ff7f45d45bf7c2..e307de9474d98222c38c9de5480b72d51c41b70d 100644 (file)
 
 #define XPAR_DDR2_SDRAM_MEM_BASEADDR   0x00000000
 #define XPAR_IIC_EEPROM_BASEADDR       0x81600000
-#define XPAR_INTC_0_BASEADDR           0x81800000
-#define XPAR_UARTLITE_0_BASEADDR       0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR       0xFE000000
+#define XPAR_INTC_0_BASEADDR           0x87000000
+#define XPAR_FLASH_MEM0_BASEADDR       0xF0000000
 #define XPAR_PLB_CLOCK_FREQ_HZ         100000000
 #define XPAR_CORE_CLOCK_FREQ_HZ                400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS  13
-#define XPAR_UARTLITE_0_BAUDRATE       9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS  32
+#define XPAR_UARTNS550_0_BASEADDR      0xdeadbeef
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
 
 #endif
index 876750b13820ba89b488d132feb95f84569b50c8..c5579e1a81388e6f23e1f3bd85cf64ced2ca68dc 100644 (file)
 #define CONFIG_SYS_BAUDRATE_TABLE      { CONFIG_BAUDRATE }
 #else
 #ifdef XPAR_UARTNS550_0_BASEADDR
+#define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    4
 #define CONFIG_CONS_INDEX              1