arm: rmobile: Add support gose board

The gose board has R8A7793, 1GB DDR3-SDRAM, USB, Ethernet, and more.
This patch supports the following functions:
 - DDR3-SDRAM
 - SCIF
 - QSPI
 - SPI

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 8444d4224a3e51270b3f2f37e3d5370cd197829e..6d94199de854f3f0bec29a5fee642b63a53b5e54 100644 (file)
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -6,6 +6,9 @@ choice
 config TARGET_ARMADILLO_800EVA
        bool "armadillo 800 eva board"
 
+config TARGET_GOSE
+       bool "Gose board"
+
 config TARGET_KOELSCH
        bool "Koelsch board"
 
@@ -29,6 +32,7 @@ config RMOBILE_EXTRAM_BOOT
        default n
 
 source "board/atmark-techno/armadillo-800eva/Kconfig"
+source "board/renesas/gose/Kconfig"
 source "board/renesas/koelsch/Kconfig"
 source "board/renesas/lager/Kconfig"
 source "board/kmc/kzm9g/Kconfig"

diff --git a/board/renesas/gose/Kconfig b/board/renesas/gose/Kconfig
new file mode 100644 (file)
index 0000000..930a445
--- /dev/null
+++ b/board/renesas/gose/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GOSE
+
+config SYS_BOARD
+       default "gose"
+
+config SYS_VENDOR
+       default "renesas"
+
+config SYS_CONFIG_NAME
+       default "gose"
+
+endif

diff --git a/board/renesas/gose/MAINTAINERS b/board/renesas/gose/MAINTAINERS
new file mode 100644 (file)
index 0000000..cad5be9
--- /dev/null
+++ b/board/renesas/gose/MAINTAINERS
@@ -0,0 +1,6 @@
+ALT BOARD
+M:     Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S:     Maintained
+F:     board/renesas/gose/
+F:     include/configs/gose.h
+F:     configs/gose_defconfig

diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile
new file mode 100644 (file)
index 0000000..a4fb6cc
--- /dev/null
+++ b/board/renesas/gose/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/alt/Makefile
+#
+# Copyright (C) 2014 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := gose.o qos.o

diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
new file mode 100644 (file)
index 0000000..09905af
--- /dev/null
+++ b/board/renesas/gose/gose.c
@@ -0,0 +1,116 @@
+/*
+ * board/renesas/gose/gose.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <i2c.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)   (clk / 1000 / 1000)
+void s_init(void)
+{
+       struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+       struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+       u32 stc;
+
+       /* Watchdog init */
+       writel(0xA5A5A500, &rwdt->rwtcsra);
+       writel(0xA5A5A500, &swdt->swtcsra);
+
+       /* CPU frequency setting. Set to 1.5GHz */
+       stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+       clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+       /* QoS */
+       qos_init();
+}
+
+#define MSTPSR1                0xE6150038
+#define SMSTPCR1       0xE6150134
+#define TMU0_MSTP125   (1 << 25)
+
+#define MSTPSR7                0xE61501C4
+#define SMSTPCR7       0xE615014C
+#define SCIF0_MSTP721  (1 << 21)
+
+#define mstp_setbits(type, addr, saddr, set) \
+       out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+       out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+       mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear) \
+       mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+       /* TMU0 */
+       mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+       /* SCIF0 */
+       mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+       return 0;
+}
+
+#define TSTR0          0x04
+#define TSTR0_STR0     0x01
+void arch_preboot_os(void)
+{
+       /* stop TMU0 */
+       mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
+       /* Disable TMU0 */
+       mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+}
+
+int board_init(void)
+{
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = GOSE_SDRAM_BASE + 0x100;
+
+       /* Init PFC controller */
+       r8a7793_pinmux_init();
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+       CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = GOSE_SDRAM_BASE;
+       gd->bd->bi_dram[0].size = GOSE_SDRAM_SIZE;
+}
+
+void reset_cpu(ulong addr)
+{
+       u8 val;
+
+       i2c_set_bus_num(2); /* PowerIC connected to ch2 */
+       i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+       val |= 0x02;
+       i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}

diff --git a/board/renesas/gose/qos.c b/board/renesas/gose/qos.c
new file mode 100644 (file)
index 0000000..64e52cf
--- /dev/null
+++ b/board/renesas/gose/qos.c
@@ -0,0 +1,1155 @@
+/*
+ * board/renesas/gose/qos.c
+ *     This file is gose QoS setting.
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+/* QoS version 0.20 */
+enum {
+       DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+       DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+       DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+       DBSC3_15,
+       DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+       [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+       [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+       [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+       [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+       [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+       [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+       [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+       [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+       [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+       [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+       [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+       [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+       [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+       [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+       [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+       [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+       [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+       [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+       [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+       [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+       [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+       [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+       [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+       [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+       [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+       [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+       [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+       [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+       [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+       [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+       [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+       [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+       int i;
+       struct rcar_s3c *s3c;
+       struct rcar_s3c_qos *s3c_qos;
+       struct rcar_dbsc3_qos *qos_addr;
+       struct rcar_mxi *mxi;
+       struct rcar_mxi_qos *mxi_qos;
+       struct rcar_axi_qos *axi_qos;
+
+       /* DBSC DBADJ2 */
+       writel(0x20042004, DBSC3_0_DBADJ2);
+
+       /* S3C -QoS */
+       s3c = (struct rcar_s3c *)S3C_BASE;
+       writel(0x00000000, &s3c->s3cadsplcr);
+       writel(0x1F0B0908, &s3c->s3crorr);
+       writel(0x1F0C0A08, &s3c->s3cworr);
+
+       /* QoS Control Registers */
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+       writel(0x00890089, &s3c_qos->s3cqos0);
+       writel(0x20960010, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA2200, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960010, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA2200, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+       writel(0x00890089, &s3c_qos->s3cqos0);
+       writel(0x20960010, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA2200, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960010, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA2200, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+       writel(0x00820082, &s3c_qos->s3cqos0);
+       writel(0x20960020, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA20DC, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960020, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA20DC, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+       writel(0x00820082, &s3c_qos->s3cqos0);
+       writel(0x20960020, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA20FA, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960020, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA20FA, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       /* DBSC -QoS */
+       /* DBSC0 - Read */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+               writel(0x00000002, &qos_addr->dblgcnt);
+               writel(0x00002096, &qos_addr->dbtmval0);
+               writel(0x00002064, &qos_addr->dbtmval1);
+               writel(0x00002032, &qos_addr->dbtmval2);
+               writel(0x00001FB0, &qos_addr->dbtmval3);
+               writel(0x00000001, &qos_addr->dbrqctr);
+               writel(0x00002078, &qos_addr->dbthres0);
+               writel(0x0000204B, &qos_addr->dbthres1);
+               writel(0x0000201E, &qos_addr->dbthres2);
+               writel(0x00000001, &qos_addr->dblgqon);
+       }
+
+       /* DBSC0 - Write */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+               writel(0x00000002, &qos_addr->dblgcnt);
+               writel(0x00002096, &qos_addr->dbtmval0);
+               writel(0x00002064, &qos_addr->dbtmval1);
+               writel(0x00002050, &qos_addr->dbtmval2);
+               writel(0x0000203A, &qos_addr->dbtmval3);
+               writel(0x00000001, &qos_addr->dbrqctr);
+               writel(0x00002078, &qos_addr->dbthres0);
+               writel(0x0000204B, &qos_addr->dbthres1);
+               writel(0x0000203C, &qos_addr->dbthres2);
+               writel(0x00000001, &qos_addr->dblgqon);
+       }
+
+       /* CCI-400 -QoS */
+       writel(0x20001000, CCI_400_MAXOT_1);
+       writel(0x20001000, CCI_400_MAXOT_2);
+       writel(0x0000000C, CCI_400_QOSCNTL_1);
+       writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+       /* MXI -QoS */
+       /* Transaction Control (MXI) */
+       mxi = (struct rcar_mxi *)MXI_BASE;
+       writel(0x00000013, &mxi->mxrtcr);
+       writel(0x00000013, &mxi->mxwtcr);
+       writel(0x00200000, &mxi->mxs3cracr);
+       writel(0x00200000, &mxi->mxs3cwacr);
+       writel(0x00200000, &mxi->mxaxiracr);
+       writel(0x00200000, &mxi->mxaxiwacr);
+
+       /* QoS Control (MXI) */
+       mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+       writel(0x0000000C, &mxi_qos->vspdu0);
+       writel(0x0000000C, &mxi_qos->vspdu1);
+       writel(0x0000000E, &mxi_qos->du0);
+
+       /* AXI -QoS */
+       /* Transaction Control (MXI) */
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002021, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002037, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002021, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002021, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002029, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (RT-AXI) */
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002299, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002029, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002029, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (MP-AXI) */
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002037, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002014, &axi_qos->qosctset0);
+       writel(0x00000040, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002014, &axi_qos->qosctset0);
+       writel(0x00000040, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00001FF0, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00002001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000206E, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (SYS-AXI256) */
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (CCI-AXI) */
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (Media-AXI) */
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020DC, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x000020AA, &axi_qos->qosthres0);
+       writel(0x00002032, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020DC, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x000020AA, &axi_qos->qosthres0);
+       writel(0x00002032, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00001FF0, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00002001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x00002063, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x00002063, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */

diff --git a/board/renesas/gose/qos.h b/board/renesas/gose/qos.h
new file mode 100644 (file)
index 0000000..ffd4047
--- /dev/null
+++ b/board/renesas/gose/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif

diff --git a/configs/gose_defconfig b/configs/gose_defconfig
new file mode 100644 (file)
index 0000000..54a56f5
--- /dev/null
+++ b/configs/gose_defconfig
@@ -0,0 +1,3 @@
+CONFIG_ARM=y
+CONFIG_RMOBILE=y
+CONFIG_TARGET_GOSE=y

diff --git a/include/configs/gose.h b/include/configs/gose.h
new file mode 100644 (file)
index 0000000..57da28b
--- /dev/null
+++ b/include/configs/gose.h
@@ -0,0 +1,150 @@
+/*
+ * include/configs/gose.h
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __GOSE_H
+#define __GOSE_H
+
+#undef DEBUG
+#define CONFIG_R8A7793
+#define CONFIG_RMOBILE_BOARD_STRING "Gose"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE   0x70000000
+#else
+#define CONFIG_SYS_TEXT_BASE   0xE6304000
+#endif
+
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define        CONFIG_CMDLINE_TAG
+#define        CONFIG_SETUP_MEMORY_TAGS
+#define        CONFIG_INITRD_TAG
+#define        CONFIG_CMDLINE_EDITING
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_BAUDRATE                38400
+#define CONFIG_BOOTDELAY       3
+#define CONFIG_BOOTARGS                ""
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR                0x7003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR                0xE633FFFC
+#endif
+
+#define STACK_AREA_SIZE                        0xC000
+#define LOW_LEVEL_MERAM_STACK  \
+       (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define GOSE_SDRAM_BASE                0x40000000
+#define GOSE_SDRAM_SIZE                0x40000000
+#define GOSE_UBOOT_SDRAM_SIZE  0x20000000
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_PBSIZE              256
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE            512
+#define CONFIG_SYS_BAUDRATE_TABLE      { 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SCIF_USE_EXT_CLK
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START       (GOSE_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + \
+                                        504 * 1024 * 1024)
+#undef CONFIG_SYS_ALT_MEMTEST
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE          (GOSE_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE          (GOSE_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS           1
+
+#define CONFIG_SYS_MONITOR_BASE                0x00000000
+#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ           (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_SPANSION
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_ADDR        0xC0000
+
+/* Common ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE   (256 * 1024)
+#define CONFIG_ENV_OFFSET      (CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE                (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK       20000000u
+#define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
+#define CONFIG_SH_SCIF_CLK_FREQ        14745600
+#define CONFIG_SYS_TMU_CLK_DIV 4
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE   0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS      3
+#define CONFIG_SYS_I2C_SH_BASE0                0xE6500000
+#define CONFIG_SYS_I2C_SH_SPEED0       400000
+#define CONFIG_SYS_I2C_SH_BASE1                0xE6510000
+#define CONFIG_SYS_I2C_SH_SPEED1       400000
+#define CONFIG_SYS_I2C_SH_BASE2                0xE60B0000
+#define CONFIG_SYS_I2C_SH_SPEED2       400000
+#define CONFIG_SH_I2C_DATA_HIGH        4
+#define CONFIG_SH_I2C_DATA_LOW 5
+#define CONFIG_SH_I2C_CLOCK    10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
+#endif /* __GOSE_H */