ARIA MPC5121e
- AMX860 MPC860
- ETX094 MPC850
FPS850L MPC850
FPS860L MPC860
ICU862 MPC862
IVMS8 MPC860
IVMS8_128 MPC860
IVMS8_256 MPC860
- LANTEC MPC850
LWMON MPC823
R360MPI MPC823
RRvision MPC823
TQM855L MPC855
TQM860L MPC860
TQM860L_FEC MPC860
- c2mon MPC855
hermes MPC860
lwmon MPC823
PN62 MPC8240
IPHASE4539 MPC8260
- SCM MPC8260
Anatolij Gustschin <agust@denx.de>
FADS850SAR MPC8xx
FADS860T MPC8xx
GENIETV MPC8xx
- IAD210 MPC8xx
MBX MPC8xx
MBX860T MPC8xx
NX823 MPC8xx
fi
if [ $BUILD_MANY == 1 ] ; then
- ${MAKE} tidy
+ ${MAKE} -s tidy
if [ -s ${LOG_DIR}/${target}.ERR ] ; then
cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target}
# MA 02111-1307 USA
#
-VERSION = 2012
-PATCHLEVEL = 10
+VERSION = 2013
+PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
endif
LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cbfs/libcbfs.o \
+LIBS-y += fs/libfs.o \
+ fs/cbfs/libcbfs.o \
fs/cramfs/libcramfs.o \
fs/ext4/libext4fs.o \
fs/fat/libfat.o \
CONFIG_CMD_EEPROM * EEPROM read/write support
CONFIG_CMD_ELF * bootelf, bootvx
CONFIG_CMD_EXPORTENV * export the environment
+ CONFIG_CMD_EXT2 * ext2 command support
+ CONFIG_CMD_EXT4 * ext4 command support
CONFIG_CMD_SAVEENV saveenv
CONFIG_CMD_FDC * Floppy Disk Support
- CONFIG_CMD_FAT * FAT partition support
+ CONFIG_CMD_FAT * FAT command support
CONFIG_CMD_FDOS * Dos diskette Support
CONFIG_CMD_FLASH flinfo, erase, protect
CONFIG_CMD_FPGA FPGA device initialization support
devices.
CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
+ The environment variable 'scsidevs' is set to the number of
+ SCSI devices found during the last scan.
+
- NETWORK Support (PCI):
CONFIG_E1000
Support for Intel 8254x/8257x gigabit chips.
following board configurations are known to be
"pRAM-clean":
- ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
- HERMES, IP860, RPXlite, LWMON, LANTEC,
+ IVMS8, IVML24, SPD8xx, TQM8xxL,
+ HERMES, IP860, RPXlite, LWMON,
FLAGADM, TQM8260
- Error Recovery:
- CONFIG_SYS_VENDOR
- CONFIG_SYS_SOC
+ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+ Define this in order to add variables describing certain
+ run-time determined information about the hardware to the
+ environment. These will be named board_name, board_rev.
+
- DataFlash Support:
CONFIG_HAS_DATAFLASH
#define tdm_extra_clk {TDM_PLL, 1}
#define tdm1_clk {TDM_PLL, 2}
-/* Optimization barrier */
-#define barrier() \
- __asm__ __volatile__("mov r0, r0\n" : : : "memory");
-
static const struct lpsc_map lpsc_clk_map[] = {
[TNETV107X_LPSC_ARM] = sys_arm1176_clk,
[TNETV107X_LPSC_GEM] = sys_dsp_clk,
* Trap & Exception support
*/
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("\n");
}
-void
-show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
}
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
}
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
panic("machine check");
}
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Alignment Exception");
}
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
int i, j;
panic("Program Check Exception");
}
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Software Emulation Exception");
}
-
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
{
#if 0
int retval;
* Trap & Exception support
*/
-void
-print_backtrace (unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
- puts ("Call backtrace: ");
+ puts("Call backtrace: ");
while (sp) {
if ((uint)sp > END_OF_MEM)
break;
i = sp[1];
if (cnt++ % 7 == 0)
- putc ('\n');
- printf ("%08lX ", i);
+ putc('\n');
+ printf("%08lX ", i);
if (cnt > 32) break;
sp = (unsigned long *) *sp;
}
- putc ('\n');
+ putc('\n');
}
-void show_regs (struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
- printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+ printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
- printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+ printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0,
regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0,
regs->msr & MSR_IR ? 1 : 0,
regs->msr & MSR_DR ? 1 : 0);
- putc ('\n');
+ putc('\n');
for (i = 0; i < 32; i++) {
if ((i % 8) == 0) {
- printf ("GPR%02d: ", i);
+ printf("GPR%02d: ", i);
}
- printf ("%08lX ", regs->gpr[i]);
+ printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7) {
- putc ('\n');
+ putc('\n');
}
}
}
-void
-_exception (int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
- show_regs (regs);
- print_backtrace ((unsigned long *)regs->gpr[1]);
- panic ("Exception at pc %lx signal %d", regs->nip,signr);
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Exception at pc %lx signal %d", regs->nip, signr);
}
-void
-MachineCheckException (struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
- unsigned long fixup;
+ unsigned long fixup = search_exception_table(regs->nip);
- if ((fixup = search_exception_table (regs->nip)) != 0) {
+ if (fixup) {
regs->nip = fixup;
return;
}
return;
#endif
- puts ("Machine check.\nCaused by (from msr): ");
- printf ("regs %p ",regs);
+ puts("Machine check.\nCaused by (from msr): ");
+ printf("regs %p ", regs);
switch (regs->msr & 0x00FF0000) {
case (0x80000000 >> 10):
- puts ("Instruction cache parity signal\n");
+ puts("Instruction cache parity signal\n");
break;
case (0x80000000 >> 11):
- puts ("Data cache parity signal\n");
+ puts("Data cache parity signal\n");
break;
case (0x80000000 >> 12):
- puts ("Machine check signal\n");
+ puts("Machine check signal\n");
break;
case (0x80000000 >> 13):
- puts ("Transfer error ack signal\n");
+ puts("Transfer error ack signal\n");
break;
case (0x80000000 >> 14):
- puts ("Data parity signal\n");
+ puts("Data parity signal\n");
break;
case (0x80000000 >> 15):
- puts ("Address parity signal\n");
+ puts("Address parity signal\n");
break;
default:
- puts ("Unknown values in msr\n");
+ puts("Unknown values in msr\n");
}
- show_regs (regs);
- print_backtrace ((unsigned long *)regs->gpr[1]);
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
- panic ("machine check");
+ panic("machine check");
}
-void
-AlignmentException (struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#ifdef CONFIG_CMD_KGDB
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
- show_regs (regs);
- print_backtrace ((unsigned long *)regs->gpr[1]);
- panic ("Alignment Exception");
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Alignment Exception");
}
-void
-ProgramCheckException (struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
#ifdef CONFIG_CMD_KGDB
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
- show_regs (regs);
- print_backtrace ((unsigned long *)regs->gpr[1]);
- panic ("Program Check Exception");
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Program Check Exception");
}
-void
-SoftEmuException (struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
{
#ifdef CONFIG_CMD_KGDB
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
- show_regs (regs);
- print_backtrace ((unsigned long *)regs->gpr[1]);
- panic ("Software Emulation Exception");
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Software Emulation Exception");
}
-void
-UnknownException (struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#ifdef CONFIG_CMD_KGDB
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
- printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+ printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
- _exception (0, regs);
+ _exception(0, regs);
}
#ifdef CONFIG_CMD_BEDBUG
-extern void do_bedbug_breakpoint (struct pt_regs *);
+extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
-void
-DebugException (struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
{
- printf ("Debugger trap at @ %lx\n", regs->nip );
- show_regs (regs);
+ printf("Debugger trap at @ %lx\n", regs->nip);
+ show_regs(regs);
#ifdef CONFIG_CMD_BEDBUG
- do_bedbug_breakpoint (regs);
+ do_bedbug_breakpoint(regs);
#endif
}
/*
* Print stack backtrace
*/
-void print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
/*
* Print current registers
*/
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
/*
* General exception handler routine
*/
-void _exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
* Trap & Exception support
*/
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("\n");
}
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
}
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
}
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
panic("machine check");
}
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Alignment Exception");
}
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Program Check Exception");
}
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
}
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
{
#if 0
int retval;
#include <asm/processor.h>
/* Returns 0 if exception not found and fixup otherwise. */
-extern unsigned long search_exception_table (unsigned long);
+extern unsigned long search_exception_table(unsigned long);
/* THIS NEEDS CHANGING to use the board info structure.
*/
* Trap & Exception support
*/
-void print_backtrace (unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
- printf ("Call backtrace: ");
+ printf("Call backtrace: ");
while (sp) {
if ((uint) sp > END_OF_MEM)
break;
i = sp[1];
if (cnt++ % 7 == 0)
- printf ("\n");
- printf ("%08lX ", i);
+ printf("\n");
+ printf("%08lX ", i);
if (cnt > 32)
break;
sp = (unsigned long *) *sp;
}
- printf ("\n");
+ printf("\n");
}
-void show_regs (struct pt_regs *regs)
+void show_regs(struct pt_regs *regs)
{
int i;
- printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+ printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
- printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+ printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
regs->msr,
regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0,
regs->msr & MSR_FP ? 1 : 0, regs->msr & MSR_ME ? 1 : 0,
regs->msr & MSR_IR ? 1 : 0, regs->msr & MSR_DR ? 1 : 0);
- printf ("\n");
+ printf("\n");
for (i = 0; i < 32; i++) {
if ((i % 8) == 0) {
- printf ("GPR%02d: ", i);
+ printf("GPR%02d: ", i);
}
- printf ("%08lX ", regs->gpr[i]);
+ printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7) {
- printf ("\n");
+ printf("\n");
}
}
}
-void _exception (int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
- show_regs (regs);
- print_backtrace ((unsigned long *) regs->gpr[1]);
- panic ("Exception in kernel pc %lx signal %d", regs->nip, signr);
+ show_regs(regs);
+ print_backtrace((unsigned long *) regs->gpr[1]);
+ panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
}
-void MachineCheckException (struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
- unsigned long fixup;
+ unsigned long fixup = search_exception_table(regs->nip);
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
* the PCI exception handler.
*/
- if ((fixup = search_exception_table (regs->nip)) != 0) {
+ if (fixup) {
regs->nip = fixup;
return;
}
#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler
- && (*debugger_exception_handler) (regs))
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
- printf ("Machine check in kernel mode.\n");
- printf ("Caused by (from msr): ");
- printf ("regs %p ", regs);
+ printf("Machine check in kernel mode.\n");
+ printf("Caused by (from msr): ");
+ printf("regs %p ", regs);
/* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */
switch (regs->msr & 0x000F0000) {
case (0x80000000 >> 12):
- printf ("Machine check signal - probably due to mm fault\n"
+ printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
break;
case (0x80000000 >> 13):
- printf ("Transfer error ack signal\n");
+ printf("Transfer error ack signal\n");
break;
case (0x80000000 >> 14):
- printf ("Data parity signal\n");
+ printf("Data parity signal\n");
break;
case (0x80000000 >> 15):
- printf ("Address parity signal\n");
+ printf("Address parity signal\n");
break;
default:
- printf ("Unknown values in msr\n");
+ printf("Unknown values in msr\n");
}
- show_regs (regs);
- print_backtrace ((unsigned long *) regs->gpr[1]);
- panic ("machine check");
+ show_regs(regs);
+ print_backtrace((unsigned long *) regs->gpr[1]);
+ panic("machine check");
}
-void AlignmentException (struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler
- && (*debugger_exception_handler) (regs))
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
- show_regs (regs);
- print_backtrace ((unsigned long *) regs->gpr[1]);
- panic ("Alignment Exception");
+ show_regs(regs);
+ print_backtrace((unsigned long *) regs->gpr[1]);
+ panic("Alignment Exception");
}
-void ProgramCheckException (struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler
- && (*debugger_exception_handler) (regs))
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
- show_regs (regs);
- print_backtrace ((unsigned long *) regs->gpr[1]);
- panic ("Program Check Exception");
+ show_regs(regs);
+ print_backtrace((unsigned long *) regs->gpr[1]);
+ panic("Program Check Exception");
}
-void SoftEmuException (struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler
- && (*debugger_exception_handler) (regs))
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
- show_regs (regs);
- print_backtrace ((unsigned long *) regs->gpr[1]);
- panic ("Software Emulation Exception");
+ show_regs(regs);
+ print_backtrace((unsigned long *) regs->gpr[1]);
+ panic("Software Emulation Exception");
}
-void UnknownException (struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler
- && (*debugger_exception_handler) (regs))
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
- printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+ printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
- _exception (0, regs);
+ _exception(0, regs);
}
#if defined(CONFIG_CMD_BEDBUG)
-extern void do_bedbug_breakpoint (struct pt_regs *);
+extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
-void DebugException (struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
{
- printf ("Debugger trap at @ %lx\n", regs->nip);
- show_regs (regs);
+ printf("Debugger trap at @ %lx\n", regs->nip);
+ show_regs(regs);
#if defined(CONFIG_CMD_BEDBUG)
- do_bedbug_breakpoint (regs);
+ do_bedbug_breakpoint(regs);
#endif
}
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
-int addr_probe (uint * addr)
+int addr_probe(uint *addr)
{
#if 0
int retval;
* Trap & Exception support
*/
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("\n");
}
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
}
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
}
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
panic("machine check");
}
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Alignment Exception");
}
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Program Check Exception");
}
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
}
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
{
#if 0
int retval;
* Trap & Exception support
*/
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
putc ('\n');
}
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
}
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
}
#endif
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
panic("machine check");
}
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Alignment Exception");
}
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Program Check Exception");
}
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
}
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
{
#if 0
int retval;
u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path, "interrupts", 0);
+ prop = fdt_getprop(blob, path, "interrupts",
+ NULL);
if (prop)
fdt_setprop(blob, path, "interrupts",
&tmp, sizeof(tmp));
u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path, "interrupts", 0);
+ prop = fdt_getprop(blob, path, "interrupts",
+ NULL);
if (prop)
fdt_setprop(blob, path, "interrupts",
&tmp, sizeof(tmp));
mult_t vco_divider;
} corecnf_t;
-corecnf_t corecnf_tab[] = {
+static corecnf_t corecnf_tab[] = {
{_byp, _byp}, /* 0x00 */
{_byp, _byp}, /* 0x01 */
{_byp, _byp}, /* 0x02 */
return gd->mem_clk;
}
-int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char buf[32];
* Trap & Exception support
*/
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
putc ('\n');
}
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
}
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
}
#endif
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
panic("machine check");
}
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Alignment Exception");
}
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Program Check Exception");
}
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
}
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
{
#if 0
int retval;
printf("Corenet Platform Cache: %d KB enabled\n", size);
}
-void invalidate_cpc(void)
+static void invalidate_cpc(void)
{
int i;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
}
-void __soc_serdes_init(void)
+static void __soc_serdes_init(void)
{
/* Allow for SoC-specific initialization in <SOC>_serdes.c */
};
* Trap & Exception support
*/
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("\n");
}
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
}
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
}
-void
-CritcalInputException(struct pt_regs *regs)
+void CritcalInputException(struct pt_regs *regs)
{
panic("Critical Input Exception");
}
int machinecheck_count = 0;
int machinecheck_error = 0;
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
unsigned int mcsr, mcsrr0, mcsrr1, mcar;
}
}
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Alignment Exception");
}
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
long esr_val;
panic("Program Check Exception");
}
-void
-PITException(struct pt_regs *regs)
+void PITException(struct pt_regs *regs)
{
/*
* Reset PIT interrupt
timer_interrupt(NULL);
}
-
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
_exception(0, regs);
}
-void
-ExtIntException(struct pt_regs *regs)
+void ExtIntException(struct pt_regs *regs)
{
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
print_backtrace((unsigned long *)regs->gpr[1]);
}
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
{
return 0;
}
* Trap & Exception support
*/
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("\n");
}
-void
-show_regs(struct pt_regs *regs)
+void show_regs(struct pt_regs *regs)
{
int i;
}
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
}
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
panic("machine check");
}
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
panic("Alignment Exception");
}
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
int i, j;
panic("Program Check Exception");
}
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
panic("Software Emulation Exception");
}
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
* If not present, return -1,
* otherwise return 0.
*/
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
{
return 0;
}
#endif /* !CONFIG_RMII */
-#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
+#elif !defined(CONFIG_ICU862)
/*
* Configure all of port D for MII.
*/
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif /* MPC860ADS */
-#if defined(CONFIG_AMX860)
- /*
- * Port B is used to control the PHY,MC68160.
- */
- immr->im_cpm.cp_pbdir |=
- (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
-
- immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
- immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
-
- immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
- immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
-#endif /* AMX860 */
-
#ifdef CONFIG_RPXCLASSIC
*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
*/
#if defined (CONFIG_FADS)
udelay (10000); /* wait 10 ms */
-#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
+#elif defined(CONFIG_RPXCLASSIC)
udelay (100000); /* wait 100 ms */
#endif
* Trap & Exception support
*/
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("\n");
}
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
}
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
}
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
panic("machine check");
}
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Alignment Exception");
}
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Program Check Exception");
}
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
}
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
_exception(0, regs);
}
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
{
#if 0
int retval;
DECLARE_GLOBAL_DATA_PTR;
-struct cpu_type cpu_type_list [] = {
+static struct cpu_type cpu_type_list[] = {
#if defined(CONFIG_MPC85xx)
CPU_TYPE_ENTRY(8533, 8533, 1),
CPU_TYPE_ENTRY(8535, 8535, 1),
#define compute_ppc_cpumask() 1
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
-struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
+static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
struct cpu_type *identify_cpu(u32 ver)
{
/*
* Return a 32-bit mask indicating which cores are present on this SOC.
*/
-u32 cpu_mask()
+u32 cpu_mask(void)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->cpu;
/*
* Return the number of cores on this SOC.
*/
-int cpu_numcores() {
+int cpu_numcores(void)
+{
struct cpu_type *cpu = gd->cpu;
/*
#error "Undefined _DDR_ADDR"
#endif
-u32 fsl_ddr_get_version(void)
+static u32 fsl_ddr_get_version(void)
{
ccsr_ddr_t *ddr;
u32 ver_major_minor_errata;
#include "ddr.h"
-unsigned int
+#if defined(CONFIG_FSL_DDR3)
+static unsigned int
compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms)
return 0;
}
+#endif
/*
* compute_lowest_common_dimm_parameters()
#ifdef CONFIG_MPC85xx
/* Boards should provide their own version of this if they use lbc sdram */
-void __lbc_sdram_init(void)
+static void __lbc_sdram_init(void)
{
/* Do nothing */
}
* Trap & Exception support
*/
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("\n");
}
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
{
int i;
}
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception");
}
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup, val;
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
panic("machine check");
}
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
panic("Alignment Exception");
}
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
{
long esr_val;
panic("Program Check Exception");
}
-void
-DecrementerPITException(struct pt_regs *regs)
+void DecrementerPITException(struct pt_regs *regs)
{
/*
* Reset PIT interrupt
}
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
_exception(0, regs);
}
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
/*
* Non ordered and non-swapping "raw" accessors
*/
-#define __iomem
#define PCI_FIX_ADDR(addr) (addr)
static inline unsigned char __raw_readb(const volatile void __iomem *addr)
/*
* Prototypes
*/
-inline void ppc4xx_ibm_ddr2_register_dump(void);
+void ppc4xx_ibm_ddr2_register_dump(void);
u32 mfdcr_any(u32);
void mtdcr_any(u32, u32);
u32 ddr_wrdtr(u32);
/***********************************************************************/
-void __board_add_ram_info(int use_default)
+static void __board_add_ram_info(int use_default)
{
/* please define platform specific board_add_ram_info() */
}
void board_add_ram_info(int)
__attribute__ ((weak, alias("__board_add_ram_info")));
-int __board_flash_wp_on(void)
+static int __board_flash_wp_on(void)
{
/*
* Most flashes can't be detected when write protection is enabled,
int board_flash_wp_on(void)
__attribute__ ((weak, alias("__board_flash_wp_on")));
-void __cpu_secondary_init_r(void)
+static void __cpu_secondary_init_r(void)
{
}
* Initialization sequence
*/
-init_fnc_t *init_sequence[] = {
+static init_fnc_t *init_sequence[] = {
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
probecpu,
#endif
#endif
}
-int __fixup_cpu(void)
+static int __fixup_cpu(void)
{
return 0;
}
#ifdef CONFIG_POST
post_bootmode_init();
- post_run(NULL, POST_ROM | post_bootmode_get(0));
+ post_run(NULL, POST_ROM | post_bootmode_get(NULL));
#endif
WATCHDOG_RESET();
return 0;
}
-__attribute__((noinline))
+noinline
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
int ret;
return 0;
}
-int ex_tab_message = 1;
-
unsigned long
search_exception_table(unsigned long addr)
{
ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr);
/* if the serial port does not hang in exception, printf can be used */
#if !defined(CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION)
- if (ex_tab_message)
- debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret);
+ debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret);
#endif
if (ret) return ret;
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o flash.o pcmcia.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
- 0x1FF77C47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- puts ("Board: TTTech C2MON ");
-
- for (i = 0; i < l; ++i) {
- if (buf[i] == ' ')
- break;
- putc (buf[i]);
- }
-
- putc ('\n');
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long reg;
- long int size8, size9;
- long int size = 0;
-
- upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 2 the SDRAM bank 2 at physical address 0.
- */
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
- udelay (1);
- memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
- udelay (1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL,
- SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL,
- SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if (size < 0x02000000) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay (1000);
- }
-
- /*
- * Final mapping
- */
- memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- /*
- * No bank 1
- *
- * invalidate bank
- */
- memctl->memc_br3 = 0;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
-
- udelay (10000);
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#ifndef CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
- memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- &flash_info[1]);
-#endif
- } else {
- memctl->memc_br1 = 0; /* invalidate bank */
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-
- value = addr[0];
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "C2MON"
-
-static void cfg_ports (void)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- ushort sreg;
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
- /*
- * Configure Port C for TPS2211 PC-Card Power-Interface Switch
- *
- * Switch off all voltages, assert shutdown
- */
- sreg = immap->im_ioport.iop_pcdat;
- sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1); /* VAVPP => Hi-Z */
- sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1); /* 3V and 5V off */
- immap->im_ioport.iop_pcdat = sreg;
-
- immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS);
- immap->im_ioport.iop_pcdir |= TPS2211_OUTPUTS;
-
- debug ("Set Port C: PAR: %04x DIR: %04x DAT: %04x\n",
- immap->im_ioport.iop_pcpar,
- immap->im_ioport.iop_pcdir,
- immap->im_ioport.iop_pcdat);
-
- /*
- * Configure Port B for TPS2211 PC-Card Power-Interface Switch
- *
- * Over-Current Input only
- */
- cp->cp_pbpar &= ~(TPS2211_INPUTS);
- cp->cp_pbdir &= ~(TPS2211_INPUTS);
-
- debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
- cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
-}
-
-int pcmcia_hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, pipr, mask;
- ushort sreg;
- int i;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
- /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
- cfg_ports ();
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- pipr = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- pipr,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-
- sreg = immap->im_ioport.iop_pcdat;
- if ((pipr & mask) == mask) {
- sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
- TPS2211_VCCD1); /* 5V on */
- sreg &= ~(TPS2211_VCCD0); /* 3V off */
- puts (" 5.0V card found: ");
- } else {
- sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
- TPS2211_VCCD0); /* 3V on */
- sreg &= ~(TPS2211_VCCD1); /* 5V off */
- puts (" 3.3V card found: ");
- }
-
- debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n",
- sreg,
- ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off",
- (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) ? "on" : "off"
- );
-
- immap->im_ioport.iop_pcdat = sreg;
-
- /* Wait 500 ms; use this to check for over-current */
- for (i=0; i<5000; ++i) {
- if ((cp->cp_pbdat & TPS2211_OC) == 0) {
- printf (" *** Overcurrent - Safety shutdown ***\n");
- immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1);
- return (1);
- }
- udelay (100);
- }
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- /* ALl voltages off / Hi-Z */
- immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 |
- TPS2211_VCCD0 | TPS2211_VCCD1 );
-
- udelay(10000);
-
- return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
- ushort sreg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
- debug ("PCMCIA power OFF\n");
- cfg_ports (); /* Enables switch, but all in Hi-Z */
-
- sreg = immap->im_ioport.iop_pcdat;
- sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */
-
- switch(vcc) {
- case 0: break; /* Switch off */
- case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */
- sreg &= ~TPS2211_VCCD1;
- break;
- case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */
- sreg |= TPS2211_VCCD1;
- break;
- default: goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
- immap->im_ioport.iop_pcdat = sreg;
-
-#ifdef DEBUG
-{
- char *s;
-
- if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) {
- s = "at 3.3V";
- } else if (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) {
- s = "at 5.0V";
- } else {
- s = "down";
- }
- printf ("PCMCIA powered %s\n", s);
-}
-#endif
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* CONFIG_PCMCIA */
+++ /dev/null
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- net/libnet.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
net/libnet.o (.text*)
board/esteem192e/libesteem192e.o (.text*)
- *(.text.*printf)
. = env_offset;
common/env_embedded.o (.text*)
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o flash.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-static void read_hw_vers (void);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
-
- /* single read (offset 0x00 in upm ram) */
-
- 0xEECEFC24, 0x100DFC24, 0xE02FBC04, 0x01AA7C04,
- 0x1FB5FC00, 0xFFFFFC05, _NOT_USED_, _NOT_USED_,
-
- /* burst read (offset 0x08 in upm ram) */
-
- 0xEECEFC24, 0x100DFC24, 0xE0FFBC04, 0x10FF7C04,
- 0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC00, 0xFFFFFC00,
- 0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* single write (offset 0x18 in upm ram) */
-
- 0xEECEFC24, 0x100DFC24, 0xE02BBC04, 0x01A27C00,
- 0xEFAAFC04, 0x1FB5FC05, _NOT_USED_, _NOT_USED_,
-
- /* burst write (offset 0x20 in upm ram) */
-
- 0xEECEFC24, 0x103DFC24, 0xE0FBBC00, 0x10F77C00,
- 0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC04, 0xFFFFFC05,
-
- /* init part1 (offset 0x28 in upm ram) */
-
- 0xEFFAFC3C, 0x1FF4FC34, 0xEFFCBC34, 0x1FFC3C34,
- 0xFFFC3C35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* refresh (offset 0x30 in upm ram) */
-
- 0xEFFEBC0C, 0x1FFD7C04, 0xFFFFFC04, 0xFFFFFC05,
-
- /* init part2 (offset 0x34 in upm ram) */
-
- 0xFFFEBC04, 0xEFFC3CB4, 0x1FFC3C34, 0xFFFC3C34,
- 0xFFFC3C34, 0xEFE83CB4, 0x1FB57C35, _NOT_USED_,
-
- /* exception (offset 0x3C in upm ram) */
-
- 0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test ETX ID string (ETX_xxx...)
- *
- * Return 1 always.
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- puts ("Board: ");
-
-#ifdef SB_ETX094
- gd->board_type = 0; /* 0 = 2SDRAM-Device */
-#else
- gd->board_type = 1; /* 1 = 1SDRAM-Device */
-#endif
-
- if (l < 0 || strncmp(buf, "ETX_", 4)) {
- puts ("### No HW ID - assuming ETX_094\n");
- read_hw_vers ();
- return (0);
- }
-
- for (i = 0; i < l; ++i) {
- if (buf[i] == ' ')
- break;
- putc(buf[i]);
- }
- putc ('\n');
-
- read_hw_vers ();
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0, size_b1, size8, size9;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; /* MPTPR_PTP_DIV32 0x0200 */
-
- /* A3(SDRAM)=0 => Bursttype = Sequential
- * A2-A0(SDRAM)=010 => Burst length = 4
- * A4-A6(SDRAM)=010 => CasLat=2
- */
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
- if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
- }
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80004128; /* SDRAM bank 0 (CS2) - Init Part 1 */
- memctl->memc_mcr = 0x80004734; /* SDRAM bank 0 (CS2) - Init Part 2 */
- udelay (1);
-
- if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
- memctl->memc_mcr = 0x80006128; /* SDRAM bank 1 (CS3) - Init Part 1 */
- memctl->memc_mcr = 0x80006734; /* SDRAM bank 1 (CS3) - Init Part 2 */
- udelay (1);
- }
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size_b0 = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size_b0 = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
- /*
- * Check Bank 1 Memory Size
- * use current column settings
- * [9 column SDRAM may also be used in 8 column mode,
- * but then only half the real size will be used.]
- */
- size_b1 =
- dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM,
- SDRAM_MAX_SIZE);
-/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
- } else {
- size_b1 = 0;
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type, both banks
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /*DIV16 */
- udelay (1000);
- }
-
- /*
- * Final mapping: map bigger bank first
- */
- if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
-
- memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br3 =
- (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- if (size_b0 > 0) {
- /*
- * Position Bank 0 immediately above Bank 1
- */
- memctl->memc_or2 =
- ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br2 =
- ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
- + size_b1;
- } else {
- unsigned long reg;
-
- /*
- * No bank 0
- *
- * invalidate bank
- */
- memctl->memc_br2 = 0;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
- }
-
- } else { /* SDRAM Bank 0 is bigger - map first */
-
- memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br2 =
- (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- if (size_b1 > 0) {
- /*
- * Position Bank 1 immediately above Bank 0
- */
- memctl->memc_or3 =
- ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br3 =
- ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
- + size_b0;
- } else {
- unsigned long reg;
-
- /*
- * No bank 1
- *
- * invalidate bank
- */
- memctl->memc_br3 = 0;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
- }
- }
-
- udelay (10000);
-
- return (size_b0 + size_b1);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* HW-ID Table (Bits: 2^9;2^7;2^5) */
-#define HW_ID_0 0x0000
-#define HW_ID_1 0x0020
-#define HW_ID_2 0x0080
-#define HW_ID_3 0x00a0
-#define HW_ID_4 0x0200
-#define HW_ID_5 0x0220
-#define HW_ID_6 0x0280
-#define HW_ID_7 0x02a0
-
-void read_hw_vers ()
-{
- unsigned short rd_msk = 0x02A0;
-
- /* HW-ID pin-definition */
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- immr->im_ioport.iop_pddir &= ~(rd_msk);
- immr->im_ioport.iop_pdpar &= ~(rd_msk);
-
- /* debug printf("State of PD: %x\n",immr->im_ioport.iop_pddat); */
-
- /* Check the HW-ID */
- printf ("HW-Version: ");
- switch (immr->im_ioport.iop_pddat & rd_msk) {
- case HW_ID_0:
- printf ("V0.1 - V0.3 / W97238-Q3162-A1-1-2\n");
- break;
- case HW_ID_1:
- printf ("V0.9 / W50037-Q1-D6-1\n");
- break;
- case HW_ID_2:
- printf ("NOT USED - assuming ID#2\n");
- break;
- case HW_ID_3:
- printf ("NOT USED - assuming ID#3\n");
- break;
- case HW_ID_4:
- printf ("NOT USED - assuming ID#4\n");
- break;
- case HW_ID_5:
- printf ("NOT USED - assuming ID#5\n");
- break;
- case HW_ID_6:
- printf ("NOT USED - assuming ID#6\n");
- break;
- case HW_ID_7:
- printf ("NOT USED - assuming ID#7\n");
- break;
- default:
- printf ("###Error###\n");
- break;
- }
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long *addr, flash_info_t *info);
-static int write_word(flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-#ifdef CONFIG_FLASH_16BIT
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
- BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */
-#else
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
- BR_MS_GPCM | BR_V;
-#endif
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE,
- &flash_info[0]);
-
- flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- memctl->memc_br1 = 0; /* invalidate bank 1 */
-
- flash_info[0].size = size_b0;
-
- return size_b0;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return;
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00002000);
-
- return;
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
-#ifdef CONFIG_FLASH_16BIT
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
-#else
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
-#endif
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--)
- info->start[i] = base + i * 0x00020000;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_SST:
- printf("SST ");
- break;
- case FLASH_MAN_STM:
- printf("STM ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST200A:
- printf("39xF200A (2M = 128K x 16)\n");
- break;
- case FLASH_SST400A:
- printf("39xF400A (4M = 256K x 16)\n");
- break;
- case FLASH_SST800A:
- printf("39xF800A (8M = 512K x 16)\n");
- break;
- case FLASH_STM800AB:
- printf("M29W800AB (8M = 512K x 16)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
-#ifdef CONFIG_FLASH_16BIT
- vu_short *s_addr = (vu_short *)addr;
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_addr[0x5555] = 0x0090;
- value = s_addr[0];
- value = value|(value<<16);
-#else
- addr[0x5555] = 0x00AA00AA;
- addr[0x2AAA] = 0x00550055;
- addr[0x5555] = 0x00900090;
- value = addr[0];
-#endif
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return 0; /* no or unknown flash */
- }
-#ifdef CONFIG_FLASH_16BIT
- value = s_addr[1];
- value = value|(value<<16);
-#else
- value = addr[1]; /* device ID */
-#endif
-
- switch (value) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
-#ifdef CONFIG_FLASH_16BIT
- info->sector_count = 19;
- info->size = 0x00100000; /* => 1 MB */
-#else
- info->sector_count = 19;
- info->size = 0x00200000; /* => 2 MB */
-#endif
- break;
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
-#ifdef CONFIG_FLASH_16BIT
- info->sector_count = 35;
- info->size = 0x00200000; /* => 2 MB */
-#else
- info->sector_count = 35;
- info->size = 0x00400000; /* => 4 MB */
-#endif
-
- break;
- case SST_ID_xF200A:
- info->flash_id += FLASH_SST200A;
- info->sector_count = 64; /* 39xF200A (2M = 128K x 16) */
- info->size = 0x00080000;
- break;
- case SST_ID_xF400A:
- info->flash_id += FLASH_SST400A;
- info->sector_count = 128; /* 39xF400A (4M = 256K x 16) */
- info->size = 0x00100000;
- break;
- case SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 256; /* 39xF800A (8M = 512K x 16) */
- info->size = 0x00200000;
- break; /* => 2 MB */
- case STM_ID_x800AB:
- info->flash_id += FLASH_STM800AB;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return 0; /* => no or unknown flash */
-
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00002000);
- } else { /* AMD and Fujitsu types */
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
-#ifdef CONFIG_FLASH_16BIT
-
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++)
- info->start[i] = base +
- (i * 0x00010000) - 0x00030000;
-#else
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++)
- info->start[i] = base +
- (i * 0x00020000) - 0x00060000;
-#endif
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--)
- info->start[i] = base + i * 0x00020000;
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /*
- * read sector protection at sector address:
- * (A7 .. A0) = 0x02
- * D0 = 1 if protected
- */
-#ifdef CONFIG_FLASH_16BIT
- s_addr = (volatile unsigned short *)(info->start[i]);
- info->protect[i] = s_addr[2] & 1;
-#else
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
-#endif
- }
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
-#ifdef CONFIG_FLASH_16BIT
- s_addr = (volatile unsigned short *)(info->start[0]);
- *s_addr = 0x00F0; /* reset bank */
-#else
- addr = (volatile unsigned long *)info->start[0];
- *addr = 0x00F000F0; /* reset bank */
-#endif
-
- }
- return info->size;
-}
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long *)(info->start[0]);
- int flag, prot, sect;
- ulong start, now, last;
-#ifdef CONFIG_FLASH_16BIT
- vu_short *s_addr = (vu_short *)addr;
-#endif
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf("- missing\n");
- else
- printf("- no sectors to erase\n");
- return 1;
- }
-/*#ifndef CONFIG_FLASH_16BIT
- ulong type;
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return;
- }
-#endif*/
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- start = get_timer(0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
-#ifdef CONFIG_FLASH_16BIT
- vu_short *s_sect_addr = (vu_short *)(info->start[sect]);
-#else
- vu_long *sect_addr = (vu_long *)(info->start[sect]);
-#endif
- /* Disable interrupts which might cause a timeout */
- flag = disable_interrupts();
-
-#ifdef CONFIG_FLASH_16BIT
-
- /*printf("\ns_sect_addr=%x",s_sect_addr);*/
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_addr[0x5555] = 0x0080;
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_sect_addr[0] = 0x0030;
-#else
- addr[0x5555] = 0x00AA00AA;
- addr[0x2AAA] = 0x00550055;
- addr[0x5555] = 0x00800080;
- addr[0x5555] = 0x00AA00AA;
- addr[0x2AAA] = 0x00550055;
- sect_addr[0] = 0x00300030;
-#endif
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
-#ifdef CONFIG_FLASH_16BIT
- while ((s_sect_addr[0] & 0x0080) != 0x0080) {
-#else
- while ((sect_addr[0] & 0x00800080) != 0x00800080) {
-#endif
- now = get_timer(start);
- if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return 1;
- }
- /* show every second that we're waiting */
- if ((now - last) > 1000) {
- putc('.');
- last = now;
- }
- }
- }
- }
-
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
-#ifdef CONFIG_FLASH_16BIT
- s_addr[0] = 0x00F0; /* reset bank */
-#else
- addr[0] = 0x00F000F0; /* reset bank */
-#endif
-
- printf(" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return 4;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- l = addr - wp;
-
- if (l != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp)
- data = (data << 8) | (*(uchar *)cp);
-
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *)cp);
-
- rc = write_word(info, wp, data);
-
- if (rc != 0)
- return rc;
-
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i)
- data = (data << 8) | *src++;
-
- rc = write_word(info, wp, data);
- if (rc != 0)
- return rc;
-
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0)
- return 0;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *)cp);
-
- return write_word(info, wp, data);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word(flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)(info->start[0]);
-
-#ifdef CONFIG_FLASH_16BIT
- vu_short high_data;
- vu_short low_data;
- vu_short *s_addr = (vu_short *)addr;
-#endif
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data)
- return 2;
-
-#ifdef CONFIG_FLASH_16BIT
- /* Write the 16 higher-bits */
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- high_data = ((data>>16) & 0x0000ffff);
-
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_addr[0x5555] = 0x00A0;
-
- *((vu_short *)dest) = high_data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return 1;
- }
-
- /* Write the 16 lower-bits */
-#endif
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-#ifdef CONFIG_FLASH_16BIT
- dest += 0x2;
- low_data = (data & 0x0000ffff);
-
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_addr[0x5555] = 0x00A0;
- *((vu_short *)dest) = low_data;
-
-#else
- addr[0x5555] = 0x00AA00AA;
- addr[0x2AAA] = 0x00550055;
- addr[0x5555] = 0x00A000A0;
- *((vu_long *)dest) = data;
-#endif
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
-
-#ifdef CONFIG_FLASH_16BIT
- while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
-#else
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-#endif
-
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return 1;
- }
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- *(.text.vsprintf)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
return 0;
}
-U_BOOT_CMD(
- pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
- "Reset the board using the FPGA sequencer",
+#ifdef CONFIG_SYS_LONGHELP
+static char pixis_help_text[] =
"- hard reset to default bank\n"
"pixis_reset altbank - reset to alternate bank\n"
#ifdef DEBUG
"pixis_reset dump - display the PIXIS registers\n"
#endif
- "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n"
+ "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n";
+#endif
+
+U_BOOT_CMD(
+ pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+ "Reset the board using the FPGA sequencer", pixis_help_text
);
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
#ifndef CONFIG_NAND_SPL
static struct pci_region pci_regions[] = {
{
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
+ .size = CONFIG_SYS_PCI1_MEM_SIZE,
+ .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
+ .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
+ .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
+ .size = CONFIG_SYS_PCI1_MMIO_SIZE,
+ .flags = PCI_REGION_MEM
},
{
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
+ .bus_start = CONFIG_SYS_PCI1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
+ .size = CONFIG_SYS_PCI1_IO_SIZE,
+ .flags = PCI_REGION_IO
}
};
#include "bcsr.h"
-void enable_8568mds_duart()
+void enable_8568mds_duart(void)
{
volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
bcsr[5] |= 0x01; /* Enable Duart in BCSR*/
}
-void enable_8568mds_flash_write()
+void enable_8568mds_flash_write(void)
{
volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
bcsr[9] |= 0x01;
}
-void disable_8568mds_flash_write()
+void disable_8568mds_flash_write(void)
{
volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
bcsr[9] &= ~(0x01);
}
-void enable_8568mds_qe_mdio()
+void enable_8568mds_qe_mdio(void)
{
u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
#include "bcsr.h"
-void enable_8569mds_flash_write()
+void enable_8569mds_flash_write(void)
{
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}
-void disable_8569mds_flash_write()
+void disable_8569mds_flash_write(void)
{
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}
-void enable_8569mds_qe_uec()
+void enable_8569mds_qe_uec(void)
{
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
#endif
}
-void disable_8569mds_brd_eeprom_write_protect()
+void disable_8569mds_brd_eeprom_write_protect(void)
{
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
}
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o flash.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Derived from ../tqm8xx/flash.c
- * [Torsten Stevens, FHG IMS; Bruno Achauer, Exet AG]
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0: "
- "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
- flash_info[0].flash_id,
- size_b0, size_b0<<20);
- }
-
- DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE5_PRELIM);
-
- size_b1 = flash_get_size((vu_long *)FLASH_BASE5_PRELIM, &flash_info[1]);
-
- DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-
- DEBUGF ("## Before remap: "
- "BR0: 0x%08x OR0: 0x%08x "
- "BR1: 0x%08x OR1: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0,
- memctl->memc_br1, memctl->memc_or1);
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \
- BR_MS_GPCM | BR_PS_32 | BR_V;
-
- DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0);
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- memctl->memc_or5 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
- memctl->memc_br5 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_PS_32 | BR_V;
-
- DEBUGF("## BR5: 0x%08x OR5: 0x%08x\n",
- memctl->memc_br5, memctl->memc_or5);
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
-
- flash_info[1].size = size_b1;
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[1]);
-#endif
- } else {
- memctl->memc_br5 = 0; /* invalidate bank */
- memctl->memc_or5 = 0; /* invalidate bank */
-
- DEBUGF("## DISABLE BR5: 0x%08x OR5: 0x%08x\n",
- memctl->memc_br5, memctl->memc_or5);
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- flash_info[1].size = 0;
- }
-
- DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-
- value = addr[0];
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2001
- * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
- * Bruno Achauer, Exet AG, bruno@exet-ag.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Derived from ../tqm8xx/tqm8xx.c
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test TQ ID string (TQM8xx...)
- * If present, check for "L" type (no second DRAM bank),
- * otherwise "L" type is assumed as default.
- *
- * Return 1 for "L" type, 0 else.
- */
-
-int checkboard (void)
-{
- printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0;
- int i;
-
- /*
- * Configure UPMA for SDRAM
- */
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K /* XXX CONFIG_SYS_MPTPR XXX */ ;
-
- /* burst length=4, burst type=sequential, CAS latency=2 */
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- /* initialize memory address register */
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */
-
- /* mode initialization (offset 5) */
- udelay (200); /* 0x80006105 */
- memctl->memc_mcr =
- MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
-
- /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
- udelay (1); /* 0x80006130 */
- memctl->memc_mcr =
- MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
- udelay (1); /* 0x80006130 */
- memctl->memc_mcr =
- MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
-
- udelay (1); /* 0x80006106 */
- memctl->memc_mcr =
- MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
-
- memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
-
- udelay (200);
-
- /* Need at least 10 DRAM accesses to stabilize */
- for (i = 0; i < 10; ++i) {
- volatile unsigned long *addr =
- (volatile unsigned long *) SDRAM_BASE3_PRELIM;
- unsigned long val;
-
- val = *(addr + i);
- *(addr + i) = val;
- }
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
- size_b0 = dram_size (CONFIG_SYS_MAMR_8COL,
- (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
-
- /*
- * Final mapping:
- */
-
- memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
- udelay (1000);
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
- drivers/rtc/librtc.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Paul Geerinckx
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <net.h>
-#include "atm.h"
-#include <i2c.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-/* used PLD registers */
-# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
-# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10)
-# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
-# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12)
-# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13)
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
- _NOT_USED_,
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0xFFFAF834, 0xFFE5B435, /* last */
- _NOT_USED_,
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
- 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
- 0xF1AAF804, 0xFFA5F447, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
- 0xFFAFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * MRS sequence (Offset 38 in UPMA RAM)
- */
- 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
- _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0xFFAFFC04, 0xFFAFFC05, /* last */
- _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile fec_t *fecp = &immap->im_cpm.cp_fec;
- long int size;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
- udelay (1);
- memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
- udelay (1);
-
- memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
- udelay (1);
- memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
- udelay (1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- */
- size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
-
- memctl->memc_mamr = CONFIG_SYS_MAMR;
- udelay (1000);
-
- /*
- * Final mapping
- */
- memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
-
- udelay (10000);
-
- /* prepare pin multiplexing for fast ethernet */
-
- atmLoad ();
- fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
- iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
-
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- return (0);
-}
-
-void board_serial_init (void)
-{
- ; /* nothing to do here */
-}
-
-void board_ether_init (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile fec_t *fecp = &immap->im_cpm.cp_fec;
-
- atmLoad ();
- fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
- iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
-}
-
-int board_early_init_f (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile iop8xx_t *iop = &immap->im_ioport;
-
- /* configure the LED timing output pins - port A pin 4 */
- iop->iop_papar = 0x0800;
- iop->iop_padir = 0x0800;
-
- /* start timer 2 for the 4hz LED blink rate */
- timers->cpmt_tmr2 = 0xff2c; /* 4HZ for 64MHz */
- timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
- timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
-
- /* chip select for PLD access */
- memctl->memc_br6 = 0x10000401;
- memctl->memc_or6 = 0xFC000908;
-
- /* PLD initial values ( set LEDs, remove reset on LXT) */
-
- *PLD_GCR1_REG = 0x06;
- *PLD_EXT_RES = 0xC0;
- *PLD_EXT_FETH = 0x40;
- *PLD_EXT_LED = 0xFF;
- *PLD_EXT_X21 = 0x04;
- return 0;
-}
-
-static void board_get_enetaddr(uchar *addr)
-{
- int i;
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpm = &immap->im_cpm;
- unsigned int rccrtmp;
-
- char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
-
- for (i = 0; i < 6; i++)
- addr[i] = default_mac_addr[i];
-
- printf ("There is an error in the i2c driver .. /n");
- printf ("You need to fix it first....../n");
-
- rccrtmp = cpm->cp_rccr;
- cpm->cp_rccr |= 0x0020;
-
- i2c_reg_read (0xa0, 0);
- printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
- i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
- i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
- i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
-
- cpm->cp_rccr = rccrtmp;
-}
-
-int misc_init_r(void)
-{
- uchar enetaddr[6];
-
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- board_get_enetaddr(enetaddr);
- eth_setenv_enetaddr("ethaddr", enetaddr);
- }
-
- return 0;
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o flash.o atm.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-
-#include "atm.h"
-#include <linux/stddef.h>
-
-#define SYNC __asm__("sync")
-#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
-
-#define FALSE 1
-#define TRUE 0
-#define OK 0
-#define ERROR -1
-
-struct atm_connection_t g_conn[NUM_CONNECTIONS] =
-{
- { NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */
-};
-
-struct atm_driver_t g_atm =
-{
- FALSE, /* loaded */
- FALSE, /* started */
- NULL, /* csram */
- 0, /* csram_size */
- NULL, /* am_top */
- NULL, /* ap_top */
- NULL, /* int_reload_ptr */
- NULL, /* int_serv_ptr */
- NULL, /* rbd_base_ptr */
- NULL, /* tbd_base_ptr */
- 0 /* linerate */
-};
-
-char csram[1024]; /* more than enough for doing nothing*/
-
-int atmLoad(void);
-void atmUnload(void);
-int atmMemInit(void);
-void atmIntInit(void);
-void atmApcInit(void);
-void atmAmtInit(void);
-void atmCpmInit(void);
-void atmUtpInit(void);
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmLoad
- *
- * DESCRIPTION: Basic ATM initialization.
- *
- * PARAMETERS: none
- *
- * RETURNS: OK or ERROR
- *
- ****************************************************************************/
-int atmLoad()
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
- volatile iop8xx_t *iop = &immap->im_ioport;
-
- timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
- immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
- iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
-
- if ( atmMemInit() != OK ) return ERROR;
-
- atmIntInit();
- atmApcInit();
- atmAmtInit();
- atmCpmInit();
- atmUtpInit();
-
- g_atm.loaded = TRUE;
-
- return OK;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmUnload
- *
- * DESCRIPTION: Disables ATM and UTOPIA.
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- ****************************************************************************/
-void atmUnload()
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
- volatile iop8xx_t *iop = &immap->im_ioport;
-
- timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
- immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
- iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
- g_atm.loaded = FALSE;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmMemInit
- *
- * DESCRIPTION:
- *
- * The ATM driver uses the following resources:
- *
- * A. Memory in DPRAM to hold
- *
- * 1/ CT = Connection Table ( RCT & TCT )
- * 2/ TCTE = Transmit Connection Table Extension
- * 3/ MPHYPT = Multi-PHY Pointing Table
- * 4/ APCP = APC Parameter Table
- * 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
- * 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
- * 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
- * 8/ TQ = Transmit Queue
- * 9/ AM = Address Matching Table
- * 10/ AP = Address Pointing Table
- *
- * B. Memory in cache safe RAM to hold
- *
- * 1/ INT = Interrupt Queue
- * 2/ RBD = Receive Buffer Descriptors
- * 3/ TBD = Transmit Buffer Descriptors
- *
- * This function
- * 1. clears the ATM DPRAM area,
- * 2. Allocates and clears cache safe memory,
- * 3. Initializes 'g_conn'.
- *
- * PARAMETERS: none
- *
- * RETURNS: OK or ERROR
- *
- ****************************************************************************/
-int atmMemInit()
-{
- int i;
- unsigned immr = CONFIG_SYS_IMMR;
- int total_num_rbd = 0;
- int total_num_tbd = 0;
-
- memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
-
- g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
-
- for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
- total_num_rbd += g_conn[i].num_rbd;
- total_num_tbd += g_conn[i].num_tbd;
- }
-
- g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
-
- g_atm.csram = &csram[0];
- memset(&(g_atm.csram), 0x00, g_atm.csram_size);
-
- g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4);
- g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
- g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
-
- g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
- g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
- g_conn[0].ct_ptr = CT_PTR(immr);
- g_conn[0].tcte_ptr = TCTE_PTR(immr);
-
- return OK;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmIntInit
- *
- * DESCRIPTION:
- *
- * Initialization of the MPC860 ESAR Interrupt Queue.
- * This function
- * - clears all entries in the INT,
- * - sets the WRAP bit of the last INT entry,
- * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
- * to the first INT entry.
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- * REMARKS:
- *
- * - The INT resides in external cache safe memory.
- * - The base address of the INT is stored in g_atm.int_reload_ptr.
- * - The number of entries in the INT is given by NUM_INT_ENTRIES.
- * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
- *
- ****************************************************************************/
-void atmIntInit()
-{
- int i;
- for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
- g_atm.int_reload_ptr[i] = INT_WRAP;
- g_atm.int_serv_ptr = g_atm.int_reload_ptr;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmApcInit
- *
- * DESCRIPTION:
- *
- * This function initializes the following ATM Pace Controller related
- * data structures:
- *
- * - 1 MPHY Pointing Table (contains only one entry)
- * - 3 APC Parameter Tables (one PHY with 3 priorities)
- * - 3 APC Tables (one table for each priority)
- * - 1 Transmit Queue (one transmit queue per PHY)
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- ****************************************************************************/
-void atmApcInit()
-{
- int i;
- /* unsigned immr = CONFIG_SYS_IMMR; */
- uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR);
- struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR);
- uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR);
- uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR);
- /***************************************************/
- /* Initialize MPHY Pointing Table (only one entry) */
- /***************************************************/
- *mphypt_ptr = APCP_BASE;
-
- /********************************************/
- /* Initialize APC parameters for priority 1 */
- /********************************************/
- apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
- apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
- apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE;
- apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
- apcp_ptr->etqbase = TQ_BASE;
- apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
- apcp_ptr->etqaptr = TQ_BASE;
- apcp_ptr->etqtptr = TQ_BASE;
- apcp_ptr->apc_mi = 8;
- apcp_ptr->ncits = 0x0100; /* NCITS = 1 */
- apcp_ptr->apcnt = 0;
- apcp_ptr->reserved1 = 0;
- apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */
- apcp_ptr->ptp_counter = 0;
- apcp_ptr->ptp_txch = 0;
- apcp_ptr->reserved2 = 0;
-
-
- /***************************************************/
- /* Initialize APC Tables with empty slots (0xFFFF) */
- /***************************************************/
- for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
-
- /************************/
- /* Clear Transmit Queue */
- /************************/
- for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmAmtInit
- *
- * DESCRIPTION:
- *
- * This function clears the first entry in the Address Matching Table and
- * lets the first entry in the Address Pointing table point to the first
- * entry in the TCT table (i.e. the raw cell channel).
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- * REMARKS:
- *
- * The values for the AMBASE, AMEND and APBASE registers in SAR parameter
- * RAM are initialized by atmCpmInit().
- *
- ****************************************************************************/
-void atmAmtInit()
-{
- unsigned immr = CONFIG_SYS_IMMR;
-
- g_atm.am_top = AM_PTR(immr);
- g_atm.ap_top = AP_PTR(immr);
-
- *(g_atm.ap_top--) = CT_BASE;
- *(g_atm.am_top--) = 0;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmCpmInit
- *
- * DESCRIPTION:
- *
- * This function initializes the Utopia Interface Parameter RAM Map
- * (SCC4, ATM Protocol) of the Communication Processor Modudule.
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- ****************************************************************************/
-void atmCpmInit()
-{
- unsigned immr = CONFIG_SYS_IMMR;
-
- memset((char *)immr + 0x3F00, 0x00, 0xC0);
-
- /*-----------------------------------------------------------------*/
- /* RBDBASE - Receive buffer descriptors base address */
- /* The RBDs reside in cache safe external memory. */
- /*-----------------------------------------------------------------*/
- *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
-
- /*-----------------------------------------------------------------*/
- /* SRFCR - SAR receive function code */
- /* 0-2 rsvd = 000 */
- /* 3-4 BO = 11 Byte ordering (big endian). */
- /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
- /* when the SDMA channel accesses memory. */
- /*-----------------------------------------------------------------*/
- *SRFCR(immr) = 0x18;
-
- /*-----------------------------------------------------------------*/
- /* SRSTATE - SAR receive status */
- /* 0 EXT = 0 Extended mode off. */
- /* 1 ACP = 0 Valid only if EXT = 1. */
- /* 2 EC = 0 Standard 53-byte ATM cell. */
- /* 3 SNC = 0 In sync. Must be set to 0 during initialization. */
- /* 4 ESAR = 1 Enhanced SAR functionality enabled. */
- /* 5 MCF = 1 Management Cell Filter active. */
- /* 6 SER = 0 UTOPIA mode. */
- /* 7 MPY = 1 Multiple PHY mode. */
- /*-----------------------------------------------------------------*/
- *SRSTATE(immr) = 0x0D;
-
- /*-----------------------------------------------------------------*/
- /* MRBLR - Maximum receive buffer length register. */
- /* Must be cleared for ATM operation (see also SMRBLR). */
- /*-----------------------------------------------------------------*/
- *MRBLR(immr) = 0;
-
- /*-----------------------------------------------------------------*/
- /* RSTATE - SCC internal receive state parameters */
- /* The first byte must be initialized with the value of SRFCR. */
- /*-----------------------------------------------------------------*/
- *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
-
- /*-----------------------------------------------------------------*/
- /* STFCR - SAR transmit function code */
- /* 0-2 rsvd = 000 */
- /* 3-4 BO = 11 Byte ordering (big endian). */
- /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
- /* when the SDMA channel accesses memory. */
- /*-----------------------------------------------------------------*/
- *STFCR(immr) = 0x18;
-
- /*-----------------------------------------------------------------*/
- /* SRSTATE - SAR transmit status */
- /* 0 EXT = 0 : Extended mode off */
- /* 1 rsvd = 0 : */
- /* 2 EC = 0 : Standard 53-byte ATM cell */
- /* 3 rsvd = 0 : */
- /* 4 ESAR = 1 : Enhanced SAR functionality enabled */
- /* 5 rsvd = 0 : */
- /* 6 SER = 0 : UTOPIA mode */
- /* 7 MPY = 1 : Multiple PHY mode */
- /*-----------------------------------------------------------------*/
- *STSTATE(immr) = 0x09;
-
- /*-----------------------------------------------------------------*/
- /* TBDBASE - Transmit buffer descriptors base address */
- /* The TBDs reside in cache safe external memory. */
- /*-----------------------------------------------------------------*/
- *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
-
- /*-----------------------------------------------------------------*/
- /* TSTATE - SCC internal transmit state parameters */
- /* The first byte must be initialized with the value of STFCR. */
- /*-----------------------------------------------------------------*/
- *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
-
- /*-----------------------------------------------------------------*/
- /* CTBASE - Connection table base address */
- /* Offset from the beginning of DPRAM (64-byte aligned). */
- /*-----------------------------------------------------------------*/
- *CTBASE(immr) = CT_BASE;
-
- /*-----------------------------------------------------------------*/
- /* INTBASE - Interrupt queue base pointer. */
- /* The interrupt queue resides in cache safe external memory. */
- /*-----------------------------------------------------------------*/
- *INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
-
- /*-----------------------------------------------------------------*/
- /* INTPTR - Pointer into interrupt queue. */
- /* Initialize to INTBASE. */
- /*-----------------------------------------------------------------*/
- *INTPTR(immr) = *INTBASE(immr);
-
- /*-----------------------------------------------------------------*/
- /* C_MASK - Constant mask for CRC32 */
- /* Must be initialized to 0xDEBB20E3. */
- /*-----------------------------------------------------------------*/
- *C_MASK(immr) = 0xDEBB20E3;
-
- /*-----------------------------------------------------------------*/
- /* INT_ICNT - Interrupt threshold value */
- /*-----------------------------------------------------------------*/
- *INT_ICNT(immr) = 1;
-
- /*-----------------------------------------------------------------*/
- /* INT_CNT - Interrupt counter */
- /* Initalize to INT_ICNT. Decremented for each interrupt entry */
- /* reported in the interrupt queue. On zero an interrupt is */
- /* signaled to the host by setting the GINT bit in the event */
- /* register. The counter is reinitialized with INT_ICNT. */
- /*-----------------------------------------------------------------*/
- *INT_CNT(immr) = *INT_ICNT(immr);
-
- /*-----------------------------------------------------------------*/
- /* SMRBLR - SAR maximum receive buffer length register. */
- /* Must be a multiple of 48 bytes. Common for all ATM connections. */
- /*-----------------------------------------------------------------*/
- *SMRBLR(immr) = SAR_RXB_SIZE;
-
- /*-----------------------------------------------------------------*/
- /* APCST - APC status register. */
- /* 0 rsvd 0 */
- /* 1-2 CSER 11 Initialize with the same value as NSER. */
- /* 3-4 NSER 11 Next serial or UTOPIA channel. */
- /* 5-7 rsvd 000 */
- /* 8-10 rsvd 000 */
- /* 11 rsvd 0 */
- /* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */
- /* 13 DIS 0 APC disable. Must be initiazed to 0. */
- /* 14 PL2 0 Not used. */
- /* 15 MPY 1 Multiple PHY mode on. */
- /*-----------------------------------------------------------------*/
- *APCST(immr) = 0x7809;
-
- /*-----------------------------------------------------------------*/
- /* APCPTR - Pointer to the APC parameter table */
- /* In MPHY master mode this parameter points to the MPHY pointing */
- /* table. 2-byte aligned. */
- /*-----------------------------------------------------------------*/
- *APCPTR(immr) = MPHYPT_BASE;
-
- /*-----------------------------------------------------------------*/
- /* HMASK - Header mask */
- /* Each incoming cell is masked with HMASK before being compared */
- /* to the entries in the address matching table. */
- /*-----------------------------------------------------------------*/
- *HMASK(immr) = AM_HMASK;
-
- /*-----------------------------------------------------------------*/
- /* AMBASE - Address matching table base address */
- /*-----------------------------------------------------------------*/
- *AMBASE(immr) = AM_BASE;
-
- /*-----------------------------------------------------------------*/
- /* AMEND - Address matching table end address */
- /*-----------------------------------------------------------------*/
- *AMEND(immr) = AM_BASE;
-
- /*-----------------------------------------------------------------*/
- /* APBASE - Address pointing table base address */
- /*-----------------------------------------------------------------*/
- *APBASE(immr) = AP_BASE;
-
- /*-----------------------------------------------------------------*/
- /* MPHYST - MPHY status register */
- /* 0-1 rsvd 00 */
- /* 2-6 NMPHY 00000 1 PHY */
- /* 7-9 rsvd 000 */
- /* 10-14 CMPHY 00000 Initialize with same value as NMPHY */
- /*-----------------------------------------------------------------*/
- *MPHYST(immr) = 0x0000;
-
- /*-----------------------------------------------------------------*/
- /* TCTEBASE - Transmit connection table extension base address */
- /* Offset from the beginning of DPRAM (32-byte aligned). */
- /*-----------------------------------------------------------------*/
- *TCTEBASE(immr) = TCTE_BASE;
-
- /*-----------------------------------------------------------------*/
- /* Clear not used registers. */
- /*-----------------------------------------------------------------*/
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmUtpInit
- *
- * DESCRIPTION:
- *
- * This function initializes the ATM interface for
- *
- * - UTOPIA mode
- * - muxed bus
- * - master operation
- * - multi PHY (because of a bug in the MPC860P rev. E.0)
- * - internal clock = SYSCLK / 2
- *
- * EXTERNAL EFFECTS:
- *
- * After calling this function, the MPC860ESAR UTOPIA bus is
- * active and uses the following ports/pins:
- *
- * Port Pin Signal Description
- * ------ --- ------- -------------------------------------------
- * PB[15] R17 TxClav Transmit cell available input/output signal
- * PC[15] D16 RxClav Receive cell available input/output signal
- * PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal
- * PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal
- * PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal
- * PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal
- * PD[11] T16 RXENB Receive enable input/output signal
- * PD[10] W18 TXENB Transmit enable input/output signal
- * PD[9] V17 UTPCLK UTOPIA clock input/output signal
- * PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal
- * PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal
- * PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal
- * PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal
- * PD[3] W16 SOC Start of cell input/output signal
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- * REMARK:
- *
- * The ATM parameters and data structures must be configured before
- * initializing the UTOPIA port. The UTOPIA port activates immediately
- * upon initialization, and if its associated data structures are not
- * initialized, the CPM will lock up.
- *
- ****************************************************************************/
-void atmUtpInit()
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile car8xx_t *car = &immap->im_clkrst;
- volatile cpm8xx_t *cpm = &immap->im_cpm;
- int flag;
-
- flag = disable_interrupts();
-
- /*-----------------------------------------------------------------*/
- /* SCCR - System Clock Control Register */
- /* */
- /* The UTOPIA clock can be selected to be internal clock or */
- /* external clock (selected by the UTOPIA mode register). */
- /* In case of internal clock, the UTOPIA clock is derived from */
- /* the system frequency divided by two dividers. */
- /* Bits 27-31 of the SCCR register are defined to control the */
- /* UTOPIA clock. */
- /* */
- /* SCCR[27:29] DFUTP Division factor. Divide the system clock */
- /* by 2^DFUTP. */
- /* SCCR[30:31] DFAUTP Additional division factor. Divide the */
- /* system clock by the following value: */
- /* 00 = divide by 1 */
- /* 00 = divide by 3 */
- /* 10 = divide by 5 */
- /* 11 = divide by 7 */
- /* */
- /* Note that the UTOPIA clock must be programmed as to operate */
- /* within the range SYSCLK/10 .. 50MHz. */
- /*-----------------------------------------------------------------*/
- car->car_sccr &= 0xFFFFFFE0;
- car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
-
- /*-----------------------------------------------------------------*/
- /* RCCR - RISC Controller Configuration Register */
- /* */
- /* RCCR[8] DR1M IDMA Request 0 Mode */
- /* 0 = edge sensitive */
- /* 1 = level sensitive */
- /* RCCR[9] DR0M IDMA Request 0 Mode */
- /* 0 = edge sensitive */
- /* 1 = level sensitive */
- /* RCCR[10:11] DRQP IDMA Request Priority */
- /* 00 = IDMA req. have more prio. than SCCs */
- /* 01 = IDMA req. have less prio. then SCCs */
- /* 10 = IDMA requests have the lowest prio. */
- /* 11 = reserved */
- /* */
- /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
- /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
- /* higher priority. */
- /*-----------------------------------------------------------------*/
- cpm->cp_rccr &= 0xFF0F;
- cpm->cp_rccr |= 0x00D0;
-
- /*-----------------------------------------------------------------*/
- /* Port B - TxClav Signal */
- /*-----------------------------------------------------------------*/
- cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
- cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
-
- /*-----------------------------------------------------------------*/
- /* UTOPIA Mode Register */
- /* */
- /* - muxed bus (master operation only) */
- /* - multi PHY (because of a bug in the MPC860P rev.E.0) */
- /* - internal clock */
- /* - no loopback */
- /* - do no activate statistical counters */
- /*-----------------------------------------------------------------*/
- iop->utmode = 0x00000004; SYNC;
-
- /*-----------------------------------------------------------------*/
- /* Port D - UTOPIA Data and Control Signals */
- /* */
- /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */
- /* 11 RXENB UTOPIA receive enable input/output signal */
- /* 10 TXENB UTOPIA transmit enable input/output signal */
- /* 9 TUPCLK UTOPIA clock input/output signal */
- /* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */
- /* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */
- /* 3 SOC UTOPIA Start of cell input/output signal */
- /* 2 Reserved */
- /* 1 Enable UTOPIA mode */
- /* 0 Enable SAR */
- /*-----------------------------------------------------------------*/
- iop->iop_pdpar |= 0xDF7F; SYNC;
- iop->iop_pddir &= 0x2080; SYNC;
-
- /*-----------------------------------------------------------------*/
- /* Port C - RxClav Signal */
- /*-----------------------------------------------------------------*/
- iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */
- iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */
- iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */
-
- if (flag)
- enable_interrupts();
-}
+++ /dev/null
-typedef unsigned char uint8;
-typedef unsigned short uint16;
-typedef unsigned int uint32;
-typedef volatile unsigned char vuint8;
-typedef volatile unsigned short vuint16;
-typedef volatile unsigned int vuint32;
-
-
-#define DPRAM_ATM CONFIG_SYS_IMMR + 0x3000
-
-#define ATM_DPRAM_BEGIN (DPRAM_ATM - CONFIG_SYS_IMMR - 0x2000)
-#define NUM_CONNECTIONS 1
-#define SAR_RXB_SIZE 1584
-#define AM_HMASK 0x0FFFFFF0
-
-#define NUM_CT_ENTRIES (NUM_CONNECTIONS)
-#define NUM_TCTE_ENTRIES (NUM_CONNECTIONS)
-#define NUM_AM_ENTRIES (NUM_CONNECTIONS+1)
-#define NUM_AP_ENTRIES (NUM_CONNECTIONS+1)
-#define NUM_MPHYPT_ENTRIES 1
-#define NUM_APCP_ENTRIES 1
-#define NUM_APCT_PRIO_1_ENTRIES 146 /* Determines minimum rate */
-#define NUM_TQ_ENTRIES 12
-
-#define SIZE_OF_CT_ENTRY 64
-#define SIZE_OF_TCTE_ENTRY 32
-#define SIZE_OF_AM_ENTRY 4
-#define SIZE_OF_AP_ENTRY 2
-#define SIZE_OF_MPHYPT_ENTRY 2
-#define SIZE_OF_APCP_ENTRY 32
-#define SIZE_OF_APCT_ENTRY 2
-#define SIZE_OF_TQ_ENTRY 2
-
-#define CT_BASE ((ATM_DPRAM_BEGIN + 63) & 0xFFC0) /*64 */
-#define TCTE_BASE (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32 */
-#define APCP_BASE (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY) /*32 */
-#define AM_BEGIN (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY) /*4 */
-#define AM_BASE (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
-#define AP_BEGIN (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY) /*2 */
-#define AP_BASE (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
-#define MPHYPT_BASE (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY) /*2 */
-#define APCT_PRIO_1_BASE (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY) /*2 */
-#define TQ_BASE (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY) /*2 */
-#define ATM_DPRAM_SIZE ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)
-
-#define CT_PTR(base) ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
-#define TCTE_PTR(base) ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE))
-#define AM_PTR(base) ((uint32 *)((char *)(base) + 0x2000 + AM_BASE))
-#define AP_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + AP_BASE))
-#define MPHYPT_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE))
-#define APCP_PTR(base) ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE))
-#define APCT1_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE))
-#define APCT2_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE))
-#define APCT3_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE))
-#define TQ_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))
-
-/* SAR registers */
-#define RBDBASE(base) ((vuint32 *)(base + 0x3F00)) /* Base address of RxBD-List */
-#define SRFCR(base) ((vuint8 *)(base + 0x3F04)) /* DMA Receive function code */
-#define SRSTATE(base) ((vuint8 *)(base + 0x3F05)) /* DMA Receive status */
-#define MRBLR(base) ((vuint16 *)(base + 0x3F06)) /* Init to 0 for ATM */
-#define RSTATE(base) ((vuint32 *)(base + 0x3F08)) /* Do not write to */
-#define R_CNT(base) ((vuint16 *)(base + 0x3F10)) /* Do not write to */
-#define STFCR(base) ((vuint8 *)(base + 0x3F12)) /* DMA Transmit function code */
-#define STSTATE(base) ((vuint8 *)(base + 0x3F13)) /* DMA Transmit status */
-#define TBDBASE(base) ((vuint32 *)(base + 0x3F14)) /* Base address of TxBD-List */
-#define TSTATE(base) ((vuint32 *)(base + 0x3F18)) /* Do not write to */
-#define COMM_CH(base) ((vuint16 *)(base + 0x3F1C)) /* Command channel */
-#define STCHNUM(base) ((vuint16 *)(base + 0x3F1E)) /* Do not write to */
-#define T_CNT(base) ((vuint16 *)(base + 0x3F20)) /* Do not write to */
-#define CTBASE(base) ((vuint16 *)(base + 0x3F22)) /* Base address of Connection-table */
-#define ECTBASE(base) ((vuint32 *)(base + 0x3F24)) /* Valid only for external Conn.-table */
-#define INTBASE(base) ((vuint32 *)(base + 0x3F28)) /* Base address of Interrupt-table */
-#define INTPTR(base) ((vuint32 *)(base + 0x3F2C)) /* Pointer to Interrupt-queue */
-#define C_MASK(base) ((vuint32 *)(base + 0x3F30)) /* CRC-mask */
-#define SRCHNUM(base) ((vuint16 *)(base + 0x3F34)) /* Do not write to */
-#define INT_CNT(base) ((vuint16 *)(base + 0x3F36)) /* Interrupt-Counter */
-#define INT_ICNT(base) ((vuint16 *)(base + 0x3F38)) /* Interrupt threshold */
-#define TSTA(base) ((vuint16 *)(base + 0x3F3A)) /* Time-stamp-address */
-#define OLDLEN(base) ((vuint16 *)(base + 0x3F3C)) /* Do not write to */
-#define SMRBLR(base) ((vuint16 *)(base + 0x3F3E)) /* SAR max RXBuffer length */
-#define EHEAD(base) ((vuint32 *)(base + 0x3F40)) /* Valid for serial mode */
-#define EPAYLOAD(base) ((vuint32 *)(base + 0x3F44)) /* Valid for serial mode */
-#define TQBASE(base) ((vuint16 *)(base + 0x3F48)) /* Base address of Tx queue */
-#define TQEND(base) ((vuint16 *)(base + 0x3F4A)) /* End address of Tx queue */
-#define TQAPTR(base) ((vuint16 *)(base + 0x3F4C)) /* TQ APC pointer */
-#define TQTPTR(base) ((vuint16 *)(base + 0x3F4E)) /* TQ Tx pointer */
-#define APCST(base) ((vuint16 *)(base + 0x3F50)) /* APC status */
-#define APCPTR(base) ((vuint16 *)(base + 0x3F52)) /* APC parameter pointer */
-#define HMASK(base) ((vuint32 *)(base + 0x3F54)) /* Header mask */
-#define AMBASE(base) ((vuint16 *)(base + 0x3F58)) /* Address match table base */
-#define AMEND(base) ((vuint16 *)(base + 0x3F5A)) /* Address match table end */
-#define APBASE(base) ((vuint16 *)(base + 0x3F5C)) /* Address match parameter */
-#define FLBASE(base) ((vuint32 *)(base + 0x3F54)) /* First-level table base */
-#define SLBASE(base) ((vuint32 *)(base + 0x3F58)) /* Second-level table base */
-#define FLMASK(base) ((vuint16 *)(base + 0x3F5C)) /* First-level mask */
-#define ECSIZE(base) ((vuint16 *)(base + 0x3F5E)) /* Valid for extended mode */
-#define APCT_REAL(base) ((vuint32 *)(base + 0x3F60)) /* APC 32 bit counter */
-#define R_PTR(base) ((vuint32 *)(base + 0x3F64)) /* Do not write to */
-#define RTEMP(base) ((vuint32 *)(base + 0x3F68)) /* Do not write to */
-#define T_PTR(base) ((vuint32 *)(base + 0x3F6C)) /* Do not write to */
-#define TTEMP(base) ((vuint32 *)(base + 0x3F70)) /* Do not write to */
-
-/* ESAR registers */
-#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80)) /* Perf.Mon.Timestamp */
-#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84)) /* Perf.Mon.Template */
-#define PMPTR(base) ((vuint16 *)(base + 0x3F88)) /* Perf.Mon.Table */
-#define PMCHANNEL(base) ((vuint16 *)(base + 0x3F8A)) /* Perf.Mon.Channel */
-#define MPHYST(base) ((vuint16 *)(base + 0x3F90)) /* Multi-PHY Status */
-#define TCTEBASE(base) ((vuint16 *)(base + 0x3F92)) /* Internal TCT Extension Base */
-#define ETCTEBASE(base) ((vuint32 *)(base + 0x3F94)) /* External TCT Extension Base */
-#define COMM_CH2(base) ((vuint32 *)(base + 0x3F98)) /* 2nd command channel word */
-#define STATBASE(base) ((vuint16 *)(base + 0x3F9C)) /* Statistics table pointer */
-
-/* UTOPIA Mode Register */
-#define UTMODE(base) (CAST(vuint32 *)(base + 0x0978))
-
-/* SAR commands */
-#define TRANSMIT_CHANNEL_ACTIVATE_CMD 0x0FC1
-#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1
-#define STOP_TRANSMIT_CMD 0x2FC1
-#define RESTART_TRANSMIT_CMD 0x3FC1
-#define STOP_RECEIVE_CMD 0x4FC1
-#define RESTART_RECEIVE_CMD 0x5FC1
-#define APC_BYPASS_CMD 0x6FC1
-#define MEM_WRITE_CMD 0x7FC1
-#define CPCR_FLG 0x0001
-
-/* INT flags */
-#define INT_VALID 0x80000000
-#define INT_WRAP 0x40000000
-#define INT_APCO 0x00800000
-#define INT_TQF 0x00200000
-#define INT_RXF 0x00080000
-#define INT_BSY 0x00040000
-#define INT_TXB 0x00020000
-#define INT_RXB 0x00010000
-
-#define NUM_INT_ENTRIES 80
-#define SIZE_OF_INT_ENTRY 4
-
-struct apc_params_t {
- vuint16 apct_base1; /* APC Table - First Priority Base pointer */
- vuint16 apct_end1; /* First APC Table - Length */
- vuint16 apct_ptr1; /* First APC Table Pointer */
- vuint16 apct_sptr1; /* APC Table First Priority Service pointer */
- vuint16 etqbase; /* Enhanced Transmit Queue Base pointer */
- vuint16 etqend; /* Enhanced Transmit Queue End pointer */
- vuint16 etqaptr; /* Enhanced Transmit Queue APC pointer */
- vuint16 etqtptr; /* Enhanced Transmit Queue Transmitter pointer */
- vuint16 apc_mi; /* APC - Max Iteration */
- vuint16 ncits; /* Number of Cells In TimeSlot */
- vuint16 apcnt; /* APC - N Timer */
- vuint16 reserved1; /* reserved */
- vuint16 eapcst; /* APC status */
- vuint16 ptp_counter; /* PTP queue length */
- vuint16 ptp_txch; /* PTP channel */
- vuint16 reserved2; /* reserved */
-};
-
-struct ct_entry_t {
- /* RCT */
- unsigned fhnt:1;
- unsigned pm_rct:1;
- unsigned reserved0:6;
- unsigned hec:1;
- unsigned clp:1;
- unsigned cng_ncrc:1;
- unsigned inf_rct:1;
- unsigned cngi_ptp:1;
- unsigned cdis_rct:1;
- unsigned aal_rct:2;
- uint16 rbalen;
- uint32 rcrc;
- uint32 rb_ptr;
- uint16 rtmlen;
- uint16 rbd_ptr;
- uint16 rbase;
- uint16 tstamp;
- uint16 imask;
- unsigned ft:2;
- unsigned nim:1;
- unsigned reserved1:2;
- unsigned rpmt:6;
- unsigned reserved2:5;
- uint8 reserved3[8];
- /* TCT */
- unsigned reserved4:1;
- unsigned pm_tct:1;
- unsigned reserved5:6;
- unsigned pc:1;
- unsigned reserved6:2;
- unsigned inf_tct:1;
- unsigned cr10:1;
- unsigned cdis_tct:1;
- unsigned aal_tct:2;
- uint16 tbalen;
- uint32 tcrc;
- uint32 tb_ptr;
- uint16 ttmlen;
- uint16 tbd_ptr;
- uint16 tbase;
- unsigned reserved7:5;
- unsigned tpmt:6;
- unsigned reserved8:3;
- unsigned avcf:1;
- unsigned act:1;
- uint32 chead;
- uint16 apcl;
- uint16 apcpr;
- unsigned out:1;
- unsigned bnr:1;
- unsigned tservice:2;
- unsigned apcp:12;
- uint16 apcpf;
-};
-
-struct tcte_entry_t {
- unsigned res1:4;
- unsigned scr:12;
- uint16 scrf;
- uint16 bt;
- uint16 buptrh;
- uint32 buptrl;
- unsigned vbr2:1;
- unsigned res2:15;
- uint16 oobr;
- uint16 res3[8];
-};
-
-#define SIZE_OF_RBD 12
-#define SIZE_OF_TBD 12
-
-struct atm_bd_t {
- vuint16 flags;
- vuint16 length;
- unsigned char *buffer_ptr;
- vuint16 cpcs_uu_cpi;
- vuint16 reserved;
-};
-
-/* BD flags */
-#define EMPTY 0x8000
-#define READY 0x8000
-#define WRAP 0x2000
-#define INTERRUPT 0x1000
-#define LAST 0x0800
-#define FIRST 0x0400
-#define OAM 0x0400
-#define CONTINUOUS 0x0200
-#define HEC_ERROR 0x0080
-#define CELL_LOSS 0x0040
-#define CONGESTION 0x0020
-#define ABORT 0x0010
-#define LEN_ERROR 0x0002
-#define CRC_ERROR 0x0001
-
-struct atm_connection_t {
- struct atm_bd_t *rbd_ptr;
- int num_rbd;
- struct atm_bd_t *tbd_ptr;
- int num_tbd;
- struct ct_entry_t *ct_ptr;
- struct tcte_entry_t *tcte_ptr;
- void *drv;
- void (*notify) (void *drv, int event);
-};
-
-struct atm_driver_t {
- int loaded;
- int started;
- char *csram;
- int csram_size;
- uint32 *am_top;
- uint16 *ap_top;
- uint32 *int_reload_ptr;
- uint32 *int_serv_ptr;
- struct atm_bd_t *rbd_base_ptr;
- struct atm_bd_t *tbd_base_ptr;
- unsigned linerate_in_bps;
-};
-
-extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
-extern struct atm_driver_t g_atm;
-
-extern int atmLoad (void);
-extern void atmUnload (void);
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size;
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-
- value = addr[0];
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- net/libnet.o (.text*)
- drivers/rtc/librtc.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common $(obj)../../tqc/tqm8xx)
-endif
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \
- ../../tqc/tqm8xx/load_sernum_ethaddr.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Flash Routines for AMD devices on the TQM8260 board
- *
- *--------------------------------------------------------------------
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#define V_ULONG(a) (*(volatile unsigned long *)( a ))
-#define V_BYTE(a) (*(volatile unsigned char *)( a ))
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-/*-----------------------------------------------------------------------
- */
-void flash_reset (void)
-{
- if (flash_info[0].flash_id != FLASH_UNKNOWN) {
- V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
- V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_get_size (ulong baseaddr, flash_info_t * info)
-{
- short i;
- unsigned long flashtest_h, flashtest_l;
-
- /* Write auto select command sequence and test FLASH answer */
- V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
- V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
- V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
- V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
-
- flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */
- flashtest_l = V_ULONG (baseaddr + 4);
-
- switch ((int) flashtest_h) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- flashtest_h = V_ULONG (baseaddr + 8); /* device ID */
- flashtest_l = V_ULONG (baseaddr + 12);
- if (flashtest_h != flashtest_l) {
- info->flash_id = FLASH_UNKNOWN;
- } else {
- switch (flashtest_h) {
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00400000;
- break; /* 4 * 1 MB = 4 MB */
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00400000;
- break; /* 4 * 1 MB = 4 MB */
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00800000;
- break; /* 4 * 2 MB = 8 MB */
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00800000;
- break; /* 4 * 2 MB = 8 MB */
- case AMD_ID_DL322T:
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x01000000;
- break; /* 4 * 4 MB = 16 MB */
- case AMD_ID_DL322B:
- info->flash_id += FLASH_AMDL322B;
- info->sector_count = 71;
- info->size = 0x01000000;
- break; /* 4 * 4 MB = 16 MB */
- case AMD_ID_DL323T:
- info->flash_id += FLASH_AMDL323T;
- info->sector_count = 71;
- info->size = 0x01000000;
- break; /* 4 * 4 MB = 16 MB */
- case AMD_ID_DL323B:
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x01000000;
- break; /* 4 * 4 MB = 16 MB */
- case AMD_ID_LV640U:
- info->flash_id += FLASH_AM640U;
- info->sector_count = 128;
- info->size = 0x02000000;
- break; /* 4 * 8 MB = 32 MB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* no or unknown flash */
- }
- }
-
- if (flashtest_h == AMD_ID_LV640U) {
-
- /* set up sector start adress table (uniform sector type) */
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = baseaddr + (i * 0x00040000);
-
- } else if (info->flash_id & FLASH_BTYPE) {
-
- /* set up sector start adress table (bottom sector type) */
- info->start[0] = baseaddr + 0x00000000;
- info->start[1] = baseaddr + 0x00010000;
- info->start[2] = baseaddr + 0x00018000;
- info->start[3] = baseaddr + 0x00020000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
- }
-
- } else {
-
- /* set up sector start adress table (top sector type) */
- i = info->sector_count - 1;
- info->start[i--] = baseaddr + info->size - 0x00010000;
- info->start[i--] = baseaddr + info->size - 0x00018000;
- info->start[i--] = baseaddr + info->size - 0x00020000;
- for (; i >= 0; i--) {
- info->start[i] = baseaddr + i * 0x00040000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
- (V_ULONG (info->start[i] + 20) & 0x00010001)) {
- info->protect[i] = 1; /* D0 = 1 if protected */
- } else {
- info->protect[i] = 0;
- }
- }
-
- flash_reset ();
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size_b0 = 0;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here (only one bank) */
-
- size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 >> 20);
- }
-
- /*
- * protect monitor and environment sectors
- */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf ("FUJITSU ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM800T:
- printf ("29LV800T (8 M, top sector)\n");
- break;
- case FLASH_AM800B:
- printf ("29LV800T (8 M, bottom sector)\n");
- break;
- case FLASH_AM160T:
- printf ("29LV160T (16 M, top sector)\n");
- break;
- case FLASH_AM160B:
- printf ("29LV160B (16 M, bottom sector)\n");
- break;
- case FLASH_AMDL322T:
- printf ("29DL322T (32 M, top sector)\n");
- break;
- case FLASH_AMDL322B:
- printf ("29DL322B (32 M, bottom sector)\n");
- break;
- case FLASH_AMDL323T:
- printf ("29DL323T (32 M, top sector)\n");
- break;
- case FLASH_AMDL323B:
- printf ("29DL323B (32 M, bottom sector)\n");
- break;
- case FLASH_AM640U:
- printf ("29LV640D (64 M, uniform sector)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
- udelay (1000);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- V_ULONG (info->start[sect]) = 0x00300030;
- V_ULONG (info->start[sect] + 4) = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
- (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
- {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- flash_reset ();
-
- printf (" done\n");
- return 0;
-}
-
-static int write_dword (flash_info_t *, ulong, unsigned char *);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong dp;
- static unsigned char bb[8];
- int i, l, rc, cc = cnt;
-
- dp = (addr & ~7); /* get lower dword aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - dp) != 0) {
- for (i = 0; i < 8; i++)
- bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
- if ((rc = write_dword (info, dp, bb)) != 0) {
- return (rc);
- }
- dp += 8;
- cc -= 8 - l;
- }
-
- /*
- * handle word aligned part
- */
- while (cc >= 8) {
- if ((rc = write_dword (info, dp, src)) != 0) {
- return (rc);
- }
- dp += 8;
- src += 8;
- cc -= 8;
- }
-
- if (cc <= 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- for (i = 0; i < 8; i++) {
- bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
- }
- return (write_dword (info, dp, bb));
-}
-
-/*-----------------------------------------------------------------------
- * Write a dword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
-{
- ulong start, cl, ch;
- int flag, i;
-
- for (ch = 0, i = 0; i < 4; i++)
- ch = (ch << 8) + *pdata++; /* high word */
- for (cl = 0, i = 0; i < 4; i++)
- cl = (cl << 8) + *pdata++; /* low word */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *) dest) & ch) != ch
- || (*((vu_long *) (dest + 4)) & cl) != cl) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
- V_ULONG (dest) = ch;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
- V_ULONG (dest + 4) = cl;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
- ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <mpc8260.h>
-#include <common.h>
-#include "../common/fpga.h"
-
-fpga_t fpga_list[] = {
- {"FIOX", CONFIG_SYS_FIOX_BASE,
- CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE}
- ,
- {"FDOHM", CONFIG_SYS_FDOHM_BASE,
- CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE}
-};
-int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
-
-
-ulong fpga_control (fpga_t * fpga, int cmd)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- switch (cmd) {
- case FPGA_INIT_IS_HIGH:
- immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
- return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;
-
- case FPGA_INIT_SET_LOW:
- immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
- immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
- break;
-
- case FPGA_INIT_SET_HIGH:
- immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
- immr->im_ioport.iop_pdatd |= fpga->init_mask;
- break;
-
- case FPGA_PROG_SET_LOW:
- immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
- break;
-
- case FPGA_PROG_SET_HIGH:
- immr->im_ioport.iop_pdatd |= fpga->prog_mask;
- break;
-
- case FPGA_DONE_IS_HIGH:
- return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;
-
- case FPGA_READ_MODE:
- break;
-
- case FPGA_LOAD_MODE:
- break;
-
- case FPGA_GET_ID:
- if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) {
- ulong ver =
- *(volatile ulong *) (fpga->conf_base + 0x10);
- return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
- } else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) {
- return (*(volatile ushort *) fpga->conf_base) & 0xff;
- } else {
- return *(volatile ulong *) fpga->conf_base;
- }
-
- case FPGA_INIT_PORTS:
- immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
- immr->im_ioport.iop_psord &= ~fpga->init_mask;
- immr->im_ioport.iop_pdird &= ~fpga->init_mask;
-
- immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
- immr->im_ioport.iop_psord &= ~fpga->prog_mask;
- immr->im_ioport.iop_pdird |= fpga->prog_mask;
-
- immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
- immr->im_ioport.iop_psord &= ~fpga->done_mask;
- immr->im_ioport.iop_pdird &= ~fpga->done_mask;
-
- break;
-
- }
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <linux/compiler.h>
-
-#include "scm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void config_scoh_cs(void);
-extern int fpga_init(void);
-
-#if 0
-#define DEBUGF(fmt,args...) printf (fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 1, 0, 0 },
- /* PA24 */ { 0, 0, 0, 1, 0, 0 },
- /* PA23 */ { 0, 0, 0, 1, 0, 0 },
- /* PA22 */ { 0, 0, 0, 1, 0, 0 },
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 1, 0, 0 },
- /* PA12 */ { 0, 0, 0, 1, 0, 0 },
- /* PA11 */ { 0, 0, 0, 1, 0, 0 },
- /* PA10 */ { 0, 0, 0, 1, 0, 0 },
- /* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */
- /* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */
- /* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */
- /* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */
- /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */
- /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */
- /* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */
- /* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */
- /* PA1 */ { 0, 0, 0, 1, 0, 0 },
- /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */
- /* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */
- /* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */
- /* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */
- /* PB27 */ { 0, 1, 0, 0, 0, 0 },
- /* PB26 */ { 0, 1, 0, 0, 0, 0 },
- /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */
- /* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */
- /* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */
- /* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */
- /* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */
- /* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */
- /* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */
- /* PB18 */ { 0, 1, 0, 0, 0, 0 },
- /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
- /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
- /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
- /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
- /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
- /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
- /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
- /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
- /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
- /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
- /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
- /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
- /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
- /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */
- /* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */
- /* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */
- /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */
- /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */
- /* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 },
- /* PC24 */ { 0, 0, 0, 1, 0, 0 },
- /* PC23 */ { 0, 1, 0, 1, 0, 0 },
- /* PC22 */ { 0, 1, 0, 0, 0, 0 },
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
- /* PC19 */ { 0, 1, 0, 0, 0, 0 },
- /* PC18 */ { 0, 1, 0, 0, 0, 0 },
- /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
- /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
- /* PC15 */ { 0, 0, 0, 1, 0, 0 },
- /* PC14 */ { 0, 1, 0, 0, 0, 0 },
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */
- /* PC12 */ { 0, 0, 0, 1, 0, 0 },
- /* PC11 */ { 0, 0, 0, 1, 0, 0 },
- /* PC10 */ { 0, 0, 0, 1, 0, 0 },
- /* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 },
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */
- /* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */
- },
-
- /* Port D configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */
- /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 },
- /* PD24 */ { 0, 0, 0, 1, 0, 0 },
- /* PD23 */ { 0, 0, 0, 1, 0, 0 },
- /* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */
- /* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */
- /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
- /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */
- /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */
- /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */
- /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */
-#if defined(CONFIG_SOFT_I2C)
- /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#else /* normal I/O port pins */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#endif
-#endif
- /* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */
- /* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */
- /* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */
- /* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 },
- /* PD6 */ { 0, 0, 0, 1, 0, 1 },
- /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */
- /* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof (str));
-
- puts ("Board: ");
-
- if (!i || strncmp (str, "TQM8260", 7)) {
- puts ("### No HW ID - assuming TQM8260\n");
- return (0);
- }
-
- puts (str);
- putc ('\n');
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff)) / 2;
-
- /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
- * we are configuring CS1 if base != 0
- */
- sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
- orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
-
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-/*
- * Test Power-On-Reset.
- */
-int power_on_reset (void)
-{
- /* Test Reset Status Register */
- return gd->reset_status & RSR_CSRS ? 0 : 1;
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
- long size8, size9;
-#endif
- long psize, lsize;
-
- psize = 16 * 1024 * 1024;
- lsize = 0;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#if 0 /* Just for debugging */
-#define prt_br_or(brX,orX) do { \
- ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
- ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
- printf ("\n" \
- #brX " 0x%08x " #orX " 0x%08x " \
- "==> 0x%08lx ... 0x%08lx = %ld MB\n", \
- memctl->memc_ ## brX, memctl->memc_ ## orX, \
- start, start+sizem, (sizem+1)>>20); \
- } while (0)
- prt_br_or (br0, or0);
- prt_br_or (br1, or1);
- prt_br_or (br2, or2);
- prt_br_or (br3, or3);
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* 60x SDRAM setup:
- */
- size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-
- if (size8 < size9) {
- psize = size9;
- printf ("(60x:9COL - %ld MB, ", psize >> 20);
- } else {
- psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- printf ("(60x:8COL - %ld MB, ", psize >> 20);
- }
-
- /* Local SDRAM setup:
- */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
- size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) SDRAM_BASE2_PRELIM);
- size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
- (uchar *) SDRAM_BASE2_PRELIM);
-
- if (size8 < size9) {
- lsize = size9;
- printf ("Local:9COL - %ld MB) using ", lsize >> 20);
- } else {
- lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) SDRAM_BASE2_PRELIM);
- printf ("Local:8COL - %ld MB) using ", lsize >> 20);
- }
-
-#if 0
- /* Set up BR2 so that the local SDRAM goes
- * right after the 60x SDRAM
- */
- memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
- (CONFIG_SYS_SDRAM_BASE + psize);
-#endif
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-#endif /* CONFIG_SYS_RAMBOOT */
-
- icache_enable ();
-
- config_scoh_cs ();
-
- return (psize);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void config_scoh_cs (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immr->im_memctl;
- volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE;
- __maybe_unused volatile uint tmp, i;
-
- /* Initialize OR3 / BR3 for CAN Bus Controller 0 */
- memctl->memc_or3 = CONFIG_SYS_CAN0_OR3;
- memctl->memc_br3 = CONFIG_SYS_CAN0_BR3;
- /* Initialize OR4 / BR4 for CAN Bus Controller 1 */
- memctl->memc_or4 = CONFIG_SYS_CAN1_OR4;
- memctl->memc_br4 = CONFIG_SYS_CAN1_BR4;
-
- /* Initialize MAMR to write in the array at address 0x0 */
- memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
-
- /* Initialize UPMA for CAN: single read */
- memctl->memc_mdr = 0xcffeec00;
- udelay (1); /* Necessary to have the data correct in the UPM array!!!! */
- /* The read on the CAN controller write the data of mdr in UPMA array. */
- /* The index to the array will be incremented automatically
- through this read */
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x0ffcec00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x0ffcec00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x0ffcec00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x0ffcec00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x0ffcfc00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x0ffcfc00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0xfffdec07;
- udelay (1);
- tmp = can->cpu_interface;
-
-
- /* Initialize MAMR to write in the array at address 0x18 */
- memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
-
- /* Initialize UPMA for CAN: single write */
- memctl->memc_mdr = 0xfcffec00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x00ffec00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x00ffec00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x00ffec00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x00ffec00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x00fffc00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x00fffc00;
- udelay (1);
- tmp = can->cpu_interface;
-
- memctl->memc_mdr = 0x30ffec07;
- udelay (1);
- tmp = can->cpu_interface;
-
- /* Initialize MAMR */
- memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */
-
-
- /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
- memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5;
- memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5;
- /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
- memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6;
- memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6;
-
- /* Initialize OR7 / BR7 for the Glue Logic */
- memctl->memc_or7 = CONFIG_SYS_FIOX_OR7;
- memctl->memc_br7 = CONFIG_SYS_FIOX_BR7;
-
- /* Initialize OR8 / BR8 for the DOH Logic */
- memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8;
- memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8;
-
- DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
- DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
- DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
- DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
- DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
- DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
- DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
- DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
- DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
-
- DEBUGF ("UPMA addr 0x0\n");
- memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
- for (i = 0; i < 0x8; i++) {
- tmp = can->cpu_interface;
- udelay (1);
- DEBUGF (" %08x ", memctl->memc_mdr);
- }
- DEBUGF ("\nUPMA addr 0x18\n");
- memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
- for (i = 0; i < 0x8; i++) {
- tmp = can->cpu_interface;
- udelay (1);
- DEBUGF (" %08x ", memctl->memc_mdr);
- }
- DEBUGF ("\n");
- memctl->memc_mamr = MxMR_GPL_x4DIS;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r (void)
-{
- fpga_init ();
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SCM_H
-#define __SCM_H
-
-/*----------------*/
-/* CAN Structures */
-/*----------------*/
-
-/* Message */
-struct can_msg {
- uchar ctrl_0;
- uchar ctrl_1;
- uchar arbit_0;
- uchar arbit_1;
- uchar arbit_2;
- uchar arbit_3;
- uchar config;
- uchar data[8];
-} __attribute__ ((packed));
-
-typedef struct can_msg can_msg_t;
-
-/* CAN Register */
-typedef struct can_reg {
- uchar ctrl;
- uchar status;
- uchar cpu_interface;
- uchar resv0;
- ushort high_speed_rd;
- ushort gbl_mask_std;
- uint gbl_mask_extd;
- uint msg15_mask;
- can_msg_t msg1;
- uchar clkout;
- can_msg_t msg2;
- uchar bus_config;
- can_msg_t msg3;
- uchar bit_timing_0;
- can_msg_t msg4;
- uchar bit_timing_1;
- can_msg_t msg5;
- uchar interrupt;
- can_msg_t msg6;
- uchar resv1;
- can_msg_t msg7;
- uchar resv2;
- can_msg_t msg8;
- uchar resv3;
- can_msg_t msg9;
- uchar p1conf;
- can_msg_t msg10;
- uchar p2conf;
- can_msg_t msg11;
- uchar p1in;
- can_msg_t msg12;
- uchar p2in;
- can_msg_t msg13;
- uchar p1out;
- can_msg_t msg14;
- uchar p2out;
- can_msg_t msg15;
- uchar ser_res_addr;
- uchar resv_cs[0x8000-0x100]; /* 0x8000 is the min size for CS */
-} can_reg_t;
-
-
-#endif /* __SCM_H */
+++ /dev/null
-CCM/SCM-Ergaenzungen fuer U-Boot und Linux:
--------------------------------------------
-
-Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs:
-
- => help fpga
- fpga fpga status [name] - print FPGA status
- fpga reset [name] - reset FPGA
- fpga load [name] addr - load FPGA configuration data
-
-Der Name kann beim CCM-Module auch weggelassen werden.
-Die Laengenangabe und damit "puma_len" ist nicht mehr
-noetig:
-
- => fpga load puma 40600000
- FPGA load PUMA: addr 40600000: (00000005)... done
-
-Die MTD-Partitionierung kann nun mittels "bootargs" ueber-
-geben werden:
-
- => printenv addmtd
- addmtd=setenv bootargs ${bootargs}
- mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2)
-
-Die Portierung auf SMC ist natuerlich noch nicht getestet.
-
-Wolfgang Grandegger (04.06.2002)
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <common.h>
-
-#include "fpga.h"
-
-int power_on_reset(void);
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-
-static int fpga_get_version(fpga_t* fpga, char* name)
-{
- char vname[12];
- /*
- * Net-list string format:
- * "vvvvvvvvddddddddn...".
- * Version Date Name
- * "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
- */
- if (strlen(name) < (16 + strlen(fpga->name)))
- goto failure;
- /* Check FPGA name */
- if (strcmp(&name[16], fpga->name) != 0)
- goto failure;
- /* Get version number */
- memcpy(vname, name, 8);
- vname[8] = '\0';
- return simple_strtoul(vname, NULL, 16);
-
- failure:
- printf("Image name %s is invalid\n", name);
- return -1;
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static fpga_t* fpga_get(char* fpga_name)
-{
- char name[FPGA_NAME_LEN];
- int i;
-
- if (strlen(fpga_name) >= FPGA_NAME_LEN)
- goto failure;
- for (i = 0; i < strlen(fpga_name); i++)
- name[i] = toupper(fpga_name[i]);
- name[i] = '\0';
- for (i = 0; i < fpga_count; i++) {
- if (strcmp(name, fpga_list[i].name) == 0)
- return &fpga_list[i];
- }
- failure:
- printf("FPGA: name %s is invalid\n", fpga_name);
- return NULL;
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static void fpga_status (fpga_t* fpga)
-{
- /* Check state */
- if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
- printf ("%s is loaded (%08lx)\n",
- fpga->name, fpga_control(fpga, FPGA_GET_ID));
- else
- printf ("%s is NOT loaded\n", fpga->name);
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
-
-static int fpga_reset (fpga_t* fpga)
-{
- int i;
-
- /* Set PROG to low and wait til INIT goes low */
- fpga_control(fpga, FPGA_PROG_SET_LOW);
- for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
- udelay (100);
- if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
- break;
- }
- if (i == FPGA_RESET_TIMEOUT)
- goto failure;
-
- /* Set PROG to high and wait til INIT goes high */
- fpga_control(fpga, FPGA_PROG_SET_HIGH);
- for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
- udelay (100);
- if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
- break;
- }
- if (i == FPGA_RESET_TIMEOUT)
- goto failure;
-
- return 0;
- failure:
- return 1;
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
-
-static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
-{
- volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
- image_header_t *hdr = (image_header_t *)addr;
- ulong len;
- uchar *data;
- char msg[32];
- int verify, i;
-
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- /*
- * Check the image header and data of the net-list
- */
- if (!image_check_magic (hdr)) {
- strcpy (msg, "Bad Image Magic Number");
- goto failure;
- }
-
- if (!image_check_hcrc (hdr)) {
- strcpy (msg, "Bad Image Header CRC");
- goto failure;
- }
-
- data = (uchar*)image_get_data (hdr);
- len = image_get_data_size (hdr);
-
- verify = getenv_yesno ("verify");
- if (verify) {
- if (!image_check_dcrc (hdr)) {
- strcpy (msg, "Bad Image Data CRC");
- goto failure;
- }
- }
-
- if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0)
- return 1;
-
- /* align length */
- if (len & 1)
- ++len;
-
- /*
- * Reset FPGA and wait for completion
- */
- if (fpga_reset(fpga)) {
- strcpy (msg, "Reset Timeout");
- goto failure;
- }
-
- printf ("(%s)... ", image_get_name (hdr));
- /*
- * Copy data to FPGA
- */
- fpga_control (fpga, FPGA_LOAD_MODE);
- while (len--) {
- *fpga_addr = *data++;
- }
- fpga_control (fpga, FPGA_READ_MODE);
-
- /*
- * Wait for completion and check error status if timeout
- */
- for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
- udelay (100);
- if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
- break;
- }
- if (i == FPGA_LOAD_TIMEOUT) {
- if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
- strcpy(msg, "Invalid Size");
- else
- strcpy(msg, "CRC Error");
- goto failure;
- }
-
- printf("done\n");
- return 0;
-
- failure:
-
- printf("ERROR: %s\n", msg);
- return 1;
-}
-
-#if defined(CONFIG_CMD_BSP)
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr = 0;
- int i;
- fpga_t* fpga;
-
- if (argc < 2)
- goto failure;
-
- if (strncmp(argv[1], "stat", 4) == 0) { /* status */
- if (argc == 2) {
- for (i = 0; i < fpga_count; i++) {
- fpga_status (&fpga_list[i]);
- }
- }
- else if (argc == 3) {
- if ((fpga = fpga_get(argv[2])) == 0)
- goto failure;
- fpga_status (fpga);
- }
- else
- goto failure;
- }
- else if (strcmp(argv[1],"load") == 0) { /* load */
- if (argc == 3 && fpga_count == 1) {
- fpga = &fpga_list[0];
- }
- else if (argc == 4) {
- if ((fpga = fpga_get(argv[2])) == 0)
- goto failure;
- }
- else
- goto failure;
-
- addr = simple_strtoul(argv[argc-1], NULL, 16);
-
- printf ("FPGA load %s: addr %08lx: ",
- fpga->name, addr);
- fpga_load (fpga, addr, 1);
-
- }
- else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */
- if (argc == 2 && fpga_count == 1) {
- fpga = &fpga_list[0];
- }
- else if (argc == 3) {
- if ((fpga = fpga_get(argv[2])) == 0)
- goto failure;
- }
- else
- goto failure;
-
- printf ("FPGA reset %s: ", fpga->name);
- if (fpga_reset(fpga))
- printf ("ERROR: Timeout\n");
- else
- printf ("done\n");
- }
- else
- goto failure;
-
- return 0;
-
- failure:
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- fpga, 4, 1, do_fpga,
- "access FPGA(s)",
- "fpga status [name] - print FPGA status\n"
- "fpga reset [name] - reset FPGA\n"
- "fpga load [name] addr - load FPGA configuration data"
-);
-
-#endif
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-int fpga_init (void)
-{
- ulong addr;
- ulong new_id, old_id = 0;
- image_header_t *hdr;
- fpga_t* fpga;
- int do_load, i, j;
- char name[16], *s;
-
- /*
- * Port setup for FPGA control
- */
- for (i = 0; i < fpga_count; i++) {
- fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
- }
-
- /*
- * Load FPGA(s): a new net-list is loaded if the FPGA is
- * empty, Power-on-Reset or the old one is not up-to-date
- */
- for (i = 0; i < fpga_count; i++) {
- fpga = &fpga_list[i];
- printf ("%s: ", fpga->name);
-
- for (j = 0; j < strlen(fpga->name); j++)
- name[j] = tolower(fpga->name[j]);
- name[j] = '\0';
- sprintf(name, "%s_addr", name);
- addr = 0;
- if ((s = getenv(name)) != NULL)
- addr = simple_strtoul(s, NULL, 16);
-
- if (!addr) {
- printf ("env. variable %s undefined\n", name);
- return 1;
- }
-
- hdr = (image_header_t *)addr;
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- if ((new_id = fpga_get_version(fpga, image_get_name (hdr))) == -1)
- return 1;
-
- do_load = 1;
-
- if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
- old_id = fpga_control(fpga, FPGA_GET_ID);
- if (new_id == old_id)
- do_load = 0;
- }
-
- if (do_load) {
- printf ("loading ");
- fpga_load (fpga, addr, 0);
- } else {
- printf ("loaded (%08lx)\n", old_id);
- }
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#ifndef _FPGA_H_
-#define _FPGA_H_
-
-#define FPGA_INIT_IS_HIGH 0
-#define FPGA_INIT_SET_HIGH 1
-#define FPGA_INIT_SET_LOW 2
-#define FPGA_PROG_SET_HIGH 3
-#define FPGA_PROG_SET_LOW 4
-#define FPGA_DONE_IS_HIGH 5
-#define FPGA_READ_MODE 6
-#define FPGA_LOAD_MODE 7
-#define FPGA_GET_ID 8
-#define FPGA_INIT_PORTS 9
-
-#define FPGA_NAME_LEN 8
-typedef struct {
- char name[FPGA_NAME_LEN];
- ulong conf_base;
- uint init_mask;
- uint prog_mask;
- uint done_mask;
-} fpga_t;
-
-extern fpga_t fpga_list[];
-extern int fpga_count;
-
-ulong fpga_control (fpga_t* fpga, int cmd);
-
-#endif /* _FPGA_H_ */
return 0;
}
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ char safe_string[HDR_NAME_LEN + 1];
+
+ /* Now set variables based on the header. */
+ strncpy(safe_string, (char *)header.name, sizeof(header.name));
+ safe_string[sizeof(header.name)] = 0;
+ setenv("board_name", safe_string);
+
+ strncpy(safe_string, (char *)header.version, sizeof(header.version));
+ safe_string[sizeof(header.version)] = 0;
+ setenv("board_rev", safe_string);
+#endif
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_DRIVER_TI_CPSW
static void cpsw_control(int enabled)
{
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2012
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
drivers/net/libnet.o (.text*)
drivers/pcmcia/libpcmcia.o (.text.pcmcia_on)
drivers/pcmcia/libpcmcia.o (.text.pcmcia_hardware_enable)
- drivers/rtc/librtc.o (.text*)
- drivers/misc/libmisc.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv*)
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o flash.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint edo_60ns[] =
-{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
- 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
- 0x8fffec24, 0x0ffbec04, 0x08f3ec04, 0x07f3ec08,
- 0x08f3ec04, 0x07f3ec48, 0x08f3ec04, 0x07f3ec48,
- 0x08f3ec04, 0x07f3ec48, 0x1ff7ec47, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
- 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- puts ("Board: AMX860\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */
-
- upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
-
-#ifndef CONFIG_AMX_RAM_EXT
- memctl->memc_mptpr = 0x0400; /* divide by 16 */
-#else
- memctl->memc_mptpr = 0x0200;
-#endif
-
- memctl->memc_mamr = 0x30a21114;
- memctl->memc_or2 = 0xffc00800;
-#ifndef CONFIG_AMX_RAM_EXT
- memctl->memc_br2 = 0x81;
-
- return (4 << 20);
-#else
- memctl->memc_or1 = 0xff000800;
- memctl->memc_br1 = 0x00000081;
- memctl->memc_br2 = 0x01000081;
-
- return (20 << 20);
-#endif
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
-#if defined(FLASH_BASE1_PRELIM) && (FLASH_BASE1_PRELIM != 0)
- DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
-
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-#else
- size_b1 = 0;
-#endif /* FLASH_BASE1_PRELIM */
-
- DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- DEBUGF ("## Before remap: "
- "BR0: 0x%08x OR0: 0x%08x "
- "BR1: 0x%08x OR1: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0,
- memctl->memc_br1, memctl->memc_or1);
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
- DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0);
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK);
- memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_V;
-
- DEBUGF("## BR1: 0x%08x OR1: 0x%08x\n",
- memctl->memc_br1, memctl->memc_or1);
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
-
- flash_info[1].size = size_b1;
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-# endif
-
-# ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[1]);
-#endif
- } else {
-#ifndef CONFIG_AMX_RAM_EXT
- memctl->memc_br1 = 0; /* invalidate bank */
- memctl->memc_or1 = 0; /* invalidate bank */
-#endif
-
- DEBUGF("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
- memctl->memc_br1, memctl->memc_or1);
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- flash_info[1].size = 0;
- }
-
- DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- /* set sector offsets for uniform sector type */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00040000);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-
- value = addr[0];
-
- DEBUGF("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- DEBUGF("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
- switch (value) {
- case AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- net/libnet.o (.text*)
- board/westel/amx860/libamx860.o (.text*)
- *(.text.*printf)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz
mgcoge powerpc mpc8260 km82xx keymile - km82xx:MGCOGE
mgcoge3ne powerpc mpc8260 km82xx keymile - km82xx:MGCOGE3NE
-SCM powerpc mpc8260 - siemens
TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz
TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz
TQM8260_AB powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x
AdderII powerpc mpc8xx adder - - Adder:MPC852T
AdderUSB powerpc mpc8xx adder - - Adder
ADS860 powerpc mpc8xx fads
-c2mon powerpc mpc8xx
cogent_mpc8xx powerpc mpc8xx cogent
-EP88x powerpc mpc8xx ep88x
ESTEEM192E powerpc mpc8xx esteem192e
-ETX094 powerpc mpc8xx etx094
FADS823 powerpc mpc8xx fads
FADS850SAR powerpc mpc8xx fads
FADS860T powerpc mpc8xx fads
IVMS8 powerpc mpc8xx ivm - - IVMS8:IVMS8_16M
IVMS8_128 powerpc mpc8xx ivm - - IVMS8:IVMS8_32M
IVMS8_256 powerpc mpc8xx ivm - - IVMS8:IVMS8_64M
-LANTEC powerpc mpc8xx lantec
lwmon powerpc mpc8xx
MBX powerpc mpc8xx mbx8xx
MBX860T powerpc mpc8xx mbx8xx
KUP4X powerpc mpc8xx kup4x kup
ELPT860 powerpc mpc8xx elpt860 LEOX
uc100 powerpc mpc8xx - manroland
-IAD210 powerpc mpc8xx - siemens
QS823 powerpc mpc8xx qs850 snmc
QS850 powerpc mpc8xx qs850 snmc
QS860T powerpc mpc8xx qs860t snmc
TTTech powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ104V7DS01
virtlab2 powerpc mpc8xx tqm8xx tqc
wtk powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ065T9DR51U
-AMX860 powerpc mpc8xx amx860 westel
csb272 powerpc ppc4xx
csb472 powerpc ppc4xx
G2000 powerpc ppc4xx g2000
COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
COBJS-$(CONFIG_CMD_EXT4) += cmd_ext4.o
COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
-ifdef CONFIG_CMD_EXT4
-COBJS-y += cmd_ext_common.o
-else
-COBJS-$(CONFIG_CMD_EXT2) += cmd_ext_common.o
-endif
COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o
COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
ifdef CONFIG_FPGA
COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
endif
+COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
/* Allow ports to override the default behavior */
__attribute__((weak))
-unsigned long do_go_exec (ulong (*entry)(int, char * const []), int argc, char * const argv[])
+unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+ char * const argv[])
{
return entry (argc, argv);
}
-int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_go(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, rc;
int rcode = 0;
bootm_headers_t images; /* pointers to os/initrd/fdt images */
/* Allow for arch specific config before we boot */
-void __arch_preboot_os(void)
+static void __arch_preboot_os(void)
{
/* please define platform specific arch_preboot_os() */
}
U_BOOT_CMD_MKENT(go, 0, 1, (void *)BOOTM_STATE_OS_GO, "", ""),
};
-int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc,
+static int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int ret = 0;
return (void *)img_addr;
}
-U_BOOT_CMD(
- bootm, CONFIG_SYS_MAXARGS, 1, do_bootm,
- "boot application image from memory",
+#ifdef CONFIG_SYS_LONGHELP
+static char bootm_help_text[] =
"[addr [arg ...]]\n - boot application image stored in memory\n"
"\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
"\t'arg' can be the address of an initrd image\n"
"\tcmdline - OS specific command line processing/setup\n"
"\tbdt - OS specific bd_t processing\n"
"\tprep - OS specific prep before relocation or go\n"
- "\tgo - start OS"
+ "\tgo - start OS";
+#endif
+
+U_BOOT_CMD(
+ bootm, CONFIG_SYS_MAXARGS, 1, do_bootm,
+ "boot application image from memory", bootm_help_text
);
/*******************************************************************/
/* iminfo - print header info for a requested image */
/*******************************************************************/
#if defined(CONFIG_CMD_IMI)
-int do_iminfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_iminfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int arg;
ulong addr;
/* imls - list all images found in flash */
/*******************************************************************/
#if defined(CONFIG_CMD_IMLS)
-int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
flash_info_t *info;
int i, j;
return 1;
}
-U_BOOT_CMD(
- bootz, CONFIG_SYS_MAXARGS, 1, do_bootz,
- "boot Linux zImage image from memory",
+#ifdef CONFIG_SYS_LONGHELP
+static char bootz_help_text[] =
"[addr [initrd[:size]] [fdt]]\n"
" - boot Linux zImage stored in memory\n"
"\tThe argument 'initrd' is optional and specifies the address\n"
"\tuse a '-' for the second argument. If you do not pass a third\n"
"\ta bd_info struct will be passed instead\n"
#endif
+ "";
+#endif
+
+U_BOOT_CMD(
+ bootz, CONFIG_SYS_MAXARGS, 1, do_bootz,
+ "boot Linux zImage image from memory", bootz_help_text
);
#endif /* CONFIG_CMD_BOOTZ */
#include <stdio_dev.h>
extern void _do_coninfo (void);
-int do_coninfo (cmd_tbl_t * cmd, int flag, int argc, char * const argv[])
+static int do_coninfo(cmd_tbl_t *cmd, int flag, int argc, char * const argv[])
{
int l;
struct list_head *list = stdio_get_list();
int mk_date (const char *, struct rtc_time *);
-int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct rtc_time tm;
int rcode = 0;
#include <common.h>
#include <command.h>
-int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
int putnl = 1;
#include <common.h>
#include <command.h>
-int do_exit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_exit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int r;
/*
* Ext2fs support
*/
-#include <common.h>
-#include <ext_common.h>
+#include <fs.h>
int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (do_ext_ls(cmdtp, flag, argc, argv))
- return -1;
-
- return 0;
+ return do_ls(cmdtp, flag, argc, argv, FS_TYPE_EXT);
}
/******************************************************************************
*/
int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (do_ext_load(cmdtp, flag, argc, argv))
- return -1;
-
- return 0;
+ return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16);
}
U_BOOT_CMD(
"load binary file from a Ext2 filesystem",
"<interface> <dev[:part]> [addr] [filename] [bytes]\n"
" - load binary file 'filename' from 'dev' on 'interface'\n"
- " to address 'addr' from ext2 filesystem"
+ " to address 'addr' from ext2 filesystem.\n"
+ " All numeric parameters are assumed to be hex."
);
#include <image.h>
#include <linux/ctype.h>
#include <asm/byteorder.h>
-#include <ext_common.h>
#include <ext4fs.h>
#include <linux/stat.h>
#include <malloc.h>
+#include <fs.h>
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
#include <usb.h>
int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
- if (do_ext_load(cmdtp, flag, argc, argv))
- return -1;
-
- return 0;
+ return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16);
}
int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
- if (do_ext_ls(cmdtp, flag, argc, argv))
- return -1;
-
- return 0;
+ return do_ls(cmdtp, flag, argc, argv, FS_TYPE_EXT);
}
#if defined(CONFIG_CMD_EXT4_WRITE)
/* mount the filesystem */
if (!ext4fs_mount(info.size)) {
- printf("Bad ext4 partition %s %d:%lu\n", argv[1], dev, part);
+ printf("Bad ext4 partition %s %d:%d\n", argv[1], dev, part);
goto fail;
}
U_BOOT_CMD(ext4write, 6, 1, do_ext4_write,
"create a file in the root directory",
"<interface> <dev[:part]> [Absolute filename path] [Address] [sizebytes]\n"
- " - create a file in / directory");
+ " - create a file in / directory");
#endif
U_BOOT_CMD(ext4ls, 4, 1, do_ext4_ls,
"list files in a directory (default /)",
"<interface> <dev[:part]> [directory]\n"
- " - list files from 'dev' on 'interface' in a 'directory'");
+ " - list files from 'dev' on 'interface' in a 'directory'");
U_BOOT_CMD(ext4load, 6, 0, do_ext4_load,
"load binary file from a Ext4 filesystem",
"<interface> <dev[:part]> [addr] [filename] [bytes]\n"
- " - load binary file 'filename' from 'dev' on 'interface'\n"
- " to address 'addr' from ext4 filesystem");
+ " - load binary file 'filename' from 'dev' on 'interface'\n"
+ " to address 'addr' from ext4 filesystem.\n"
+ " All numeric parameters are assumed to be hex.");
+++ /dev/null
-/*
- * (C) Copyright 2011 - 2012 Samsung Electronics
- * EXT2/4 filesystem implementation in Uboot by
- * Uma Shankar <uma.shankar@samsung.com>
- * Manjunatha C Achar <a.manjunatha@samsung.com>
- *
- * Ext4fs support
- * made from existing cmd_ext2.c file of Uboot
- *
- * (C) Copyright 2004
- * esd gmbh <www.esd-electronics.com>
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * made from cmd_reiserfs by
- *
- * (C) Copyright 2003 - 2004
- * Sysgo Real-Time Solutions, AG <www.elinos.com>
- * Pavel Bartusek <pba@sysgo.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Changelog:
- * 0.1 - Newly created file for ext4fs support. Taken from cmd_ext2.c
- * file in uboot. Added ext4fs ls load and write support.
- */
-
-#include <common.h>
-#include <part.h>
-#include <config.h>
-#include <command.h>
-#include <image.h>
-#include <linux/ctype.h>
-#include <asm/byteorder.h>
-#include <ext_common.h>
-#include <ext4fs.h>
-#include <linux/stat.h>
-#include <malloc.h>
-
-#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
-#include <usb.h>
-#endif
-
-#if !defined(CONFIG_DOS_PARTITION) && !defined(CONFIG_EFI_PARTITION)
-#error DOS or EFI partition support must be selected
-#endif
-
-#define DOS_PART_MAGIC_OFFSET 0x1fe
-#define DOS_FS_TYPE_OFFSET 0x36
-#define DOS_FS32_TYPE_OFFSET 0x52
-
-int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
-{
- char *filename = NULL;
- int dev, part;
- ulong addr = 0;
- int filelen;
- disk_partition_t info;
- block_dev_desc_t *dev_desc;
- char buf[12];
- unsigned long count;
- const char *addr_str;
-
- count = 0;
- addr = simple_strtoul(argv[3], NULL, 16);
- filename = getenv("bootfile");
- switch (argc) {
- case 3:
- addr_str = getenv("loadaddr");
- if (addr_str != NULL)
- addr = simple_strtoul(addr_str, NULL, 16);
- else
- addr = CONFIG_SYS_LOAD_ADDR;
-
- break;
- case 4:
- break;
- case 5:
- filename = argv[4];
- break;
- case 6:
- filename = argv[4];
- count = simple_strtoul(argv[5], NULL, 16);
- break;
-
- default:
- return cmd_usage(cmdtp);
- }
-
- if (!filename) {
- puts("** No boot file defined **\n");
- return 1;
- }
-
- part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
- if (part < 0)
- return 1;
-
- dev = dev_desc->dev;
- printf("Loading file \"%s\" from %s device %d%c%c\n",
- filename, argv[1], dev,
- part ? ':' : ' ', part ? part + '0' : ' ');
-
- ext4fs_set_blk_dev(dev_desc, &info);
-
- if (!ext4fs_mount(info.size)) {
- printf("** Bad ext2 partition or disk - %s %d:%d **\n",
- argv[1], dev, part);
- ext4fs_close();
- goto fail;
- }
-
- filelen = ext4fs_open(filename);
- if (filelen < 0) {
- printf("** File not found %s\n", filename);
- ext4fs_close();
- goto fail;
- }
- if ((count < filelen) && (count != 0))
- filelen = count;
-
- if (ext4fs_read((char *)addr, filelen) != filelen) {
- printf("** Unable to read \"%s\" from %s %d:%d **\n",
- filename, argv[1], dev, part);
- ext4fs_close();
- goto fail;
- }
-
- ext4fs_close();
- /* Loading ok, update default load address */
- load_addr = addr;
-
- printf("%d bytes read\n", filelen);
- sprintf(buf, "%X", filelen);
- setenv("filesize", buf);
-
- return 0;
-fail:
- return 1;
-}
-
-int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- const char *filename = "/";
- int dev;
- int part;
- block_dev_desc_t *dev_desc;
- disk_partition_t info;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
- if (part < 0)
- return 1;
-
- if (argc == 4)
- filename = argv[3];
-
- dev = dev_desc->dev;
- ext4fs_set_blk_dev(dev_desc, &info);
-
- if (!ext4fs_mount(info.size)) {
- printf("** Bad ext2 partition or disk - %s %d:%d **\n",
- argv[1], dev, part);
- ext4fs_close();
- goto fail;
- }
-
- if (ext4fs_ls(filename)) {
- printf("** Error extfs_ls() **\n");
- ext4fs_close();
- goto fail;
- };
-
- ext4fs_close();
- return 0;
-
-fail:
- return 1;
-}
#include <ata.h>
#include <part.h>
#include <fat.h>
-
+#include <fs.h>
int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- long size;
- unsigned long offset;
- unsigned long count = 0;
- unsigned long pos = 0;
- char buf [12];
- block_dev_desc_t *dev_desc=NULL;
- disk_partition_t info;
- int part, dev;
-
- if (argc < 5) {
- printf("usage: fatload <interface> [<dev[:part]>] "
- "<addr> <filename> [bytes [pos]]\n");
- return 1;
- }
-
- part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
- if (part < 0)
- return 1;
-
- dev = dev_desc->dev;
- if (fat_register_device(dev_desc,part)!=0) {
- printf("\n** Unable to use %s %d:%d for fatload **\n",
- argv[1], dev, part);
- return 1;
- }
- offset = simple_strtoul(argv[3], NULL, 16);
- if (argc >= 6)
- count = simple_strtoul(argv[5], NULL, 16);
- if (argc >= 7)
- pos = simple_strtoul(argv[6], NULL, 16);
- size = file_fat_read_at(argv[4], pos, (unsigned char *)offset, count);
-
- if(size==-1) {
- printf("\n** Unable to read \"%s\" from %s %d:%d **\n",
- argv[4], argv[1], dev, part);
- return 1;
- }
-
- printf("\n%ld bytes read\n", size);
-
- sprintf(buf, "%lX", size);
- setenv("filesize", buf);
-
- return 0;
+ return do_load(cmdtp, flag, argc, argv, FS_TYPE_FAT, 16);
}
" 'pos' gives the file position to start loading from.\n"
" If 'pos' is omitted, 0 is used. 'pos' requires 'bytes'.\n"
" 'bytes' gives the size to load. If 'bytes' is 0 or omitted,\n"
- " the load stops on end of file."
+ " the load stops on end of file.\n"
+ " All numeric parameters are assumed to be hex."
);
-int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_fat_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- char *filename = "/";
- int ret, dev, part;
- block_dev_desc_t *dev_desc=NULL;
- disk_partition_t info;
-
- if (argc < 2) {
- printf("usage: fatls <interface> [<dev[:part]>] [directory]\n");
- return 0;
- }
-
- part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
- if (part < 0)
- return 1;
-
- dev = dev_desc->dev;
- if (fat_register_device(dev_desc,part)!=0) {
- printf("\n** Unable to use %s %d:%d for fatls **\n",
- argv[1], dev, part);
- return 1;
- }
- if (argc == 4)
- ret = file_fat_ls(argv[3]);
- else
- ret = file_fat_ls(filename);
-
- if(ret!=0)
- printf("No Fat FS detected\n");
- return ret;
+ return do_ls(cmdtp, flag, argc, argv, FS_TYPE_FAT);
}
U_BOOT_CMD(
" - list files from 'dev' on 'interface' in a 'directory'"
);
-int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_fat_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
int dev, part;
block_dev_desc_t *dev_desc;
return 1;
dev = dev_desc->dev;
- if (fat_register_device(dev_desc,part)!=0) {
+ if (fat_set_blk_dev(dev_desc, &info) != 0) {
printf("\n** Unable to use %s %d:%d for fatinfo **\n",
argv[1], dev, part);
return 1;
dev = dev_desc->dev;
- if (fat_register_device(dev_desc, part) != 0) {
+ if (fat_set_blk_dev(dev_desc, &info) != 0) {
printf("\n** Unable to use %s %d:%d for fatwrite **\n",
argv[1], dev, part);
return 1;
/*
* Flattened Device Tree command, see the help for parameter definitions.
*/
-int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
return CMD_RET_USAGE;
/* Get address */
char buf[11];
- sprintf(buf, "0x%08X", (uint32_t)nodep);
+ sprintf(buf, "0x%p", nodep);
setenv(var, buf);
} else if (subcmd[0] == 's') {
/* Get size */
cp = newp;
tmp = simple_strtoul(cp, &newp, 0);
- *(uint32_t *)data = __cpu_to_be32(tmp);
+ *(__be32 *)data = __cpu_to_be32(tmp);
data += 4;
*len += 4;
if ((len %4) == 0) {
if (len > CONFIG_CMD_FDT_MAX_DUMP)
- printf("* 0x%08x [0x%08x]", (unsigned int)data, len);
+ printf("* 0x%p [0x%08x]", data, len);
else {
- const u32 *p;
+ const __be32 *p;
printf("<");
for (j = 0, p = data; j < len/4; j++)
}
} else { /* anything else... hexdump */
if (len > CONFIG_CMD_FDT_MAX_DUMP)
- printf("* 0x%08x [0x%08x]", (unsigned int)data, len);
+ printf("* 0x%p [0x%08x]", data, len);
else {
const u8 *s;
}
/********************************************************************/
-
-U_BOOT_CMD(
- fdt, 255, 0, do_fdt,
- "flattened device tree utility commands",
- "addr <addr> [<length>] - Set the fdt location to <addr>\n"
+#ifdef CONFIG_SYS_LONGHELP
+static char fdt_help_text[] =
+ "addr <addr> [<length>] - Set the fdt location to <addr>\n"
#ifdef CONFIG_OF_BOARD_SETUP
"fdt boardsetup - Do board-specific set up\n"
#endif
"fdt chosen [<start> <end>] - Add/update the /chosen branch in the tree\n"
" <start>/<end> - initrd start/end addr\n"
"NOTE: Dereference aliases by omiting the leading '/', "
- "e.g. fdt print ethernet0."
+ "e.g. fdt print ethernet0.";
+#endif
+
+U_BOOT_CMD(
+ fdt, 255, 0, do_fdt,
+ "flattened device tree utility commands", fdt_help_text
);
}
#endif /* CONFIG_SYS_NO_FLASH */
-int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_flinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifndef CONFIG_SYS_NO_FLASH
ulong bank;
return 0;
}
-int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_flerase(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifndef CONFIG_SYS_NO_FLASH
flash_info_t *info = NULL;
}
#endif /* CONFIG_SYS_NO_FLASH */
-int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_protect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 0;
#ifndef CONFIG_SYS_NO_FLASH
--- /dev/null
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Inspired by cmd_ext_common.c, cmd_fat.c.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fs.h>
+
+int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY, 0);
+}
+
+U_BOOT_CMD(
+ load, 7, 0, do_load_wrapper,
+ "load binary file from a filesystem",
+ "<interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]]\n"
+ " - Load binary file 'filename' from partition 'part' on device\n"
+ " type 'interface' instance 'dev' to address 'addr' in memory.\n"
+ " 'bytes' gives the size to load in bytes.\n"
+ " If 'bytes' is 0 or omitted, the file is read until the end.\n"
+ " 'pos' gives the file byte position to start reading from.\n"
+ " If 'pos' is 0 or omitted, the file is read from the start.\n"
+ " All numeric parameters are assumed to be decimal,\n"
+ " unless specified otherwise using a leading \"0x\"."
+);
+
+int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return do_ls(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+ ls, 4, 1, do_ls_wrapper,
+ "list files in a directory (default /)",
+ "<interface> [<dev[:part]> [directory]]\n"
+ " - List files in directory 'directory' of partition 'part' on\n"
+ " device type 'interface' instance 'dev'."
+);
#include <common.h>
#include <command.h>
-int do_help(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd);
const int len = ll_entry_count(cmd_tbl_t, cmd);
#define DISP_LINE_LEN 16
/* implement possible board specific board init */
-void __def_i2c_init_board(void)
+static void __def_i2c_init_board(void)
{
return;
}
__attribute__((weak, alias("__def_i2c_init_board")));
/* TODO: Implement architecture-specific get/set functions */
-unsigned int __def_i2c_get_bus_speed(void)
+static unsigned int __def_i2c_get_bus_speed(void)
{
return CONFIG_SYS_I2C_SPEED;
}
unsigned int i2c_get_bus_speed(void)
__attribute__((weak, alias("__def_i2c_get_bus_speed")));
-int __def_i2c_set_bus_speed(unsigned int speed)
+static int __def_i2c_set_bus_speed(unsigned int speed)
{
if (speed != CONFIG_SYS_I2C_SPEED)
return -1;
}
/***************************************************/
-
-U_BOOT_CMD(
- i2c, 6, 1, do_i2c,
- "I2C sub-system",
+#ifdef CONFIG_SYS_LONGHELP
+static char i2c_help_text[] =
#if defined(CONFIG_I2C_MUX)
"bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
#endif /* CONFIG_I2C_MUX */
#if defined(CONFIG_CMD_SDRAM)
"i2c sdram chip - print SDRAM configuration information\n"
#endif
- "i2c speed [speed] - show or set I2C bus speed"
+ "i2c speed [speed] - show or set I2C bus speed";
+#endif
+
+U_BOOT_CMD(
+ i2c, 6, 1, do_i2c,
+ "I2C sub-system",
+ i2c_help_text
);
#if defined(CONFIG_I2C_MUX)
#ifdef CONFIG_ATAPI
static void atapi_inquiry(block_dev_desc_t *dev_desc);
-ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer);
+static ulong atapi_read(int device, ulong blknr, lbaint_t blkcnt,
+ void *buffer);
#endif
/* ------------------------------------------------------------------------- */
-ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer)
+ulong ide_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
{
ulong n = 0;
unsigned char c;
lba48 = 1;
}
#endif
- debug("ide_read dev %d start %lX, blocks %lX buffer at %lX\n",
+ debug("ide_read dev %d start %lX, blocks " LBAF " buffer at %lX\n",
device, blknr, blkcnt, (ulong) buffer);
ide_led(DEVICE_LED(device), 1); /* LED on */
if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
ATA_STAT_DRQ) {
-#if defined(CONFIG_SYS_64BIT_LBA)
- printf("Error (no IRQ) dev %d blk %lld: status 0x%02x\n",
+ printf("Error (no IRQ) dev %d blk %ld: status %#02x\n",
device, blknr, c);
-#else
- printf("Error (no IRQ) dev %d blk %ld: status 0x%02x\n",
- device, (ulong) blknr, c);
-#endif
break;
}
/* ------------------------------------------------------------------------- */
-ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, const void *buffer)
+ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
ulong n = 0;
unsigned char c;
if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
ATA_STAT_DRQ) {
-#if defined(CONFIG_SYS_64BIT_LBA)
- printf("Error (no IRQ) dev %d blk %lld: status 0x%02x\n",
+ printf("Error (no IRQ) dev %d blk %ld: status %#02x\n",
device, blknr, c);
-#else
- printf("Error (no IRQ) dev %d blk %ld: status 0x%02x\n",
- device, (ulong) blknr, c);
-#endif
goto WR_OUT;
}
#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
-ulong atapi_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer)
+ulong atapi_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
{
ulong n = 0;
unsigned char ccb[12]; /* Command descriptor block */
ulong cnt;
- debug("atapi_read dev %d start %lX, blocks %lX buffer at %lX\n",
+ debug("atapi_read dev %d start %lX, blocks " LBAF " buffer at %lX\n",
device, blknr, blkcnt, (ulong) buffer);
do {
#include <config.h>
#include <command.h>
-int do_interrupts(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_interrupts(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
if (argc != 2)
return (0);
}
-int binary_test (char *op, char *arg1, char *arg2, int w)
+static int binary_test(char *op, char *arg1, char *arg2, int w)
{
int len, i;
const op_tbl_t *optp;
}
/* command line interface to the shell test */
-int do_itest ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
+static int do_itest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int value, w;
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_LOADB)
-static ulong load_serial_ymodem (ulong offset);
+static ulong load_serial_ymodem(ulong offset);
#endif
#if defined(CONFIG_CMD_LOADS)
-static ulong load_serial (long offset);
-static int read_record (char *buf, ulong len);
+static ulong load_serial(long offset);
+static int read_record(char *buf, ulong len);
# if defined(CONFIG_CMD_SAVES)
-static int save_serial (ulong offset, ulong size);
-static int write_record (char *buf);
+static int save_serial(ulong offset, ulong size);
+static int write_record(char *buf);
#endif
static int do_echo = 1;
/* -------------------------------------------------------------------- */
#if defined(CONFIG_CMD_LOADS)
-int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_load_serial(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
long offset = 0;
ulong addr;
load_baudrate = current_baudrate;
}
if (load_baudrate != current_baudrate) {
- printf ("## Switch baudrate to %d bps and press ENTER ...\n",
+ printf("## Switch baudrate to %d bps and press ENTER ...\n",
load_baudrate);
udelay(50000);
gd->baudrate = load_baudrate;
- serial_setbrg ();
+ serial_setbrg();
udelay(50000);
for (;;) {
if (getc() == '\r')
}
#endif /* CONFIG_SYS_LOADS_BAUD_CHANGE */
- printf ("## Ready for S-Record download ...\n");
+ printf("## Ready for S-Record download ...\n");
- addr = load_serial (offset);
+ addr = load_serial(offset);
/*
* Gather any trailing characters (for instance, the ^D which
}
if (addr == ~0) {
- printf ("## S-Record download aborted\n");
+ printf("## S-Record download aborted\n");
rcode = 1;
} else {
- printf ("## Start Addr = 0x%08lX\n", addr);
+ printf("## Start Addr = 0x%08lX\n", addr);
load_addr = addr;
}
#ifdef CONFIG_SYS_LOADS_BAUD_CHANGE
if (load_baudrate != current_baudrate) {
- printf ("## Switch baudrate to %d bps and press ESC ...\n",
+ printf("## Switch baudrate to %d bps and press ESC ...\n",
current_baudrate);
- udelay (50000);
+ udelay(50000);
gd->baudrate = current_baudrate;
- serial_setbrg ();
- udelay (50000);
+ serial_setbrg();
+ udelay(50000);
for (;;) {
if (getc() == 0x1B) /* ESC */
break;
return rcode;
}
-static ulong
-load_serial (long offset)
+static ulong load_serial(long offset)
{
char record[SREC_MAXRECLEN + 1]; /* buffer for one S-Record */
char binbuf[SREC_MAXBINLEN]; /* buffer for binary data */
int line_count = 0;
while (read_record(record, SREC_MAXRECLEN + 1) >= 0) {
- type = srec_decode (record, &binlen, &addr, binbuf);
+ type = srec_decode(record, &binlen, &addr, binbuf);
if (type < 0) {
return (~0); /* Invalid S-Record */
rc = flash_write((char *)binbuf,store_addr,binlen);
if (rc != 0) {
- flash_perror (rc);
+ flash_perror(rc);
return (~0);
}
} else
#endif
{
- memcpy ((char *)(store_addr), binbuf, binlen);
+ memcpy((char *)(store_addr), binbuf, binlen);
}
if ((store_addr) < start_addr)
start_addr = store_addr;
case SREC_END2:
case SREC_END3:
case SREC_END4:
- udelay (10000);
+ udelay(10000);
size = end_addr - start_addr + 1;
- printf ("\n"
+ printf("\n"
"## First Load Addr = 0x%08lX\n"
"## Last Load Addr = 0x%08lX\n"
"## Total Size = 0x%08lX = %ld Bytes\n",
start_addr, end_addr, size, size
);
- flush_cache (start_addr, size);
+ flush_cache(start_addr, size);
sprintf(buf, "%lX", size);
setenv("filesize", buf);
return (addr);
}
if (!do_echo) { /* print a '.' every 100 lines */
if ((++line_count % 100) == 0)
- putc ('.');
+ putc('.');
}
}
return (~0); /* Download aborted */
}
-static int
-read_record (char *buf, ulong len)
+static int read_record(char *buf, ulong len)
{
char *p;
char c;
for (p=buf; p < buf+len; ++p) {
c = getc(); /* read character */
if (do_echo)
- putc (c); /* ... and echo it */
+ putc(c); /* ... and echo it */
switch (c) {
case '\r':
save_baudrate = current_baudrate;
}
if (save_baudrate != current_baudrate) {
- printf ("## Switch baudrate to %d bps and press ENTER ...\n",
+ printf("## Switch baudrate to %d bps and press ENTER ...\n",
save_baudrate);
udelay(50000);
gd->baudrate = save_baudrate;
- serial_setbrg ();
+ serial_setbrg();
udelay(50000);
for (;;) {
if (getc() == '\r')
}
#endif /* CONFIG_SYS_LOADS_BAUD_CHANGE */
- printf ("## Ready for S-Record upload, press ENTER to proceed ...\n");
+ printf("## Ready for S-Record upload, press ENTER to proceed ...\n");
for (;;) {
if (getc() == '\r')
break;
}
- if(save_serial (offset, size)) {
- printf ("## S-Record upload aborted\n");
+ if (save_serial(offset, size)) {
+ printf("## S-Record upload aborted\n");
} else {
- printf ("## S-Record upload complete\n");
+ printf("## S-Record upload complete\n");
}
#ifdef CONFIG_SYS_LOADS_BAUD_CHANGE
if (save_baudrate != current_baudrate) {
- printf ("## Switch baudrate to %d bps and press ESC ...\n",
+ printf("## Switch baudrate to %d bps and press ESC ...\n",
(int)current_baudrate);
- udelay (50000);
+ udelay(50000);
gd->baudrate = current_baudrate;
- serial_setbrg ();
- udelay (50000);
+ serial_setbrg();
+ udelay(50000);
for (;;) {
if (getc() == 0x1B) /* ESC */
break;
#define SREC3_END "S70500000000FA\n"
#define SREC_BYTES_PER_RECORD 16
-static int save_serial (ulong address, ulong count)
+static int save_serial(ulong address, ulong count)
{
int i, c, reclen, checksum, length;
char *hex = "0123456789ABCDEF";
return(0);
}
-static int
-write_record (char *buf)
+static int write_record(char *buf)
{
char c;
static void set_kerm_bin_mode(unsigned long *);
static int k_recv(void);
-static ulong load_serial_bin (ulong offset);
+static ulong load_serial_bin(ulong offset);
-char his_eol; /* character he needs at end of packet */
-int his_pad_count; /* number of pad chars he needs */
-char his_pad_char; /* pad chars he needs */
-char his_quote; /* quote chars he'll use */
+static char his_eol; /* character he needs at end of packet */
+static int his_pad_count; /* number of pad chars he needs */
+static char his_pad_char; /* pad chars he needs */
+static char his_quote; /* quote chars he'll use */
-int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_load_serial_bin(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
ulong offset = 0;
ulong addr;
}
if (load_baudrate != current_baudrate) {
- printf ("## Switch baudrate to %d bps and press ENTER ...\n",
+ printf("## Switch baudrate to %d bps and press ENTER ...\n",
load_baudrate);
udelay(50000);
gd->baudrate = load_baudrate;
- serial_setbrg ();
+ serial_setbrg();
udelay(50000);
for (;;) {
if (getc() == '\r')
}
if (strcmp(argv[0],"loady")==0) {
- printf ("## Ready for binary (ymodem) download "
+ printf("## Ready for binary (ymodem) download "
"to 0x%08lX at %d bps...\n",
offset,
load_baudrate);
- addr = load_serial_ymodem (offset);
+ addr = load_serial_ymodem(offset);
} else {
- printf ("## Ready for binary (kermit) download "
+ printf("## Ready for binary (kermit) download "
"to 0x%08lX at %d bps...\n",
offset,
load_baudrate);
- addr = load_serial_bin (offset);
+ addr = load_serial_bin(offset);
if (addr == ~0) {
load_addr = 0;
- printf ("## Binary (kermit) download aborted\n");
+ printf("## Binary (kermit) download aborted\n");
rcode = 1;
} else {
- printf ("## Start Addr = 0x%08lX\n", addr);
+ printf("## Start Addr = 0x%08lX\n", addr);
load_addr = addr;
}
}
if (load_baudrate != current_baudrate) {
- printf ("## Switch baudrate to %d bps and press ESC ...\n",
+ printf("## Switch baudrate to %d bps and press ESC ...\n",
current_baudrate);
- udelay (50000);
+ udelay(50000);
gd->baudrate = current_baudrate;
- serial_setbrg ();
- udelay (50000);
+ serial_setbrg();
+ udelay(50000);
for (;;) {
if (getc() == 0x1B) /* ESC */
break;
}
-static ulong load_serial_bin (ulong offset)
+static ulong load_serial_bin(ulong offset)
{
int size, i;
char buf[32];
- set_kerm_bin_mode ((ulong *) offset);
- size = k_recv ();
+ set_kerm_bin_mode((ulong *) offset);
+ size = k_recv();
/*
* Gather any trailing characters (for instance, the ^D which
udelay(1000);
}
- flush_cache (offset, size);
+ flush_cache(offset, size);
printf("## Total Size = 0x%08x = %d Bytes\n", size, size);
sprintf(buf, "%X", size);
return offset;
}
-void send_pad (void)
+static void send_pad(void)
{
int count = his_pad_count;
while (count-- > 0)
- putc (his_pad_char);
+ putc(his_pad_char);
}
/* converts escaped kermit char to binary char */
-char ktrans (char in)
+static char ktrans(char in)
{
if ((in & 0x60) == 0x40) {
return (char) (in & ~0x40);
return in;
}
-int chk1 (char *buffer)
+static int chk1(char *buffer)
{
int total = 0;
return (int) ((total + ((total >> 6) & 0x03)) & 0x3f);
}
-void s1_sendpacket (char *packet)
+static void s1_sendpacket(char *packet)
{
- send_pad ();
+ send_pad();
while (*packet) {
- putc (*packet++);
+ putc(*packet++);
}
}
static char a_b[24];
-void send_ack (int n)
+static void send_ack(int n)
{
a_b[0] = START_CHAR;
- a_b[1] = tochar (3);
- a_b[2] = tochar (n);
+ a_b[1] = tochar(3);
+ a_b[2] = tochar(n);
a_b[3] = ACK_TYPE;
a_b[4] = '\0';
- a_b[4] = tochar (chk1 (&a_b[1]));
+ a_b[4] = tochar(chk1(&a_b[1]));
a_b[5] = his_eol;
a_b[6] = '\0';
- s1_sendpacket (a_b);
+ s1_sendpacket(a_b);
}
-void send_nack (int n)
+static void send_nack(int n)
{
a_b[0] = START_CHAR;
- a_b[1] = tochar (3);
- a_b[2] = tochar (n);
+ a_b[1] = tochar(3);
+ a_b[2] = tochar(n);
a_b[3] = NACK_TYPE;
a_b[4] = '\0';
- a_b[4] = tochar (chk1 (&a_b[1]));
+ a_b[4] = tochar(chk1(&a_b[1]));
a_b[5] = his_eol;
a_b[6] = '\0';
- s1_sendpacket (a_b);
+ s1_sendpacket(a_b);
}
-void (*os_data_init) (void);
-void (*os_data_char) (char new_char);
+static void (*os_data_init)(void);
+static void (*os_data_char)(char new_char);
static int os_data_state, os_data_state_saved;
static char *os_data_addr, *os_data_addr_saved;
static char *bin_start_address;
-static void bin_data_init (void)
+static void bin_data_init(void)
{
os_data_state = 0;
os_data_addr = bin_start_address;
}
-static void os_data_save (void)
+static void os_data_save(void)
{
os_data_state_saved = os_data_state;
os_data_addr_saved = os_data_addr;
}
-static void os_data_restore (void)
+static void os_data_restore(void)
{
os_data_state = os_data_state_saved;
os_data_addr = os_data_addr_saved;
}
-static void bin_data_char (char new_char)
+static void bin_data_char(char new_char)
{
switch (os_data_state) {
case 0: /* data */
}
}
-static void set_kerm_bin_mode (unsigned long *addr)
+static void set_kerm_bin_mode(unsigned long *addr)
{
bin_start_address = (char *) addr;
os_data_init = bin_data_init;
/* k_data_* simply handles the kermit escape translations */
static int k_data_escape, k_data_escape_saved;
-void k_data_init (void)
+static void k_data_init(void)
{
k_data_escape = 0;
- os_data_init ();
+ os_data_init();
}
-void k_data_save (void)
+static void k_data_save(void)
{
k_data_escape_saved = k_data_escape;
- os_data_save ();
+ os_data_save();
}
-void k_data_restore (void)
+static void k_data_restore(void)
{
k_data_escape = k_data_escape_saved;
- os_data_restore ();
+ os_data_restore();
}
-void k_data_char (char new_char)
+static void k_data_char(char new_char)
{
if (k_data_escape) {
/* last char was escape - translate this character */
- os_data_char (ktrans (new_char));
+ os_data_char(ktrans(new_char));
k_data_escape = 0;
} else {
if (new_char == his_quote) {
k_data_escape = 1;
} else {
/* otherwise send this char as-is */
- os_data_char (new_char);
+ os_data_char(new_char);
}
}
}
#define SEND_DATA_SIZE 20
-char send_parms[SEND_DATA_SIZE];
-char *send_ptr;
+static char send_parms[SEND_DATA_SIZE];
+static char *send_ptr;
/* handle_send_packet interprits the protocol info and builds and
sends an appropriate ack for what we can do */
-void handle_send_packet (int n)
+static void handle_send_packet(int n)
{
int length = 3;
int bytes;
break;
/* handle MAXL - max length */
/* ignore what he says - most I'll take (here) is 94 */
- a_b[++length] = tochar (94);
+ a_b[++length] = tochar(94);
if (bytes-- <= 0)
break;
/* handle TIME - time you should wait for my packets */
/* ignore what he says - don't wait for my ack longer than 1 second */
- a_b[++length] = tochar (1);
+ a_b[++length] = tochar(1);
if (bytes-- <= 0)
break;
/* handle NPAD - number of pad chars I need */
/* remember what he says - I need none */
- his_pad_count = untochar (send_parms[2]);
- a_b[++length] = tochar (0);
+ his_pad_count = untochar(send_parms[2]);
+ a_b[++length] = tochar(0);
if (bytes-- <= 0)
break;
/* handle PADC - pad chars I need */
/* remember what he says - I need none */
- his_pad_char = ktrans (send_parms[3]);
+ his_pad_char = ktrans(send_parms[3]);
a_b[++length] = 0x40; /* He should ignore this */
if (bytes-- <= 0)
break;
/* handle EOL - end of line he needs */
/* remember what he says - I need CR */
- his_eol = untochar (send_parms[4]);
- a_b[++length] = tochar (END_CHAR);
+ his_eol = untochar(send_parms[4]);
+ a_b[++length] = tochar(END_CHAR);
if (bytes-- <= 0)
break;
/* handle QCTL - quote control char he'll use */
break;
/* handle CAPAS - the capabilities mask */
/* ignore what he says - I only do long packets - I don't do windows */
- a_b[++length] = tochar (2); /* only long packets */
- a_b[++length] = tochar (0); /* no windows */
- a_b[++length] = tochar (94); /* large packet msb */
- a_b[++length] = tochar (94); /* large packet lsb */
+ a_b[++length] = tochar(2); /* only long packets */
+ a_b[++length] = tochar(0); /* no windows */
+ a_b[++length] = tochar(94); /* large packet msb */
+ a_b[++length] = tochar(94); /* large packet lsb */
} while (0);
a_b[0] = START_CHAR;
- a_b[1] = tochar (length);
- a_b[2] = tochar (n);
+ a_b[1] = tochar(length);
+ a_b[2] = tochar(n);
a_b[3] = ACK_TYPE;
a_b[++length] = '\0';
- a_b[length] = tochar (chk1 (&a_b[1]));
+ a_b[length] = tochar(chk1(&a_b[1]));
a_b[++length] = his_eol;
a_b[++length] = '\0';
- s1_sendpacket (a_b);
+ s1_sendpacket(a_b);
}
/* k_recv receives a OS Open image file over kermit line */
-static int k_recv (void)
+static int k_recv(void)
{
char new_char;
char k_state, k_state_saved;
/* initialize the k_recv and k_data state machine */
done = 0;
k_state = 0;
- k_data_init ();
+ k_data_init();
k_state_saved = k_state;
- k_data_save ();
+ k_data_save();
n = 0; /* just to get rid of a warning */
last_n = -1;
START:
/* get length of packet */
sum = 0;
- new_char = getc ();
+ new_char = getc();
if ((new_char & 0xE0) == 0)
goto packet_error;
sum += new_char & 0xff;
- length = untochar (new_char);
+ length = untochar(new_char);
/* get sequence number */
- new_char = getc ();
+ new_char = getc();
if ((new_char & 0xE0) == 0)
goto packet_error;
sum += new_char & 0xff;
- n = untochar (new_char);
+ n = untochar(new_char);
--length;
/* NEW CODE - check sequence numbers for retried packets */
if (n == last_n) {
/* same sequence number, restore the previous state */
k_state = k_state_saved;
- k_data_restore ();
+ k_data_restore();
} else {
/* new sequence number, checkpoint the download */
last_n = n;
k_state_saved = k_state;
- k_data_save ();
+ k_data_save();
}
/* END NEW CODE */
/* get packet type */
- new_char = getc ();
+ new_char = getc();
if ((new_char & 0xE0) == 0)
goto packet_error;
sum += new_char & 0xff;
if (length == -2) {
/* (length byte was 0, decremented twice) */
/* get the two length bytes */
- new_char = getc ();
+ new_char = getc();
if ((new_char & 0xE0) == 0)
goto packet_error;
sum += new_char & 0xff;
- len_hi = untochar (new_char);
- new_char = getc ();
+ len_hi = untochar(new_char);
+ new_char = getc();
if ((new_char & 0xE0) == 0)
goto packet_error;
sum += new_char & 0xff;
- len_lo = untochar (new_char);
+ len_lo = untochar(new_char);
length = len_hi * 95 + len_lo;
/* check header checksum */
- new_char = getc ();
+ new_char = getc();
if ((new_char & 0xE0) == 0)
goto packet_error;
- if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f))
+ if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f))
goto packet_error;
sum += new_char & 0xff;
/* --length; */ /* new length includes only data and block check to come */
}
/* bring in rest of packet */
while (length > 1) {
- new_char = getc ();
+ new_char = getc();
if ((new_char & 0xE0) == 0)
goto packet_error;
sum += new_char & 0xff;
}
}
/* get and validate checksum character */
- new_char = getc ();
+ new_char = getc();
if ((new_char & 0xE0) == 0)
goto packet_error;
- if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f))
+ if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f))
goto packet_error;
/* get END_CHAR */
- new_char = getc ();
+ new_char = getc();
if (new_char != END_CHAR) {
packet_error:
/* restore state machines */
k_state = k_state_saved;
- k_data_restore ();
+ k_data_restore();
/* send a negative acknowledge packet in */
- send_nack (n);
+ send_nack(n);
} else if (k_state == SEND_TYPE) {
/* crack the protocol parms, build an appropriate ack packet */
- handle_send_packet (n);
+ handle_send_packet(n);
} else {
/* send simple acknowledge packet in */
- send_ack (n);
+ send_ack(n);
/* quit if end of transmission */
if (k_state == BREAK_TYPE)
done = 1;
return (getc());
return -1;
}
-static ulong load_serial_ymodem (ulong offset)
+static ulong load_serial_ymodem(ulong offset)
{
int size;
char buf[32];
size = 0;
info.mode = xyzModem_ymodem;
- res = xyzModem_stream_open (&info, &err);
+ res = xyzModem_stream_open(&info, &err);
if (!res) {
while ((res =
- xyzModem_stream_read (ymodemBuf, 1024, &err)) > 0) {
+ xyzModem_stream_read(ymodemBuf, 1024, &err)) > 0) {
store_addr = addr + offset;
size += res;
addr += res;
#ifndef CONFIG_SYS_NO_FLASH
- if (addr2info (store_addr)) {
+ if (addr2info(store_addr)) {
int rc;
- rc = flash_write ((char *) ymodemBuf,
+ rc = flash_write((char *) ymodemBuf,
store_addr, res);
if (rc != 0) {
flash_perror (rc);
} else
#endif
{
- memcpy ((char *) (store_addr), ymodemBuf,
+ memcpy((char *)(store_addr), ymodemBuf,
res);
}
}
} else {
- printf ("%s\n", xyzModem_error (err));
+ printf("%s\n", xyzModem_error(err));
}
- xyzModem_stream_close (&err);
- xyzModem_stream_terminate (false, &getcxmodem);
+ xyzModem_stream_close(&err);
+ xyzModem_stream_terminate(false, &getcxmodem);
- flush_cache (offset, size);
+ flush_cache(offset, size);
- printf ("## Total Size = 0x%08x = %d Bytes\n", size, size);
- sprintf (buf, "%X", size);
- setenv ("filesize", buf);
+ printf("## Total Size = 0x%08x = %d Bytes\n", size, size);
+ sprintf(buf, "%X", size);
+ setenv("filesize", buf);
return offset;
}
/* -------------------------------------------------------------------- */
#if defined(CONFIG_CMD_HWFLOW)
-int do_hwflow (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_hwflow(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
extern int hwflow_onoff(int);
return 0;
}
-int mdio_write_ranges(struct mii_dev *bus, int addrlo,
- int addrhi, int devadlo, int devadhi,
- int reglo, int reghi, unsigned short data)
+static int mdio_write_ranges(struct mii_dev *bus, int addrlo,
+ int addrhi, int devadlo, int devadhi,
+ int reglo, int reghi, unsigned short data)
{
int addr, devad, reg;
int err = 0;
return err;
}
-int mdio_read_ranges(struct mii_dev *bus, int addrlo,
- int addrhi, int devadlo, int devadhi,
- int reglo, int reghi)
+static int mdio_read_ranges(struct mii_dev *bus, int addrlo,
+ int addrhi, int devadlo, int devadhi,
+ int reglo, int reghi)
{
int addr, devad, reg;
}
/* The register will be in the form [a[-b].]x[-y] */
-int extract_reg_range(char *input, int *devadlo, int *devadhi,
- int *reglo, int *reghi)
+static int extract_reg_range(char *input, int *devadlo, int *devadhi,
+ int *reglo, int *reghi)
{
char *regstr;
return extract_range(regstr, reglo, reghi);
}
-int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus,
- int *addrlo, int *addrhi)
+static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus,
+ int *addrlo, int *addrhi)
{
struct phy_device *phydev;
* md{.b, .w, .l} {addr} {len}
*/
#define DISP_LINE_LEN 16
-int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, length;
#if defined(CONFIG_HAS_DATAFLASH)
return (rc);
}
-int do_mem_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_mm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return mod_mem (cmdtp, 1, flag, argc, argv);
}
-int do_mem_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_nm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return mod_mem (cmdtp, 0, flag, argc, argv);
}
-int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, writeval, count;
int size;
}
#endif /* CONFIG_MX_CYCLIC */
-int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr1, addr2, count, ngood;
int size;
return rcode;
}
-int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, dest, count;
int size;
return 0;
}
-int do_mem_base (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_base(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
if (argc > 1) {
/* Set new base address.
return 0;
}
-int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
ulong addr, length, i;
int size;
* configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until
* interrupted by ctrl-c or by a failure of one of the sub-tests.
*/
-int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
vu_long *addr, *start, *end;
ulong val;
#if defined(CONFIG_SYS_MEMTEST_SCRATCH)
vu_long *dummy = (vu_long*)CONFIG_SYS_MEMTEST_SCRATCH;
#else
- vu_long *dummy = 0; /* yes, this is address 0x0, not NULL */
+ vu_long *dummy = NULL; /* yes, this is address 0x0, not NULL */
#endif
int j;
#ifndef CONFIG_CRC32_VERIFY
-int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mem_crc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, length;
ulong crc;
#include <common.h>
#include <command.h>
-int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_sleep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong start = get_timer(0);
ulong delay;
delay = simple_strtoul(argv[1], NULL, 10) * CONFIG_SYS_HZ;
while (get_timer(start) < delay) {
- if (ctrlc ())
+ if (ctrlc())
return (-1);
- udelay (100);
+ udelay(100);
}
return 0;
printf("Bus Width: %d-bit\n", mmc->bus_width);
}
-int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct mmc *mmc;
"- dislay info of the current MMC device"
);
-int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
enum mmc_state state;
addr = (void *)simple_strtoul(argv[idx], NULL, 16);
++idx;
} else
- addr = 0;
+ addr = NULL;
blk = simple_strtoul(argv[idx], NULL, 16);
cnt = simple_strtoul(argv[idx + 1], NULL, 16);
#include <common.h>
#include <command.h>
-int
+static int
cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long cpuid;
return 0;
}
+#ifdef CONFIG_SYS_LONGHELP
+static char cpu_help_text[] =
+ "<num> reset - Reset cpu <num>\n"
+ "cpu <num> status - Status of cpu <num>\n"
+ "cpu <num> disable - Disable cpu <num>\n"
+ "cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]"
#ifdef CONFIG_PPC
-#define CPU_ARCH_HELP \
+ "\n"
" [args] : <pir> <r3> <r6>\n" \
" pir - processor id (if writeable)\n" \
" r3 - value for gpr 3\n" \
" When cpu <num> is released r4 and r5 = 0.\n" \
" r7 will contain the size of the initial mapped area"
#endif
+ "";
+#endif
U_BOOT_CMD(
cpu, CONFIG_SYS_MAXARGS, 1, cpu_cmd,
- "Multiprocessor CPU boot manipulation and release",
- "<num> reset - Reset cpu <num>\n"
- "cpu <num> status - Status of cpu <num>\n"
- "cpu <num> disable - Disable cpu <num>\n"
- "cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]"
-#ifdef CPU_ARCH_HELP
- "\n"
- CPU_ARCH_HELP
-#endif
+ "Multiprocessor CPU boot manipulation and release", cpu_help_text
);
extern void jffs2_free_cache(struct part_info *part);
/* mtdids mapping list, filled by parse_ids() */
-struct list_head mtdids;
+static struct list_head mtdids;
/* device/partition list, parse_cmdline() parses into here */
-struct list_head devices;
+static struct list_head devices;
/* current active device and partition number */
struct mtd_device *current_mtd_dev = NULL;
* @param size a pointer to the size of the mtd device (output)
* @return 0 if device is valid, 1 otherwise
*/
-int mtd_device_validate(u8 type, u8 num, u32 *size)
+static int mtd_device_validate(u8 type, u8 num, u32 *size)
{
struct mtd_info *mtd = NULL;
* @param dev_num parsed device number (output)
* @return 0 on success, 1 otherwise
*/
-int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num)
+int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type,
+ u8 *dev_num)
{
const char *p = id;
* @param argv arguments list
* @return 0 on success, 1 otherwise
*/
-int do_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* command line only */
struct mtd_device *dev;
* @param argv arguments list
* @return 0 on success, 1 otherwise
*/
-int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
if (argc == 2) {
if (strcmp(argv[1], "default") == 0) {
" - change active partition (e.g. part-id = nand0,1)"
);
-U_BOOT_CMD(
- mtdparts, 6, 0, do_mtdparts,
- "define flash/nand partitions",
+#ifdef CONFIG_SYS_LONGHELP
+static char mtdparts_help_text[] =
"\n"
" - list partition table\n"
"mtdparts delall\n"
"<size> := standard linux memsize OR '-' to denote all remaining space\n"
"<offset> := partition start offset within the device\n"
"<name> := '(' NAME ')'\n"
- "<ro-flag> := when set to 'ro' makes partition read-only (not used, passed to kernel)"
+ "<ro-flag> := when set to 'ro' makes partition read-only (not used, passed to kernel)";
+#endif
+
+U_BOOT_CMD(
+ mtdparts, 6, 0, do_mtdparts,
+ "define flash/nand partitions", mtdparts_help_text
);
/***************************************************/
{
nand_info_t *nand = &nand_info[idx];
struct nand_chip *chip = nand->priv;
- const int bufsz = 32;
- char buf[bufsz];
+ char buf[32];
printf("Device %d: ", idx);
if (chip->numchips > 1)
return ret;
}
-int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i, ret = 0;
ulong addr;
return CMD_RET_USAGE;
}
-U_BOOT_CMD(
- nand, CONFIG_SYS_MAXARGS, 1, do_nand,
- "NAND sub-system",
+#ifdef CONFIG_SYS_LONGHELP
+static char nand_help_text[] =
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read - addr off|partition size\n"
"nand env.oob set off|partition - set enviromnent offset\n"
"nand env.oob get - get environment offset"
#endif
+ "";
+#endif
+
+U_BOOT_CMD(
+ nand, CONFIG_SYS_MAXARGS, 1, do_nand,
+ "NAND sub-system", nand_help_text
);
static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
return bootm_maybe_autostart(cmdtp, cmd);
}
-int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_nandboot(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
char *boot_device = NULL;
int idx;
static int netboot_common(enum proto_t, cmd_tbl_t *, int, char * const []);
-int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_bootp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- return netboot_common (BOOTP, cmdtp, argc, argv);
+ return netboot_common(BOOTP, cmdtp, argc, argv);
}
U_BOOT_CMD(
"[loadAddress] [[hostIPaddr:]bootfilename]"
);
-int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int ret;
#ifdef CONFIG_CMD_RARP
-int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_rarpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- return netboot_common (RARP, cmdtp, argc, argv);
+ return netboot_common(RARP, cmdtp, argc, argv);
}
U_BOOT_CMD(
#endif
#if defined(CONFIG_CMD_DHCP)
-int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_dhcp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return netboot_common(DHCP, cmdtp, argc, argv);
}
#endif
#if defined(CONFIG_CMD_NFS)
-int do_nfs (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_nfs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return netboot_common(NFS, cmdtp, argc, argv);
}
);
#endif
-static void netboot_update_env (void)
+static void netboot_update_env(void)
{
char tmp[22];
if (NetOurGatewayIP) {
- ip_to_string (NetOurGatewayIP, tmp);
- setenv ("gatewayip", tmp);
+ ip_to_string(NetOurGatewayIP, tmp);
+ setenv("gatewayip", tmp);
}
if (NetOurSubnetMask) {
- ip_to_string (NetOurSubnetMask, tmp);
- setenv ("netmask", tmp);
+ ip_to_string(NetOurSubnetMask, tmp);
+ setenv("netmask", tmp);
}
if (NetOurHostName[0])
- setenv ("hostname", NetOurHostName);
+ setenv("hostname", NetOurHostName);
if (NetOurRootPath[0])
- setenv ("rootpath", NetOurRootPath);
+ setenv("rootpath", NetOurRootPath);
if (NetOurIP) {
- ip_to_string (NetOurIP, tmp);
- setenv ("ipaddr", tmp);
+ ip_to_string(NetOurIP, tmp);
+ setenv("ipaddr", tmp);
}
#if !defined(CONFIG_BOOTP_SERVERIP)
/*
* could have set it
*/
if (NetServerIP) {
- ip_to_string (NetServerIP, tmp);
- setenv ("serverip", tmp);
+ ip_to_string(NetServerIP, tmp);
+ setenv("serverip", tmp);
}
#endif
if (NetOurDNSIP) {
- ip_to_string (NetOurDNSIP, tmp);
- setenv ("dnsip", tmp);
+ ip_to_string(NetOurDNSIP, tmp);
+ setenv("dnsip", tmp);
}
#if defined(CONFIG_BOOTP_DNS2)
if (NetOurDNS2IP) {
- ip_to_string (NetOurDNS2IP, tmp);
- setenv ("dnsip2", tmp);
+ ip_to_string(NetOurDNS2IP, tmp);
+ setenv("dnsip2", tmp);
}
#endif
if (NetOurNISDomain[0])
- setenv ("domain", NetOurNISDomain);
+ setenv("domain", NetOurNISDomain);
#if defined(CONFIG_CMD_SNTP) \
&& defined(CONFIG_BOOTP_TIMEOFFSET)
if (NetTimeOffset) {
- sprintf (tmp, "%d", NetTimeOffset);
- setenv ("timeoffset", tmp);
+ sprintf(tmp, "%d", NetTimeOffset);
+ setenv("timeoffset", tmp);
}
#endif
#if defined(CONFIG_CMD_SNTP) \
&& defined(CONFIG_BOOTP_NTPSERVER)
if (NetNtpServerIP) {
- ip_to_string (NetNtpServerIP, tmp);
- setenv ("ntpserverip", tmp);
+ ip_to_string(NetNtpServerIP, tmp);
+ setenv("ntpserverip", tmp);
}
#endif
}
break;
case 3: load_addr = simple_strtoul(argv[1], NULL, 16);
- copy_filename (BootFile, argv[2], sizeof(BootFile));
+ copy_filename(BootFile, argv[2], sizeof(BootFile));
break;
}
#if defined(CONFIG_CMD_PING)
-int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ping(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
return -1;
}
-int do_cdp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_cdp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int r;
#endif
#if defined(CONFIG_CMD_SNTP)
-int do_sntp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_sntp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *toff;
if (argc < 2) {
- NetNtpServerIP = getenv_IPaddr ("ntpserverip");
+ NetNtpServerIP = getenv_IPaddr("ntpserverip");
if (NetNtpServerIP == 0) {
- printf ("ntpserverip not set\n");
+ printf("ntpserverip not set\n");
return (1);
}
} else {
NetNtpServerIP = string_to_ip(argv[1]);
if (NetNtpServerIP == 0) {
- printf ("Bad NTP server IP address\n");
+ printf("Bad NTP server IP address\n");
return (1);
}
}
- toff = getenv ("timeoffset");
- if (toff == NULL) NetTimeOffset = 0;
- else NetTimeOffset = simple_strtol (toff, NULL, 10);
+ toff = getenv("timeoffset");
+ if (toff == NULL)
+ NetTimeOffset = 0;
+ else
+ NetTimeOffset = simple_strtol(toff, NULL, 10);
if (NetLoop(SNTP) < 0) {
printf("SNTP failed: host %pI4 not responding\n",
return 0;
}
-int do_env_print (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_env_print(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
int i;
int rcode = 0;
* Set a new environment variable,
* or replace or delete an existing one.
*/
-int _do_env_set(int flag, int argc, char * const argv[])
+static int _do_env_set(int flag, int argc, char * const argv[])
{
int i, len;
char *name, *value, *s;
}
#ifndef CONFIG_SPL_BUILD
-int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
return CMD_RET_USAGE;
* Interactively edit an environment variable
*/
#if defined(CONFIG_CMD_EDITENV)
-int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
char buffer[CONFIG_SYS_CBSIZE];
char *init_val;
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
-int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
printf("Saving Environment to %s...\n", env_name_spec);
return CMD_RET_USAGE;
}
-U_BOOT_CMD(
- env, CONFIG_SYS_MAXARGS, 1, do_env,
- "environment handling commands",
+#ifdef CONFIG_SYS_LONGHELP
+static char env_help_text[] =
#if defined(CONFIG_CMD_ASKENV)
"ask name [message] [size] - ask for environment variable\nenv "
#endif
#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
"env save - save environment\n"
#endif
- "env set [-f] name [arg ...]\n"
+ "env set [-f] name [arg ...]\n";
+#endif
+
+U_BOOT_CMD(
+ env, CONFIG_SYS_MAXARGS, 1, do_env,
+ "environment handling commands", env_help_text
);
/*
#include <asm/io.h>
#include <pci.h>
-unsigned char ShortPCIListing = 1;
-
/*
* Follows routines for the output of infos about devices on PCI bus.
*/
* pci modify[.b, .w, .l] bus.device.function [addr]
* pci write[.b, .w, .l] bus.device.function addr value
*/
-int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr = 0, value = 0, size = 0;
pci_dev_t bdf = 0;
/***************************************************/
-
-U_BOOT_CMD(
- pci, 5, 1, do_pci,
- "list and access PCI Configuration Space",
+#ifdef CONFIG_SYS_LONGHELP
+static char pci_help_text[] =
"[bus] [long]\n"
" - short or long list of PCI devices on bus 'bus'\n"
#ifdef CONFIG_CMD_PCI_ENUM
"pci modify[.b, .w, .l] b.d.f address\n"
" - modify, auto increment CFG address\n"
"pci write[.b, .w, .l] b.d.f address value\n"
- " - write to CFG address"
+ " - write to CFG address";
+#endif
+
+U_BOOT_CMD(
+ pci, 5, 1, do_pci,
+ "list and access PCI Configuration Space", pci_help_text
);
extern void mpc85xx_reginfo(void);
#endif
-int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
#if defined(CONFIG_8xx)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
#include <part.h>
#include <sata.h>
-int sata_curr_device = -1;
+static int sata_curr_device = -1;
block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
int __sata_initialize(void)
}
#endif
-int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
#include <image.h>
#include <pci.h>
+#ifdef CONFIG_SCSI_DEV_LIST
+#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
+#else
#ifdef CONFIG_SCSI_SYM53C8XX
#define SCSI_VEND_ID 0x1000
#ifndef CONFIG_SCSI_DEV_ID
#elif !defined(CONFIG_SCSI_AHCI_PLAT)
#error no scsi device defined
#endif
+#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#endif
-
+#ifdef CONFIG_PCI
+const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
+#endif
static ccb tempccb; /* temporary scsi command buffer */
static unsigned char tempbuff[512]; /* temporary data buffer */
* forward declerations of some Setup Routines
*/
void scsi_setup_test_unit_ready(ccb * pccb);
-void scsi_setup_read_capacity(ccb * pccb);
void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks);
void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks);
+static void scsi_setup_write_ext(ccb *pccb, unsigned long start,
+ unsigned short blocks);
void scsi_setup_inquiry(ccb * pccb);
void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
-ulong scsi_read(int device, ulong blknr, ulong blkcnt, void *buffer);
+static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
+ unsigned long *blksz);
+static ulong scsi_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer);
+static ulong scsi_write(int device, ulong blknr,
+ lbaint_t blkcnt, const void *buffer);
/*********************************************************************************
void scsi_scan(int mode)
{
unsigned char i,perq,modi,lun;
- unsigned long capacity,blksz;
+ lbaint_t capacity;
+ unsigned long blksz;
ccb* pccb=(ccb *)&tempccb;
if(mode==1) {
scsi_dev_desc[i].dev=i;
scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
scsi_dev_desc[i].block_read=scsi_read;
+ scsi_dev_desc[i].block_write = scsi_write;
}
scsi_max_devs=0;
for(i=0;i<CONFIG_SYS_SCSI_MAX_SCSI_ID;i++) {
scsi_print_error(pccb);
continue;
}
- pccb->datalen=8;
- scsi_setup_read_capacity(pccb);
- if(scsi_exec(pccb)!=TRUE) {
+ if (scsi_read_capacity(pccb, &capacity, &blksz)) {
scsi_print_error(pccb);
continue;
}
- capacity=((unsigned long)tempbuff[0]<<24)|((unsigned long)tempbuff[1]<<16)|
- ((unsigned long)tempbuff[2]<<8)|((unsigned long)tempbuff[3]);
- blksz=((unsigned long)tempbuff[4]<<24)|((unsigned long)tempbuff[5]<<16)|
- ((unsigned long)tempbuff[6]<<8)|((unsigned long)tempbuff[7]);
scsi_dev_desc[scsi_max_devs].lba=capacity;
scsi_dev_desc[scsi_max_devs].blksz=blksz;
scsi_dev_desc[scsi_max_devs].type=perq;
scsi_curr_dev=0;
else
scsi_curr_dev = -1;
+
+ printf("Found %d device(s).\n", scsi_max_devs);
+ setenv_ulong("scsidevs", scsi_max_devs);
+}
+
+int scsi_get_disk_count(void)
+{
+ return scsi_max_devs;
}
#ifdef CONFIG_PCI
void scsi_init(void)
{
int busdevfunc;
+ int i;
+ /*
+ * Find a device from the list, this driver will support a single
+ * controller.
+ */
+ for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
+ /* get PCI Device ID */
+ busdevfunc = pci_find_device(scsi_device_list[i].vendor,
+ scsi_device_list[i].device,
+ 0);
+ if (busdevfunc != -1)
+ break;
+ }
- busdevfunc=pci_find_device(SCSI_VEND_ID,SCSI_DEV_ID,0); /* get PCI Device ID */
- if(busdevfunc==-1) {
- printf("Error SCSI Controller (%04X,%04X) not found\n",SCSI_VEND_ID,SCSI_DEV_ID);
+ if (busdevfunc == -1) {
+ printf("Error: SCSI Controller(s) ");
+ for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
+ printf("%04X:%04X ",
+ scsi_device_list[i].vendor,
+ scsi_device_list[i].device);
+ }
+ printf("not found\n");
return;
}
#ifdef DEBUG
else {
- printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",SCSI_VEND_ID,SCSI_DEV_ID,(busdevfunc>>16)&0xFF,(busdevfunc>>11)&0x1F,(busdevfunc>>8)&0x7);
+ printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",
+ scsi_device_list[i].vendor,
+ scsi_device_list[i].device,
+ (busdevfunc >> 16) & 0xFF,
+ (busdevfunc >> 11) & 0x1F,
+ (busdevfunc >> 8) & 0x7);
}
#endif
scsi_low_level_init(busdevfunc);
n = scsi_read(scsi_curr_dev, blk, cnt, (ulong *)addr);
printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR");
return 0;
+ } else if (strcmp(argv[1], "write") == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong blk = simple_strtoul(argv[3], NULL, 16);
+ ulong cnt = simple_strtoul(argv[4], NULL, 16);
+ ulong n;
+ printf("\nSCSI write: device %d block # %ld, "
+ "count %ld ... ",
+ scsi_curr_dev, blk, cnt);
+ n = scsi_write(scsi_curr_dev, blk, cnt,
+ (ulong *)addr);
+ printf("%ld blocks written: %s\n", n,
+ (n == cnt) ? "OK" : "ERROR");
+ return 0;
}
} /* switch */
return CMD_RET_USAGE;
#define SCSI_MAX_READ_BLK 0xFFFF /* almost the maximum amount of the scsi_ext command.. */
-ulong scsi_read(int device, ulong blknr, ulong blkcnt, void *buffer)
+static ulong scsi_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
{
- ulong start,blks, buf_addr;
+ lbaint_t start, blks;
+ uintptr_t buf_addr;
unsigned short smallblks;
ccb* pccb=(ccb *)&tempccb;
device&=0xff;
buf_addr=(unsigned long)buffer;
start=blknr;
blks=blkcnt;
- debug ("\nscsi_read: dev %d startblk %lx, blccnt %lx buffer %lx\n",device,start,blks,(unsigned long)buffer);
+ debug("\nscsi_read: dev %d startblk " LBAF
+ ", blccnt " LBAF " buffer %lx\n",
+ device, start, blks, (unsigned long)buffer);
do {
pccb->pdata=(unsigned char *)buf_addr;
if(blks>SCSI_MAX_READ_BLK) {
start+=blks;
blks=0;
}
- debug ("scsi_read_ext: startblk %lx, blccnt %x buffer %lx\n",start,smallblks,buf_addr);
+ debug("scsi_read_ext: startblk " LBAF
+ ", blccnt %x buffer %lx\n",
+ start, smallblks, buf_addr);
if(scsi_exec(pccb)!=TRUE) {
scsi_print_error(pccb);
blkcnt-=blks;
}
buf_addr+=pccb->datalen;
} while(blks!=0);
- debug ("scsi_read_ext: end startblk %lx, blccnt %x buffer %lx\n",start,smallblks,buf_addr);
+ debug("scsi_read_ext: end startblk " LBAF
+ ", blccnt %x buffer %lx\n", start, smallblks, buf_addr);
return(blkcnt);
}
+/*******************************************************************************
+ * scsi_write
+ */
+
+/* Almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_WRITE_BLK 0xFFFF
+
+static ulong scsi_write(int device, ulong blknr,
+ lbaint_t blkcnt, const void *buffer)
+{
+ lbaint_t start, blks;
+ uintptr_t buf_addr;
+ unsigned short smallblks;
+ ccb* pccb = (ccb *)&tempccb;
+ device &= 0xff;
+ /* Setup device
+ */
+ pccb->target = scsi_dev_desc[device].target;
+ pccb->lun = scsi_dev_desc[device].lun;
+ buf_addr = (unsigned long)buffer;
+ start = blknr;
+ blks = blkcnt;
+ debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
+ __func__, device, start, blks, (unsigned long)buffer);
+ do {
+ pccb->pdata = (unsigned char *)buf_addr;
+ if (blks > SCSI_MAX_WRITE_BLK) {
+ pccb->datalen = (scsi_dev_desc[device].blksz *
+ SCSI_MAX_WRITE_BLK);
+ smallblks = SCSI_MAX_WRITE_BLK;
+ scsi_setup_write_ext(pccb, start, smallblks);
+ start += SCSI_MAX_WRITE_BLK;
+ blks -= SCSI_MAX_WRITE_BLK;
+ } else {
+ pccb->datalen = scsi_dev_desc[device].blksz * blks;
+ smallblks = (unsigned short)blks;
+ scsi_setup_write_ext(pccb, start, smallblks);
+ start += blks;
+ blks = 0;
+ }
+ debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n",
+ __func__, start, smallblks, buf_addr);
+ if (scsi_exec(pccb) != TRUE) {
+ scsi_print_error(pccb);
+ blkcnt -= blks;
+ break;
+ }
+ buf_addr += pccb->datalen;
+ } while (blks != 0);
+ debug("%s: end startblk " LBAF ", blccnt %x buffer %lx\n",
+ __func__, start, smallblks, buf_addr);
+ return blkcnt;
+}
+
/* copy src to dest, skipping leading and trailing blanks
* and null terminate the string
*/
}
}
+int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
+{
+ *capacity = 0;
+
+ memset(pccb->cmd, 0, sizeof(pccb->cmd));
+ pccb->cmd[0] = SCSI_RD_CAPAC10;
+ pccb->cmd[1] = pccb->lun << 5;
+ pccb->cmdlen = 10;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+
+ pccb->datalen = 8;
+ if (scsi_exec(pccb) != TRUE)
+ return 1;
+
+ *capacity = ((lbaint_t)pccb->pdata[0] << 24) |
+ ((lbaint_t)pccb->pdata[1] << 16) |
+ ((lbaint_t)pccb->pdata[2] << 8) |
+ ((lbaint_t)pccb->pdata[3]);
+
+ if (*capacity != 0xffffffff) {
+ /* Read capacity (10) was sufficient for this drive. */
+ *blksz = ((unsigned long)pccb->pdata[4] << 24) |
+ ((unsigned long)pccb->pdata[5] << 16) |
+ ((unsigned long)pccb->pdata[6] << 8) |
+ ((unsigned long)pccb->pdata[7]);
+ return 0;
+ }
+
+ /* Read capacity (10) was insufficient. Use read capacity (16). */
+
+ memset(pccb->cmd, 0, sizeof(pccb->cmd));
+ pccb->cmd[0] = SCSI_RD_CAPAC16;
+ pccb->cmd[1] = 0x10;
+ pccb->cmdlen = 16;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+
+ pccb->datalen = 16;
+ if (scsi_exec(pccb) != TRUE)
+ return 1;
+
+ *capacity = ((uint64_t)pccb->pdata[0] << 56) |
+ ((uint64_t)pccb->pdata[1] << 48) |
+ ((uint64_t)pccb->pdata[2] << 40) |
+ ((uint64_t)pccb->pdata[3] << 32) |
+ ((uint64_t)pccb->pdata[4] << 24) |
+ ((uint64_t)pccb->pdata[5] << 16) |
+ ((uint64_t)pccb->pdata[6] << 8) |
+ ((uint64_t)pccb->pdata[7]);
+
+ *blksz = ((uint64_t)pccb->pdata[8] << 56) |
+ ((uint64_t)pccb->pdata[9] << 48) |
+ ((uint64_t)pccb->pdata[10] << 40) |
+ ((uint64_t)pccb->pdata[11] << 32) |
+ ((uint64_t)pccb->pdata[12] << 24) |
+ ((uint64_t)pccb->pdata[13] << 16) |
+ ((uint64_t)pccb->pdata[14] << 8) |
+ ((uint64_t)pccb->pdata[15]);
+
+ return 0;
+}
+
/************************************************************************************
* Some setup (fill-in) routines
pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
}
-void scsi_setup_read_capacity(ccb * pccb)
-{
- pccb->cmd[0]=SCSI_RD_CAPAC;
- pccb->cmd[1]=pccb->lun<<5;
- pccb->cmd[2]=0;
- pccb->cmd[3]=0;
- pccb->cmd[4]=0;
- pccb->cmd[5]=0;
- pccb->cmd[6]=0;
- pccb->cmd[7]=0;
- pccb->cmd[8]=0;
- pccb->cmd[9]=0;
- pccb->cmdlen=10;
- pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-
-}
-
void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks)
{
pccb->cmd[0]=SCSI_READ10;
pccb->cmd[7],pccb->cmd[8]);
}
+void scsi_setup_write_ext(ccb *pccb, unsigned long start, unsigned short blocks)
+{
+ pccb->cmd[0] = SCSI_WRITE10;
+ pccb->cmd[1] = pccb->lun << 5;
+ pccb->cmd[2] = ((unsigned char) (start>>24)) & 0xff;
+ pccb->cmd[3] = ((unsigned char) (start>>16)) & 0xff;
+ pccb->cmd[4] = ((unsigned char) (start>>8)) & 0xff;
+ pccb->cmd[5] = ((unsigned char) (start)) & 0xff;
+ pccb->cmd[6] = 0;
+ pccb->cmd[7] = ((unsigned char) (blocks>>8)) & 0xff;
+ pccb->cmd[8] = (unsigned char)blocks & 0xff;
+ pccb->cmd[9] = 0;
+ pccb->cmdlen = 10;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+ debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+ __func__,
+ pccb->cmd[0], pccb->cmd[1],
+ pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+ pccb->cmd[7], pccb->cmd[8]);
+}
+
void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks)
{
pccb->cmd[0]=SCSI_READ6;
"scsi device [dev] - show or set current device\n"
"scsi part [dev] - print partition table of one or all SCSI devices\n"
"scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
- " to memory address `addr'"
+ " to memory address `addr'\n"
+ "scsi write addr blk# cnt - write `cnt' blocks starting at block\n"
+ " `blk#' from memory address `addr'"
);
U_BOOT_CMD(
}
}
-int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong a, b;
char buf[16];
return rcode;
}
-U_BOOT_CMD(
- source, 2, 0, do_source,
- "run script from memory",
+#ifdef CONFIG_SYS_LONGHELP
+static char source_help_text[] =
"[addr]\n"
"\t- run script starting at addr\n"
"\t- A valid image header must be present"
"For FIT format uImage addr must include subimage\n"
"unit name in the form of addr:<subimg_uname>"
#endif
+ "";
+#endif
+
+U_BOOT_CMD(
+ source, 2, 0, do_source,
+ "run script from memory", source_help_text
);
#endif
#include <common.h>
#include <command.h>
-int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char * const *ap;
int left, adv, expr, last_expr, neg, last_cmp;
"[args..]"
);
-int do_false(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_false(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return 1;
}
NULL
);
-int do_true(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_true(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return 0;
}
#endif
/* some display routines (info command) */
-char *usb_get_class_desc(unsigned char dclass)
+static char *usb_get_class_desc(unsigned char dclass)
{
switch (dclass) {
case USB_CLASS_PER_INTERFACE:
}
}
-void usb_display_class_sub(unsigned char dclass, unsigned char subclass,
- unsigned char proto)
+static void usb_display_class_sub(unsigned char dclass, unsigned char subclass,
+ unsigned char proto)
{
switch (dclass) {
case USB_CLASS_PER_INTERFACE:
}
}
-void usb_display_string(struct usb_device *dev, int index)
+static void usb_display_string(struct usb_device *dev, int index)
{
ALLOC_CACHE_ALIGN_BUFFER(char, buffer, 256);
}
}
-void usb_display_desc(struct usb_device *dev)
+static void usb_display_desc(struct usb_device *dev)
{
if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) {
printf("%d: %s, USB Revision %x.%x\n", dev->devnum,
}
-void usb_display_conf_desc(struct usb_configuration_descriptor *config,
- struct usb_device *dev)
+static void usb_display_conf_desc(struct usb_configuration_descriptor *config,
+ struct usb_device *dev)
{
printf(" Configuration: %d\n", config->bConfigurationValue);
printf(" - Interfaces: %d %s%s%dmA\n", config->bNumInterfaces,
}
}
-void usb_display_if_desc(struct usb_interface_descriptor *ifdesc,
- struct usb_device *dev)
+static void usb_display_if_desc(struct usb_interface_descriptor *ifdesc,
+ struct usb_device *dev)
{
printf(" Interface: %d\n", ifdesc->bInterfaceNumber);
printf(" - Alternate Setting %d, Endpoints: %d\n",
}
}
-void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc)
+static void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc)
{
printf(" - Endpoint %d %s ", epdesc->bEndpointAddress & 0xf,
(epdesc->bEndpointAddress & 0x80) ? "In" : "Out");
}
/* main routine to diasplay the configs, interfaces and endpoints */
-void usb_display_config(struct usb_device *dev)
+static void usb_display_config(struct usb_device *dev)
{
struct usb_config *config;
struct usb_interface *ifdesc;
}
/* shows the device tree recursively */
-void usb_show_tree_graph(struct usb_device *dev, char *pre)
+static void usb_show_tree_graph(struct usb_device *dev, char *pre)
{
int i, index;
int has_child, last_child;
}
/* main routine for the tree command */
-void usb_show_tree(struct usb_device *dev)
+static void usb_show_tree(struct usb_device *dev)
{
char preamble[32];
* usb boot command intepreter. Derived from diskboot
*/
#ifdef CONFIG_USB_STORAGE
-int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return common_diskboot(cmdtp, "usb", argc, argv);
}
/******************************************************************************
* usb command intepreter
*/
-int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
const char __weak version_string[] = U_BOOT_VERSION_STRING;
-int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf("\n%s\n", version_string);
#ifdef CC_VERSION_STRING
#define CONFIG_SYS_XIMG_LEN 0x800000
#endif
-int
+static int
do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
ulong addr = load_addr;
return 0;
}
-U_BOOT_CMD(
- imxtract, 4, 1, do_imgextract,
- "extract a part of a multi-image",
+#ifdef CONFIG_SYS_LONGHELP
+static char imgextract_help_text[] =
"addr part [dest]\n"
" - extract <part> from legacy image at <addr> and copy to <dest>"
#if defined(CONFIG_FIT)
"addr uname [dest]\n"
" - extract <uname> subimage from FIT image at <addr> and copy to <dest>"
#endif
+ "";
+#endif
+
+U_BOOT_CMD(
+ imxtract, 4, 1, do_imgextract,
+ "extract a part of a multi-image", imgextract_help_text
);
#define DOS_FS_TYPE_OFFSET 0x36
#define DOS_FS32_TYPE_OFFSET 0x52
-static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *filename = NULL;
int dev;
-static int do_zfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_zfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
const char *filename = "/";
int part;
int i;
int rcode = 0;
+ if (cmd_items > CONFIG_SYS_MAXARGS) {
+ printf("%s: cmd_items %d exceeds hardcoded limit %d."
+ " Recompile with higher CONFIG_SYS_MAXARGS?\n",
+ __func__, cmd_items, CONFIG_SYS_MAXARGS);
+ return -1;
+ }
+
if (argc == 1) { /*show list of commands */
- cmd_tbl_t *cmd_array[cmd_items];
+ cmd_tbl_t *cmd_array[CONFIG_SYS_MAXARGS];
int i, j, swaps;
/* Make array of commands from .uboot_cmd section */
#define IAV(i) bin_at(i), bin_at(i)
static mbinptr av_[NAV * 2 + 2] = {
- 0, 0,
+ NULL, NULL,
IAV(0), IAV(1), IAV(2), IAV(3), IAV(4), IAV(5), IAV(6), IAV(7),
IAV(8), IAV(9), IAV(10), IAV(11), IAV(12), IAV(13), IAV(14), IAV(15),
IAV(16), IAV(17), IAV(18), IAV(19), IAV(20), IAV(21), IAV(22), IAV(23),
/* check if mem_malloc_init() was run */
if ((mem_malloc_start == 0) && (mem_malloc_end == 0)) {
/* not initialized yet */
- return 0;
+ return NULL;
}
- if ((long)bytes < 0) return 0;
+ if ((long)bytes < 0) return NULL;
nb = request2size(bytes); /* padded request size; */
/* Try to extend */
malloc_extend_top(nb);
if ( (remainder_size = chunksize(top) - nb) < (long)MINSIZE)
- return 0; /* propagate failure */
+ return NULL; /* propagate failure */
}
victim = top;
mchunkptr fwd; /* misc temp for linking */
int islr; /* track whether merging with last_remainder */
- if (mem == 0) /* free(0) has no effect */
+ if (mem == NULL) /* free(0) has no effect */
return;
p = mem2chunk(mem);
if (bytes == 0) { fREe(oldmem); return 0; }
#endif
- if ((long)bytes < 0) return 0;
+ if ((long)bytes < 0) return NULL;
/* realloc of null is supposed to be same as malloc */
- if (oldmem == 0) return mALLOc(bytes);
+ if (oldmem == NULL) return mALLOc(bytes);
newp = oldp = mem2chunk(oldmem);
newsize = oldsize = chunksize(oldp);
}
else
{
- next = 0;
+ next = NULL;
nextsize = 0;
}
/* try forward + backward first to save a later consolidation */
- if (next != 0)
+ if (next != NULL)
{
/* into top */
if (next == top)
}
/* backward only */
- if (prev != 0 && (long)(prevsize + newsize) >= (long)nb)
+ if (prev != NULL && (long)(prevsize + newsize) >= (long)nb)
{
unlink(prev, bck, fwd);
newp = prev;
newmem = mALLOc (bytes);
- if (newmem == 0) /* propagate failure */
- return 0;
+ if (newmem == NULL) /* propagate failure */
+ return NULL;
/* Avoid copy if newp is next chunk after oldp. */
/* (This can only happen when new chunk is sbrk'ed.) */
mchunkptr remainder; /* spare room at end to split off */
long remainder_size; /* its size */
- if ((long)bytes < 0) return 0;
+ if ((long)bytes < 0) return NULL;
/* If need less alignment than we give anyway, just relay to malloc */
nb = request2size(bytes);
m = (char*)(mALLOc(nb + alignment + MINSIZE));
- if (m == 0) return 0; /* propagate failure */
+ if (m == NULL) return NULL; /* propagate failure */
p = mem2chunk(m);
#endif
Void_t* mem = mALLOc (sz);
- if ((long)n < 0) return 0;
+ if ((long)n < 0) return NULL;
- if (mem == 0)
- return 0;
+ if (mem == NULL)
+ return NULL;
else
{
p = mem2chunk(mem);
#endif
{
mchunkptr p;
- if (mem == 0)
+ if (mem == NULL)
return 0;
else
{
char **global_argv;
unsigned int global_argc;
#endif
-unsigned int last_return_code;
-int nesting_level;
+static unsigned int last_return_code;
#ifndef __U_BOOT__
extern char **environ; /* This is in <unistd.h>, but protected with __USE_GNU */
#endif
* NAME=VALUE format. So the first order of business is to
* split 's' on the '=' into 'name' and 'value' */
value = strchr(name, '=');
- if (value==0 && ++value==0) {
+ if (value == NULL && ++value == NULL) {
free(name);
return -1;
}
result = -1;
} else {
cur->name = strdup(name);
- if(cur->name == 0) {
+ if (cur->name == NULL) {
free(cur);
result = -1;
} else {
struct variables *bottom = top_vars;
cur->value = strdup(value);
- cur->next = 0;
+ cur->next = NULL;
cur->flg_export = flg_export;
cur->flg_read_only = 0;
while(bottom->next) bottom=bottom->next;
if(strcmp(cur->name, name)==0)
break;
}
- if(cur!=0) {
+ if (cur != NULL) {
struct variables *next = top_vars;
if(cur->flg_read_only) {
error_msg("%s: readonly variable", name);
}
#endif
-struct pipe *new_pipe(void) {
+static struct pipe *new_pipe(void)
+{
struct pipe *pi;
pi = xmalloc(sizeof(struct pipe));
pi->num_progs = 0;
};
#define NRES (sizeof(reserved_list)/sizeof(struct reserved_combo))
-int reserved_word(o_string *dest, struct p_context *ctx)
+static int reserved_word(o_string *dest, struct p_context *ctx)
{
struct reserved_combo *r;
for (r=reserved_list;
#endif
/* return code is 0 for normal exit, 1 for syntax error */
-int parse_stream(o_string *dest, struct p_context *ctx,
- struct in_str *input, int end_trigger)
+static int parse_stream(o_string *dest, struct p_context *ctx,
+ struct in_str *input, int end_trigger)
{
unsigned int ch, m;
#ifndef __U_BOOT__
return 0;
}
-void mapset(const unsigned char *set, int code)
+static void mapset(const unsigned char *set, int code)
{
const unsigned char *s;
for (s=set; *s; s++) map[*s] = code;
}
-void update_ifs_map(void)
+static void update_ifs_map(void)
{
/* char *ifs and char map[256] are both globals. */
ifs = (uchar *)getenv("IFS");
/* most recursion does not come through here, the exeception is
* from builtin_source() */
-int parse_stream_outer(struct in_str *inp, int flag)
+static int parse_stream_outer(struct in_str *inp, int flag)
{
struct p_context ctx;
top_vars = malloc(sizeof(struct variables));
top_vars->name = "HUSH_VERSION";
top_vars->value = "0.01";
- top_vars->next = 0;
+ top_vars->next = NULL;
top_vars->flg_export = 0;
top_vars->flg_read_only = 1;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
}
#ifdef __U_BOOT__
-int do_showvar (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_showvar(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
int i, k;
int rcode = 0;
int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size)
{
void *fdt_blob = *of_flat_tree;
- void *of_start = 0;
+ void *of_start = NULL;
char *fdt_high;
ulong of_len = 0;
int err;
of_start =
(void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
(ulong)desired_addr);
- if (of_start == 0) {
+ if (of_start == NULL) {
puts("Failed using fdt_high value for Device Tree");
goto error;
}
+ getenv_bootm_low());
}
- if (of_start == 0) {
+ if (of_start == NULL) {
puts("device tree - allocation error\n");
goto error;
}
return 0;
error:
- *of_flat_tree = 0;
+ *of_flat_tree = NULL;
*of_size = 0;
return 1;
}
#define HIST_MAX 20
#define HIST_SIZE CONFIG_SYS_CBSIZE
-static int hist_max = 0;
-static int hist_add_idx = 0;
+static int hist_max;
+static int hist_add_idx;
static int hist_cur = -1;
-unsigned hist_num = 0;
+static unsigned hist_num;
-char* hist_list[HIST_MAX];
-char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */
+static char *hist_list[HIST_MAX];
+static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */
#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
#include <command.h>
#include <flash.h>
#include <net.h>
+#include <net/tftp.h>
#include <malloc.h>
/* env variable holding the location of the update file */
}
#endif
-void usb_show_progress(void)
+static void usb_show_progress(void)
{
debug(".");
}
result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0),
US_BBB_RESET,
USB_TYPE_CLASS | USB_RECIP_INTERFACE,
- 0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT * 5);
+ 0, us->ifnum, NULL, 0, USB_CNTL_TIMEOUT * 5);
if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) {
USB_STOR_PRINTF("RESET:stall\n");
* Set up the command for a BBB device. Note that the actual SCSI
* command is copied into cbw.CBWCDB.
*/
-int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
+static int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
{
int result;
int actlen;
/* FIXME: we also need a CBI_command which sets up the completion
* interrupt, and waits for it
*/
-int usb_stor_CB_comdat(ccb *srb, struct us_data *us)
+static int usb_stor_CB_comdat(ccb *srb, struct us_data *us)
{
int result = 0;
int dir_in, retry;
}
-int usb_stor_CBI_get_status(ccb *srb, struct us_data *us)
+static int usb_stor_CBI_get_status(ccb *srb, struct us_data *us)
{
int timeout;
(void *) &us->ip_data, us->irqmaxp, us->irqinterval);
timeout = 1000;
while (timeout--) {
- if ((volatile int *) us->ip_wanted == 0)
+ if ((volatile int *) us->ip_wanted == NULL)
break;
mdelay(10);
}
#define USB_TRANSPORT_NOT_READY_RETRY 10
/* clear a stall on an endpoint - special for BBB devices */
-int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt)
+static int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt)
{
int result;
/* ENDPOINT_HALT = 0, so set value to 0 */
result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0),
USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT,
- 0, endpt, 0, 0, USB_CNTL_TIMEOUT * 5);
+ 0, endpt, NULL, 0, USB_CNTL_TIMEOUT * 5);
return result;
}
-int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
+static int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
{
int result, retry;
int dir_in;
return result;
}
-int usb_stor_CB_transport(ccb *srb, struct us_data *us)
+static int usb_stor_CB_transport(ccb *srb, struct us_data *us)
{
int result, status;
ccb *psrb;
#ifndef REDBOOT /*SB */
typedef int cyg_int32;
-int
+static int
CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
{
#define DELAY 20
return 0;
}
-void
+static void
CYGACC_COMM_IF_PUTC (char x, char y)
{
putc (y);
}
/* Parse (scan) a number */
-bool
+static bool
parse_num (char *s, unsigned long *val, char **es, char *delim)
{
bool first = true;
This patch series adds support for ext4 ls,load and write features in uboot
Journaling is supported for write feature.
+To enable support for the ext4 (and ext2) filesystem implementation,
+#define CONFIG_FS_EXT4
+
+If you want write support,
+#define CONFIG_EXT4_WRITE
+
To Enable ext2 ls and load commands, modify the board specific config file with
#define CONFIG_CMD_EXT2
+This automatically defines CONFIG_FS_EXT4 for you.
To Enable ext4 ls and load commands, modify the board specific config file with
#define CONFIG_CMD_EXT4
+This automatically defines CONFIG_FS_EXT4 for you.
To enable ext4 write command, modify the board specific config file with
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
+These automatically define CONFIG_FS_EXT4 and CONFIG_EXT4_WRITE for you.
+
+Also relevant are the generic filesystem commands,
+#define CONFIG_CMD_FS_GENERIC
+This does not automatically enable EXT4 support for you.
Steps to test:
Board Arch CPU removed Commit last known maintainer/contact
=============================================================================
+AMX860 powerpc mpc860 - - Wolfgang Denk <wd@denx.de>
+c2mon powerpc mpc855 - - Wolfgang Denk <wd@denx.de>
+ETX094 powerpc mpc850 - - Wolfgang Denk <wd@denx.de>
+IAD210 powerpc mpc860 - - -
+LANTEC powerpc mpc850 - - Wolfgang Denk <wd@denx.de>
+SCM powerpc mpc8260 - - Wolfgang Grandegger <wg@denx.de>
SX1 arm arm925t - -
TQM85xx powerpc MPC85xx d923a5d5 2012-10-04 Stefan Roese <sr@denx.de>
apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park <kyungmin.park@samsung.com>
alias reinhardm Reinhard Meyer <u-boot@emk-elektronik.de>
alias sbabic Stefano Babic <sbabic@denx.de>
alias scottwood Scott Wood <scottwood@freescale.com>
+alias sjg Simon Glass <sjg@chromium.org>
alias smcnutt Scott McNutt <smcnutt@psyent.com>
alias stroese Stefan Roese <sr@denx.de>
alias vapier Mike Frysinger <vapier@gentoo.org>
alias s3c samsung
alias s5pc samsung
alias samsung uboot, prom
-alias tegra uboot, Simon Glass <sjg@chromium.org>, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
+alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
alias ti uboot, Tom Rini <trini@ti.com>
alias ppc7xx uboot, wd
alias ppc74xx uboot, wd
-alias sandbox Simon Glass <sjg@chromium.org>
+alias sandbox sjg
alias sb sandbox
alias sparc uboot, Daniel Hellstrom <daniel@gaisler.com>
alias superh uboot, iwamatsu
alias sh superh
-alias x86 uboot, gruss
+alias x86 uboot, sjg, gruss
# Subsystem aliases
alias cfi uboot, stroese
#include <linux/ctype.h>
#include <ahci.h>
+static int ata_io_flush(u8 port);
+
struct ahci_probe_ent *probe_ent = NULL;
hd_driveid_t *ataid[AHCI_MAX_PORTS];
#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
+/*
+ * Some controllers limit number of blocks they can read/write at once.
+ * Contemporary SSD devices work much faster if the read/write size is aligned
+ * to a power of 2. Let's set default to 128 and allowing to be overwritten if
+ * needed.
+ */
+#ifndef MAX_SATA_BLOCKS_READ_WRITE
+#define MAX_SATA_BLOCKS_READ_WRITE 0x80
+#endif
+
+/* Maximum timeouts for each event */
+#define WAIT_MS_SPINUP 10000
+#define WAIT_MS_DATAIO 5000
+#define WAIT_MS_FLUSH 5000
+#define WAIT_MS_LINKUP 4
static inline u32 ahci_port_base(u32 base, u32 port)
{
#define msleep(a) udelay(a * 1000)
-#define ssleep(a) msleep(a * 1000)
+
+static void ahci_dcache_flush_range(unsigned begin, unsigned len)
+{
+ const unsigned long start = begin;
+ const unsigned long end = start + len;
+
+ debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
+ flush_dcache_range(start, end);
+}
+
+/*
+ * SATA controller DMAs to physical RAM. Ensure data from the
+ * controller is invalidated from dcache; next access comes from
+ * physical RAM.
+ */
+static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
+{
+ const unsigned long start = begin;
+ const unsigned long end = start + len;
+
+ debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
+ invalidate_dcache_range(start, end);
+}
+
+/*
+ * Ensure data for SATA controller is flushed out of dcache and
+ * written to physical memory.
+ */
+static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
+{
+ ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
+ AHCI_PORT_PRIV_DMA_SZ);
+}
static int waiting_for_cmd_completed(volatile u8 *offset,
int timeout_msec,
unsigned short vendor;
#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
- u32 tmp, cap_save;
+ u32 tmp, cap_save, cmd;
int i, j;
volatile u8 *port_mmio;
+ debug("ahci_host_init: start\n");
+
cap_save = readl(mmio + HOST_CAP);
cap_save &= ((1 << 28) | (1 << 17));
- cap_save |= (1 << 27);
+ cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
/* global controller reset */
tmp = readl(mmio + HOST_CTL);
/* reset must complete within 1 second, or
* the hardware should be considered fried.
*/
- ssleep(1);
-
- tmp = readl(mmio + HOST_CTL);
- if (tmp & HOST_RESET) {
- debug("controller reset failed (0x%x)\n", tmp);
- return -1;
- }
+ i = 1000;
+ do {
+ udelay(1000);
+ tmp = readl(mmio + HOST_CTL);
+ if (!i--) {
+ debug("controller reset failed (0x%x)\n", tmp);
+ return -1;
+ }
+ } while (tmp & HOST_RESET);
writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
writel(cap_save, mmio + HOST_CAP);
debug("cap 0x%x port_map 0x%x n_ports %d\n",
probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
+ if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
+ probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
+
for (i = 0; i < probe_ent->n_ports; i++) {
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
port_mmio = (u8 *) probe_ent->port[i].port_mmio;
tmp = readl(port_mmio + PORT_CMD);
if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
PORT_CMD_FIS_RX | PORT_CMD_START)) {
+ debug("Port %d is active. Deactivating.\n", i);
tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
PORT_CMD_FIS_RX | PORT_CMD_START);
writel_with_flush(tmp, port_mmio + PORT_CMD);
msleep(500);
}
- writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
-
+ /* Add the spinup command to whatever mode bits may
+ * already be on in the command register.
+ */
+ cmd = readl(port_mmio + PORT_CMD);
+ cmd |= PORT_CMD_FIS_RX;
+ cmd |= PORT_CMD_SPIN_UP;
+ writel_with_flush(cmd, port_mmio + PORT_CMD);
+
+ /* Bring up SATA link.
+ * SATA link bringup time is usually less than 1 ms; only very
+ * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
+ */
j = 0;
- while (j < 100) {
- msleep(10);
+ while (j < WAIT_MS_LINKUP) {
tmp = readl(port_mmio + PORT_SCR_STAT);
if ((tmp & 0xf) == 0x3)
break;
+ udelay(1000);
j++;
}
+ if (j == WAIT_MS_LINKUP) {
+ printf("SATA link %d timeout.\n", i);
+ continue;
+ } else {
+ debug("SATA link ok.\n");
+ }
+
+ /* Clear error status */
+ tmp = readl(port_mmio + PORT_SCR_ERR);
+ if (tmp)
+ writel(tmp, port_mmio + PORT_SCR_ERR);
+
+ debug("Spinning up device on SATA port %d... ", i);
+
+ j = 0;
+ while (j < WAIT_MS_SPINUP) {
+ tmp = readl(port_mmio + PORT_TFDATA);
+ if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))
+ break;
+ udelay(1000);
+ j++;
+ }
+ printf("Target spinup took %d ms.\n", j);
+ if (j == WAIT_MS_SPINUP)
+ debug("timeout.\n");
+ else
+ debug("ok.\n");
tmp = readl(port_mmio + PORT_SCR_ERR);
debug("PORT_SCR_ERR 0x%x\n", tmp);
/* set irq mask (enables interrupts) */
writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
- /*register linkup ports */
+ /* register linkup ports */
tmp = readl(port_mmio + PORT_SCR_STAT);
- debug("Port %d status: 0x%x\n", i, tmp);
+ debug("SATA port %d status: 0x%x\n", i, tmp);
if ((tmp & 0xf) == 0x03)
probe_ent->link_port_map |= (0x01 << i);
}
u16 cc;
#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
- u32 vers, cap, impl, speed;
+ u32 vers, cap, cap2, impl, speed;
const char *speed_s;
const char *scc_s;
vers = readl(mmio + HOST_VERSION);
cap = probe_ent->cap;
+ cap2 = readl(mmio + HOST_CAP2);
impl = probe_ent->port_map;
speed = (cap >> 20) & 0xf;
speed_s = "1.5";
else if (speed == 2)
speed_s = "3";
+ else if (speed == 3)
+ speed_s = "6";
else
speed_s = "?";
((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
printf("flags: "
- "%s%s%s%s%s%s"
- "%s%s%s%s%s%s%s\n",
+ "%s%s%s%s%s%s%s"
+ "%s%s%s%s%s%s%s"
+ "%s%s%s%s%s%s\n",
cap & (1 << 31) ? "64bit " : "",
cap & (1 << 30) ? "ncq " : "",
cap & (1 << 28) ? "ilck " : "",
cap & (1 << 19) ? "nz " : "",
cap & (1 << 18) ? "only " : "",
cap & (1 << 17) ? "pmp " : "",
+ cap & (1 << 16) ? "fbss " : "",
cap & (1 << 15) ? "pio " : "",
cap & (1 << 14) ? "slum " : "",
- cap & (1 << 13) ? "part " : "");
+ cap & (1 << 13) ? "part " : "",
+ cap & (1 << 7) ? "ccc " : "",
+ cap & (1 << 6) ? "ems " : "",
+ cap & (1 << 5) ? "sxs " : "",
+ cap2 & (1 << 2) ? "apst " : "",
+ cap2 & (1 << 1) ? "nvmp " : "",
+ cap2 & (1 << 0) ? "boh " : "");
}
#ifndef CONFIG_SCSI_AHCI_PLAT
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
- probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR,
- PCI_REGION_MEM);
+ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
+ debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
/* Take from kernel:
* JMicron-specific fixup:
}
+#ifdef CONFIG_AHCI_SETFEATURES_XFER
static void ahci_set_feature(u8 port)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
u32 cmd_fis_len = 5; /* five dwords */
u8 fis[20];
- /*set feature */
- memset(fis, 0, 20);
+ /* set feature */
+ memset(fis, 0, sizeof(fis));
fis[0] = 0x27;
fis[1] = 1 << 7;
fis[2] = ATA_CMD_SETF;
fis[3] = SETFEATURES_XFER;
fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
- memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
+ memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
ahci_fill_cmd_slot(pp, cmd_fis_len);
+ ahci_dcache_flush_sata_cmd(pp);
writel(1, port_mmio + PORT_CMD_ISSUE);
readl(port_mmio + PORT_CMD_ISSUE);
- if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
- printf("set feature error!\n");
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
+ WAIT_MS_DATAIO, 0x1)) {
+ printf("set feature error on port %d!\n", port);
}
}
+#endif
static int ahci_port_start(u8 port)
* First item in chunk of DMA memory: 32-slot command table,
* 32 bytes each in size
*/
- pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
- debug("cmd_slot = %p\n", pp->cmd_slot);
+ pp->cmd_slot =
+ (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
+ debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
mem += (AHCI_CMD_SLOT_SZ + 224);
/*
* Second item: Received-FIS area
*/
- pp->rx_fis = mem;
+ pp->rx_fis = virt_to_phys((void *)mem);
mem += AHCI_RX_FIS_SZ;
/*
* Third item: data area for storing a single command
* and its scatter-gather table
*/
- pp->cmd_tbl = mem;
+ pp->cmd_tbl = virt_to_phys((void *)mem);
debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
mem += AHCI_CMD_TBL_HDR;
- pp->cmd_tbl_sg = (struct ahci_sg *)mem;
+ pp->cmd_tbl_sg =
+ (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
}
-static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
- int buf_len)
+static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
+ int buf_len, u8 is_write)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
u32 port_status;
int sg_count;
- debug("Enter get_ahci_device_data: for port %d\n", port);
+ debug("Enter %s: for port %d\n", __func__, port);
if (port > probe_ent->n_ports) {
- printf("Invaild port number %d\n", port);
+ printf("Invalid port number %d\n", port);
return -1;
}
memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
sg_count = ahci_fill_sg(port, buf, buf_len);
- opts = (fis_len >> 2) | (sg_count << 16);
+ opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
ahci_fill_cmd_slot(pp, opts);
+ ahci_dcache_flush_sata_cmd(pp);
+ ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
+
writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
- if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
+ WAIT_MS_DATAIO, 0x1)) {
printf("timeout exit!\n");
return -1;
}
- debug("get_ahci_device_data: %d byte transferred.\n",
- pp->cmd_slot->status);
+
+ ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
+ debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
return 0;
}
if (pccb->datalen <= 35)
return 0;
- memset(fis, 0, 20);
+ memset(fis, 0, sizeof(fis));
/* Construct the FIS */
fis[0] = 0x27; /* Host to device FIS. */
fis[1] = 1 << 7; /* Command FIS. */
if (!(tmpid = malloc(sizeof(hd_driveid_t))))
return -ENOMEM;
- if (get_ahci_device_data(port, (u8 *) & fis, 20,
- tmpid, sizeof(hd_driveid_t))) {
+ if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
+ sizeof(hd_driveid_t), 0)) {
debug("scsi_ahci: SCSI inquiry command failure.\n");
return -EIO;
}
/*
- * SCSI READ10 command operation.
+ * SCSI READ10/WRITE10 command operation.
*/
-static int ata_scsiop_read10(ccb * pccb)
+static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
{
- u32 len = 0;
+ u32 lba = 0;
+ u16 blocks = 0;
u8 fis[20];
+ u8 *user_buffer = pccb->pdata;
+ u32 user_buffer_size = pccb->datalen;
- len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
+ /* Retrieve the base LBA number from the ccb structure. */
+ memcpy(&lba, pccb->cmd + 2, sizeof(lba));
+ lba = be32_to_cpu(lba);
- /* For 10-byte and 16-byte SCSI R/W commands, transfer
+ /*
+ * And the number of blocks.
+ *
+ * For 10-byte and 16-byte SCSI R/W commands, transfer
* length 0 means transfer 0 block of data.
* However, for ATA R/W commands, sector count 0 means
* 256 or 65536 sectors, not 0 sectors as in SCSI.
*
* WARNING: one or two older ATA drives treat 0 as 0...
*/
- if (!len)
- return 0;
- memset(fis, 0, 20);
+ blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
- /* Construct the FIS */
- fis[0] = 0x27; /* Host to device FIS. */
- fis[1] = 1 << 7; /* Command FIS. */
- fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
-
- /* LBA address, only support LBA28 in this driver */
- fis[4] = pccb->cmd[5];
- fis[5] = pccb->cmd[4];
- fis[6] = pccb->cmd[3];
- fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
-
- /* Sector Count */
- fis[12] = pccb->cmd[8];
- fis[13] = pccb->cmd[7];
-
- /* Read from ahci */
- if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
- pccb->pdata, pccb->datalen)) {
- debug("scsi_ahci: SCSI READ10 command failure.\n");
- return -EIO;
+ debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
+ is_write ? "write" : "read", (unsigned)lba, blocks);
+
+ /* Preset the FIS */
+ memset(fis, 0, sizeof(fis));
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ /* Command byte (read/write). */
+ fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
+
+ while (blocks) {
+ u16 now_blocks; /* number of blocks per iteration */
+ u32 transfer_size; /* number of bytes per iteration */
+
+ now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
+
+ transfer_size = ATA_BLOCKSIZE * now_blocks;
+ if (transfer_size > user_buffer_size) {
+ printf("scsi_ahci: Error: buffer too small.\n");
+ return -EIO;
+ }
+
+ /* LBA48 SATA command but only use 32bit address range within
+ * that. The next smaller command range (28bit) is too small.
+ */
+ fis[4] = (lba >> 0) & 0xff;
+ fis[5] = (lba >> 8) & 0xff;
+ fis[6] = (lba >> 16) & 0xff;
+ fis[7] = 1 << 6; /* device reg: set LBA mode */
+ fis[8] = ((lba >> 24) & 0xff);
+ fis[3] = 0xe0; /* features */
+
+ /* Block (sector) count */
+ fis[12] = (now_blocks >> 0) & 0xff;
+ fis[13] = (now_blocks >> 8) & 0xff;
+
+ /* Read/Write from ahci */
+ if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
+ user_buffer, user_buffer_size,
+ is_write)) {
+ debug("scsi_ahci: SCSI %s10 command failure.\n",
+ is_write ? "WRITE" : "READ");
+ return -EIO;
+ }
+
+ /* If this transaction is a write, do a following flush.
+ * Writes in u-boot are so rare, and the logic to know when is
+ * the last write and do a flush only there is sufficiently
+ * difficult. Just do a flush after every write. This incurs,
+ * usually, one extra flush when the rare writes do happen.
+ */
+ if (is_write) {
+ if (-EIO == ata_io_flush(pccb->target))
+ return -EIO;
+ }
+ user_buffer += transfer_size;
+ user_buffer_size -= transfer_size;
+ blocks -= now_blocks;
+ lba += now_blocks;
}
return 0;
static int ata_scsiop_read_capacity10(ccb *pccb)
{
u32 cap;
+ u32 block_size;
if (!ataid[pccb->target]) {
printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
}
cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
+ if (cap == 0xfffffff) {
+ unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
+ if (cap48[2] || cap48[3]) {
+ cap = 0xffffffff;
+ } else {
+ cap = (le16_to_cpu(cap48[1]) << 16) |
+ (le16_to_cpu(cap48[0]));
+ }
+ }
+
+ cap = cpu_to_be32(cap);
+ memcpy(pccb->pdata, &cap, sizeof(cap));
+
+ block_size = cpu_to_be32((u32)512);
+ memcpy(&pccb->pdata[4], &block_size, 4);
+
+ return 0;
+}
+
+
+/*
+ * SCSI READ CAPACITY16 command operation.
+ */
+static int ata_scsiop_read_capacity16(ccb *pccb)
+{
+ u64 cap;
+ u64 block_size;
+
+ if (!ataid[pccb->target]) {
+ printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
+ "\tNo ATA info!\n"
+ "\tPlease run SCSI commmand INQUIRY firstly!\n");
+ return -EPERM;
+ }
+
+ cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
+ if (cap == 0xfffffff) {
+ memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
+ cap = le64_to_cpu(cap);
+ }
+
+ cap = cpu_to_be64(cap);
memcpy(pccb->pdata, &cap, sizeof(cap));
- pccb->pdata[4] = pccb->pdata[5] = 0;
- pccb->pdata[6] = 512 >> 8;
- pccb->pdata[7] = 512 & 0xff;
+ block_size = cpu_to_be64((u64)512);
+ memcpy(&pccb->pdata[8], &block_size, 8);
return 0;
}
switch (pccb->cmd[0]) {
case SCSI_READ10:
- ret = ata_scsiop_read10(pccb);
+ ret = ata_scsiop_read_write(pccb, 0);
break;
- case SCSI_RD_CAPAC:
+ case SCSI_WRITE10:
+ ret = ata_scsiop_read_write(pccb, 1);
+ break;
+ case SCSI_RD_CAPAC10:
ret = ata_scsiop_read_capacity10(pccb);
break;
+ case SCSI_RD_CAPAC16:
+ ret = ata_scsiop_read_capacity16(pccb);
+ break;
case SCSI_TST_U_RDY:
ret = ata_scsiop_test_unit_ready(pccb);
break;
printf("Can not start port %d\n", i);
continue;
}
+#ifdef CONFIG_AHCI_SETFEATURES_XFER
ahci_set_feature((u8) i);
+#endif
}
}
}
printf("Can not start port %d\n", i);
continue;
}
+#ifdef CONFIG_AHCI_SETFEATURES_XFER
ahci_set_feature((u8) i);
+#endif
}
}
err_out:
}
#endif
+/*
+ * In the general case of generic rotating media it makes sense to have a
+ * flush capability. It probably even makes sense in the case of SSDs because
+ * one cannot always know for sure what kind of internal cache/flush mechanism
+ * is embodied therein. At first it was planned to invoke this after the last
+ * write to disk and before rebooting. In practice, knowing, a priori, which
+ * is the last write is difficult. Because writing to the disk in u-boot is
+ * very rare, this flush command will be invoked after every block write.
+ */
+static int ata_io_flush(u8 port)
+{
+ u8 fis[20];
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ u32 cmd_fis_len = 5; /* five dwords */
+
+ /* Preset the FIS */
+ memset(fis, 0, 20);
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ fis[2] = ATA_CMD_FLUSH_EXT;
+
+ memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
+ ahci_fill_cmd_slot(pp, cmd_fis_len);
+ writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
+
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
+ WAIT_MS_FLUSH, 0x1)) {
+ debug("scsi_ahci: flush command timeout on port %d.\n", port);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+
void scsi_bus_reset(void)
{
/*Not implement*/
mdelay(1000);
}
-void dprint_buffer(unsigned char *buf, int len)
-{
- int i, j;
-
- i = 0;
- j = 0;
- printf("\n\r");
-
- for (i = 0; i < len; i++) {
- printf("%02x ", *buf++);
- j++;
- if (j == 16) {
- printf("\n\r");
- j = 0;
- }
- }
- printf("\n\r");
-}
-
static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
{
printf("Status FIS dump:\n\r");
printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
}
-static int ata_wait_register(volatile unsigned *addr, u32 mask,
+static int ata_wait_register(unsigned __iomem *addr, u32 mask,
u32 val, u32 timeout_msec)
{
int i;
cmd_hdr_tbl_t *cmd_hdr;
u32 cda;
u32 val32;
- fsl_sata_reg_t *reg;
+ fsl_sata_reg_t __iomem *reg;
u32 sig;
int i;
fsl_sata_t *sata;
return 0;
}
-/* Hardware reset, like Power-on and COMRESET */
-void fsl_sata_hardware_reset(u32 reg_base)
-{
- fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base;
- u32 scontrol;
-
- /* Disable the SATA interface and put PHY offline */
- scontrol = in_le32(®->scontrol);
- scontrol = (scontrol & 0x0f0) | 0x304;
- out_le32(®->scontrol, scontrol);
-
- /* No speed strict */
- scontrol = in_le32(®->scontrol);
- scontrol = scontrol & ~0x0f0;
- out_le32(®->scontrol, scontrol);
-
- /* Issue PHY wake/reset, Hardware_reset_asserted */
- scontrol = in_le32(®->scontrol);
- scontrol = (scontrol & 0x0f0) | 0x301;
- out_le32(®->scontrol, scontrol);
-
- mdelay(100);
-
- /* Resume PHY, COMRESET negated, the device initialize hardware
- * and execute diagnostics, send good status-signature to host,
- * which is D2H register FIS, and then the device enter idle state.
- */
- scontrol = in_le32(®->scontrol);
- scontrol = (scontrol & 0x0f0) | 0x300;
- out_le32(®->scontrol, scontrol);
-
- mdelay(100);
- return;
-}
-
-static void fsl_sata_dump_regs(fsl_sata_reg_t *reg)
+static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
{
printf("\n\rSATA: %08x\n\r", (u32)reg);
printf("CQR: %08x\n\r", in_le32(®->cqr));
u32 prde_count;
u32 val32;
u32 ttl;
- fsl_sata_reg_t *reg = sata->reg_base;
+ fsl_sata_reg_t __iomem *reg = sata->reg_base;
int i;
/* Check xfer length */
return blkcnt;
}
-void fsl_sata_flush_cache(int dev)
+static void fsl_sata_flush_cache(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
return blkcnt;
}
-u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
+static u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer,
+ int is_write)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
return blkcnt;
}
-void fsl_sata_flush_cache_ext(int dev)
+static void fsl_sata_flush_cache_ext(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
}
-/* Software reset, set SRST of the Device Control register */
-void fsl_sata_software_reset(int dev)
-{
- return;
-}
-
static void fsl_sata_init_wcache(int dev, u16 *id)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
return sata->flush_ext;
}
-u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
+static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
const void *buffer, int is_write)
{
u32 start, blks;
return blkcnt;
}
-u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, const void *buffer,
- int is_write)
+static u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt,
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
* Command Header Entry
*/
typedef struct cmd_hdr_entry {
- u32 cda; /* Command Descriptor Address, 4 bytes aligned */
- u32 prde_fis_len; /* Number of PRD entries and FIS length */
- u32 ttl; /* Total transfer length */
- u32 attribute; /* the attribute of command */
+ __le32 cda; /* Command Descriptor Address,
+ 4 bytes aligned */
+ __le32 prde_fis_len; /* Number of PRD entries and FIS length */
+ __le32 ttl; /* Total transfer length */
+ __le32 attribute; /* the attribute of command */
} __attribute__ ((packed)) cmd_hdr_entry_t;
#define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry)
* PRD entry - Physical Region Descriptor entry
*/
typedef struct prd_entry {
- u32 dba; /* Data base address, 4 bytes aligned */
+ __le32 dba; /* Data base address, 4 bytes aligned */
u32 res1;
u32 res2;
- u32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */
+ __le32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */
} __attribute__ ((packed)) prd_entry_t;
#define SATA_HC_CMD_DESC_PRD_SIZE sizeof(struct prd_entry)
#include <fis.h>
#include <sata.h>
#include <libata.h>
+#include <sata.h>
#include "sata_sil.h"
/* Convert sectorsize to wordsize */
return blkcnt;
}
-ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
- const void *buffer, int is_write)
+static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
+ const void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
return blkcnt;
}
-ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
- const void *buffer, int is_write)
+static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
+ const void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
return blkcnt;
}
-void sil_sata_cmd_flush_cache(int dev)
+static void sil_sata_cmd_flush_cache(int dev)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;
sil_exec_cmd(dev, pcmd, 0);
}
-void sil_sata_cmd_flush_cache_ext(int dev)
+static void sil_sata_cmd_flush_cache_ext(int dev)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;
}
/* Establish the initial state */
+ (*fn->config) (FALSE, TRUE, cookie); /* De-assert nCONFIG */
+ udelay(100);
(*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
udelay(2); /* T_cfg > 2us */
}
/* Configure GPIO registers early */
-void mpc83xx_gpio_init_f()
+void mpc83xx_gpio_init_f(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
}
/* Initialize GPIO soft-copies */
-void mpc83xx_gpio_init_r()
+void mpc83xx_gpio_init_r(void)
{
#if MPC83XX_GPIO_CTRLRS >= 1
gpio_output_value[0] = CONFIG_MPC83XX_GPIO_0_INIT_VALUE;
return speed;
}
-unsigned int get_i2c_clock(int bus)
+static unsigned int get_i2c_clock(int bus)
{
if (bus)
return gd->i2c2_clk; /* I2C2 clock */
/* Maximum number of output characters that an ANSI sequence expands to */
#define ANSI_CHAR_MAX 3
-int input_queue_ascii(struct input_config *config, int ch)
+static int input_queue_ascii(struct input_config *config, int ch)
{
if (config->fifo_in + 1 == INPUT_BUFFER_LEN) {
if (!config->fifo_out)
};
/* Return the XFERTYP flags for a given command and data packet */
-uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
+static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
uint xfertyp = 0;
int board_mmc_getcd(struct mmc *mmc)__attribute__((weak,
alias("__board_mmc_getcd")));
-int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
{
struct mmc_data backup;
int ret;
return ret;
}
-int mmc_send_status(struct mmc *mmc, int timeout)
+static int mmc_send_status(struct mmc *mmc, int timeout)
{
struct mmc_cmd cmd;
int err, retries = 5;
return 0;
}
-int mmc_set_blocklen(struct mmc *mmc, int len)
+static int mmc_set_blocklen(struct mmc *mmc, int len)
{
struct mmc_cmd cmd;
return blkcnt;
}
-int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start, lbaint_t blkcnt)
+static int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start,
+ lbaint_t blkcnt)
{
struct mmc_cmd cmd;
struct mmc_data data;
return blkcnt;
}
-int mmc_go_idle(struct mmc* mmc)
+static int mmc_go_idle(struct mmc *mmc)
{
struct mmc_cmd cmd;
int err;
return 0;
}
-int
-sd_send_op_cond(struct mmc *mmc)
+static int sd_send_op_cond(struct mmc *mmc)
{
int timeout = 1000;
int err;
return 0;
}
-int mmc_send_op_cond(struct mmc *mmc)
+static int mmc_send_op_cond(struct mmc *mmc)
{
int timeout = 10000;
struct mmc_cmd cmd;
}
-int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
+static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
{
struct mmc_cmd cmd;
struct mmc_data data;
}
-int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
+static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
{
struct mmc_cmd cmd;
int timeout = 1000;
}
-int mmc_change_freq(struct mmc *mmc)
+static int mmc_change_freq(struct mmc *mmc)
{
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
char cardtype;
return cd;
}
-int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
+static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
{
struct mmc_cmd cmd;
struct mmc_data data;
}
-int sd_change_freq(struct mmc *mmc)
+static int sd_change_freq(struct mmc *mmc)
{
int err;
struct mmc_cmd cmd;
80,
};
-void mmc_set_ios(struct mmc *mmc)
+static void mmc_set_ios(struct mmc *mmc)
{
mmc->set_ios(mmc);
}
mmc_set_ios(mmc);
}
-void mmc_set_bus_width(struct mmc *mmc, uint width)
+static void mmc_set_bus_width(struct mmc *mmc, uint width)
{
mmc->bus_width = width;
mmc_set_ios(mmc);
}
-int mmc_startup(struct mmc *mmc)
+static int mmc_startup(struct mmc *mmc)
{
int err, width;
uint mult, freq;
if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
/* check ext_csd version and capacity */
err = mmc_send_ext_csd(mmc, ext_csd);
- if (!err & (ext_csd[EXT_CSD_REV] >= 2)) {
+ if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
/*
* According to the JEDEC Standard, the value of
* ext_csd's capacity is valid if the value is more
return 0;
}
-int mmc_send_if_cond(struct mmc *mmc)
+static int mmc_send_if_cond(struct mmc *mmc)
{
struct mmc_cmd cmd;
int err;
*/
static flash_sect_t find_sector (flash_info_t * info, ulong addr)
{
- static flash_sect_t saved_sector = 0; /* previously found sector */
- static flash_info_t *saved_info = 0; /* previously used flash bank */
+ static flash_sect_t saved_sector; /* previously found sector */
+ static flash_info_t *saved_info; /* previously used flash bank */
flash_sect_t sector = saved_sector;
if ((info != saved_info) || (sector >= info->sector_count))
}
if (use_flash_status_poll(info)) {
- cfiword_t cword = (cfiword_t)0xffffffffffffffffULL;
+ cfiword_t cword;
void *dest;
+ cword.ll = 0xffffffffffffffffULL;
dest = flash_map(info, sect, 0);
st = flash_status_poll(info, &cword, dest,
info->erase_blk_tout, "erase");
static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot)
{
- if ((info->manufacturer_id == (uchar)INTEL_MANUFACT) &&
- (info->device_id == NUMONYX_256MBIT)) {
+ if (info->manufacturer_id == ((INTEL_MANUFACT & FLASH_VENDMASK) >> 16)
+ && info->device_id == NUMONYX_256MBIT) {
/*
* see errata called
* "Numonyx Axcell P33/P30 Specification Update" :)
case CFI_CMDSET_AMD_EXTENDED:
case CFI_CMDSET_AMD_STANDARD:
/* U-Boot only checks the first byte */
- if (info->manufacturer_id == (uchar)ATM_MANUFACT) {
+ if (info->manufacturer_id ==
+ ((ATM_MANUFACT & FLASH_VENDMASK) >> 16)) {
if (prot) {
flash_unlock_seq (info, 0);
flash_write_cmd (info, 0,
0, ATM_CMD_UNLOCK_SECT);
}
}
- if (info->manufacturer_id == (uchar)AMD_MANUFACT) {
+ if (info->manufacturer_id ==
+ ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
int flag = disable_interrupts();
int lock_flag;
flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
#ifdef CONFIG_SYS_FLASH_PROTECTION
- if (info->ext_addr && info->manufacturer_id == (uchar)AMD_MANUFACT) {
+ if (info->ext_addr && info->manufacturer_id ==
+ ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
ushort spus;
/* read sector protect/unprotect scheme */
p[i] = flash_read_uchar(info, start + i);
}
-void __flash_cmd_reset(flash_info_t *info)
+static void __flash_cmd_reset(flash_info_t *info)
{
/*
* We do not yet know what kind of commandset to use, so we issue
int *maf_id, int *dev_id,
const struct nand_flash_dev *type)
{
+ const char *name;
int i, maf_idx;
u8 id_data[8];
int ret;
chip->cmdfunc = nand_command_lp;
/* TODO onfi flash name */
- MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
- " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
- nand_manuf_ids[maf_idx].name,
+ name = type->name;
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
- chip->onfi_version ? chip->onfi_params.model : type->name);
-#else
- type->name);
+ if (chip->onfi_version)
+ name = chip->onfi_params.model;
#endif
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
+ " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
+ nand_manuf_ids[maf_idx].name, name);
return type;
}
#include <asm/errno.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand_ecc.h>
/* The PPC4xx NDFC uses Smart Media (SMC) bytes order */
#ifdef CONFIG_NAND_NDFC
#include "crc32defs.h"
#define CRC_LE_BITS 8
-# define __force
-#ifndef __constant_cpu_to_le32
-#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x))
-#endif
-#ifndef __constant_le32_to_cpu
-#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x))
-#endif
-
#if CRC_LE_BITS == 8
-#define tole(x) __constant_cpu_to_le32(x)
-#define tobe(x) __constant_cpu_to_be32(x)
+#define tole(x) cpu_to_le32(x)
+#define tobe(x) cpu_to_be32(x)
#else
#define tole(x) (x)
#define tobe(x) (x)
TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
/* Configure the TBI for SGMII operation */
-void dtsec_configure_serdes(struct fm_eth *priv)
+static void dtsec_configure_serdes(struct fm_eth *priv)
{
#ifdef CONFIG_SYS_FMAN_V3
u32 value;
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
-u32 port_to_devdisr[] = {
+static u32 port_to_devdisr[] = {
[FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1,
[FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2,
};
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
-u32 port_to_devdisr[] = {
+static u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
-u32 port_to_devdisr[] = {
+static u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
* until the write is done before it returns. All PHY configuration has to be
* done through the TSEC1 MIIM regs
*/
-int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
- int regnum, u16 value)
+static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum, u16 value)
{
u32 mdio_ctl;
u32 stat_val;
* Clears miimcom first. All PHY configuration has to be done through the
* TSEC1 MIIM regs
*/
-int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
- int regnum)
+static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum)
{
u32 mdio_ctl;
u32 stat_val;
return in_be32(®s->mdio_data) & 0xffff;
}
-int tgec_mdio_reset(struct mii_dev *bus)
+static int tgec_mdio_reset(struct mii_dev *bus)
{
return 0;
}
#include "macb.h"
-#define barrier() asm volatile("" ::: "memory")
-
#define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
#define CONFIG_SYS_MACB_TX_RING_SIZE 16
return 0;
}
-struct phy_driver AR8021_driver = {
+static struct phy_driver AR8021_driver = {
.name = "AR8021",
.uid = 0x4dd040,
.mask = 0xfffff0,
* what is supported. Returns < 0 on error, 0 if the PHY's advertisement
* hasn't changed, and > 0 if it has changed.
*/
-int genphy_config_advert(struct phy_device *phydev)
+static int genphy_config_advert(struct phy_device *phydev)
{
u32 advertise;
int oldadv, adv;
* Description: Configures MII_BMCR to force speed/duplex
* to the values in phydev. Assumes that the values are valid.
*/
-int genphy_setup_forced(struct phy_device *phydev)
+static int genphy_setup_forced(struct phy_device *phydev)
{
int err;
int ctl = 0;
return 0;
}
-int phy_probe(struct phy_device *phydev)
+static int phy_probe(struct phy_device *phydev)
{
int err = 0;
return &genphy_driver;
}
-struct phy_driver *get_phy_driver(struct phy_device *phydev,
+static struct phy_driver *get_phy_driver(struct phy_device *phydev,
phy_interface_t interface)
{
struct list_head *entry;
return generic_for_interface(interface);
}
-struct phy_device *phy_device_create(struct mii_dev *bus, int addr, int phy_id,
- phy_interface_t interface)
+static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
+ int phy_id,
+ phy_interface_t interface)
{
struct phy_device *dev;
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, stores it in @phy_id and returns zero on success.
*/
-int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, then allocates and returns the phy_device to represent it.
*/
-struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
- phy_interface_t interface)
+static struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
+ phy_interface_t interface)
{
u32 phy_id = 0x1fffffff;
int i;
}
/* Vitesse VSC8601 */
-int vsc8601_config(struct phy_device *phydev)
+static int vsc8601_config(struct phy_device *phydev)
{
/* Configure some basic stuff */
#ifdef CONFIG_SYS_VSC8601_SKEWFIX
* inx,outx functions fixed this problem.
*/
-#define barrier() __asm__ __volatile__("": : :"memory")
-
static inline word SMC_inw(struct eth_device *dev, dword offset)
{
word v;
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
+#include "vsc7385.h"
/*
* Upload a Vitesse VSC7385 firmware image to the hardware
#error "Bad: you didn't configure serial ..."
#endif
-#define barrier() asm volatile("" ::: "memory")
-
/*
* The coefficient, used to calculate the baudrate on S3C6400 UARTs is
* calculated as
/* Multi serial device functions */
#define DECLARE_ESERIAL_FUNCTIONS(port) \
- int eserial##port##_init (void) {\
- int clock_divisor; \
- clock_divisor = calc_divisor(serial_ports[port-1]); \
- NS16550_init(serial_ports[port-1], clock_divisor); \
- return(0);}\
- void eserial##port##_setbrg (void) {\
- serial_setbrg_dev(port);}\
- int eserial##port##_getc (void) {\
- return serial_getc_dev(port);}\
- int eserial##port##_tstc (void) {\
- return serial_tstc_dev(port);}\
- void eserial##port##_putc (const char c) {\
- serial_putc_dev(port, c);}\
- void eserial##port##_puts (const char *s) {\
- serial_puts_dev(port, s);}
+ static int eserial##port##_init(void) \
+ { \
+ int clock_divisor; \
+ clock_divisor = calc_divisor(serial_ports[port-1]); \
+ NS16550_init(serial_ports[port-1], clock_divisor); \
+ return 0 ; \
+ } \
+ static void eserial##port##_setbrg(void) \
+ { \
+ serial_setbrg_dev(port); \
+ } \
+ static int eserial##port##_getc(void) \
+ { \
+ return serial_getc_dev(port); \
+ } \
+ static int eserial##port##_tstc(void) \
+ { \
+ return serial_tstc_dev(port); \
+ } \
+ static void eserial##port##_putc(const char c) \
+ { \
+ serial_putc_dev(port, c); \
+ } \
+ static void eserial##port##_puts(const char *s) \
+ { \
+ serial_puts_dev(port, s); \
+ }
/* Serial device descriptor */
#define INIT_ESERIAL_STRUCTURE(port, __name) { \
p = q;
}
- if (i == 6) /* it looks ok */
- return 1;
+ /* Now check the contents. */
+ return is_valid_ether_addr(ea);
}
return 0;
}
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
#
# See file CREDITS for list of people who contributed to this
# project.
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-#
-subdirs-$(CONFIG_CMD_CBFS) += cbfs
-subdirs-$(CONFIG_CMD_CRAMFS) := cramfs
-subdirs-$(CONFIG_CMD_EXT4) += ext4
-ifndef CONFIG_CMD_EXT4
-subdirs-$(CONFIG_CMD_EXT2) += ext4
-endif
-subdirs-$(CONFIG_CMD_FAT) += fat
-subdirs-$(CONFIG_CMD_FDOS) += fdos
-subdirs-$(CONFIG_CMD_JFFS2) += jffs2
-subdirs-$(CONFIG_CMD_REISER) += reiserfs
-subdirs-$(CONFIG_YAFFS2) += yaffs2
-subdirs-$(CONFIG_CMD_UBIFS) += ubifs
-subdirs-$(CONFIG_CMD_ZFS) += zfs
-
-SUBDIRS := $(subdirs-y)
-
-$(obj).depend all:
- @for dir in $(SUBDIRS) ; do \
- $(MAKE) -C $$dir $@ ; done
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libfs.o
+
+COBJS-y += fs.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
LIB = $(obj)libext4fs.o
AOBJS =
-COBJS-$(CONFIG_CMD_EXT4) := ext4fs.o ext4_common.o dev.o
-ifndef CONFIG_CMD_EXT4
-COBJS-$(CONFIG_CMD_EXT2) := ext4fs.o ext4_common.o dev.o
-endif
-COBJS-$(CONFIG_CMD_EXT4_WRITE) += ext4_journal.o crc16.o
+COBJS-$(CONFIG_FS_EXT4) := ext4fs.o ext4_common.o dev.o
+COBJS-$(CONFIG_EXT4_WRITE) += ext4_journal.o crc16.o
SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y))
struct ext2_inode *g_parent_inode;
static int symlinknest;
-#if defined(CONFIG_CMD_EXT4_WRITE)
+#if defined(CONFIG_EXT4_WRITE)
uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n)
{
uint32_t res = size / n;
#include <ext4fs.h>
#include <malloc.h>
#include <asm/errno.h>
-#if defined(CONFIG_CMD_EXT4_WRITE)
+#if defined(CONFIG_EXT4_WRITE)
#include "ext4_journal.h"
#include "crc16.h"
#endif
int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
struct ext2fs_node **fnode, int *ftype);
-#if defined(CONFIG_CMD_EXT4_WRITE)
+#if defined(CONFIG_EXT4_WRITE)
uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n);
int ext4fs_checksum_update(unsigned int i);
int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags);
return ext4fs_read_file(ext4fs_file, 0, len, buf);
}
-#if defined(CONFIG_CMD_EXT4_WRITE)
+#if defined(CONFIG_EXT4_WRITE)
static void ext4fs_update(void)
{
short i;
LIB = $(obj)libfat.o
AOBJS =
-COBJS-$(CONFIG_CMD_FAT) := fat.o
+COBJS-$(CONFIG_FS_FAT) := fat.o
COBJS-$(CONFIG_FAT_WRITE):= fat_write.o
ifndef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_CMD_FAT) += file.o
+COBJS-$(CONFIG_FS_FAT) += file.o
endif
SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
}
static block_dev_desc_t *cur_dev;
-static unsigned int cur_part_nr;
static disk_partition_t cur_part_info;
#define DOS_BOOT_MAGIC_OFFSET 0x1fe
cur_part_info.start + block, nr_blocks, buf);
}
-int fat_register_device(block_dev_desc_t * dev_desc, int part_no)
+int fat_set_blk_dev(block_dev_desc_t *dev_desc, disk_partition_t *info)
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
- /* First close any currently found FAT filesystem */
- cur_dev = NULL;
-
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) )
-
- /* Read the partition table, if present */
- if (!get_partition_info(dev_desc, part_no, &cur_part_info)) {
- cur_dev = dev_desc;
- cur_part_nr = part_no;
- }
-#endif
-
- /* Otherwise it might be a superfloppy (whole-disk FAT filesystem) */
- if (!cur_dev) {
- if (part_no != 0) {
- printf("** Partition %d not valid on device %d **\n",
- part_no, dev_desc->dev);
- return -1;
- }
-
- cur_dev = dev_desc;
- cur_part_nr = 1;
- cur_part_info.start = 0;
- cur_part_info.size = dev_desc->lba;
- cur_part_info.blksz = dev_desc->blksz;
- memset(cur_part_info.name, 0, sizeof(cur_part_info.name));
- memset(cur_part_info.type, 0, sizeof(cur_part_info.type));
- }
+ cur_dev = dev_desc;
+ cur_part_info = *info;
/* Make sure it has a valid FAT header */
if (disk_read(0, 1, buffer) != 1) {
return -1;
}
+int fat_register_device(block_dev_desc_t *dev_desc, int part_no)
+{
+ disk_partition_t info;
+
+ /* First close any currently found FAT filesystem */
+ cur_dev = NULL;
+
+ /* Read the partition table, if present */
+ if (get_partition_info(dev_desc, part_no, &info)) {
+ if (part_no != 0) {
+ printf("** Partition %d not valid on device %d **\n",
+ part_no, dev_desc->dev);
+ return -1;
+ }
+
+ info.start = 0;
+ info.size = dev_desc->lba;
+ info.blksz = dev_desc->blksz;
+ info.name[0] = 0;
+ info.type[0] = 0;
+ info.bootable = 0;
+#ifdef CONFIG_PARTITION_UUIDS
+ info.uuid[0] = 0;
+#endif
+ }
+
+ return fat_set_blk_dev(dev_desc, &info);
+}
/*
* Get the first occurence of a directory delimiter ('/' or '\') in a string.
vol_label[11] = '\0';
volinfo.fs_type[5] = '\0';
- printf("Partition %d: Filesystem: %s \"%s\"\n", cur_part_nr,
- volinfo.fs_type, vol_label);
+ printf("Filesystem: %s \"%s\"\n", volinfo.fs_type, vol_label);
return 0;
}
--- /dev/null
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <part.h>
+#include <ext4fs.h>
+#include <fat.h>
+#include <fs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static block_dev_desc_t *fs_dev_desc;
+static disk_partition_t fs_partition;
+static int fs_type = FS_TYPE_ANY;
+
+static inline int fs_ls_unsupported(const char *dirname)
+{
+ printf("** Unrecognized filesystem type **\n");
+ return -1;
+}
+
+static inline int fs_read_unsupported(const char *filename, ulong addr,
+ int offset, int len)
+{
+ printf("** Unrecognized filesystem type **\n");
+ return -1;
+}
+
+#ifdef CONFIG_FS_FAT
+static int fs_probe_fat(void)
+{
+ return fat_set_blk_dev(fs_dev_desc, &fs_partition);
+}
+
+static void fs_close_fat(void)
+{
+}
+
+#define fs_ls_fat file_fat_ls
+
+static int fs_read_fat(const char *filename, ulong addr, int offset, int len)
+{
+ int len_read;
+
+ len_read = file_fat_read_at(filename, offset,
+ (unsigned char *)addr, len);
+ if (len_read == -1) {
+ printf("** Unable to read file %s **\n", filename);
+ return -1;
+ }
+
+ return len_read;
+}
+#else
+static inline int fs_probe_fat(void)
+{
+ return -1;
+}
+
+static inline void fs_close_fat(void)
+{
+}
+
+#define fs_ls_fat fs_ls_unsupported
+#define fs_read_fat fs_read_unsupported
+#endif
+
+#ifdef CONFIG_FS_EXT4
+static int fs_probe_ext(void)
+{
+ ext4fs_set_blk_dev(fs_dev_desc, &fs_partition);
+
+ if (!ext4fs_mount(fs_partition.size)) {
+ ext4fs_close();
+ return -1;
+ }
+
+ return 0;
+}
+
+static void fs_close_ext(void)
+{
+ ext4fs_close();
+}
+
+#define fs_ls_ext ext4fs_ls
+
+static int fs_read_ext(const char *filename, ulong addr, int offset, int len)
+{
+ int file_len;
+ int len_read;
+
+ if (offset != 0) {
+ printf("** Cannot support non-zero offset **\n");
+ return -1;
+ }
+
+ file_len = ext4fs_open(filename);
+ if (file_len < 0) {
+ printf("** File not found %s **\n", filename);
+ ext4fs_close();
+ return -1;
+ }
+
+ if (len == 0)
+ len = file_len;
+
+ len_read = ext4fs_read((char *)addr, len);
+ ext4fs_close();
+
+ if (len_read != len) {
+ printf("** Unable to read file %s **\n", filename);
+ return -1;
+ }
+
+ return len_read;
+}
+#else
+static inline int fs_probe_ext(void)
+{
+ return -1;
+}
+
+static inline void fs_close_ext(void)
+{
+}
+
+#define fs_ls_ext fs_ls_unsupported
+#define fs_read_ext fs_read_unsupported
+#endif
+
+static struct {
+ int fstype;
+ int (*probe)(void);
+} fstypes[] = {
+ {
+ .fstype = FS_TYPE_FAT,
+ .probe = fs_probe_fat,
+ },
+ {
+ .fstype = FS_TYPE_EXT,
+ .probe = fs_probe_ext,
+ },
+};
+
+int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype)
+{
+ int part, i;
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ static int relocated;
+
+ if (!relocated) {
+ for (i = 0; i < ARRAY_SIZE(fstypes); i++)
+ fstypes[i].probe += gd->reloc_off;
+ relocated = 1;
+ }
+#endif
+
+ part = get_device_and_partition(ifname, dev_part_str, &fs_dev_desc,
+ &fs_partition, 1);
+ if (part < 0)
+ return -1;
+
+ for (i = 0; i < ARRAY_SIZE(fstypes); i++) {
+ if ((fstype != FS_TYPE_ANY) && (fstype != fstypes[i].fstype))
+ continue;
+
+ if (!fstypes[i].probe()) {
+ fs_type = fstypes[i].fstype;
+ return 0;
+ }
+ }
+
+ printf("** Unrecognized filesystem type **\n");
+ return -1;
+}
+
+static void fs_close(void)
+{
+ switch (fs_type) {
+ case FS_TYPE_FAT:
+ fs_close_fat();
+ break;
+ case FS_TYPE_EXT:
+ fs_close_ext();
+ break;
+ default:
+ break;
+ }
+
+ fs_type = FS_TYPE_ANY;
+}
+
+int fs_ls(const char *dirname)
+{
+ int ret;
+
+ switch (fs_type) {
+ case FS_TYPE_FAT:
+ ret = fs_ls_fat(dirname);
+ break;
+ case FS_TYPE_EXT:
+ ret = fs_ls_ext(dirname);
+ break;
+ default:
+ ret = fs_ls_unsupported(dirname);
+ break;
+ }
+
+ fs_close();
+
+ return ret;
+}
+
+int fs_read(const char *filename, ulong addr, int offset, int len)
+{
+ int ret;
+
+ switch (fs_type) {
+ case FS_TYPE_FAT:
+ ret = fs_read_fat(filename, addr, offset, len);
+ break;
+ case FS_TYPE_EXT:
+ ret = fs_read_ext(filename, addr, offset, len);
+ break;
+ default:
+ ret = fs_read_unsupported(filename, addr, offset, len);
+ break;
+ }
+
+ fs_close();
+
+ return ret;
+}
+
+int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype, int cmdline_base)
+{
+ unsigned long addr;
+ const char *addr_str;
+ const char *filename;
+ unsigned long bytes;
+ unsigned long pos;
+ int len_read;
+ char buf[12];
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ if (argc > 7)
+ return CMD_RET_USAGE;
+
+ if (fs_set_blk_dev(argv[1], (argc >= 3) ? argv[2] : NULL, fstype))
+ return 1;
+
+ if (argc >= 4) {
+ addr = simple_strtoul(argv[3], NULL, cmdline_base);
+ } else {
+ addr_str = getenv("loadaddr");
+ if (addr_str != NULL)
+ addr = simple_strtoul(addr_str, NULL, 16);
+ else
+ addr = CONFIG_SYS_LOAD_ADDR;
+ }
+ if (argc >= 5) {
+ filename = argv[4];
+ } else {
+ filename = getenv("bootfile");
+ if (!filename) {
+ puts("** No boot file defined **\n");
+ return 1;
+ }
+ }
+ if (argc >= 6)
+ bytes = simple_strtoul(argv[5], NULL, cmdline_base);
+ else
+ bytes = 0;
+ if (argc >= 7)
+ pos = simple_strtoul(argv[6], NULL, cmdline_base);
+ else
+ pos = 0;
+
+ len_read = fs_read(filename, addr, pos, bytes);
+ if (len_read <= 0)
+ return 1;
+
+ printf("%d bytes read\n", len_read);
+
+ sprintf(buf, "0x%x", len_read);
+ setenv("filesize", buf);
+
+ return 0;
+}
+
+int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype)
+{
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ if (argc > 4)
+ return CMD_RET_USAGE;
+
+ if (fs_set_blk_dev(argv[1], (argc >= 3) ? argv[2] : NULL, fstype))
+ return 1;
+
+ if (fs_ls(argc >= 4 ? argv[3] : "/"))
+ return 1;
+
+ return 0;
+}
#ifdef NO_inline
#define inline
-#else
-#define inline __inline__
#endif
#define cond_resched() do {} while (0)
return err;
}
-static int
-zfs_label(device_t device, char **label)
-{
- char *nvlist;
- int err;
- struct zfs_data *data;
-
- data = zfs_mount(device);
- if (!data)
- return ZFS_ERR_BAD_FS;
-
- err = int_zfs_fetch_nvlist(data, &nvlist);
- if (err) {
- zfs_unmount(data);
- return err;
- }
-
- *label = zfs_nvlist_lookup_string(nvlist, ZPOOL_CONFIG_POOL_NAME);
- free(nvlist);
- zfs_unmount(data);
- return ZFS_ERR_NONE;
-}
-
-static int
-zfs_uuid(device_t device, char **uuid)
-{
- struct zfs_data *data;
-
- data = zfs_mount(device);
- if (!data)
- return ZFS_ERR_BAD_FS;
-
- *uuid = malloc(17); /* %016llx + nil */
- if (!*uuid)
- return ZFS_ERR_OUT_OF_MEMORY;
-
- /* *uuid = xasprintf ("%016llx", (long long unsigned) data->pool_guid);*/
- snprintf(*uuid, 17, "%016llx", (long long unsigned) data->pool_guid);
- zfs_unmount(data);
-
- return ZFS_ERR_NONE;
-}
-
/*
* zfs_open() locates a file in the rootpool by following the
* MOS and places the dnode of the file in the memory address DNODE.
struct zfs_data *data;
int err;
int isfs;
-#if 0
- char *label = NULL;
-
- zfs_label(device, &label);
- if (label)
- printf("ZPOOL label '%s'\n",
- label);
-#endif
data = zfs_mount(device);
if (!data)
#define HOST_IRQ_STAT 0x08 /* interrupt status */
#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
+#define HOST_CAP2 0x24 /* host capabilities, extended */
/* HOST_CTL bits */
#define HOST_RESET (1 << 0) /* reset controller; self-clear */
#define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */
#define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */
+#define ATA_CMD_FLUSH 0xE7 /* Flush drive cache */
+#define ATA_CMD_FLUSH_EXT 0xEA /* Flush drive cache, with 48bit addressing */
+
/*
* ATAPI Commands
*/
int getenv_f (const char *name, char *buf, unsigned len);
ulong getenv_ulong(const char *name, int base, ulong default_val);
int saveenv (void);
-#ifdef CONFIG_PPC /* ARM version to be fixed! */
-int inline setenv (const char *, const char *);
-#else
int setenv (const char *, const char *);
int setenv_ulong(const char *varname, ulong value);
int setenv_addr(const char *varname, const void *addr);
-#endif /* CONFIG_PPC */
#ifdef CONFIG_ARM
# include <asm/mach-types.h>
# include <asm/setup.h>
#endif /* MPC860ADS */
-/*** AMX860 **********************************************/
-
-#if defined(CONFIG_AMX860)
-
-/* This ENET stuff is for the AMX860 with ethernet on SCC1.
- */
-
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-
-#define PA_ENET_RXD ((ushort)0x0001)
-#define PA_ENET_TXD ((ushort)0x0002)
-#define PA_ENET_TCLK ((ushort)0x0400)
-#define PA_ENET_RCLK ((ushort)0x0800)
-
-#define PB_ENET_TENA ((uint)0x00001000)
-
-#define PC_ENET_CLSN ((ushort)0x0010)
-#define PC_ENET_RENA ((ushort)0x0020)
-
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000003e)
-
-/* 68160 PHY control */
-
-#define PB_ENET_ETHLOOP ((uint)0x00020000)
-#define PB_ENET_TPFLDL ((uint)0x00010000)
-#define PB_ENET_TPSQEL ((uint)0x00008000)
-#define PD_ENET_ETH_EN ((ushort)0x0004)
-
-#endif /* CONFIG_AMX860 */
-
/*** BSEIP **********************************************************/
#ifdef CONFIG_BSEIP
#define SICR_ENET_CLKRT ((uint)0x00003400)
#endif /* CONFIG_FLAGADM */
-/*** C2MON **********************************************************/
-
-#ifdef CONFIG_C2MON
-
-# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */
-# error "Ethernet on SCC not supported on C2MON Board!"
-# else /* Use FEC for Fast Ethernet */
-
-#undef SCC_ENET
-#define FEC_ENET
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-# endif /* CONFIG_FEC_ENET */
-#endif /* CONFIG_C2MON */
-
-/*********************************************************************/
-
/*** ELPT860 *********************************************************/
#ifdef CONFIG_ELPT860
#endif /* CONFIG_HERMES */
-/*** IAD210 **********************************************************/
-
-/* The IAD210 uses the FEC on a MPC860P for Ethernet */
-
-#if defined(CONFIG_IAD210)
-
-# define FEC_ENET /* use FEC for Ethernet */
-# undef SCC_ENET
-
-# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */
-# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */
-# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */
-# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */
-# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */
-# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */
-# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */
-# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */
-# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */
-# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */
-# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */
-# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */
-# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */
-
-# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */
-
-#endif /* CONFIG_IAD210 */
-
/*** ICU862 **********************************************************/
#if defined(CONFIG_ICU862)
#endif /* CONFIG_KUP4K */
-
-/*** LANTEC *********************************************************/
-
-#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000FF00)
-#define SICR_ENET_CLKRT ((uint)0x00002E00)
-#endif /* CONFIG_LANTEC v2 */
-
/*** LWMON **********************************************************/
#if defined(CONFIG_LWMON)
#endif /* CONFIG_SXNI855T */
-/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/
+/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
- defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
- defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
- defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \
- defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
- (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
+ defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
+ defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
+ defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
+ defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
+#if defined(CONFIG_CMD_FAT) && !defined(CONFIG_FS_FAT)
+#define CONFIG_FS_FAT
+#endif
+
+#if (defined(CONFIG_CMD_EXT4) || defined(CONFIG_CMD_EXT2)) && \
+ !defined(CONFIG_FS_EXT4)
+#define CONFIG_FS_EXT4
+#endif
+
+#if defined(CONFIG_CMD_EXT4_WRITE) && !defined(CONFIG_EXT4_WRITE)
+#define CONFIG_EXT4_WRITE
+#endif
+
#endif /* __CONFIG_FALLBACKS_H */
+++ /dev/null
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1
-#define CONFIG_AMX860 1
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */
-#undef CONFIG_8xx_CONS_SMC2
-#define CONFIG_8xx_CONS_SCC2 1
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-
-#define MPC8XX_FACT 10 /* Multiply by 10 */
-#define MPC8XX_XIN 5000000 /* 5 MHz in */
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm" /* autoboot command */
-
-#undef CONFIG_BOOTARGS
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * U-Boot for AMX board supports two types of memory extension
- * modules: one that provides 4 MB flash memory, and another one with
- * 16 MB EDO DRAM.
- *
- * The flash module swaps the CS0 and CS1 signals: if the module is
- * installed, CS0 is connected to Flash on the module and CS1 is
- * connected to the on-board Flash. This means that you must intall
- * U-Boot when the Flash module is plugged in, if you plan to use
- * it.
- *
- * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
- * must be defined. The DRAM module uses CS1.
- *
- * Only one of these modules may be installed at a time. If U-Boot
- * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
- * work if the Flash extension module is installed instead of the
- * DRAM module.
- */
-#define CONFIG_AMX_RAM_EXT /* 16Mb Ext. DRAM module support */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- *
- * Use 4 MB for without and 8 MB with 16 MB DRAM extension module
- * (CONFIG_AMX_RAM_EXT)
- */
-#ifdef CONFIG_AMX_RAM_EXT
-# define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#else
-# define CONFIG_SYS_BOOTMAPSZ (4 << 20) /* Initial Memory map for Linux */
-#endif
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
-
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#ifndef CONFIG_AMX_RAM_EXT
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
-#endif
-
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
-/* 0x00000800 0x00000400 0x00000100 0x00000030 0x00000004 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-
-#define CONFIG_SYS_OR0_PRELIM 0xFFC00954 /* Real values for the board */
-#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */
-
-#ifndef CONFIG_AMX_RAM_EXT
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM 0xFFC00954 /* Real values for the board */
-#define CONFIG_SYS_BR1_PRELIM 0x60000001 /* Real values for the board */
-#endif
-
-/* DSP ("Glue") Xilinx */
-#define CONFIG_SYS_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */
-#define CONFIG_SYS_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
-#define CONFIG_ETX094 1 /* ...on a ETX_094 board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 57600
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */
-#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */
-#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */
-
-#define CONFIG_ETHADDR 08:00:06:00:00:00
-
-#ifdef CONFIG_ETHADDR
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */
-#endif
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \
- "U-Boot_version=U-Boot-1.0.x-Date " \
- "panic=1 " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-#define CONFIG_NFSBOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_WATCHDOG 1 /* watchdog enabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#ifdef CONFIG_FLASH_16BIT
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
-#else
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \
- OR_SCY_2_CLK | OR_TRLX )
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-
-#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
-#else /* 32 bit data port */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
-#endif /* CONFIG_FLASH_16BIT */
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 23 /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <mpc8xx_irq.h>
-
-
-# ifdef DEBUG
-# warning DEBUG Defined
-# endif /* DEBUG */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC860 1
-#define CONFIG_IAD210 1 /* ...on a IAD210 module */
-#define CONFIG_MPC860T 1
-#define CONFIG_MPC862 1
-
-#define CONFIG_SYS_TEXT_BASE 0x08000000
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-
-#undef CONFIG_8xx_CONS_SMC1
-#undef CONFIG_8xx_CONS_SMC2
-#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600
-
-
-# define MPC8XX_FACT 16
-# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */
-# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#if 0
-# define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-/* using this define saves us updating another source file */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R
-
-#undef CONFIG_BOOTARGS
-/* #define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-*/
-
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/nfs" \
- "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
-# define CONFIG_FEC_ENET 1 /* use FEC ethernet */
-# define CONFIG_MII 1
-# define CONFIG_SYS_DISCOVER_PHY 1
-# define CONFIG_FEC_UTOPIA 1
-# define CONFIG_ETHADDR 08:00:06:26:A2:6D
-# define CONFIG_IPADDR 192.168.28.128
-# define CONFIG_SERVERIP 139.10.137.138
-# define CONFIG_SYS_DISCOVER_PHY 1
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0xDD
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#if defined(DEBUG)
-# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-
-# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-# define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
- SCCR_DFLCD000 |SCCR_DFALCD00 )
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
-#define CONFIG_SYS_RCCR 0x0020
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define PCMCIA_MEM_ADDR ((uint)0xff020000)
-#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently. Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register. For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0xF8000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xF8000000 /* OR addr mask */
-
-/* FLASH timing:
- TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \
- OR_SCY_3_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4)
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 124 /* start with divider for 64 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X)
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2001
- * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
- * Bruno Achauer, Exet AG, bruno@exet-ag.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- * [derived from config_TQM850L.h]
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
-#define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-/*
- * Port assignments (CONFIG_LANTEC == 1):
- * - SMC1: J11 (MDB) ?
- * - SMC2: J6 (Feature connector)
- * - SCC2: J9 (RJ45)
- * - SCC3: J8 (Sub-D9)
- *
- * Port assignments (CONFIG_LANTEC == 2): TBD
- */
-
-
-#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */
-#define CONFIG_8xx_CONS_SCC3
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-#undef CONFIG_CMD_XIMG
-
-#if !(CONFIG_LANTEC >= 2)
- #undef CONFIG_CMD_DATE
- #undef CONFIG_CMD_NET
-#endif
-
-
-#if CONFIG_LANTEC >= 2
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
-
-/*-----------------------------------------------------------------------
- * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
- *-----------------------------------------------------------------------
- */
-#define CONFIG_8xx_GCLK_FREQ 33000000
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
- /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
- /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/5 and OR0/5 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \
- OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR5_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses */
-#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
-
-#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL \
- ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT ""
-#define MTDPARTS_DEFAULT ""
-*/
-
-#endif /* __CONFIG_H */
#endif
#if defined(CONFIG_SYS_NAND_BOOT)
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_OFFSET 0x80000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
-#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
-#define CONFIG_SCM 1 /* ...on a System Controller Module */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#if (CONFIG_TQM8260 <= 100)
-# error "TQM8260 module revison not supported"
-#endif
-
-/* We use a TQM8260 module with a 300MHz CPU */
-#define CONFIG_300MHz
-
-/* Define 60x busmode only if your TQM8260 has L2 cache! */
-#ifdef CONFIG_L2_CACHE
-# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */
-#else
-# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */
-#endif
-
-/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
-#ifdef CONFIG_300MHz
-# define CONFIG_BUSMODE_60x
-#endif
-
-#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
-#endif
-
-#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- *
- * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK12
- * - Tx-CLK is CLK11
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifndef CONFIG_300MHz
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_8260_CLKIN 83333000 /* in Hz */
-#endif
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE 230400
-#else
-#define CONFIG_BAUDRATE 115200
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_BSP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
-
-#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH1_BASE 0x60000000
-#define CONFIG_SYS_FLASH0_SIZE 32
-#define CONFIG_SYS_FLASH1_SIZE 32
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
-#define CONFIG_ENV_SIZE 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#else
-/* Final version: environment in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0
-#define CONFIG_ENV_SIZE 2048
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if defined(CONFIG_266MHz)
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
- HRCW_MODCK_H0111)
-#elif defined(CONFIG_300MHz)
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
- HRCW_MODCK_H0110)
-#else
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#ifdef CONFIG_BUSMODE_60x
-#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
- BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
-#else
-#define BCR_APD01 0x10000000
-#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
-#else
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR 0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 64 bit FLASH
- * 1 60x SDRAM 64 bit SDRAM
- * 2 Local SDRAM 32 bit SDRAM
- *
- */
-
- /* Initialize SDRAM on local bus
- */
-#define CONFIG_SYS_INIT_LOCAL_SDRAM
-
-#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
-#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
-
-#define CONFIG_SYS_MPTPR 0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
- * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
- * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
- * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
- * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS 0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
- /* SDRAM on TQM8260 can have either 8 or 9 columns.
- * The number affects configuration values.
- */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT 0x20
-#define CONFIG_SYS_LSRT 0x20
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
-
-
- /* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A7 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
- PSDMR_SDAM_A15_IS_A5 |\
- PSDMR_BSMA_A12_A14 |\
- PSDMR_SDA10_PBI1_A8 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_EAMUX |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A5 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
- PSDMR_SDAM_A16_IS_A5 |\
- PSDMR_BSMA_A12_A14 |\
- PSDMR_SDA10_PBI1_A7 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_EAMUX |\
- PSDMR_CL_2)
-
-/* Bank 2 - Local bus SDRAM
- */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_SDRAM_L |\
- BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
-
-#define SDRAM_BASE2_PRELIM 0x80000000
-
- /* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A8 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\
- PSDMR_SDAM_A15_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI1_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_BL |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A6 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\
- PSDMR_SDAM_A16_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI1_A8 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_BL |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_CL_2)
-
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#define CONFIG_SYS_CAN0_BASE 0xc0000000
-#define CONFIG_SYS_CAN1_BASE 0xc0008000
-#define CONFIG_SYS_FIOX_BASE 0xc0010000
-#define CONFIG_SYS_FDOHM_BASE 0xc0018000
-#define CONFIG_SYS_EXTPROM_BASE 0xc2000000
-
-#define CONFIG_SYS_CAN_SIZE 0x00000100
-#define CONFIG_SYS_FIOX_SIZE 0x00000020
-#define CONFIG_SYS_FDOHM_SIZE 0x00002000
-#define CONFIG_SYS_EXTPROM_BANK_SIZE 0x01000000
-
-#define EXT_EEPROM_MAX_FLASH_BANKS 0x02
-
-/* CS3 - CAN 0
- */
-#define CONFIG_SYS_CAN0_BR3 ((CONFIG_SYS_CAN0_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_UPMA |\
- BRx_V)
-
-#define CONFIG_SYS_CAN0_OR3 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\
- ORxU_BI |\
- ORxU_EHTR_4IDLE)
-
-/* CS4 - CAN 1
- */
-#define CONFIG_SYS_CAN1_BR4 ((CONFIG_SYS_CAN1_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_UPMA |\
- BRx_V)
-
-#define CONFIG_SYS_CAN1_OR4 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\
- ORxU_BI |\
- ORxU_EHTR_4IDLE)
-
-/* CS5 - Extended PROM (16MB optional)
- */
-#define CONFIG_SYS_EXTPROM_BR5 ((CONFIG_SYS_EXTPROM_BASE & BRx_BA_MSK)|\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_EXTPROM_OR5 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\
- ORxG_CSNT |\
- ORxG_ACS_DIV4 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX)
-
-/* CS6 - Extended PROM (16MB optional)
- */
-#define CONFIG_SYS_EXTPROM_BR6 (((CONFIG_SYS_EXTPROM_BASE + \
- CONFIG_SYS_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_EXTPROM_OR6 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\
- ORxG_CSNT |\
- ORxG_ACS_DIV4 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX)
-
-/* CS7 - FPGA FIOX: Glue Logic
- */
-#define CONFIG_SYS_FIOX_BR7 ((CONFIG_SYS_FIOX_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_FIOX_OR7 (P2SZ_TO_AM(CONFIG_SYS_FIOX_SIZE) |\
- ORxG_ACS_DIV4 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX)
-
-/* CS8 - FPGA DOH Master
- */
-#define CONFIG_SYS_FDOHM_BR8 ((CONFIG_SYS_FDOHM_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_FDOHM_OR8 (P2SZ_TO_AM(CONFIG_SYS_FDOHM_SIZE) |\
- ORxG_ACS_DIV4 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX)
-
-
-/* FPGA configuration */
-#define CONFIG_SYS_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */
-#define CONFIG_SYS_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */
-#define CONFIG_SYS_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */
-
-#define CONFIG_SYS_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */
-#define CONFIG_SYS_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */
-#define CONFIG_SYS_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */
-
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "U-Boot# "
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_NO_FLASH
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 1
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x80F80000\0" \
"rdaddr=0x81000000\0" \
"bootfile=/boot/uImage\0" \
+ "fdtfile=\0" \
"console=ttyO0,115200n8\0" \
"optargs=\0" \
"mmcdev=0\0" \
"ramboot=echo Booting from ramdisk ...; " \
"run ramargs; " \
"bootm ${loadaddr}\0" \
+ "findfdt="\
+ "if test $board_name = A335BONE; then " \
+ "setenv fdtfile am335x-bone.dtb; fi; " \
+ "if test $board_name = A33515BB; then " \
+ "setenv fdtfile am335x-evm.dtb; fi; " \
+ "if test $board_name = A335X_SK; then " \
+ "setenv fdtfile am335x-evmsk.dtb; fi\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
+++ /dev/null
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
-#define CONFIG_C2MON 1 /* ...on a C2MON module */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#undef CONFIG_STATUS_LED /* Status LED disabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_PLPRCR \
- ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif /* CONFIG_80MHz */
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#else /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#endif /* CONFIG_80MHz */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * PCMCIA Power Switch
- *
- * The C2MON uses a TPS2211A PC-Card Power-Interface Switch to
- * control the voltages on the PCMCIA slot which is connected
- * to Port C (all outputs) and Port B (Over-Current Input)
- *-----------------------------------------------------------------------
- */
- /* Output pins */
-#define TPS2211_VCCD0 0x0002 /* PC.14 */
-#define TPS2211_VCCD1 0x0004 /* PC.13 */
-#define TPS2211_VPPD0 0x0008 /* PC.12 */
-#define TPS2211_VPPD1 0x0010 /* PC.11 */
-#define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \
- TPS2211_VPPD0 | TPS2211_VPPD1 )
-
- /* Input pins */
-#define TPS2211_OC 0x00000200 /* PB.22: Over-Current */
-#define TPS2211_INPUTS ( TPS2211_OC )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif /* CONFIG_CAN_DRIVER */
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#endif /* __CONFIG_H */
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SYS_64BIT_LBA
+#define CONFIG_SATA_INTEL 1
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
/*-----------------------------------------------------------------------
* Real Time Clock Configuration
*/
"arch=" CONFIG_SYS_ARCH "\0"
"cpu=" CONFIG_SYS_CPU "\0"
"board=" CONFIG_SYS_BOARD "\0"
+ "board_name=" CONFIG_SYS_BOARD "\0"
#ifdef CONFIG_SYS_VENDOR
"vendor=" CONFIG_SYS_VENDOR "\0"
#endif
extern struct ext2_data *ext4fs_root;
extern struct ext2fs_node *ext4fs_file;
-#if defined(CONFIG_CMD_EXT4_WRITE)
+#if defined(CONFIG_EXT4_WRITE)
extern struct ext2_inode *g_parent_inode;
extern int gd_index;
extern int gindex;
int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[]);
-int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[]);
-int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
#endif
unsigned long maxsize);
long file_fat_read(const char *filename, void *buffer, unsigned long maxsize);
const char *file_getfsname(int idx);
+int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
int file_fat_write(const char *filename, void *buffer, unsigned long maxsize);
--- /dev/null
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _FS_H
+#define _FS_H
+
+#include <common.h>
+
+#define FS_TYPE_ANY 0
+#define FS_TYPE_FAT 1
+#define FS_TYPE_EXT 2
+
+/*
+ * Tell the fs layer which block device an partition to use for future
+ * commands. This also internally identifies the filesystem that is present
+ * within the partition. The identification process may be limited to a
+ * specific filesystem type by passing FS_* in the fstype parameter.
+ *
+ * Returns 0 on success.
+ * Returns non-zero if there is an error accessing the disk or partition, or
+ * no known filesystem type could be recognized on it.
+ */
+int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype);
+
+/*
+ * Print the list of files on the partition previously set by fs_set_blk_dev(),
+ * in directory "dirname".
+ *
+ * Returns 0 on success. Returns non-zero on error.
+ */
+int fs_ls(const char *dirname);
+
+/*
+ * Read file "filename" from the partition previously set by fs_set_blk_dev(),
+ * to address "addr", starting at byte offset "offset", and reading "len"
+ * bytes. "offset" may be 0 to read from the start of the file. "len" may be
+ * 0 to read the entire file. Note that not all filesystem types support
+ * either/both offset!=0 or len!=0.
+ *
+ * Returns number of bytes read on success. Returns <= 0 on error.
+ */
+int fs_read(const char *filename, ulong addr, int offset, int len);
+
+/*
+ * Common implementation for various filesystem commands, optionally limited
+ * to a specific filesystem type via the fstype parameter.
+ */
+int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype, int cmdline_base);
+int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype);
+
+#endif /* _FS_H */
#define __IMAGE_H__
#include "compiler.h"
+#include <asm/byteorder.h>
#ifdef USE_HOSTCC
* all data in network byte order (aka natural aka bigendian).
*/
typedef struct image_header {
- uint32_t ih_magic; /* Image Header Magic Number */
- uint32_t ih_hcrc; /* Image Header CRC Checksum */
- uint32_t ih_time; /* Image Creation Timestamp */
- uint32_t ih_size; /* Image Data Size */
- uint32_t ih_load; /* Data Load Address */
- uint32_t ih_ep; /* Entry Point Address */
- uint32_t ih_dcrc; /* Image Data CRC Checksum */
+ __be32 ih_magic; /* Image Header Magic Number */
+ __be32 ih_hcrc; /* Image Header CRC Checksum */
+ __be32 ih_time; /* Image Creation Timestamp */
+ __be32 ih_size; /* Image Data Size */
+ __be32 ih_load; /* Data Load Address */
+ __be32 ih_ep; /* Entry Point Address */
+ __be32 ih_dcrc; /* Image Data CRC Checksum */
uint8_t ih_os; /* Operating System */
uint8_t ih_arch; /* CPU architecture */
uint8_t ih_type; /* Image Type */
#ifndef __BIG_ENDIAN_BITFIELD
#define __BIG_ENDIAN_BITFIELD
#endif
-#define __BYTE_ORDER __BIG_ENDIAN
+#define __BYTE_ORDER __BIG_ENDIAN
+#include <linux/compiler.h>
+#include <linux/types.h>
#include <linux/byteorder/swab.h>
-#define __constant_htonl(x) ((__u32)(x))
-#define __constant_ntohl(x) ((__u32)(x))
-#define __constant_htons(x) ((__u16)(x))
-#define __constant_ntohs(x) ((__u16)(x))
-#define __constant_cpu_to_le64(x) ___swab64((x))
-#define __constant_le64_to_cpu(x) ___swab64((x))
-#define __constant_cpu_to_le32(x) ___swab32((x))
-#define __constant_le32_to_cpu(x) ___swab32((x))
-#define __constant_cpu_to_le16(x) ___swab16((x))
-#define __constant_le16_to_cpu(x) ___swab16((x))
-#define __constant_cpu_to_be64(x) ((__u64)(x))
-#define __constant_be64_to_cpu(x) ((__u64)(x))
-#define __constant_cpu_to_be32(x) ((__u32)(x))
-#define __constant_be32_to_cpu(x) ((__u32)(x))
-#define __constant_cpu_to_be16(x) ((__u16)(x))
-#define __constant_be16_to_cpu(x) ((__u16)(x))
-#define __cpu_to_le64(x) __swab64((x))
-#define __le64_to_cpu(x) __swab64((x))
-#define __cpu_to_le32(x) __swab32((x))
-#define __le32_to_cpu(x) __swab32((x))
-#define __cpu_to_le16(x) __swab16((x))
-#define __le16_to_cpu(x) __swab16((x))
-#define __cpu_to_be64(x) ((__u64)(x))
-#define __be64_to_cpu(x) ((__u64)(x))
-#define __cpu_to_be32(x) ((__u32)(x))
-#define __be32_to_cpu(x) ((__u32)(x))
-#define __cpu_to_be16(x) ((__u16)(x))
-#define __be16_to_cpu(x) ((__u16)(x))
-#define __cpu_to_le64p(x) __swab64p((x))
-#define __le64_to_cpup(x) __swab64p((x))
-#define __cpu_to_le32p(x) __swab32p((x))
-#define __le32_to_cpup(x) __swab32p((x))
-#define __cpu_to_le16p(x) __swab16p((x))
-#define __le16_to_cpup(x) __swab16p((x))
-#define __cpu_to_be64p(x) (*(__u64*)(x))
-#define __be64_to_cpup(x) (*(__u64*)(x))
-#define __cpu_to_be32p(x) (*(__u32*)(x))
-#define __be32_to_cpup(x) (*(__u32*)(x))
-#define __cpu_to_be16p(x) (*(__u16*)(x))
-#define __be16_to_cpup(x) (*(__u16*)(x))
+#define __constant_htonl(x) ((__force __be32)(__u32)(x))
+#define __constant_ntohl(x) ((__force __u32)(__be32)(x))
+#define __constant_htons(x) ((__force __be16)(__u16)(x))
+#define __constant_ntohs(x) ((__force __u16)(__be16)(x))
+#define __constant_cpu_to_le64(x) ((__force __le64)___constant_swab64((x)))
+#define __constant_le64_to_cpu(x) ___constant_swab64((__force __u64)(__le64)(x))
+#define __constant_cpu_to_le32(x) ((__force __le32)___constant_swab32((x)))
+#define __constant_le32_to_cpu(x) ___constant_swab32((__force __u32)(__le32)(x))
+#define __constant_cpu_to_le16(x) ((__force __le16)___constant_swab16((x)))
+#define __constant_le16_to_cpu(x) ___constant_swab16((__force __u16)(__le16)(x))
+#define __constant_cpu_to_be64(x) ((__force __be64)(__u64)(x))
+#define __constant_be64_to_cpu(x) ((__force __u64)(__be64)(x))
+#define __constant_cpu_to_be32(x) ((__force __be32)(__u32)(x))
+#define __constant_be32_to_cpu(x) ((__force __u32)(__be32)(x))
+#define __constant_cpu_to_be16(x) ((__force __be16)(__u16)(x))
+#define __constant_be16_to_cpu(x) ((__force __u16)(__be16)(x))
+#define __cpu_to_le64(x) ((__force __le64)__swab64((x)))
+#define __le64_to_cpu(x) __swab64((__force __u64)(__le64)(x))
+#define __cpu_to_le32(x) ((__force __le32)__swab32((x)))
+#define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x))
+#define __cpu_to_le16(x) ((__force __le16)__swab16((x)))
+#define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x))
+#define __cpu_to_be64(x) ((__force __be64)(__u64)(x))
+#define __be64_to_cpu(x) ((__force __u64)(__be64)(x))
+#define __cpu_to_be32(x) ((__force __be32)(__u32)(x))
+#define __be32_to_cpu(x) ((__force __u32)(__be32)(x))
+#define __cpu_to_be16(x) ((__force __be16)(__u16)(x))
+#define __be16_to_cpu(x) ((__force __u16)(__be16)(x))
+
+static inline __le64 __cpu_to_le64p(const __u64 *p)
+{
+ return (__force __le64)__swab64p(p);
+}
+static inline __u64 __le64_to_cpup(const __le64 *p)
+{
+ return __swab64p((__u64 *)p);
+}
+static inline __le32 __cpu_to_le32p(const __u32 *p)
+{
+ return (__force __le32)__swab32p(p);
+}
+static inline __u32 __le32_to_cpup(const __le32 *p)
+{
+ return __swab32p((__u32 *)p);
+}
+static inline __le16 __cpu_to_le16p(const __u16 *p)
+{
+ return (__force __le16)__swab16p(p);
+}
+static inline __u16 __le16_to_cpup(const __le16 *p)
+{
+ return __swab16p((__u16 *)p);
+}
+static inline __be64 __cpu_to_be64p(const __u64 *p)
+{
+ return (__force __be64)*p;
+}
+static inline __u64 __be64_to_cpup(const __be64 *p)
+{
+ return (__force __u64)*p;
+}
+static inline __be32 __cpu_to_be32p(const __u32 *p)
+{
+ return (__force __be32)*p;
+}
+static inline __u32 __be32_to_cpup(const __be32 *p)
+{
+ return (__force __u32)*p;
+}
+static inline __be16 __cpu_to_be16p(const __u16 *p)
+{
+ return (__force __be16)*p;
+}
+static inline __u16 __be16_to_cpup(const __be16 *p)
+{
+ return (__force __u16)*p;
+}
#define __cpu_to_le64s(x) __swab64s((x))
#define __le64_to_cpus(x) __swab64s((x))
#define __cpu_to_le32s(x) __swab32s((x))
#define __le32_to_cpus(x) __swab32s((x))
#define __cpu_to_le16s(x) __swab16s((x))
#define __le16_to_cpus(x) __swab16s((x))
-#define __cpu_to_be64s(x) do {} while (0)
-#define __be64_to_cpus(x) do {} while (0)
-#define __cpu_to_be32s(x) do {} while (0)
-#define __be32_to_cpus(x) do {} while (0)
-#define __cpu_to_be16s(x) do {} while (0)
-#define __be16_to_cpus(x) do {} while (0)
+#define __cpu_to_be64s(x) do { (void)(x); } while (0)
+#define __be64_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be32s(x) do { (void)(x); } while (0)
+#define __be32_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be16s(x) do { (void)(x); } while (0)
+#define __be16_to_cpus(x) do { (void)(x); } while (0)
+#ifdef __KERNEL__
#include <linux/byteorder/generic.h>
+#endif
#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
#endif
#define __BYTE_ORDER __LITTLE_ENDIAN
+#include <linux/compiler.h>
+#include <linux/types.h>
#include <linux/byteorder/swab.h>
-#define __constant_htonl(x) ___constant_swab32((x))
-#define __constant_ntohl(x) ___constant_swab32((x))
-#define __constant_htons(x) ___constant_swab16((x))
-#define __constant_ntohs(x) ___constant_swab16((x))
-#define __constant_cpu_to_le64(x) ((__u64)(x))
-#define __constant_le64_to_cpu(x) ((__u64)(x))
-#define __constant_cpu_to_le32(x) ((__u32)(x))
-#define __constant_le32_to_cpu(x) ((__u32)(x))
-#define __constant_cpu_to_le16(x) ((__u16)(x))
-#define __constant_le16_to_cpu(x) ((__u16)(x))
-#define __constant_cpu_to_be64(x) ___constant_swab64((x))
-#define __constant_be64_to_cpu(x) ___constant_swab64((x))
-#define __constant_cpu_to_be32(x) ___constant_swab32((x))
-#define __constant_be32_to_cpu(x) ___constant_swab32((x))
-#define __constant_cpu_to_be16(x) ___constant_swab16((x))
-#define __constant_be16_to_cpu(x) ___constant_swab16((x))
-#define __cpu_to_le64(x) ((__u64)(x))
-#define __le64_to_cpu(x) ((__u64)(x))
-#define __cpu_to_le32(x) ((__u32)(x))
-#define __le32_to_cpu(x) ((__u32)(x))
-#define __cpu_to_le16(x) ((__u16)(x))
-#define __le16_to_cpu(x) ((__u16)(x))
-#define __cpu_to_be64(x) __swab64((x))
-#define __be64_to_cpu(x) __swab64((x))
-#define __cpu_to_be32(x) __swab32((x))
-#define __be32_to_cpu(x) __swab32((x))
-#define __cpu_to_be16(x) __swab16((x))
-#define __be16_to_cpu(x) __swab16((x))
-#define __cpu_to_le64p(x) (*(__u64*)(x))
-#define __le64_to_cpup(x) (*(__u64*)(x))
-#define __cpu_to_le32p(x) (*(__u32*)(x))
-#define __le32_to_cpup(x) (*(__u32*)(x))
-#define __cpu_to_le16p(x) (*(__u16*)(x))
-#define __le16_to_cpup(x) (*(__u16*)(x))
-#define __cpu_to_be64p(x) __swab64p((x))
-#define __be64_to_cpup(x) __swab64p((x))
-#define __cpu_to_be32p(x) __swab32p((x))
-#define __be32_to_cpup(x) __swab32p((x))
-#define __cpu_to_be16p(x) __swab16p((x))
-#define __be16_to_cpup(x) __swab16p((x))
-#define __cpu_to_le64s(x) do {} while (0)
-#define __le64_to_cpus(x) do {} while (0)
-#define __cpu_to_le32s(x) do {} while (0)
-#define __le32_to_cpus(x) do {} while (0)
-#define __cpu_to_le16s(x) do {} while (0)
-#define __le16_to_cpus(x) do {} while (0)
+#define __constant_htonl(x) ((__force __be32)___constant_swab32((x)))
+#define __constant_ntohl(x) ___constant_swab32((__force __be32)(x))
+#define __constant_htons(x) ((__force __be16)___constant_swab16((x)))
+#define __constant_ntohs(x) ___constant_swab16((__force __be16)(x))
+#define __constant_cpu_to_le64(x) ((__force __le64)(__u64)(x))
+#define __constant_le64_to_cpu(x) ((__force __u64)(__le64)(x))
+#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x))
+#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x))
+#define __constant_cpu_to_le16(x) ((__force __le16)(__u16)(x))
+#define __constant_le16_to_cpu(x) ((__force __u16)(__le16)(x))
+#define __constant_cpu_to_be64(x) ((__force __be64)___constant_swab64((x)))
+#define __constant_be64_to_cpu(x) ___constant_swab64((__force __u64)(__be64)(x))
+#define __constant_cpu_to_be32(x) ((__force __be32)___constant_swab32((x)))
+#define __constant_be32_to_cpu(x) ___constant_swab32((__force __u32)(__be32)(x))
+#define __constant_cpu_to_be16(x) ((__force __be16)___constant_swab16((x)))
+#define __constant_be16_to_cpu(x) ___constant_swab16((__force __u16)(__be16)(x))
+#define __cpu_to_le64(x) ((__force __le64)(__u64)(x))
+#define __le64_to_cpu(x) ((__force __u64)(__le64)(x))
+#define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
+#define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
+#define __cpu_to_le16(x) ((__force __le16)(__u16)(x))
+#define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
+#define __cpu_to_be64(x) ((__force __be64)__swab64((x)))
+#define __be64_to_cpu(x) __swab64((__force __u64)(__be64)(x))
+#define __cpu_to_be32(x) ((__force __be32)__swab32((x)))
+#define __be32_to_cpu(x) __swab32((__force __u32)(__be32)(x))
+#define __cpu_to_be16(x) ((__force __be16)__swab16((x)))
+#define __be16_to_cpu(x) __swab16((__force __u16)(__be16)(x))
+
+static inline __le64 __cpu_to_le64p(const __u64 *p)
+{
+ return (__force __le64)*p;
+}
+static inline __u64 __le64_to_cpup(const __le64 *p)
+{
+ return (__force __u64)*p;
+}
+static inline __le32 __cpu_to_le32p(const __u32 *p)
+{
+ return (__force __le32)*p;
+}
+static inline __u32 __le32_to_cpup(const __le32 *p)
+{
+ return (__force __u32)*p;
+}
+static inline __le16 __cpu_to_le16p(const __u16 *p)
+{
+ return (__force __le16)*p;
+}
+static inline __u16 __le16_to_cpup(const __le16 *p)
+{
+ return (__force __u16)*p;
+}
+static inline __be64 __cpu_to_be64p(const __u64 *p)
+{
+ return (__force __be64)__swab64p(p);
+}
+static inline __u64 __be64_to_cpup(const __be64 *p)
+{
+ return __swab64p((__u64 *)p);
+}
+static inline __be32 __cpu_to_be32p(const __u32 *p)
+{
+ return (__force __be32)__swab32p(p);
+}
+static inline __u32 __be32_to_cpup(const __be32 *p)
+{
+ return __swab32p((__u32 *)p);
+}
+static inline __be16 __cpu_to_be16p(const __u16 *p)
+{
+ return (__force __be16)__swab16p(p);
+}
+static inline __u16 __be16_to_cpup(const __be16 *p)
+{
+ return __swab16p((__u16 *)p);
+}
+#define __cpu_to_le64s(x) do { (void)(x); } while (0)
+#define __le64_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_le32s(x) do { (void)(x); } while (0)
+#define __le32_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_le16s(x) do { (void)(x); } while (0)
+#define __le16_to_cpus(x) do { (void)(x); } while (0)
#define __cpu_to_be64s(x) __swab64s((x))
#define __be64_to_cpus(x) __swab64s((x))
#define __cpu_to_be32s(x) __swab32s((x))
#define __cpu_to_be16s(x) __swab16s((x))
#define __be16_to_cpus(x) __swab16s((x))
+#ifdef __KERNEL__
#include <linux/byteorder/generic.h>
+#endif
#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
{
return __arch__swab16(x);
}
-static __inline__ __u16 __swab16p(__u16 *x)
+static __inline__ __u16 __swab16p(const __u16 *x)
{
return __arch__swab16p(x);
}
{
return __arch__swab32(x);
}
-static __inline__ __u32 __swab32p(__u32 *x)
+static __inline__ __u32 __swab32p(const __u32 *x)
{
return __arch__swab32p(x);
}
return __arch__swab64(x);
# endif
}
-static __inline__ __u64 __swab64p(__u64 *x)
+static __inline__ __u64 __swab64p(const __u64 *x)
{
return __arch__swab64p(x);
}
#ifndef _LINUX_COMPAT_H_
#define _LINUX_COMPAT_H_
-#define __user
-#define __iomem
-
#define ndelay(x) udelay(1)
#define printk printf
#include <linux/compat.h>
#endif
+#include <linux/compiler.h>
+
struct erase_info_user {
uint32_t start;
uint32_t length;
#include <linux/types.h>
#endif
+#ifndef __CHECKER__
#undef offsetof
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#endif
#endif
#ifndef _LINUX_UNALIGNED_GENERIC_H
#define _LINUX_UNALIGNED_GENERIC_H
-/* define __force to nothing in U-Boot */
-#define __force
-
/*
* Cause a link-time error if we try an unaligned access other than
* 1,2,4 or 8 bytes long
extern int eth_unregister(struct eth_device *dev);/* Remove network device */
extern void eth_try_another(int first_restart); /* Change the device */
extern void eth_set_current(void); /* set nterface to ethcur var */
+
/* get the current device MAC */
+extern struct eth_device *eth_current;
+
static inline __attribute__((always_inline))
struct eth_device *eth_get_dev(void)
{
- extern struct eth_device *eth_current;
-
return eth_current;
}
extern struct eth_device *eth_get_dev_by_name(const char *devname);
NETLOOP_SUCCESS,
NETLOOP_FAIL
};
+extern enum net_loop_state net_state;
+
static inline void net_set_state(enum net_loop_state state)
{
- extern enum net_loop_state net_state;
-
debug_cond(DEBUG_INT_STATE, "--- NetState set to %d\n", state);
net_state = state;
}
# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */
# define CONFIG_PCMCIA_SLOT_B
-#elif defined(CONFIG_C2MON) /* The C2MON use SLOT_B */
-# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */
# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */
#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */
#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */
+#define SCSI_RD_CAPAC10 SCSI_RD_CAPAC /* Read Capacity (10) */
+#define SCSI_RD_CAPAC16 0x9e /* Read Capacity (16) */
#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */
#define SCSI_READ_LONG 0x3E /* Read Long (O) */
#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */
void scsi_init(void);
void scsi_scan(int mode);
+/** @return the number of scsi disks */
+int scsi_get_disk_count(void);
#define SCSI_IDENTIFY 0xC0 /* not used */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** ETX_094 ********************************************************/
-#elif defined(CONFIG_ETX094)
-
-# define STATUS_LED_PAR im_ioport.iop_pdpar
-# define STATUS_LED_DIR im_ioport.iop_pddir
-# undef STATUS_LED_ODR
-# define STATUS_LED_DAT im_ioport.iop_pddat
-
-# define STATUS_LED_BIT 0x00000001
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
/***** GEN860T *********************************************************/
#elif defined(CONFIG_GEN860T)
# define STATUS_LED_GREEN 1
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
-/***** LANTEC *********************************************************/
-#elif defined(CONFIG_LANTEC)
-
-# define STATUS_LED_PAR im_ioport.iop_pdpar
-# define STATUS_LED_DIR im_ioport.iop_pddir
-# undef STATUS_LED_ODR
-# define STATUS_LED_DAT im_ioport.iop_pddat
-
-# if CONFIG_LATEC < 2
-# define STATUS_LED_BIT 0x1000
-# else
-# define STATUS_LED_BIT 0x0800
-# endif
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
/***** ICU862 ********************************************************/
#elif defined(CONFIG_ICU862)
#define Z_DEFLATED 8
/* The deflate compression method (the only one supported in this version) */
-#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */
+#define Z_NULL (void *)0 /* for initializing zalloc, zfree, opaque */
/* basic functions */
/* some reluctance to put this into a new limits.h, so it is here */
#define INT_MAX ((int)(~0U>>1))
-const char hex_asc[] = "0123456789abcdef";
+static const char hex_asc[] = "0123456789abcdef";
#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4]
{
int len, i;
- if (s == 0)
+ if (s == NULL)
s = "<NULL>";
len = strnlen(s, precision);
static char *pointer(const char *fmt, char *buf, char *end, void *ptr,
int field_width, int precision, int flags)
{
+ /*
+ * Being a boot loader, we explicitly allow pointers to
+ * (physical) address null.
+ */
+#if 0
if (!ptr)
return string(buf, end, "(null)", field_width, precision,
flags);
+#endif
#ifdef CONFIG_CMD_NET
switch (*fmt) {
#endif
/* ========================================================================= */
-uLong ZEXPORT adler32(adler, buf, len)
- uLong adler;
- const Bytef *buf;
- uInt len;
+uLong ZEXPORT adler32(uLong adler, const Bytef *buf, uInt len)
{
unsigned long sum2;
unsigned n;
requires strm->avail_out >= 258 for each loop to avoid checking for
output space.
*/
-void inflate_fast(strm, start)
-z_streamp strm;
-unsigned start; /* inflate()'s starting value for strm->avail_out */
+void inflate_fast(z_streamp strm, unsigned start)
+/* start: inflate()'s starting value for strm->avail_out */
{
struct inflate_state FAR *state;
unsigned char FAR *in; /* local strm->next_in */
local void fixedtables OF((struct inflate_state FAR *state));
local int updatewindow OF((z_streamp strm, unsigned out));
-int ZEXPORT inflateReset(strm)
-z_streamp strm;
+int ZEXPORT inflateReset(z_streamp strm)
{
struct inflate_state FAR *state;
return Z_OK;
}
-int ZEXPORT inflateInit2_(strm, windowBits, version, stream_size)
-z_streamp strm;
-int windowBits;
-const char *version;
-int stream_size;
+int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, const char *version,
+ int stream_size)
{
struct inflate_state FAR *state;
return inflateReset(strm);
}
-int ZEXPORT inflateInit_(strm, version, stream_size)
-z_streamp strm;
-const char *version;
-int stream_size;
+int ZEXPORT inflateInit_(z_streamp strm, const char *version, int stream_size)
{
return inflateInit2_(strm, DEF_WBITS, version, stream_size);
}
-local void fixedtables(state)
-struct inflate_state FAR *state;
+local void fixedtables(struct inflate_state FAR *state)
{
state->lencode = lenfix;
state->lenbits = 9;
output will fall in the output data, making match copies simpler and faster.
The advantage may be dependent on the size of the processor's data caches.
*/
-local int updatewindow(strm, out)
-z_streamp strm;
-unsigned out;
+local int updatewindow(z_streamp strm, unsigned out)
{
struct inflate_state FAR *state;
unsigned copy, dist;
when flush is set to Z_FINISH, inflate() cannot return Z_OK. Instead it
will return Z_BUF_ERROR if it has not reached the end of the stream.
*/
-int ZEXPORT inflate(strm, flush)
-z_streamp strm;
-int flush;
+int ZEXPORT inflate(z_streamp strm, int flush)
{
struct inflate_state FAR *state;
unsigned char FAR *next; /* next input */
return ret;
}
-int ZEXPORT inflateEnd(strm)
-z_streamp strm;
+int ZEXPORT inflateEnd(z_streamp strm)
{
struct inflate_state FAR *state;
if (strm == Z_NULL || strm->state == Z_NULL || strm->zfree == (free_func)0)
table index bits. It will differ if the request is greater than the
longest code or if it is less than the shortest code.
*/
-int inflate_table(type, lens, codes, table, bits, work)
-codetype type;
-unsigned short FAR *lens;
-unsigned codes;
-code FAR * FAR *table;
-unsigned FAR *bits;
-unsigned short FAR *work;
+int inflate_table(codetype type, unsigned short FAR *lens, unsigned codes,
+ code FAR * FAR *table, unsigned FAR *bits,
+ unsigned short FAR *work)
{
unsigned len; /* a code's length in bits */
unsigned sym; /* index of code symbols */
extern void free OF((voidpf ptr));
#endif
-voidpf zcalloc (opaque, items, size)
- voidpf opaque;
- unsigned items;
- unsigned size;
+voidpf zcalloc(voidpf opaque, unsigned items, unsigned size)
{
if (opaque)
items += size - size; /* make compiler happy */
(voidpf)calloc(items, size);
}
-void zcfree (opaque, ptr, nb)
- voidpf opaque;
- voidpf ptr;
- unsigned nb;
+void zcfree(voidpf opaque, voidpf ptr, unsigned nb)
{
free(ptr);
if (opaque)
#endif
IPaddr_t NetArpWaitPacketIP;
-IPaddr_t NetArpWaitReplyIP;
+static IPaddr_t NetArpWaitReplyIP;
/* MAC address of waiting packet's destination */
uchar *NetArpWaitPacketMAC;
int NetArpWaitTxPacketSize;
ulong NetArpWaitTimerStart;
int NetArpWaitTry;
-uchar *NetArpTxPacket; /* THE ARP transmit packet */
-uchar NetArpPacketBuf[PKTSIZE_ALIGN + PKTALIGN];
+static uchar *NetArpTxPacket; /* THE ARP transmit packet */
+static uchar NetArpPacketBuf[PKTSIZE_ALIGN + PKTALIGN];
void ArpInit(void)
{
int BootpTry;
#if defined(CONFIG_CMD_DHCP)
-dhcp_state_t dhcp_state = INIT;
-unsigned long dhcp_leasetime;
-IPaddr_t NetDHCPServerIP;
+static dhcp_state_t dhcp_state = INIT;
+static unsigned long dhcp_leasetime;
+static IPaddr_t NetDHCPServerIP;
static void DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
unsigned len);
int NetTimeOffset;
#endif
-uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN];
+static uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN];
/* Receive packet */
uchar *NetRxPackets[PKTBUFSRX];
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
*/
-#if defined(CONFIG_CMD_PING)
-
#ifndef __PING_H__
#define __PING_H__
void ping_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len);
#endif /* __PING_H__ */
-#endif
extern void TftpStartServer(void); /* Wait for incoming TFTP put */
#endif
+extern ulong TftpRRQTimeoutMSecs;
+extern int TftpRRQTimeoutCountMax;
+
/**********************************************************************/
#endif /* __TFTP_H__ */
immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
SCC_PSMR_NIB22 | SCC_PSMR_LPB;
-#if 0
- /*
- * Configure Ethernet TENA Signal
- */
-
-#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
- immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
- immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
-#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
- immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
- immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
-#else
-#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
-#endif
-
-#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
- /*
- * Port C is used to control the PHY,MC68160.
- */
- immr->im_ioport.iop_pcdir |=
- (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
-
- immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
- immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#endif /* MPC860ADS */
-
-#if defined(CONFIG_AMX860)
- /*
- * Port B is used to control the PHY,MC68160.
- */
- immr->im_cpm.cp_pbdir |=
- (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
-
- immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
- immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
-
- immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
- immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
-#endif /* AMX860 */
-
-#endif /* 0 */
-
#ifdef CONFIG_RPXCLASSIC
*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
*/
#if defined (CONFIG_FADS)
udelay (10000); /* wait 10 ms */
-#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
+#elif defined(CONFIG_RPXCLASSIC)
udelay (100000); /* wait 100 ms */
#endif
}
from series import Series
# Tags that we detect and remove
-re_remove = re.compile('^BUG=|^TEST=|^Change-Id:|^Review URL:'
- '|Reviewed-on:|Reviewed-by:')
+re_remove = re.compile('^BUG=|^TEST=|^BRANCH=|^Change-Id:|^Review URL:'
+ '|Reviewed-on:|Reviewed-by:|Commit-Ready:')
# Lines which are allowed after a TEST= line
re_allowed_after_test = re.compile('^Signed-off-by:')
projects / u-boot / commitdiff