]> git.sur5r.net Git - u-boot/commitdiff
siemens,am33x: add draco etamin board
authorHeiko Schocher <hs@denx.de>
Tue, 7 Jun 2016 06:55:45 +0000 (08:55 +0200)
committerTom Rini <trini@konsulko.com>
Thu, 9 Jun 2016 17:53:13 +0000 (13:53 -0400)
In the draco CPU board family, etamin is a new variant
with bigger flash and more RAM. Due to new flash that
uses larger pages (4K) some changes are necessary because
it impacts the MTD partition layout and the ubi mount
parameters.

Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Move BOOTDELAY into defconfig, just always be 3 now]
Signed-off-by: Tom Rini <trini@konsulko.com>
14 files changed:
arch/arm/Kconfig
board/siemens/common/board.c
board/siemens/draco/Kconfig
board/siemens/draco/MAINTAINERS
board/siemens/draco/board.c
board/siemens/draco/mux.c
configs/etamin_defconfig [new file with mode: 0644]
include/configs/draco.h
include/configs/etamin.h [new file with mode: 0644]
include/configs/pxm2.h
include/configs/rastaban.h
include/configs/rut.h
include/configs/siemens-am33x-common.h
include/configs/thuban.h

index 26ccf628299bb4fef8e161bf35a079994004492f..e75c4c0fa6df5a2f9f8a928458d2f290ec6e5205 100644 (file)
@@ -361,6 +361,11 @@ config TARGET_RASTABAN
        select CPU_V7
        select SUPPORT_SPL
 
+config TARGET_ETAMIN
+        bool "Support etamin"
+        select CPU_V7
+        select SUPPORT_SPL
+
 config TARGET_PXM2
        bool "Support pxm2"
        select CPU_V7
index c127f6ca271d48a9fc2136596f508043e5e67b8c..9cafcea53a3c7ea87d07cc8829710164e4f6af86 100644 (file)
@@ -83,8 +83,12 @@ int board_init(void)
 #ifdef CONFIG_FACTORYSET
        factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
 #endif
+
        gpmc_init();
 
+#ifdef CONFIG_NAND_CS_INIT
+       board_nand_cs_init();
+#endif
 #ifdef CONFIG_VIDEO
        board_video_init();
 #endif
index 819d187087f7ab631600b352cca6884b5e66b6ba..a699c7d46f79a04e0b79fd80305b501fa20a70d3 100644 (file)
@@ -45,3 +45,19 @@ config SYS_CONFIG_NAME
        default "rastaban"
 
 endif
+
+if TARGET_ETAMIN
+
+config SYS_BOARD
+        default "draco"
+
+config SYS_VENDOR
+        default "siemens"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "etamin"
+
+endif
index 484dd739c1fe017709e2ea1e593f71480bbe5e85..e9107f08bfa9f1b2ae60ff38f354139c4220edb3 100644 (file)
@@ -4,6 +4,7 @@ S:      Maintained
 F:     board/siemens/draco/
 F:     include/configs/draco.h
 F:     configs/draco_defconfig
+F:     configs/etamin_defconfig
 F:     include/configs/thuban.h
 F:     configs/thuban_defconfig
 F:     include/configs/rastaban.h
index 41bdef0f6bed0ccf9816280530094cb8e990e4e3..d8869a09dd007072d9eff554caa20f3acf69529c 100644 (file)
@@ -24,6 +24,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
@@ -33,6 +34,7 @@
 #include <watchdog.h>
 #include "board.h"
 #include "../common/factoryset.h"
+#include <nand.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct draco_baseboard_id __attribute__((section(".data"))) settings;
 
 #if DDR_PLL_FREQ == 303
+#if !defined(CONFIG_TARGET_ETAMIN)
 /* Default@303MHz-i0 */
 const struct ddr3_data ddr3_default = {
        0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
@@ -48,6 +51,16 @@ const struct ddr3_data ddr3_default = {
        "default name @303MHz           \0",
        "default marking                \0",
 };
+#else
+/* etamin board */
+const struct ddr3_data ddr3_default = {
+       0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
+       0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
+       0x0000093B, 0x0000018A,
+       "test-etamin                    \0",
+       "generic-8Gbit                  \0",
+};
+#endif
 #elif DDR_PLL_FREQ == 400
 /* Default@400MHz-i0 */
 const struct ddr3_data ddr3_default = {
@@ -210,6 +223,7 @@ struct ctrl_ioregs draco_ddr3_ioregs = {
        draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
                settings.ddr3.emif_ddr_phy_ctlr_1;
        draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+       draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
        draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 
        draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
@@ -251,6 +265,10 @@ int board_late_init(void)
 
        nand_curr_device = 0;
        omap_nand_switch_ecc(1, ecc_type);
+#ifdef CONFIG_TARGET_ETAMIN
+       nand_curr_device = 1;
+       omap_nand_switch_ecc(1, ecc_type);
+#endif
 #ifdef CONFIG_FACTORYSET
        /* Set ASN in environment*/
        if (factory_dat.asn[0] != 0) {
@@ -326,7 +344,7 @@ int board_eth_init(bd_t *bis)
 }
 
 static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
-                          char *const argv[])
+                         char *const argv[])
 {
        /* Reset SMSC LAN9303 switch for default configuration */
        gpio_request(GPIO_LAN9303_NRST, "nRST");
@@ -346,4 +364,23 @@ U_BOOT_CMD(
 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 
+#ifdef CONFIG_NAND_CS_INIT
+/* GPMC definitions for second nand cs1 */
+static const u32 gpmc_nand_config[] = {
+       ETAMIN_NAND_GPMC_CONFIG1,
+       ETAMIN_NAND_GPMC_CONFIG2,
+       ETAMIN_NAND_GPMC_CONFIG3,
+       ETAMIN_NAND_GPMC_CONFIG4,
+       ETAMIN_NAND_GPMC_CONFIG5,
+       ETAMIN_NAND_GPMC_CONFIG6,
+       /*CONFIG7- computed as params */
+};
+
+static void board_nand_cs_init(void)
+{
+       enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
+                             0x18000000, GPMC_SIZE_16M);
+}
+#endif
+
 #include "../common/board.c"
index dbcc80b61fffdca0d840c87187295a70501dc822..38a484eb4329ed0cc5e1d636770be4564c6703f1 100644 (file)
@@ -51,6 +51,7 @@ static struct module_pin_mux nand_pin_mux[] = {
        {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
        {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},   /* NAND_WPN */
        {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},      /* NAND_CS0 */
+       {OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN},    /* NAND_CS1 */
        {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
        {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},   /* NAND_OE */
        {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},       /* NAND_WEN */
@@ -68,7 +69,6 @@ static struct module_pin_mux gpios_pin_mux[] = {
        {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE},    /* Y3 GPIO2_28*/
        {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE},    /* Y7 GPIO2_27*/
        /* Triacs initial HW Rev */
-       {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS},    /* 1_30 Y0 */
        {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS},    /* 1_28 Y1 */
        {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS},    /* 1_31 Y2 */
        {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS},   /* 0_11 Y3 */
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
new file mode 100644 (file)
index 0000000..6c747df
--- /dev/null
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_TARGET_ETAMIN=y
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_OF_LIBFDT=y
index 5d866c4868551fae4144d5220b55444b2df7be7e..889178c2834bf77cbec258b23ce439f290fadab5 100644 (file)
@@ -73,6 +73,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "hostname=draco\0" \
+       "ubi_off=2048\0"\
        "nand_img_size=0x400000\0" \
        "optargs=\0" \
        "preboot=draco_led 0\0" \
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
new file mode 100644 (file)
index 0000000..4919cfe
--- /dev/null
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_ETAMIN_H
+#define __CONFIG_ETAMIN_H
+
+#include "siemens-am33x-common.h"
+/* NAND specific changes for etamin due to different page size */
+#undef CONFIG_SYS_NAND_PAGE_SIZE
+#undef CONFIG_SYS_NAND_OOBSIZE
+#undef CONFIG_SYS_NAND_BLOCK_SIZE
+#undef CONFIG_SYS_NAND_ECCPOS
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#undef CONFIG_SYS_ENV_SECT_SIZE
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_NAND_OMAP_ECCSCHEME
+#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH16_CODE_HW
+
+#define CONFIG_ENV_OFFSET       0x980000
+#define CONFIG_SYS_ENV_SECT_SIZE       (512 << 10)     /* 512 KiB */
+#define CONFIG_SYS_NAND_PAGE_SIZE       4096
+#define CONFIG_SYS_NAND_OOBSIZE         224
+#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+                               10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+                               20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+                               30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+                               40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
+                               50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+                               60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
+                               70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+                               80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
+                               90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+                       100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+                       110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+                       120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+                       130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+                       140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+                       150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+                       160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+                       170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+                       180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+                       190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+                       200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+                       }
+
+#undef CONFIG_SYS_NAND_ECCSIZE
+#undef CONFIG_SYS_NAND_ECCBYTES
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 26
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x200000
+
+#define CONFIG_SYS_NAND_MAX_CHIPS       1
+
+#undef CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_MAX_NAND_DEVICE      3
+#define CONFIG_SYS_NAND_BASE2           (0x18000000)    /* physical address */
+#define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
+                                       CONFIG_SYS_NAND_BASE2}
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_MPUCLK      300
+#define DDR_PLL_FREQ   303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+/* FWD Button = 27
+ * SRV Button = 87 */
+#define BOARD_DFU_BUTTON_GPIO  27
+#define GPIO_LAN9303_NRST      88      /* GPIO2_24 = gpio88 */
+/* In dfu mode keep led1 on */
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+       "button_dfu0=27\0" \
+       "button_dfu1=87\0" \
+       "led0=3,0,1\0" \
+       "led1=4,0,0\0" \
+       "led2=5,0,1\0" \
+       "led3=87,0,1\0" \
+       "led4=60,0,1\0" \
+       "led5=63,0,1\0"
+
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_CMD_FAT
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED           100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS     0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#undef CONFIG_MII
+#undef CONFIG_PHY_GIGE
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* use both define to compile a SPL compliance test  */
+/*
+#define CONFIG_SPL_CMT
+#define CONFIG_SPL_CMT_DEBUG
+*/
+
+/* nedded by compliance test in read mode */
+#if defined(CONFIG_SPL_CMT)
+#define CONFIG_SYS_DCACHE_OFF
+#endif
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND       0xB80000
+#define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE               (4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+
+
+#define CONFIG_DFU_MTD
+#undef COMMON_ENV_DFU_ARGS
+#define COMMON_ENV_DFU_ARGS    "dfu_args=run bootargs_defaults;" \
+                               "setenv bootargs ${bootargs};" \
+                               "mtdparts default;" \
+                               "draco_led 1;" \
+                               "dfu 0 mtd 0;" \
+                               "draco_led 0;\0" \
+
+#undef DFU_ALT_INFO_NAND_V2
+#define DFU_ALT_INFO_NAND_V2 \
+       "spl mtddev;" \
+       "spl.backup1 mtddev;" \
+       "spl.backup2 mtddev;" \
+       "spl.backup3 mtddev;" \
+       "u-boot mtddev;" \
+       "u-boot.env0 mtddev;" \
+       "u-boot.env1 mtddev;" \
+       "rootfs mtddevubi" \
+
+#undef MTDIDS_NAME_STR
+#define MTDIDS_NAME_STR                "omap2-nand_concat"
+#undef MTDIDS_DEFAULT
+#define MTDIDS_DEFAULT         "nand2=" MTDIDS_NAME_STR
+
+#undef MTDPARTS_DEFAULT_V2
+#define MTDPARTS_DEFAULT_V2     "mtdparts=" MTDIDS_NAME_STR ":" \
+                               "512k(spl)," \
+                               "512k(spl.backup1)," \
+                               "512k(spl.backup2)," \
+                               "512k(spl.backup3)," \
+                               "7680k(u-boot)," \
+                               "2048k(u-boot.env0)," \
+                               "2048k(u-boot.env1)," \
+                               "2048k(mtdoops)," \
+                               "-(rootfs)"
+
+#undef MTDPARTS_DEFAULT
+#define MTDPARTS_DEFAULT       MTDPARTS_DEFAULT_V2
+
+#undef CONFIG_ENV_SETTINGS_NAND_V2
+#define CONFIG_ENV_SETTINGS_NAND_V2 \
+       "nand_active_ubi_vol=rootfs_a\0" \
+       "rootfs_name=rootfs\0" \
+       "kernel_name=uImage\0"\
+       "nand_root_fs_type=ubifs rootwait=1\0" \
+       "nand_args=run bootargs_defaults;" \
+               "mtdparts default;" \
+               "setenv ${partitionset_active} true;" \
+               "if test -n ${A}; then " \
+                       "setenv nand_active_ubi_vol ${rootfs_name}_a;" \
+               "fi;" \
+               "if test -n ${B}; then " \
+                       "setenv nand_active_ubi_vol ${rootfs_name}_b;" \
+               "fi;" \
+               "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
+               "ubi.mtd=rootfs,${ubi_off};" \
+               "setenv bootargs ${bootargs} " \
+               "root=${nand_root} noinitrd ${mtdparts} " \
+               "rootfstype=${nand_root_fs_type} ip=${ip_method} " \
+               "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
+               "=mtdoops\0" \
+       COMMON_ENV_DFU_ARGS \
+               "dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \
+       COMMON_ENV_NAND_BOOT \
+               "ubi part rootfs ${ubi_off};" \
+               "ubifsmount ubi0:${nand_active_ubi_vol};" \
+               "ubifsload ${kloadaddr} boot/${kernel_name};" \
+               "ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \
+               "bootm ${kloadaddr} - ${loadaddr}\0" \
+       "nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \
+               "bootm ${kloadaddr} - ${loadaddr}\0" \
+       COMMON_ENV_NAND_CMDS
+
+#ifndef CONFIG_SPL_BUILD
+
+#define CONFIG_NAND_CS_INIT
+#define ETAMIN_NAND_GPMC_CONFIG1       0x00000800
+#define ETAMIN_NAND_GPMC_CONFIG2       0x001e1e00
+#define ETAMIN_NAND_GPMC_CONFIG3       0x001e1e00
+#define ETAMIN_NAND_GPMC_CONFIG4       0x16051807
+#define ETAMIN_NAND_GPMC_CONFIG5       0x00151e1e
+#define ETAMIN_NAND_GPMC_CONFIG6       0x16000f80
+#define CONFIG_MTD_CONCAT
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "hostname=etamin\0" \
+       "ubi_off=4096\0"\
+       "nand_img_size=0x400000\0" \
+       "optargs=\0" \
+       "preboot=draco_led 0\0" \
+       CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+       CONFIG_ENV_SETTINGS_V2 \
+       CONFIG_ENV_SETTINGS_NAND_V2
+
+#ifndef CONFIG_RESTORE_FLASH
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+       "run dfu_start; " \
+       "reset; " \
+"fi;" \
+"run nand_boot;" \
+"run nand_boot_backup;" \
+"reset;"
+
+
+#else
+#define CONFIG_BOOTCOMMAND                     \
+       "setenv autoload no; "                  \
+       "dhcp; "                                \
+       "if tftp 80000000 debrick.scr; then "   \
+               "source 80000000; "             \
+       "fi"
+#endif
+#endif /* CONFIG_SPL_BUILD */
+#endif /* ! __CONFIG_ETAMIN_H */
index 794650a51cb30c41ccfde212be0efa7f2768a2a6..990fd84b32af263d9084f48604c56b3960356621 100644 (file)
@@ -61,6 +61,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "hostname=pxm2\0" \
+       "ubi_off=2048\0"\
        "nand_img_size=0x500000\0" \
        "optargs=\0" \
        "preboot=draco_led 0\0" \
index 6c8681ab4a0b09550b8d9895aaafb56cb3c45a00..55be46bcf2caf1a8e7e0ab5ee282fdad166ee1e0 100644 (file)
@@ -76,6 +76,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "hostname=rastaban\0" \
+       "ubi_off=2048\0"\
        "nand_img_size=0x400000\0" \
        "optargs=\0" \
        "preboot=draco_led 0\0" \
index b0dcbd8c5a49d5fc6e0075319002bce5e4ccd101..aea8e217d019eafc0b3e174451f0e917f43ee36a 100644 (file)
@@ -56,6 +56,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "hostname=rut\0" \
+       "ubi_off=2048\0"\
        "nand_img_size=0x500000\0" \
        "splashpos=m,m\0" \
        "optargs=fixrtc --no-log consoleblank=0 \0" \
index ae26dad4aa61c47120b00a6cb504b808b907548c..5969541de6450eb48f0997bdc97e5afea058ecb5 100644 (file)
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT     (CONFIG_SYS_NAND_BLOCK_SIZE / \
                                         CONFIG_SYS_NAND_PAGE_SIZE)
                        "setenv nand_src_addr ${nand_src_addr_B};" \
                "fi;" \
                "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
-               "ubi.mtd=9,2048;" \
+               "ubi.mtd=9,${ubi_off};" \
                "setenv bootargs ${bootargs} " \
                "root=${nand_root} noinitrd ${mtdparts} " \
                "rootfstype=${nand_root_fs_type} ip=${ip_method} " \
        COMMON_ENV_DFU_ARGS \
                "dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \
        COMMON_ENV_NAND_BOOT \
-               "ubi part rootfs 2048;" \
+               "ubi part rootfs ${ubi_off};" \
                "ubifsmount ubi0:${nand_active_ubi_vol};" \
                "ubifsload ${kloadaddr} boot/${kernel_name};" \
                "ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \
index a03f87c2fb962aa2953d21e831130f64b387aebf..25ac2cba4b56b58a201d5989345e78e8b9069c66 100644 (file)
@@ -69,6 +69,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "hostname=thuban\0" \
+       "ubi_off=2048\0"\
        "nand_img_size=0x400000\0" \
        "optargs=\0" \
        "preboot=draco_led 0\0" \