armv8/fsl-lsch3: Change normal memory shareability

According to hardware implementation, a single outer shareable global
coherence group is defined. Inner shareable has not bee enabled.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 47b947f44fadb466da62872b82cacb103d45937e..ada1690ed9e50a31d643c9ef0ddf47bb05ce91d3 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -150,7 +150,7 @@ static inline void final_mmu_setup(void)
         * set level 2 table 0 to cache-inhibit, covering 0 to 1GB
         */
        section_l1t0 = 0;
-       section_l1t1 = BLOCK_SIZE_L0;
+       section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE;
        section_l2 = 0;
        for (i = 0; i < 512; i++) {
                set_pgtable_section(level1_table_0, i, section_l1t0,
@@ -168,10 +168,10 @@ static inline void final_mmu_setup(void)
                (u64)level2_table_0 | PMD_TYPE_TABLE;
        level1_table_0[2] =
                0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
-               PMD_ATTRINDX(MT_NORMAL);
+               PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
        level1_table_0[3] =
                0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
-               PMD_ATTRINDX(MT_NORMAL);
+               PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
 
        /* Rewrite table to enable cache */
        set_pgtable_section(level2_table_0,

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 4b7b67b643de7ce9e6e0cb47e47dda354a1c2b69..4b9cb5296572cc9db2d76ffd4193939237da669d 100644 (file)
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -65,7 +65,8 @@
 /*
  * Section
  */
-#define PMD_SECT_S             (3 << 8)
+#define PMD_SECT_OUTER_SHARE   (2 << 8)
+#define PMD_SECT_INNER_SHARE   (3 << 8)
 #define PMD_SECT_AF            (1 << 10)
 #define PMD_SECT_NG            (1 << 11)
 #define PMD_SECT_PXN           (UL(1) << 53)