Change PCIE1&2 deciide logic on MPC8544DS board more readable

The IO port selection for MPC8544DS board:
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2		0x4, 0x5, 0x6, 0x7
 PCIE3		0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>

diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 13c55fd37f4ea532bf82d65198c02248cdddad71..977731289b1ff659064cd27593bcd46b78287e5a 100644 (file)
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -188,7 +188,7 @@ pci_init_board(void)
        volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
        struct pci_controller *hose = &pcie1_hose;
        int pcie_ep = (host_agent == 5);
-       int pcie_configured  = io_sel & 6;
+       int pcie_configured  = io_sel >= 2;
        struct pci_region *r = hose->regions;
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -251,7 +251,7 @@ pci_init_board(void)
        volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
        struct pci_controller *hose = &pcie2_hose;
        int pcie_ep = (host_agent == 3);
-       int pcie_configured  = io_sel & 4;
+       int pcie_configured  = io_sel >= 4;
        struct pci_region *r = hose->regions;
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){