ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.c

These functions have been merged into the common GPMC init code
with this commit a0a37183 (ARM: omap: merge GPMC initialization code
for all platform). The file is not compiled any more. So remove it
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>

diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
deleted file mode 100644 (file)
index 1832aff..0000000
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *     Manikandan Pillai <mani.pillai@ti.com>
- *
- * Initial Code from:
- *     Richard Woodruff <r-woodruff2@ti.com>
- *     Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <command.h>
-
-struct gpmc *gpmc_cfg;
-
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-       M_NAND_GPMC_CONFIG1,
-       M_NAND_GPMC_CONFIG2,
-       M_NAND_GPMC_CONFIG3,
-       M_NAND_GPMC_CONFIG4,
-       M_NAND_GPMC_CONFIG5,
-       M_NAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_CMD_ONENAND)
-static const u32 gpmc_onenand[GPMC_MAX_REG] = {
-       ONENAND_GPMC_CONFIG1,
-       ONENAND_GPMC_CONFIG2,
-       ONENAND_GPMC_CONFIG3,
-       ONENAND_GPMC_CONFIG4,
-       ONENAND_GPMC_CONFIG5,
-       ONENAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_ONENAND */
-
-/********************************************************
- *  mem_ok() - test used to see if timings are correct
- *             for a part. Helps in guessing which part
- *             we are currently using.
- *******************************************************/
-u32 mem_ok(u32 cs)
-{
-       u32 val1, val2, addr;
-       u32 pattern = 0x12345678;
-
-       addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
-
-       writel(0x0, addr + 0x400);      /* clear pos A */
-       writel(pattern, addr);          /* pattern to pos B */
-       writel(0x0, addr + 4);          /* remove pattern off the bus */
-       val1 = readl(addr + 0x400);     /* get pos A value */
-       val2 = readl(addr);             /* get val2 */
-       writel(0x0, addr + 0x400);      /* clear pos A */
-
-       if ((val1 != 0) || (val2 != pattern))   /* see if pos A val changed */
-               return 0;
-       else
-               return 1;
-}
-
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-                       u32 size)
-{
-       writel(0, &cs->config7);
-       sdelay(1000);
-       /* Delay for settling */
-       writel(gpmc_config[0], &cs->config1);
-       writel(gpmc_config[1], &cs->config2);
-       writel(gpmc_config[2], &cs->config3);
-       writel(gpmc_config[3], &cs->config4);
-       writel(gpmc_config[4], &cs->config5);
-       writel(gpmc_config[5], &cs->config6);
-
-       /*
-        * Enable the config.  size is the CS size and goes in
-        * bits 11:8.  We set bit 6 to enable this CS and the base
-        * address goes into bits 5:0.
-        */
-        writel((size << 8) | (GPMC_CS_ENABLE << 6) |
-                                ((base >> 24) & GPMC_BASEADDR_MASK),
-                                &cs->config7);
-       sdelay(2000);
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
-       /* putting a blanket check on GPMC based on ZeBu for now */
-       gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
-       const u32 *gpmc_config = NULL;
-       u32 base = 0;
-       u32 size = 0;
-#endif
-       u32 config = 0;
-
-       /* global settings */
-       writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
-       writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
-
-       config = readl(&gpmc_cfg->config);
-       config &= (~0xf00);
-       writel(config, &gpmc_cfg->config);
-
-       /*
-        * Disable the GPMC0 config set by ROM code
-        * It conflicts with our MPDB (both at 0x08000000)
-        */
-       writel(0, &gpmc_cfg->cs[0].config7);
-       sdelay(1000);
-
-#if defined(CONFIG_CMD_NAND)   /* CS 0 */
-       gpmc_config = gpmc_m_nand;
-
-       base = PISMO1_NAND_BASE;
-       size = PISMO1_NAND_SIZE;
-       enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
-       gpmc_config = gpmc_onenand;
-       base = PISMO1_ONEN_BASE;
-       size = PISMO1_ONEN_SIZE;
-       enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-}