]> git.sur5r.net Git - u-boot/commitdiff
sf: Fix look for the fastest read command
authorJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Fri, 12 Dec 2014 14:06:11 +0000 (19:36 +0530)
committerSimon Glass <sjg@chromium.org>
Sat, 13 Dec 2014 22:08:04 +0000 (15:08 -0700)
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.

So this fix on sf will correctly handle the slow read supported
controllers.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
drivers/mtd/spi/sf_internal.h
drivers/mtd/spi/sf_params.c
drivers/mtd/spi/sf_probe.c

index 5b7670c9aaf1219e841cd2dfc5096bb62e7e3390..e159f04000744cf0e0add128725cd23f098b2baa 100644 (file)
@@ -23,13 +23,16 @@ enum spi_dual_flash {
 /* Enum list - Full read commands */
 enum spi_read_cmds {
        ARRAY_SLOW              = 1 << 0,
-       DUAL_OUTPUT_FAST        = 1 << 1,
-       DUAL_IO_FAST            = 1 << 2,
-       QUAD_OUTPUT_FAST        = 1 << 3,
-       QUAD_IO_FAST            = 1 << 4,
+       ARRAY_FAST              = 1 << 1,
+       DUAL_OUTPUT_FAST        = 1 << 2,
+       DUAL_IO_FAST            = 1 << 3,
+       QUAD_OUTPUT_FAST        = 1 << 4,
+       QUAD_IO_FAST            = 1 << 5,
 };
 
-#define RD_EXTN        (ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+/* Normal - Extended - Full command set */
+#define RD_NORM        (ARRAY_SLOW | ARRAY_FAST)
+#define RD_EXTN        (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
 #define RD_FULL        (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
 
 /* sf param flags */
index 61545cacaabe8415bf7a1a1fa35d2e7e8294e2b9..0f1f837106630b005ebeca12943b8c5ac700babd 100644 (file)
 /* SPI/QSPI flash device params structure */
 const struct spi_flash_params spi_flash_params_table[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL          /* ATMEL */
-       {"AT45DB011D",     0x1f2200, 0x0,       64 * 1024,     4,       0,                  SECT_4K},
-       {"AT45DB021D",     0x1f2300, 0x0,       64 * 1024,     8,       0,                  SECT_4K},
-       {"AT45DB041D",     0x1f2400, 0x0,       64 * 1024,     8,       0,                  SECT_4K},
-       {"AT45DB081D",     0x1f2500, 0x0,       64 * 1024,    16,       0,                  SECT_4K},
-       {"AT45DB161D",     0x1f2600, 0x0,       64 * 1024,    32,       0,                  SECT_4K},
-       {"AT45DB321D",     0x1f2700, 0x0,       64 * 1024,    64,       0,                  SECT_4K},
-       {"AT45DB641D",     0x1f2800, 0x0,       64 * 1024,   128,       0,                  SECT_4K},
-       {"AT25DF321",      0x1f4701, 0x0,       64 * 1024,    64,       0,                  SECT_4K},
+       {"AT45DB011D",     0x1f2200, 0x0,       64 * 1024,     4, RD_NORM,                  SECT_4K},
+       {"AT45DB021D",     0x1f2300, 0x0,       64 * 1024,     8, RD_NORM,                  SECT_4K},
+       {"AT45DB041D",     0x1f2400, 0x0,       64 * 1024,     8, RD_NORM,                  SECT_4K},
+       {"AT45DB081D",     0x1f2500, 0x0,       64 * 1024,    16, RD_NORM,                  SECT_4K},
+       {"AT45DB161D",     0x1f2600, 0x0,       64 * 1024,    32, RD_NORM,                  SECT_4K},
+       {"AT45DB321D",     0x1f2700, 0x0,       64 * 1024,    64, RD_NORM,                  SECT_4K},
+       {"AT45DB641D",     0x1f2800, 0x0,       64 * 1024,   128, RD_NORM,                  SECT_4K},
+       {"AT25DF321",      0x1f4701, 0x0,       64 * 1024,    64, RD_NORM,                  SECT_4K},
 #endif
 #ifdef CONFIG_SPI_FLASH_EON            /* EON */
-       {"EN25Q32B",       0x1c3016, 0x0,       64 * 1024,    64,       0,                        0},
-       {"EN25Q64",        0x1c3017, 0x0,       64 * 1024,   128,       0,                  SECT_4K},
-       {"EN25Q128B",      0x1c3018, 0x0,       64 * 1024,   256,       0,                        0},
-       {"EN25S64",        0x1c3817, 0x0,       64 * 1024,   128,       0,                        0},
+       {"EN25Q32B",       0x1c3016, 0x0,       64 * 1024,    64, RD_NORM,                        0},
+       {"EN25Q64",        0x1c3017, 0x0,       64 * 1024,   128, RD_NORM,                  SECT_4K},
+       {"EN25Q128B",      0x1c3018, 0x0,       64 * 1024,   256, RD_NORM,                        0},
+       {"EN25S64",        0x1c3817, 0x0,       64 * 1024,   128, RD_NORM,                        0},
 #endif
 #ifdef CONFIG_SPI_FLASH_GIGADEVICE     /* GIGADEVICE */
-       {"GD25Q64B",       0xc84017, 0x0,       64 * 1024,   128,       0,                  SECT_4K},
-       {"GD25LQ32",       0xc86016, 0x0,       64 * 1024,    64,       0,                  SECT_4K},
+       {"GD25Q64B",       0xc84017, 0x0,       64 * 1024,   128, RD_NORM,                  SECT_4K},
+       {"GD25LQ32",       0xc86016, 0x0,       64 * 1024,    64, RD_NORM,                  SECT_4K},
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX       /* MACRONIX */
-       {"MX25L2006E",     0xc22012, 0x0,       64 * 1024,     4,       0,                        0},
-       {"MX25L4005",      0xc22013, 0x0,       64 * 1024,     8,       0,                        0},
-       {"MX25L8005",      0xc22014, 0x0,       64 * 1024,    16,       0,                        0},
-       {"MX25L1605D",     0xc22015, 0x0,       64 * 1024,    32,       0,                        0},
-       {"MX25L3205D",     0xc22016, 0x0,       64 * 1024,    64,       0,                        0},
-       {"MX25L6405D",     0xc22017, 0x0,       64 * 1024,   128,       0,                        0},
+       {"MX25L2006E",     0xc22012, 0x0,       64 * 1024,     4, RD_NORM,                        0},
+       {"MX25L4005",      0xc22013, 0x0,       64 * 1024,     8, RD_NORM,                        0},
+       {"MX25L8005",      0xc22014, 0x0,       64 * 1024,    16, RD_NORM,                        0},
+       {"MX25L1605D",     0xc22015, 0x0,       64 * 1024,    32, RD_NORM,                        0},
+       {"MX25L3205D",     0xc22016, 0x0,       64 * 1024,    64, RD_NORM,                        0},
+       {"MX25L6405D",     0xc22017, 0x0,       64 * 1024,   128, RD_NORM,                        0},
        {"MX25L12805",     0xc22018, 0x0,       64 * 1024,   256, RD_FULL,                   WR_QPP},
        {"MX25L25635F",    0xc22019, 0x0,       64 * 1024,   512, RD_FULL,                   WR_QPP},
        {"MX25L51235F",    0xc2201a, 0x0,       64 * 1024,  1024, RD_FULL,                   WR_QPP},
        {"MX25L12855E",    0xc22618, 0x0,       64 * 1024,   256, RD_FULL,                   WR_QPP},
 #endif
 #ifdef CONFIG_SPI_FLASH_SPANSION       /* SPANSION */
-       {"S25FL008A",      0x010213, 0x0,       64 * 1024,    16,       0,                        0},
-       {"S25FL016A",      0x010214, 0x0,       64 * 1024,    32,       0,                        0},
-       {"S25FL032A",      0x010215, 0x0,       64 * 1024,    64,       0,                        0},
-       {"S25FL064A",      0x010216, 0x0,       64 * 1024,   128,       0,                        0},
+       {"S25FL008A",      0x010213, 0x0,       64 * 1024,    16, RD_NORM,                        0},
+       {"S25FL016A",      0x010214, 0x0,       64 * 1024,    32, RD_NORM,                        0},
+       {"S25FL032A",      0x010215, 0x0,       64 * 1024,    64, RD_NORM,                        0},
+       {"S25FL064A",      0x010216, 0x0,       64 * 1024,   128, RD_NORM,                        0},
        {"S25FL128P_256K", 0x012018, 0x0300,   256 * 1024,    64, RD_FULL,                   WR_QPP},
        {"S25FL128P_64K",  0x012018, 0x0301,    64 * 1024,   256, RD_FULL,                   WR_QPP},
        {"S25FL032P",      0x010215, 0x4d00,    64 * 1024,    64, RD_FULL,                   WR_QPP},
@@ -64,17 +64,17 @@ const struct spi_flash_params spi_flash_params_table[] = {
        {"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL,                   WR_QPP},
 #endif
 #ifdef CONFIG_SPI_FLASH_STMICRO                /* STMICRO */
-       {"M25P10",         0x202011, 0x0,       32 * 1024,     4,       0,                        0},
-       {"M25P20",         0x202012, 0x0,       64 * 1024,     4,       0,                        0},
-       {"M25P40",         0x202013, 0x0,       64 * 1024,     8,       0,                        0},
-       {"M25P80",         0x202014, 0x0,       64 * 1024,    16,       0,                        0},
-       {"M25P16",         0x202015, 0x0,       64 * 1024,    32,       0,                        0},
-       {"M25PE16",        0x208015, 0x1000,    64 * 1024,    32,       0,                        0},
+       {"M25P10",         0x202011, 0x0,       32 * 1024,     4, RD_NORM,                        0},
+       {"M25P20",         0x202012, 0x0,       64 * 1024,     4, RD_NORM,                        0},
+       {"M25P40",         0x202013, 0x0,       64 * 1024,     8, RD_NORM,                        0},
+       {"M25P80",         0x202014, 0x0,       64 * 1024,    16, RD_NORM,                        0},
+       {"M25P16",         0x202015, 0x0,       64 * 1024,    32, RD_NORM,                        0},
+       {"M25PE16",        0x208015, 0x1000,    64 * 1024,    32, RD_NORM,                        0},
        {"M25PX16",        0x207115, 0x1000,    64 * 1024,    32, RD_EXTN,                        0},
-       {"M25P32",         0x202016, 0x0,       64 * 1024,    64,       0,                        0},
-       {"M25P64",         0x202017, 0x0,       64 * 1024,   128,       0,                        0},
-       {"M25P128",        0x202018, 0x0,      256 * 1024,    64,       0,                        0},
-       {"M25PX64",        0x207117, 0x0,       64 * 1024,   128,       0,                  SECT_4K},
+       {"M25P32",         0x202016, 0x0,       64 * 1024,    64, RD_NORM,                        0},
+       {"M25P64",         0x202017, 0x0,       64 * 1024,   128, RD_NORM,                        0},
+       {"M25P128",        0x202018, 0x0,      256 * 1024,    64, RD_NORM,                        0},
+       {"M25PX64",        0x207117, 0x0,       64 * 1024,   128, RD_NORM,                  SECT_4K},
        {"N25Q32",         0x20ba16, 0x0,       64 * 1024,    64, RD_FULL,         WR_QPP | SECT_4K},
        {"N25Q32A",        0x20bb16, 0x0,       64 * 1024,    64, RD_FULL,         WR_QPP | SECT_4K},
        {"N25Q64",         0x20ba17, 0x0,       64 * 1024,   128, RD_FULL,         WR_QPP | SECT_4K},
@@ -89,25 +89,25 @@ const struct spi_flash_params spi_flash_params_table[] = {
        {"N25Q1024A",      0x20bb21, 0x0,       64 * 1024,  2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
 #endif
 #ifdef CONFIG_SPI_FLASH_SST            /* SST */
-       {"SST25VF040B",    0xbf258d, 0x0,       64 * 1024,     8,       0,          SECT_4K | SST_WP},
-       {"SST25VF080B",    0xbf258e, 0x0,       64 * 1024,    16,       0,          SECT_4K | SST_WP},
-       {"SST25VF016B",    0xbf2541, 0x0,       64 * 1024,    32,       0,          SECT_4K | SST_WP},
-       {"SST25VF032B",    0xbf254a, 0x0,       64 * 1024,    64,       0,          SECT_4K | SST_WP},
-       {"SST25VF064C",    0xbf254b, 0x0,       64 * 1024,   128,       0,                   SECT_4K},
-       {"SST25WF512",     0xbf2501, 0x0,       64 * 1024,     1,       0,          SECT_4K | SST_WP},
-       {"SST25WF010",     0xbf2502, 0x0,       64 * 1024,     2,       0,          SECT_4K | SST_WP},
-       {"SST25WF020",     0xbf2503, 0x0,       64 * 1024,     4,       0,          SECT_4K | SST_WP},
-       {"SST25WF040",     0xbf2504, 0x0,       64 * 1024,     8,       0,          SECT_4K | SST_WP},
-       {"SST25WF080",     0xbf2505, 0x0,       64 * 1024,    16,       0,          SECT_4K | SST_WP},
+       {"SST25VF040B",    0xbf258d, 0x0,       64 * 1024,     8, RD_NORM,          SECT_4K | SST_WP},
+       {"SST25VF080B",    0xbf258e, 0x0,       64 * 1024,    16, RD_NORM,          SECT_4K | SST_WP},
+       {"SST25VF016B",    0xbf2541, 0x0,       64 * 1024,    32, RD_NORM,          SECT_4K | SST_WP},
+       {"SST25VF032B",    0xbf254a, 0x0,       64 * 1024,    64, RD_NORM,          SECT_4K | SST_WP},
+       {"SST25VF064C",    0xbf254b, 0x0,       64 * 1024,   128, RD_NORM,                   SECT_4K},
+       {"SST25WF512",     0xbf2501, 0x0,       64 * 1024,     1, RD_NORM,          SECT_4K | SST_WP},
+       {"SST25WF010",     0xbf2502, 0x0,       64 * 1024,     2, RD_NORM,          SECT_4K | SST_WP},
+       {"SST25WF020",     0xbf2503, 0x0,       64 * 1024,     4, RD_NORM,          SECT_4K | SST_WP},
+       {"SST25WF040",     0xbf2504, 0x0,       64 * 1024,     8, RD_NORM,          SECT_4K | SST_WP},
+       {"SST25WF080",     0xbf2505, 0x0,       64 * 1024,    16, RD_NORM,          SECT_4K | SST_WP},
 #endif
 #ifdef CONFIG_SPI_FLASH_WINBOND                /* WINBOND */
-       {"W25P80",         0xef2014, 0x0,       64 * 1024,    16,       0,                         0},
-       {"W25P16",         0xef2015, 0x0,       64 * 1024,    32,       0,                         0},
-       {"W25P32",         0xef2016, 0x0,       64 * 1024,    64,       0,                         0},
-       {"W25X40",         0xef3013, 0x0,       64 * 1024,     8,       0,                   SECT_4K},
-       {"W25X16",         0xef3015, 0x0,       64 * 1024,    32,       0,                   SECT_4K},
-       {"W25X32",         0xef3016, 0x0,       64 * 1024,    64,       0,                   SECT_4K},
-       {"W25X64",         0xef3017, 0x0,       64 * 1024,   128,       0,                   SECT_4K},
+       {"W25P80",         0xef2014, 0x0,       64 * 1024,    16, RD_NORM,                         0},
+       {"W25P16",         0xef2015, 0x0,       64 * 1024,    32, RD_NORM,                         0},
+       {"W25P32",         0xef2016, 0x0,       64 * 1024,    64, RD_NORM,                         0},
+       {"W25X40",         0xef3013, 0x0,       64 * 1024,     8, RD_NORM,                   SECT_4K},
+       {"W25X16",         0xef3015, 0x0,       64 * 1024,    32, RD_NORM,                   SECT_4K},
+       {"W25X32",         0xef3016, 0x0,       64 * 1024,    64, RD_NORM,                   SECT_4K},
+       {"W25X64",         0xef3017, 0x0,       64 * 1024,   128, RD_NORM,                   SECT_4K},
        {"W25Q80BL",       0xef4014, 0x0,       64 * 1024,    16, RD_FULL,          WR_QPP | SECT_4K},
        {"W25Q16CL",       0xef4015, 0x0,       64 * 1024,    32, RD_FULL,          WR_QPP | SECT_4K},
        {"W25Q32BV",       0xef4016, 0x0,       64 * 1024,    64, RD_FULL,          WR_QPP | SECT_4K},
index 26364269be1a5e823efc99bd498262bd1a9d3393..7cde4c052ab71d912e91a77b132b9b6a7b6df910 100644 (file)
@@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Read commands array */
 static u8 spi_read_cmds_array[] = {
        CMD_READ_ARRAY_SLOW,
+       CMD_READ_ARRAY_FAST,
        CMD_READ_DUAL_OUTPUT_FAST,
        CMD_READ_DUAL_IO_FAST,
        CMD_READ_QUAD_OUTPUT_FAST,