exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devices

Add a TPM node to the various Chromebooks so that driver can be converted to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index 32c0098bd8be7138925d867a387cd31bd701a203..bda549998861c65b6cfd66c9c29a4fc68996c3fb 100644 (file)
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -206,6 +206,15 @@
                };
        };
 
+       i2c@12C90000 {
+               clock-frequency = <100000>;
+               tpm@20 {
+                       reg = <0x20>;
+                       u-boot,i2c-offset-len = <0>;
+                       compatible = "infineon,slb9635tt";
+               };
+       };
+
        spi@12d30000 {
                spi-max-frequency = <50000000>;
                firmware_storage_spi: flash@0 {

diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts
index 76d5323dc314ab7aedbcd910995fdb09f9aa1345..81b3d29f9cf032d962f1e41c8dc0168e8079d654 100644 (file)
--- a/arch/arm/dts/exynos5250-spring.dts
+++ b/arch/arm/dts/exynos5250-spring.dts
@@ -59,6 +59,14 @@
                                         <&gpy4 2 0>;
        };
 
+       i2c@12C90000 {
+               clock-frequency = <100000>;
+               tpm@20 {
+                       reg = <0x20>;
+                       compatible = "infineon,slb9645tt";
+               };
+       };
+
        mmc@12200000 {
                samsung,bus-width = <8>;
                samsung,timing = <1 3 3>;

diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
index 2d2b7c9bdea544ba9e15047cb383828c26d7c520..16d52f4928121afce9ca12c4d263c6ae6ddfea67 100644 (file)
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -197,9 +197,9 @@
 
        i2c@12E10000 { /* i2c9 */
                clock-frequency = <400000>;
-                tpm@20 {
-                        compatible = "infineon,slb9645tt";
-                        reg = <0x20>;
+               tpm@20 {
+                       compatible = "infineon,slb9645tt";
+                       reg = <0x20>;
                };
        };
 

diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
index 600c2948cf3eebdce9be99b91e2ffcbe4224d6f9..1d7ff23c933cbeef16c088be12030b069b08c761 100644 (file)
--- a/arch/arm/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -72,9 +72,9 @@
 
        i2c@12E10000 { /* i2c9 */
                clock-frequency = <400000>;
-                tpm@20 {
-                        compatible = "infineon,slb9645tt";
-                        reg = <0x20>;
+               tpm@20 {
+                       compatible = "infineon,slb9645tt";
+                       reg = <0x20>;
                };
        };
 

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index ad390bf11721a3b161c3b55a1c517ddf1e55eb5b..4291141dfee898a642394f65b51c911825371259 100644 (file)
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -237,6 +237,11 @@
                };
        };
 
+       tpm {
+               reg = <0xfed40000 0x5000>;
+               compatible = "infineon,slb9635lpc";
+       };
+
        microcode {
                update@0 {
 #include "microcode/m12306a9_0000001b.dtsi"

diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 84eae3ab6513ac0990ebab28255936d24ff684c0..36feb96a94d09ee2fcabe315be1f59ca3feba95b 100644 (file)
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -62,4 +62,9 @@
                };
        };
 
+       tpm {
+               reg = <0xfed40000 0x5000>;
+               compatible = "infineon,slb9635lpc";
+       };
+
 };