&qspi {
status = "okay";
- flash0: m25p80@0 {
- compatible = "s25fl512s","spi-flash";
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <96000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- tshsl-ns = <392>;
- tsd2d-ns = <392>;
- tchsh-ns = <100>;
- tslch-ns = <100>;
+ flash0: m25p80@0 {
+ compatible = "s25fl512s","spi-flash";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <96000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cdns,tshsl-ns = <392>;
+ cdns,tsd2d-ns = <392>;
+ cdns,tchsh-ns = <100>;
+ cdns,tslch-ns = <100>;
block-size = <18>;
-
- partition@0 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x00000000 0x00100000>;
- };
- partition@1 {
- label = "QSPI.u-boot-env";
- reg = <0x00100000 0x00040000>;
- };
- partition@2 {
- label = "QSPI.skern";
- reg = <0x00140000 0x0040000>;
- };
- partition@3 {
- label = "QSPI.pmmc-firmware";
- reg = <0x00180000 0x0040000>;
- };
- partition@4 {
- label = "QSPI.kernel";
- reg = <0x001C0000 0x0800000>;
- };
- partition@5 {
- label = "QSPI.file-system";
- reg = <0x009C0000 0x3640000>;
- };
- };
+ partition@0 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x00000000 0x00100000>;
+ };
+ partition@1 {
+ label = "QSPI.u-boot-env";
+ reg = <0x00100000 0x00040000>;
+ };
+ partition@2 {
+ label = "QSPI.skern";
+ reg = <0x00140000 0x0040000>;
+ };
+ partition@3 {
+ label = "QSPI.pmmc-firmware";
+ reg = <0x00180000 0x0040000>;
+ };
+ partition@4 {
+ label = "QSPI.kernel";
+ reg = <0x001C0000 0x0800000>;
+ };
+ partition@5 {
+ label = "QSPI.file-system";
+ reg = <0x009C0000 0x3640000>;
+ };
+ };
};
&mmc0 {
<0x24000000 0x4000000>;
interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
num-cs = <4>;
- fifo-depth = <256>;
- sram-size = <256>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x24000000>;
status = "disabled";
};
clocks = <&qspi_clk>;
ext-decoder = <0>; /* external decoder */
num-cs = <4>;
- fifo-depth = <128>;
- sram-size = <128>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
bus-num = <2>;
status = "disabled";
};
clocks = <&l4_main_clk>;
ext-decoder = <0>; /* external decoder */
num-chipselect = <4>;
- fifo-depth = <128>;
- sram-size = <512>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
bus-num = <2>;
status = "disabled";
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
flash1: n25q00@1 {
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
reg = <0x80203000 0x100>,
<0x40000000 0x1000000>;
clocks = <3750000>;
- sram-size = <256>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x40000000>;
status = "okay";
flash0: n25q32@0 {
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
};