]> git.sur5r.net Git - u-boot/commitdiff
Fix a bug in the slave serial programming mode for the Xilinx
authorWolfgang Denk <wd@denx.de>
Sat, 17 Nov 2007 00:30:40 +0000 (01:30 +0100)
committerWolfgang Denk <wd@denx.de>
Sat, 17 Nov 2007 00:30:40 +0000 (01:30 +0100)
Spartan2/3 FPGAs. The old code used "< 0" on a "char" type to test if
the most significant bit was set, which did not work on any
architecture where "char" defaulted to be an unsigned type.

Based on a patch by Angelos Manousaridis <amanous@inaccessnetworks.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>
common/spartan2.c
common/spartan3.c

index 0fb23b6592069140cdb56a0f09496211cd97a66c..06550b9858cde121928d6b9beab8bffebb176f1c 100644 (file)
@@ -516,7 +516,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
                                (*fn->clk) (FALSE, TRUE, cookie);
                                CONFIG_FPGA_DELAY ();
                                /* Write data */
-                               (*fn->wr) ((val 0), TRUE, cookie);
+                               (*fn->wr) ((val & 0x80), TRUE, cookie);
                                CONFIG_FPGA_DELAY ();
                                /* Assert the clock */
                                (*fn->clk) (TRUE, TRUE, cookie);
index c0f2b05e480db356d097f1689e59be4df6bd0281..f7c4f8cf2b24aa9e70110d68440198449d8c01b8 100644 (file)
@@ -521,7 +521,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
                                (*fn->clk) (FALSE, TRUE, cookie);
                                CONFIG_FPGA_DELAY ();
                                /* Write data */
-                               (*fn->wr) ((val 0), TRUE, cookie);
+                               (*fn->wr) ((val & 0x80), TRUE, cookie);
                                CONFIG_FPGA_DELAY ();
                                /* Assert the clock */
                                (*fn->clk) (TRUE, TRUE, cookie);