return &serial_ffuart_device;
}
+
int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+#ifdef CONFIG_256M_U_BOOT
+ gd->ram_size += PHYS_SDRAM_2_SIZE;
+#endif
+ return 0;
+}
+
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
- return 0;
}
#ifdef CONFIG_CMD_USB
#define CONFIG_SYS_LOAD_ADDR 0xa1000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* NOR FLASH
*/
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
#define CONFIG_SYS_LOAD_ADDR (0xa1000000)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* NOR FLASH
*/
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
# if 0
/* FIXME: switch to _documented_ registers */
/*
#undef CONFIG_SYS_SKIP_DRAM_SCRUB
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* NAND Flash
*/
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* JFFS2 partitions
*
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
#define FPGA_REGS_BASE_PHYSICAL 0x08000000
/*
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* NOR FLASH
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* NOR FLASH
*/
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR (0x5c000000)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_GBL_DATA_SIZE + CONFIG_STACKSIZE + PHYS_SDRAM_1)
/*
* NOR FLASH
#define CONFIG_ENV_ADDR 0x20000 /* absolute address for now */
#define CONFIG_ENV_SIZE 0x2000
+#define PHYS_SDRAM_1 WEP_SDRAM_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
#undef CONFIG_ENV_OVERWRITE /* env is not writable now */
/*
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* FLASH and environment organization
*/
#define CONFIG_SYS_DRAM_BASE 0xa0000000
#define CONFIG_SYS_DRAM_SIZE 0x04000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/* FLASH organization */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* NOR FLASH
*/
#undef CONFIG_SYS_SKIP_DRAM_SCRUB
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
/*
* NAND Flash