]> git.sur5r.net Git - u-boot/commitdiff
PXA: Add necessary information for RELOC
authorMarek Vasut <marek.vasut@gmail.com>
Thu, 23 Sep 2010 07:46:57 +0000 (09:46 +0200)
committerWolfgang Denk <wd@denx.de>
Tue, 19 Oct 2010 20:47:34 +0000 (22:47 +0200)
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
21 files changed:
board/vpac270/vpac270.c
include/configs/balloon3.h
include/configs/cerf250.h
include/configs/colibri_pxa270.h
include/configs/cradle.h
include/configs/csb226.h
include/configs/delta.h
include/configs/innokom.h
include/configs/lubbock.h
include/configs/palmld.h
include/configs/palmtc.h
include/configs/pleb2.h
include/configs/pxa255_idp.h
include/configs/trizepsiv.h
include/configs/vpac270.h
include/configs/wepep250.h
include/configs/xaeniax.h
include/configs/xm250.h
include/configs/xsengine.h
include/configs/zipitz2.h
include/configs/zylonite.h

index 1557d1baf05553d92885cfeea2c25d1e0c8b7d35..f91ff97b2c4a820fae10fc03e3d004a98758d627 100644 (file)
@@ -49,7 +49,17 @@ struct serial_device *default_serial_console(void)
        return &serial_ffuart_device;
 }
 
+
 int dram_init(void)
+{
+       gd->ram_size = PHYS_SDRAM_1_SIZE;
+#ifdef CONFIG_256M_U_BOOT
+       gd->ram_size += PHYS_SDRAM_2_SIZE;
+#endif
+       return 0;
+}
+
+void dram_init_banksize(void)
 {
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
@@ -58,7 +68,6 @@ int dram_init(void)
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
        gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 #endif
-       return 0;
 }
 
 #ifdef CONFIG_CMD_USB
index 9066a2430430cd7dbc3156f94b5dd0887f590180..5e2a2851f12063a9180611d67d8ef5fbeb0512ea 100644 (file)
 
 #define        CONFIG_SYS_LOAD_ADDR            0xa1000000
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * NOR FLASH
  */
index 477b94aa6194cd5ce84584ccec73c31acc34df9d..98b69e37127bccd95a753d794430cd8aea8028c3 100644 (file)
 
 #define CONFIG_SYS_FLASH_BASE                  PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * GPIO settings
  */
index 277ff67bf0b8ccc27262a56d424755c5bae2db74..5f457f80debc08db9ebe67595af63da38cbebb2c 100644 (file)
 
 #define        CONFIG_SYS_LOAD_ADDR            (0xa1000000)
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * NOR FLASH
  */
index 998e1792085c92b4d562a5021efae661f889b3e5..d1c1a48e0c9f625fe38ace8664816ab97d22d75e 100644 (file)
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * FLASH and environment organization
  */
index 0661d65aba4dfaa1e1bb8fd5b7b3439d00ab4e9e..ae05734a09eb04b14e1852575900b3818f18c89e 100644 (file)
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 # if 0
 /* FIXME: switch to _documented_ registers */
 /*
index d930fb4b2b1d43f3a5806972cad417abbbb83c91..d53acbfebcf15bd321c87098a352786a750d188e 100644 (file)
 
 #undef CONFIG_SYS_SKIP_DRAM_SCRUB
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * NAND Flash
  */
index 9cb0d42eac7b02dfd71ab8a6aec195077710f033..007ccebf436e2de76a7397498883b412e28a78b8 100644 (file)
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * JFFS2 partitions
  *
index 0a6921044c78da2301f1f97e065a03cb3dea8183..3a99ec25c4be25221ce022a6091f07a0e37acc50 100644 (file)
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
 
 /*
index affc116b9f0e6ed27b624090e01b158ea9a363d9..926728b15f4ac6771be1eb9d4b539d74ac55b9f6 100644 (file)
 
 #define        CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * NOR FLASH
  */
index f4fc9cd50d9fb0c58ca4cb563d4b5c9c737a3945..fe87648ac60b4fb8e610d3aed3d02501d5c9032c 100644 (file)
 
 #define        CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * NOR FLASH
  */
index 9e694118c5dae00864c02702b762f8c19bb4e546..3b6e60afe9f5c754f49787ebf540a435efa1f7ee 100644 (file)
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * GPIO settings
  */
index 6c1defc9ae8ba50cb0028ddba711c8a54c8b5140..4581674ed3a55381866fea4d897157e91683352b 100644 (file)
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * GPIO settings
  */
index fa5aae8a5c5c773f46650e61109d4d962c4da507..474349537bdd63c3f445426c1cb1f8593173fbef 100644 (file)
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * GPIO settings
  */
index b8440a12418771e0e0d559612b2e127c91db010b..1bcd2f3e049ec2a29be251431e391807df1767c0 100644 (file)
 #define        CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 
 #define        CONFIG_SYS_LOAD_ADDR            (0x5c000000)
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         \
+       (CONFIG_SYS_GBL_DATA_SIZE + CONFIG_STACKSIZE + PHYS_SDRAM_1)
 
 /*
  * NOR FLASH
index 9a20cce457b70bd75c77077857dd7a826f3a3c3b..a961a27922ceb7783b220259d3e18d7d6f0c9a21 100644 (file)
 #define CONFIG_ENV_ADDR                0x20000         /* absolute address for now  */
 #define CONFIG_ENV_SIZE                0x2000
 
+#define        PHYS_SDRAM_1                    WEP_SDRAM_1
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 #undef  CONFIG_ENV_OVERWRITE                    /* env is not writable now   */
 
 /*
index 1329f0f3d85a1748162c4a3f0cd5e33e452ea50f..67d4106d6f1b8a5d0b96e95f1c40dcf5b591f3c1 100644 (file)
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * FLASH and environment organization
  */
index cd56ce72e7c1ecd7cb3b9fe572a27e4fab7cdcad..2ff9a2813adc9f4e25ecb656ce97531b30416c60 100644 (file)
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * FLASH and environment organization
  */
index f68461bb227e140bf18a6372ce5f31971a998927..9606b5316bff1b4dbbd8a47c8e735f521c12ccdb 100644 (file)
@@ -53,6 +53,9 @@
 #define CONFIG_SYS_DRAM_BASE                   0xa0000000
 #define CONFIG_SYS_DRAM_SIZE                   0x04000000
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /* FLASH organization */
 #define CONFIG_SYS_MAX_FLASH_BANKS             1               /* max number of memory banks           */
 #define CONFIG_SYS_MAX_FLASH_SECT              128             /* max number of sectors on one chip    */
index a5a873ba3cff12b75bb2ebbe79f87f426958c3ab..642c5753bbbdb8dce68a86e8d2199d1bfb8480dd 100644 (file)
@@ -175,6 +175,9 @@ unsigned char zipitz2_spi_read(void);
 
 #define        CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * NOR FLASH
  */
index c8aa0461f6aaa6a82806418b8dbde7ad689b4299..c33ca2de918e8d20670bd0711aeec9c76c572d4c 100644 (file)
 
 #undef CONFIG_SYS_SKIP_DRAM_SCRUB
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * NAND Flash