Merge git://git.denx.de/u-boot-fsl-qoriq

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6698c0467d7c0240f2711b14457b2a7088668367..a90ee0afd7722c23f276de3a5a00c9ff54269ba8 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -260,8 +260,8 @@ static void erratum_rcw_src(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 static void erratum_a009203(void)
 {
-       u8 __iomem *ptr;
 #ifdef CONFIG_SYS_I2C
+       u8 __iomem *ptr;
 #ifdef I2C1_BASE_ADDR
        ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
 
@@ -297,7 +297,9 @@ void bypass_smmu(void)
 void fsl_lsch3_early_init_f(void)
 {
        erratum_rcw_src();
+#ifdef CONFIG_FSL_IFC
        init_early_memctl_regs();       /* tighten IFC timing */
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
        erratum_a009203();
 #endif
@@ -323,11 +325,14 @@ int sata_init(void)
 {
        struct ccsr_ahci __iomem *ccsr_ahci;
 
+#ifdef CONFIG_SYS_SATA2
        ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
        out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
+#endif
 
+#ifdef CONFIG_SYS_SATA1
        ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
@@ -335,6 +340,7 @@ int sata_init(void)
 
        ahci_init((void __iomem *)CONFIG_SYS_SATA1);
        scsi_scan(false);
+#endif
 
        return 0;
 }

diff --git a/arch/arm/dts/fsl-ls2081a-rdb.dts b/arch/arm/dts/fsl-ls2081a-rdb.dts
index 6489362fc0ca8f446f34bdd9d91e39b2a7f347ac..aa4aa68c9c3d11075d94d25a3502502379f4b00d 100644 (file)
--- a/arch/arm/dts/fsl-ls2081a-rdb.dts
+++ b/arch/arm/dts/fsl-ls2081a-rdb.dts
@@ -41,7 +41,7 @@
        bus-num = <0>;
        status = "okay";
 
-       qflash0: n25q512a@0 {
+       qflash0: s25fs512s@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "spi-flash";
@@ -49,7 +49,7 @@
                reg = <0>;
        };
 
-       qflash1: n25q512a@1 {
+       qflash1: s25fs512s@1 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "spi-flash";

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index a0dac86babb7b9b02d62bb11f36d7293667f92fa..4d7992465a44537c44d4a05a7afd214a25ac21ef 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -106,6 +106,7 @@ static struct mm_region early_map[] = {
        { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
          CONFIG_SYS_FSL_QSPI_SIZE1,
          PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
+#ifdef CONFIG_FSL_IFC
        /* For IFC Region #1, only the first 4MB is cache-enabled */
        { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
          CONFIG_SYS_FSL_IFC_SIZE1_1,
@@ -120,6 +121,7 @@ static struct mm_region early_map[] = {
          CONFIG_SYS_FSL_IFC_SIZE1,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#endif
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -129,11 +131,13 @@ static struct mm_region early_map[] = {
 #endif
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
+#ifdef CONFIG_FSL_IFC
        /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
        { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
          CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#endif
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
          CONFIG_SYS_FSL_DCSR_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -163,10 +167,12 @@ static struct mm_region early_map[] = {
          CONFIG_SYS_FSL_QSPI_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#ifdef CONFIG_FSL_IFC
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
          CONFIG_SYS_FSL_IFC_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#endif
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -211,11 +217,13 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#ifdef CONFIG_FSL_IFC
        { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
          CONFIG_SYS_FSL_IFC_SIZE2,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#endif
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
          CONFIG_SYS_FSL_DCSR_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -310,10 +318,12 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#ifdef CONFIG_FSL_IFC
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
          CONFIG_SYS_FSL_IFC_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#endif
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
          PTE_BLOCK_MEMTYPE(MT_NORMAL) |

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 666562d106b178a16acc1499470f5eb38bd3b72d..827bfad521d47414ff8236bdeb894f4f9ec36411 100644 (file)
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -251,6 +251,8 @@ int misc_init_r(void)
        char *env_hwconfig;
        u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
        u32 val;
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u32 svr = gur_in32(&gur->svr);
 
        val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
 
@@ -278,6 +280,16 @@ int misc_init_r(void)
 
        if (adjust_vdd(0))
                printf("Warning: Adjusting core voltage failed.\n");
+       /*
+        * Default value of board env is based on filename which is
+        * ls2080ardb. Modify board env for other supported SoCs
+        */
+       if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
+           (SVR_SOC_VER(svr) == SVR_LS2048A))
+               env_set("board", "ls2088ardb");
+       else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
+           (SVR_SOC_VER(svr) == SVR_LS2041A))
+               env_set("board", "ls2081ardb");
 
        return 0;
 }

diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index efdaaa3d69883d0a51c2efdbb59289508af3e6ba..f6ea06bfb04bc9eb392f1fce505f2110ea6705c6 100644 (file)
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -3,7 +3,6 @@ CONFIG_TARGET_LS1043ARDB=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y

diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 600990ea608c03b4727b41a26df92388009bf4ae..1d7ed3b23a01cdbee3d3b2303b9e4a06afc5c762 100644 (file)
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1046ARDB=y
 CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_FSL_LS_PPA=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y

diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 9e6c2f5dfcf62e8b06935aa9ae3c40a734f9571d..3dae20103da64a95d5ec230265fd915b5b88b36d 100644 (file)
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -130,19 +130,28 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
        u32 iommu_map[4];
        int nodeoffset;
        int lenp;
+       uint svr;
+       char *compat = NULL;
 
        /* find pci controller node */
        nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
                                                   pcie->dbi_res.start);
        if (nodeoffset < 0) {
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
-               nodeoffset = fdt_node_offset_by_compat_reg(blob,
-                               CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
+               svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+               if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+                   svr == SVR_LS2048A || svr == SVR_LS2044A ||
+                   svr == SVR_LS2081A || svr == SVR_LS2041A)
+                       compat = "fsl,ls2088a-pcie";
+               else
+                       compat = CONFIG_FSL_PCIE_COMPAT;
+
+               if (compat)
+                       nodeoffset = fdt_node_offset_by_compat_reg(blob,
+                                               compat, pcie->dbi_res.start);
+#endif
                if (nodeoffset < 0)
                        return;
-#else
-               return;
-#endif
        }
 
        /* get phandle to iommu controller */

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 002830c27e48f91aa5f39e04c4f0b95d9be3aa1d..1f9efffa5627ee877f5373d683b024fa6a5853ed 100644 (file)
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -22,7 +22,7 @@
 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
 #define SPL_NO_MMC
 #endif
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
 #define SPL_NO_IFC
 #endif
 

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 145b2856850c48ca6bc2d6b70c33cc87494376a4..9e9979e1c7fc1259fa208fc923ca31866061288d 100644 (file)
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -18,7 +18,6 @@
 #define CONFIG_QIXIS_I2C_ACCESS
 #endif
 #define CONFIG_SYS_I2C_EARLY_INIT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
 #endif
 
 #define I2C_MUX_CH_VOL_MONITOR         0xa
@@ -289,19 +288,15 @@ unsigned long get_board_sys_clk(void);
 /* SPI */
 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
-#ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_DSPI
 #define CONFIG_SPI_FLASH_STMICRO
 #endif
 #ifdef CONFIG_FSL_QSPI
-#ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SPI_FLASH_STMICRO
-#else
 #define CONFIG_SPI_FLASH_SPANSION
 #endif
 #define FSL_QSPI_FLASH_SIZE            SZ_64M  /* 64MB */
 #define FSL_QSPI_FLASH_NUM             2
 #endif
-#endif
 
 /*
  * RTC configuration
@@ -392,6 +387,7 @@ unsigned long get_board_sys_clk(void);
        "load_addr=0xa0000000\0"                \
        "kernel_size=0x2800000\0"               \
        "console=ttyAMA0,38400n8\0"             \
+       "mcmemsize=0x70000000\0"                \
        MC_INIT_CMD                             \
        BOOTENV                                 \
        "boot_scripts=ls2088ardb_boot.scr\0"    \

diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index cd3eb47da4a2de108f41411b98a8328d5fa2015a..59bfc14df68565788bd0eb19ac33e268774a52ab 100644 (file)
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -156,7 +156,7 @@
 #elif defined(CONFIG_MPC85xx)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
-#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A)
+#elif defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR        0
 #endif