[PPC440SPe] PCIe environment settings for Katmai and Yucca

- 'pciconfighost' is set by default in order to be able to scan bridges
behind the primary host/PCIe

- 'pciscandelay' env variable is recognized to allow for user-controlled
delay before the PCIe bus enumeration; some peripheral devices require a
significant delay before they can be scanned (e.g. LSI8408E); without the
delay they are not detected

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>

diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index a9ae4a373923b41caf4eaf83916f94004679f6b4..afd60ece6247fda08de2000829ce81255926c2f4 100644 (file)
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -396,6 +396,8 @@ void pcie_setup_hoses(int busno)
 {
        struct pci_controller *hose;
        int i, bus;
+       char *env;
+       unsigned int delay;
 
        /*
         * assume we're called after the PCIX hose is initialized, which takes
@@ -439,6 +441,16 @@ void pcie_setup_hoses(int busno)
                 */
 #else
                ppc440spe_setup_pcie_rootpoint(hose, i);
+
+               env = getenv ("pciscandelay");
+               if (env != NULL) {
+                       delay = simple_strtoul (env, NULL, 10);
+                       if (delay > 5)
+                               printf ("Warning, expect noticable delay before PCIe"
+                                       "scan due to 'pciscandelay' value!\n");
+                       mdelay (delay * 1000);
+               }
+
                /*
                 * Config access can only go down stream
                 */

diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 252e4fe07a61e49525180f45b40ff313473942c0..397b01873f4bc84b48ecbd57e31aab8617a2c476 100644 (file)
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -850,6 +850,8 @@ void pcie_setup_hoses(int busno)
 {
        struct pci_controller *hose;
        int i, bus;
+       char *env;
+       unsigned int delay;
 
        /*
         * assume we're called after the PCIX hose is initialized, which takes
@@ -895,6 +897,16 @@ void pcie_setup_hoses(int busno)
                 */
 #else
                ppc440spe_setup_pcie_rootpoint(hose, i);
+
+               env = getenv ("pciscandelay");
+               if (env != NULL) {
+                       delay = simple_strtoul (env, NULL, 10);
+                       if (delay > 5)
+                               printf ("Warning, expect noticable delay before PCIe"
+                                       "scan due to 'pciscandelay' value!\n");
+                       mdelay (delay * 1000);
+               }
+
                /*
                 * Config access can only go down stream
                 */

diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 7834e39084698c74d69e73db464db6fe90dc921a..7908e5a4743b2a23bbe84fc735d4d97bc7588114 100644 (file)
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -201,6 +201,7 @@
                "setenv filesize;saveenv\0"                             \
        "upd=run load;run update\0"                                     \
        "kozio=bootm ffc60000\0"                                        \
+       "pciconfighost=1\0"                                             \
        ""
 #define CONFIG_BOOTCOMMAND     "run flash_self"
 
@@ -322,7 +323,7 @@
 #define CONFIG_PCI                     /* include pci support          */
 #define CONFIG_PCI_PNP         1       /* do pci plug-and-play         */
 #define CONFIG_PCI_SCAN_SHOW   1       /* show pci devices on startup  */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /* Board-specific PCI */
 #define CFG_PCI_TARGET_INIT            /* let board init pci target    */

diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 323535aa9fc1815d88cbac0412fed07f5962fc8d..74033b4aef43af04f910ca0eae339e397b275063 100644 (file)
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -182,6 +182,7 @@
                "cp.b ${fileaddr} FFFB0000 ${filesize};"                \
                "setenv filesize;saveenv\0"                             \
        "upd=run load;run update\0"                                     \
+       "pciconfighost=1\0"                                             \
        ""
 #define CONFIG_BOOTCOMMAND     "run flash_self"
 
@@ -297,7 +298,7 @@
 #define CONFIG_PCI                     /* include pci support          */
 #define CONFIG_PCI_PNP         1       /* do pci plug-and-play         */
 #define CONFIG_PCI_SCAN_SHOW   1       /* show pci devices on startup  */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /* Board-specific PCI */
 #define CFG_PCI_TARGET_INIT            /* let board init pci target    */