AP325RXA is SH7723's reference board.
This has SCIF, NOR Flash, Ethernet, USB host, LCDC, SD Host, Camera and other.
In this patch, support SCIF, NOR Flash, and Ethernet.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
R2DPlus SH7751R
SH7763RDP SH7763
RSK7203 SH7203
+ AP325RXA SH7723
Mark Jonas <mark.jonas@de.bosch.com>
r2dplus \
sh7763rdp \
sh7785lcr \
+ ap325rxa \
"
LIST_sh=" \
+ ${LIST_sh2} \
${LIST_sh3} \
${LIST_sh4} \
"
@echo "#define CONFIG_SH7785LCR 1" >> include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr
+ap325rxa_config : unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
+ @$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa
+
#========================================================================
# SPARC
#========================================================================
--- /dev/null
+#########################################################################
+#
+# Copyright (C) 2008 Renesas Solutions Corp.
+# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+#
+# board/ap325rxa/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := ap325rxa.o cpld-ap325rxa.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+/* PRI control register */
+#define PRPRICR5 0xFF800048 /* LMB */
+#define PRPRICR5_D 0x2a
+
+/* FPGA control */
+#define FPGA_NAND_CTL 0xB410020C
+#define FPGA_NAND_RST 0x0008
+#define FPGA_NAND_INIT 0x0000
+#define FPGA_NAND_RST_WAIT 10000
+
+/* I/O port data */
+#define PACR_D 0x0000
+#define PBCR_D 0x0000
+#define PCCR_D 0x1000
+#define PDCR_D 0x0000
+#define PECR_D 0x0410
+#define PFCR_D 0xffff
+#define PGCR_D 0x0000
+#define PHCR_D 0x5011
+#define PJCR_D 0x4400
+#define PKCR_D 0x7c00
+#define PLCR_D 0x0000
+#define PMCR_D 0x0000
+#define PNCR_D 0x0000
+#define PQCR_D 0x0000
+#define PRCR_D 0x0000
+#define PSCR_D 0x0000
+#define PTCR_D 0x0010
+#define PUCR_D 0x0fff
+#define PVCR_D 0xffff
+#define PWCR_D 0x0000
+#define PXCR_D 0x7500
+#define PYCR_D 0x0000
+#define PZCR_D 0x5540
+
+/* Pin Function Controler data */
+#define PSELA_D 0x1410
+#define PSELB_D 0x0140
+#define PSELC_D 0x0000
+#define PSELD_D 0x0400
+
+/* I/O Buffer Hi-Z data */
+#define HIZCRA_D 0x0000
+#define HIZCRB_D 0x1000
+#define HIZCRC_D 0x0000
+#define HIZCRD_D 0x0000
+
+/* Module select reg data */
+#define MSELCRA_D 0x0014
+#define MSELCRB_D 0x0018
+
+/* Module Stop reg Data */
+#define MSTPCR2_D 0xFFD9F280
+
+/* CPLD loader */
+extern void init_cpld(void);
+
+int checkboard(void)
+{
+ puts("BOARD: AP325RXA\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Pin Function Controler Init */
+ outw(PSELA_D, PSELA);
+ outw(PSELB_D, PSELB);
+ outw(PSELC_D, PSELC);
+ outw(PSELD_D, PSELD);
+
+ /* I/O Buffer Hi-Z Init */
+ outw(HIZCRA_D, HIZCRA);
+ outw(HIZCRB_D, HIZCRB);
+ outw(HIZCRC_D, HIZCRC);
+ outw(HIZCRD_D, HIZCRD);
+
+ /* Module select reg Init */
+ outw(MSELCRA_D, MSELCRA);
+ outw(MSELCRB_D, MSELCRB);
+
+ /* Module Stop reg Init */
+ outl(MSTPCR2_D, MSTPCR2);
+
+ /* I/O ports */
+ outw(PACR_D, PACR);
+ outw(PBCR_D, PBCR);
+ outw(PCCR_D, PCCR);
+ outw(PDCR_D, PDCR);
+ outw(PECR_D, PECR);
+ outw(PFCR_D, PFCR);
+ outw(PGCR_D, PGCR);
+ outw(PHCR_D, PHCR);
+ outw(PJCR_D, PJCR);
+ outw(PKCR_D, PKCR);
+ outw(PLCR_D, PLCR);
+ outw(PMCR_D, PMCR);
+ outw(PNCR_D, PNCR);
+ outw(PQCR_D, PQCR);
+ outw(PRCR_D, PRCR);
+ outw(PSCR_D, PSCR);
+ outw(PTCR_D, PTCR);
+ outw(PUCR_D, PUCR);
+ outw(PVCR_D, PVCR);
+ outw(PWCR_D, PWCR);
+ outw(PXCR_D, PXCR);
+ outw(PYCR_D, PYCR);
+ outw(PZCR_D, PZCR);
+
+ /* PRI control register Init */
+ outl(PRPRICR5_D, PRPRICR5);
+
+ /* cpld init */
+ init_cpld();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+void ide_set_reset(int idereset)
+{
+ outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
+ udelay(FPGA_NAND_RST_WAIT);
+ outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
+}
--- /dev/null
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
--- /dev/null
+/***************************************************************
+ * Project:
+ * CPLD SlaveSerial Configuration via embedded microprocessor.
+ *
+ * Copyright info:
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it as you like.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Description:
+ *
+ * This is the main source file that will allow a microprocessor
+ * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II,
+ * and Spartan-II devices via the SlaveSerial Configuration Mode.
+ * This code is discussed in Xilinx Application Note, XAPP502.
+ *
+ * History:
+ * 3-October-2001 MN/MP - Created
+ * 20-August-2008 Renesas Solutions - Modified to SH7723
+ ****************************************************************/
+
+#include <common.h>
+
+/* Serial */
+#define SCIF_BASE 0xffe00000 /* SCIF0 */
+#define SCSMR (vu_short *)(SCIF_BASE + 0x00)
+#define SCBRR (vu_char *)(SCIF_BASE + 0x04)
+#define SCSCR (vu_short *)(SCIF_BASE + 0x08)
+#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C)
+#define SC_SR (vu_short *)(SCIF_BASE + 0x10)
+#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
+#define RFCR (vu_long *)0xFE400020
+
+#define SCSCR_INIT 0x0038
+#define SCSCR_CLR 0x0000
+#define SCFCR_INIT 0x0006
+#define SCSMR_INIT 0x0080
+#define RFCR_CLR 0xA400
+#define SCI_TD_E 0x0020
+#define SCI_TDRE_CLEAR 0x00df
+
+#define BPS_SETTING_VALUE 1 /* 12.5MHz */
+#define WAIT_RFCR_COUNTER 500
+
+/* CPLD data size */
+#define CPLD_DATA_SIZE 169216
+
+/* out */
+#define CPLD_PFC_ADR ((vu_short *)0xA4050112)
+
+#define CPLD_PROG_ADR ((vu_char *)0xA4050132)
+#define CPLD_PROG_DAT 0x80
+
+/* in */
+#define CPLD_INIT_ADR ((vu_char *)0xA4050132)
+#define CPLD_INIT_DAT 0x40
+#define CPLD_DONE_ADR ((vu_char *)0xA4050132)
+#define CPLD_DONE_DAT 0x20
+
+#define HIZCRB ((vu_short *)0xA405015A)
+
+/* data */
+#define CPLD_NOMAL_START 0xA0A80000
+#define CPLD_SAFE_START 0xA0AC0000
+#define MODE_SW (vu_char *)0xA405012A
+
+static void init_cpld_loader(void)
+{
+
+ *SCSCR = SCSCR_CLR;
+ *SCFCR = SCFCR_INIT;
+ *SCSMR = SCSMR_INIT;
+
+ *SCBRR = BPS_SETTING_VALUE;
+
+ *RFCR = RFCR_CLR; /* Refresh counter clear */
+
+ while (*RFCR < WAIT_RFCR_COUNTER)
+ ;
+
+ *SCFCR = 0x0; /* RTRG=00, TTRG=00 */
+ /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */
+ *SCSCR = SCSCR_INIT;
+}
+
+static int check_write_ready(void)
+{
+ u16 status = *SC_SR;
+ return status & SCI_TD_E;
+}
+
+static void write_cpld_data(char ch)
+{
+ while (!check_write_ready())
+ ;
+
+ *SC_TDR = ch;
+ *SC_SR;
+ *SC_SR = SCI_TDRE_CLEAR;
+}
+
+static int delay(void)
+{
+ int i;
+ int c = 0;
+ for (i = 0; i < 200; i++) {
+ c = *(volatile int *)0xa0000000;
+ }
+ return c;
+}
+
+/***********************************************************************
+ *
+ * Function: slave_serial
+ *
+ * Description: Initiates SlaveSerial Configuration.
+ * Calls ShiftDataOut() to output serial data
+ *
+ ***********************************************************************/
+static void slave_serial(void)
+{
+ int i;
+ unsigned char *flash;
+
+ *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
+ delay();
+
+ /*
+ * Toggle Program Pin by Toggling Program_OE bit
+ * This is accomplished by writing to the Program Register in the CPLD
+ *
+ * NOTE: The Program_OE bit should be driven high to bring the Virtex
+ * Program Pin low. Likewise, it should be driven low
+ * to bring the Virtex Program Pin to High-Z
+ */
+
+ *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */
+ delay();
+
+ /*
+ * Bring Program High-Z
+ * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z
+ */
+
+ /* Program_OE bit Low brings the Virtex Program Pin to High Z: */
+ *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
+
+ while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0)
+ delay();
+
+ /* Begin Slave-Serial Configuration */
+ flash = (unsigned char *)CPLD_NOMAL_START;
+
+ for (i = 0; i < CPLD_DATA_SIZE; i++)
+ write_cpld_data(*flash++);
+}
+
+/***********************************************************************
+ *
+ * Function: check_done_bit
+ *
+ * Description: This function takes monitors the CPLD Input Register
+ * by checking the status of the DONE bit in that Register.
+ * By doing so, it monitors the Xilinx Virtex device's DONE
+ * Pin to see if configuration bitstream has been properly
+ * loaded
+ *
+ ***********************************************************************/
+static void check_done_bit(void)
+{
+ while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT))
+ ;
+}
+
+/***********************************************************************
+ *
+ * Function: init_cpld
+ *
+ * Description: Begins Slave Serial configuration of Xilinx FPGA
+ *
+ ***********************************************************************/
+void init_cpld(void)
+{
+ /* Init serial device */
+ init_cpld_loader();
+
+ if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */
+ return;
+
+ *HIZCRB = 0x0000;
+ *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */
+
+ /* write CPLD data from NOR flash to device */
+ slave_serial();
+
+ /*
+ * Monitor the DONE bit in the CPLD Input Register to see if
+ * configuration successful
+ */
+
+ check_done_bit();
+}
--- /dev/null
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/ap325rxa/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ mov.l DRVCRA_A, r1
+ mov.l DRVCRA_D, r0
+ mov.w r0, @r1
+
+ mov.l DRVCRB_A, r1
+ mov.l DRVCRB_D, r0
+ mov.w r0, @r1
+
+ mov.l RWTCSR_A, r1
+ mov.l RWTCSR_D1, r0
+ mov.w r0, @r1
+
+ mov.l RWTCNT_A, r1
+ mov.l RWTCNT_D, r0
+ mov.w r0, @r1
+
+ mov.l RWTCSR_A, r1
+ mov.l RWTCSR_D2, r0
+ mov.w r0, @r1
+
+ mov.l FRQCR_A, r1
+ mov.l FRQCR_D, r0
+ mov.l r0, @r1
+
+ mov.l CMNCR_A, r1
+ mov.l CMNCR_D, r0
+ mov.l r0, @r1
+
+ mov.l CS0BCR_A ,r1
+ mov.l CS0BCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS4BCR_A ,r1
+ mov.l CS4BCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS5ABCR_A ,r1
+ mov.l CS5ABCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS5BBCR_A ,r1
+ mov.l CS5BBCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS6ABCR_A ,r1
+ mov.l CS6ABCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS6BBCR_A ,r1
+ mov.l CS6BBCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS0WCR_A ,r1
+ mov.l CS0WCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS4WCR_A ,r1
+ mov.l CS4WCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS5AWCR_A ,r1
+ mov.l CS5AWCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS5BWCR_A ,r1
+ mov.l CS5BWCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS6AWCR_A ,r1
+ mov.l CS6AWCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l CS6BWCR_A ,r1
+ mov.l CS6BWCR_D ,r0
+ mov.l r0, @r1
+
+ mov.l SBSC_SDCR_A, r1
+ mov.l SBSC_SDCR_D1, r0
+ mov.l r0, @r1
+
+ mov.l SBSC_SDWCR_A, r1
+ mov.l SBSC_SDWCR_D, r0
+ mov.l r0, @r1
+
+ mov.l SBSC_SDPCR_A, r1
+ mov.l SBSC_SDPCR_D, r0
+ mov.l r0, @r1
+
+ mov.l SBSC_RTCSR_A, r1
+ mov.l SBSC_RTCSR_D, r0
+ mov.l r0, @r1
+
+ mov.l SBSC_RTCNT_A, r1
+ mov.l SBSC_RTCNT_D, r0
+ mov.l r0, @r1
+
+ mov.l SBSC_RTCOR_A, r1
+ mov.l SBSC_RTCOR_D, r0
+ mov.l r0, @r1
+
+ mov.l SBSC_SDMR3_A1, r1
+ mov.l SBSC_SDMR3_D, r0
+ mov.b r0, @r1
+
+ mov.l SBSC_SDMR3_A2, r1
+ mov.l SBSC_SDMR3_D, r0
+ mov.b r0, @r1
+
+ mov.l SLEEP_CNT, r1
+2: tst r1, r1
+ nop
+ bf/s 2b
+ dt r1
+
+ mov.l SBSC_SDMR3_A3, r1
+ mov.l SBSC_SDMR3_D, r0
+ mov.b r0, @r1
+
+ mov.l SBSC_SDCR_A, r1
+ mov.l SBSC_SDCR_D2, r0
+ mov.l r0, @r1
+
+ mov.l CCR_A, r1
+ mov.l CCR_D, r0
+ mov.l r0, @r1
+
+ ! BL bit off (init = ON) (?!?)
+
+ stc sr, r0 ! BL bit off(init=ON)
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ mov #0, r0
+
+ .align 2
+
+DRVCRA_A: .long DRVCRA
+DRVCRB_A: .long DRVCRB
+DRVCRA_D: .long 0x4555
+DRVCRB_D: .long 0x0005
+
+RWTCSR_A: .long RWTCSR
+RWTCNT_A: .long RWTCNT
+FRQCR_A: .long FRQCR
+RWTCSR_D1: .long 0xa507
+RWTCSR_D2: .long 0xa504
+RWTCNT_D: .long 0x5a00
+FRQCR_D: .long 0x0b04474a
+
+SBSC_SDCR_A: .long SBSC_SDCR
+SBSC_SDWCR_A: .long SBSC_SDWCR
+SBSC_SDPCR_A: .long SBSC_SDPCR
+SBSC_RTCSR_A: .long SBSC_RTCSR
+SBSC_RTCNT_A: .long SBSC_RTCNT
+SBSC_RTCOR_A: .long SBSC_RTCOR
+SBSC_SDMR3_A1: .long 0xfe510000
+SBSC_SDMR3_A2: .long 0xfe500242
+SBSC_SDMR3_A3: .long 0xfe5c0042
+
+SBSC_SDCR_D1: .long 0x92810112
+SBSC_SDCR_D2: .long 0x92810912
+SBSC_SDWCR_D: .long 0x05162482
+SBSC_SDPCR_D: .long 0x00300087
+SBSC_RTCSR_D: .long 0xa55a0212
+SBSC_RTCNT_D: .long 0xa55a0000
+SBSC_RTCOR_D: .long 0xa55a0040
+SBSC_SDMR3_D: .long 0x00
+
+CMNCR_A: .long CMNCR
+CS0BCR_A: .long CS0BCR
+CS4BCR_A: .long CS4BCR
+CS5ABCR_A: .long CS5ABCR
+CS5BBCR_A: .long CS5BBCR
+CS6ABCR_A: .long CS6ABCR
+CS6BBCR_A: .long CS6BBCR
+CS0WCR_A: .long CS0WCR
+CS4WCR_A: .long CS4WCR
+CS5AWCR_A: .long CS5AWCR
+CS5BWCR_A: .long CS5BWCR
+CS6AWCR_A: .long CS6AWCR
+CS6BWCR_A: .long CS6BWCR
+
+CMNCR_D: .long 0x00000013
+CS0BCR_D: .long 0x24920400
+CS4BCR_D: .long 0x24920400
+CS5ABCR_D: .long 0x24920400
+CS5BBCR_D: .long 0x7fff0600
+CS6ABCR_D: .long 0x24920400
+CS6BBCR_D: .long 0x24920600
+CS0WCR_D: .long 0x00000480
+CS4WCR_D: .long 0x00000480
+CS5AWCR_D: .long 0x00000380
+CS5BWCR_D: .long 0x00000600
+CS6AWCR_D: .long 0x00000300
+CS6BWCR_D: .long 0x00000540
+
+CCR_A: .long 0xff00001c
+CCR_D: .long 0x0000090d
+
+SLEEP_CNT: .long 0x00000800
+SR_MASK_D: .long 0xEFFFFF0F
--- /dev/null
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x88000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x88000000 + (128*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
+
--- /dev/null
+/*
+ * Configuation settings for the Renesas Solutions AP-325RXA board
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AP325RXA_H
+#define __AP325RXA_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7723 1
+#define CONFIG_AP325RXA 1
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC2,38400"
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9118 */
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_32_BIT 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xB6080000
+
+/* MEMORY */
+#define AP325RXA_SDRAM_BASE (0x88000000)
+#define AP325RXA_FLASH_BASE_1 (0xA0000000)
+#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
+
+/* undef to save memory */
+#define CFG_LONGHELP
+/* Monitor Command Prompt */
+#define CFG_PROMPT "=> "
+/* Buffer size for input from the Console */
+#define CFG_CBSIZE 256
+/* Buffer size for Console output */
+#define CFG_PBSIZE 256
+/* max args accepted for monitor commands */
+#define CFG_MAXARGS 16
+/* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 38400 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
+#define CONFIG_CONS_SCIF5 1
+
+/* Suppress display of console information at boot */
+#undef CFG_CONSOLE_INFO_QUIET
+#undef CFG_CONSOLE_OVERWRITE_ROUTINE
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+#define CFG_MEMTEST_START (AP325RXA_SDRAM_BASE)
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Enable alternate, more extensive, memory test */
+#undef CFG_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef CFG_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef CFG_LOADS_BAUD_CHANGE
+
+#define CFG_SDRAM_BASE (AP325RXA_SDRAM_BASE)
+/* maybe more, but if so u-boot doesn't know about it... */
+#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
+/* default load address for scripts ?!? */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024)
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CFG_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
+/* Monitor size */
+#define CFG_MONITOR_LEN (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+/* Physical start address of Flash memory */
+#define CFG_FLASH_BASE (AP325RXA_FLASH_BASE_1)
+/* Max number of sectors on each Flash chip */
+#define CFG_MAX_FLASH_SECT 512
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET 1
+#define CFG_PIO_MODE 1
+#define CFG_IDE_MAXBUS 1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE 1
+#define CFG_ATA_BASE_ADDR 0xB4180000
+#define CFG_ATA_STRIDE 2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET 0x200 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0x200 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x210 /* alternate register offset */
+
+/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
+
+/* Timeout for Flash erase operations (in ms) */
+#define CFG_FLASH_ERASE_TOUT (3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CFG_FLASH_WRITE_TOUT (3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CFG_FLASH_LOCK_TOUT (3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
+
+/*
+ * Use hardware flash sectors protection instead
+ * of U-Boot software protection
+ */
+#undef CFG_FLASH_PROTECTION
+#undef CFG_DIRECT_FLASH_TFTP
+
+/* ENV setting */
+#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_ENV_SECT_SIZE (128 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+/* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif /* __AP325RXA_H */
projects / u-boot / commitdiff