]> git.sur5r.net Git - u-boot/commitdiff
nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
authorAnton Staaf <robotboy@chromium.org>
Mon, 17 Oct 2011 23:46:05 +0000 (16:46 -0700)
committerWolfgang Denk <wd@denx.de>
Sun, 23 Oct 2011 18:50:42 +0000 (20:50 +0200)
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Scott McNutt <smcnutt@psyent.com>
arch/nios2/include/asm/cache.h

index c78f34308b84a1d9acc69af447c75c399e96a764..2cc16e4a128f9b2a1c872971fca057f8677fe3a4 100644 (file)
 extern void flush_dcache (unsigned long start, unsigned long size);
 extern void flush_icache (unsigned long start, unsigned long size);
 
+/*
+ * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
+ * bytes.  If the board configuration has not specified one we default to the
+ * largest of these values for alignment of DMA buffers.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN      32
+#endif
+
 #endif /* __ASM_NIOS2_CACHE_H_ */