}
#endif
-void cpu_init_f (void)
+ulong cpu_init_f(void)
{
+ ulong flag = 0;
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
- gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+ flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
+ return flag;
}
/* Implement a dummy function for those platforms w/o SERDES */
DECLARE_GLOBAL_DATA_PTR;
-void cpu_init_f(void)
+ulong cpu_init_f(void)
{
#ifdef CONFIG_SYS_INIT_L2_ADDR
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
#endif
+
+ return 0;
}
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
void cpu_init_f (volatile immap_t *immr);
#endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx)
void cpu_init_f (void);
#endif
+#ifdef CONFIG_MPC85xx
+ulong cpu_init_f(void);
+#endif
int cpu_init_r (void);
#if defined(CONFIG_MPC8260)