The OpenRISC architecture is currently unmaintained, remove.
Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
T: git git://git.denx.de/u-boot-mmc.git
F: drivers/mmc/
-OPENRISC
-M: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-S: Maintained
-F: arch/openrisc/
-
PATMAN
M: Simon Glass <sjg@chromium.org>
S: Maintained
select DM
select CPU
-config OPENRISC
- bool "OpenRISC architecture"
-
config PPC
bool "PowerPC architecture"
select HAVE_PRIVATE_LIBGCC
source "arch/mips/Kconfig"
source "arch/nds32/Kconfig"
source "arch/nios2/Kconfig"
-source "arch/openrisc/Kconfig"
source "arch/powerpc/Kconfig"
source "arch/sandbox/Kconfig"
source "arch/sh/Kconfig"
+++ /dev/null
-menu "OpenRISC architecture"
- depends on OPENRISC
-
-config SYS_ARCH
- default "openrisc"
-
-choice
- prompt "Target select"
- optional
-
-config TARGET_OPENRISC_GENERIC
- bool "Support openrisc-generic"
-
-endchoice
-
-source "board/openrisc/openrisc-generic/Kconfig"
-
-endmenu
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-head-y := arch/openrisc/cpu/start.o
-
-libs-y += arch/openrisc/cpu/
-libs-y += arch/openrisc/lib/
+++ /dev/null
-#
-# (C) Copyright 2011
-# Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := or1k-elf-
-endif
-
-# r10 used for global object pointer, already set in OR32 GCC but just to be
-# clear
-PLATFORM_CPPFLAGS += -D__OR1K__ -ffixed-r10
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
+++ /dev/null
-#
-# (C) Copyright 2011
-# Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cache.o cpu.o exceptions.o interrupts.o
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/system.h>
-
-void flush_dcache_range(unsigned long addr, unsigned long stop)
-{
- ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
-
- while (addr < stop) {
- mtspr(SPR_DCBFR, addr);
- addr += block_size;
- }
-}
-
-void invalidate_dcache_range(unsigned long addr, unsigned long stop)
-{
- ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
-
- while (addr < stop) {
- mtspr(SPR_DCBIR, addr);
- addr += block_size;
- }
-}
-
-static void invalidate_icache_range(unsigned long addr, unsigned long stop)
-{
- ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;
-
- while (addr < stop) {
- mtspr(SPR_ICBIR, addr);
- addr += block_size;
- }
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
- flush_dcache_range(addr, addr + size);
- invalidate_icache_range(addr, addr + size);
-}
-
-int icache_status(void)
-{
- return mfspr(SPR_SR) & SPR_SR_ICE;
-}
-
-int checkicache(void)
-{
- unsigned long iccfgr;
- unsigned long cache_set_size;
- unsigned long cache_ways;
- unsigned long cache_block_size;
-
- iccfgr = mfspr(SPR_ICCFGR);
- cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
- cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
- cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
-
- return cache_set_size * cache_ways * cache_block_size;
-}
-
-int dcache_status(void)
-{
- return mfspr(SPR_SR) & SPR_SR_DCE;
-}
-
-int checkdcache(void)
-{
- unsigned long dccfgr;
- unsigned long cache_set_size;
- unsigned long cache_ways;
- unsigned long cache_block_size;
-
- dccfgr = mfspr(SPR_DCCFGR);
- cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
- cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
- cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
-
- return cache_set_size * cache_ways * cache_block_size;
-}
-
-void dcache_enable(void)
-{
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
-}
-
-void dcache_disable(void)
-{
- mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
-}
-
-void icache_enable(void)
-{
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
-}
-
-void icache_disable(void)
-{
- mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
-}
-
-int cache_init(void)
-{
- if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
- icache_disable();
- invalidate_icache_range(0, checkicache());
- icache_enable();
- }
-
- if (mfspr(SPR_UPR) & SPR_UPR_DCP) {
- dcache_disable();
- invalidate_dcache_range(0, checkdcache());
- dcache_enable();
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/openrisc_exc.h>
-
-static volatile int illegal_instruction;
-
-static void illegal_instruction_handler(void)
-{
- ulong *epcr = (ulong *)mfspr(SPR_EPCR_BASE);
-
- /* skip over the illegal instruction */
- mtspr(SPR_EPCR_BASE, (ulong)(++epcr));
- illegal_instruction = 1;
-}
-
-static void checkinstructions(void)
-{
- ulong ra = 1, rb = 1, rc;
-
- exception_install_handler(EXC_ILLEGAL_INSTR,
- illegal_instruction_handler);
-
- illegal_instruction = 0;
- asm volatile("l.mul %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
- printf(" Hardware multiplier: %s\n",
- illegal_instruction ? "no" : "yes");
-
- illegal_instruction = 0;
- asm volatile("l.div %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
- printf(" Hardware divider: %s\n",
- illegal_instruction ? "no" : "yes");
-
- exception_free_handler(EXC_ILLEGAL_INSTR);
-}
-
-int checkcpu(void)
-{
- ulong upr = mfspr(SPR_UPR);
- ulong vr = mfspr(SPR_VR);
- ulong iccfgr = mfspr(SPR_ICCFGR);
- ulong dccfgr = mfspr(SPR_DCCFGR);
- ulong immucfgr = mfspr(SPR_IMMUCFGR);
- ulong dmmucfgr = mfspr(SPR_DMMUCFGR);
- ulong cpucfgr = mfspr(SPR_CPUCFGR);
- uint ver = (vr & SPR_VR_VER) >> 24;
- uint rev = vr & SPR_VR_REV;
- uint block_size;
- uint ways;
- uint sets;
-
- printf("CPU: OpenRISC-%x00 (rev %d) @ %d MHz\n",
- ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));
-
- if (upr & SPR_UPR_DCP) {
- block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
- ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
- printf(" D-Cache: %d bytes, %d bytes/line, %d way(s)\n",
- checkdcache(), block_size, ways);
- } else {
- printf(" D-Cache: no\n");
- }
-
- if (upr & SPR_UPR_ICP) {
- block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
- ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
- printf(" I-Cache: %d bytes, %d bytes/line, %d way(s)\n",
- checkicache(), block_size, ways);
- } else {
- printf(" I-Cache: no\n");
- }
-
- if (upr & SPR_UPR_DMP) {
- sets = 1 << ((dmmucfgr & SPR_DMMUCFGR_NTS) >> 2);
- ways = (dmmucfgr & SPR_DMMUCFGR_NTW) + 1;
- printf(" DMMU: %d sets, %d way(s)\n",
- sets, ways);
- } else {
- printf(" DMMU: no\n");
- }
-
- if (upr & SPR_UPR_IMP) {
- sets = 1 << ((immucfgr & SPR_IMMUCFGR_NTS) >> 2);
- ways = (immucfgr & SPR_IMMUCFGR_NTW) + 1;
- printf(" IMMU: %d sets, %d way(s)\n",
- sets, ways);
- } else {
- printf(" IMMU: no\n");
- }
-
- printf(" MAC unit: %s\n",
- (upr & SPR_UPR_MP) ? "yes" : "no");
- printf(" Debug unit: %s\n",
- (upr & SPR_UPR_DUP) ? "yes" : "no");
- printf(" Performance counters: %s\n",
- (upr & SPR_UPR_PCUP) ? "yes" : "no");
- printf(" Power management: %s\n",
- (upr & SPR_UPR_PMP) ? "yes" : "no");
- printf(" Interrupt controller: %s\n",
- (upr & SPR_UPR_PICP) ? "yes" : "no");
- printf(" Timer: %s\n",
- (upr & SPR_UPR_TTP) ? "yes" : "no");
- printf(" Custom unit(s): %s\n",
- (upr & SPR_UPR_CUP) ? "yes" : "no");
-
- printf(" Supported instructions:\n");
- printf(" ORBIS32: %s\n",
- (cpucfgr & SPR_CPUCFGR_OB32S) ? "yes" : "no");
- printf(" ORBIS64: %s\n",
- (cpucfgr & SPR_CPUCFGR_OB64S) ? "yes" : "no");
- printf(" ORFPX32: %s\n",
- (cpucfgr & SPR_CPUCFGR_OF32S) ? "yes" : "no");
- printf(" ORFPX64: %s\n",
- (cpucfgr & SPR_CPUCFGR_OF64S) ? "yes" : "no");
-
- checkinstructions();
-
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- disable_interrupts();
- return 0;
-}
-
-extern void __reset(void);
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- disable_interrupts();
- /* Code the jump to __reset here as the compiler is prone to
- emitting a bad jump instruction if the function is in flash */
- __asm__("l.movhi r1,hi(__reset); \
- l.ori r1,r1,lo(__reset); \
- l.jr r1");
- /* not reached, __reset does not return */
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stdio_dev.h>
-#include <asm/system.h>
-
-static const char * const excp_table[] = {
- "Unknown exception",
- "Reset",
- "Bus Error",
- "Data Page Fault",
- "Instruction Page Fault",
- "Tick Timer",
- "Alignment",
- "Illegal Instruction",
- "External Interrupt",
- "D-TLB Miss",
- "I-TLB Miss",
- "Range",
- "System Call",
- "Floating Point",
- "Trap",
-};
-
-static void (*handlers[32])(void);
-
-void exception_install_handler(int exception, void (*handler)(void))
-{
- if (exception < 0 || exception > 31)
- return;
-
- handlers[exception] = handler;
-}
-
-void exception_free_handler(int exception)
-{
- if (exception < 0 || exception > 31)
- return;
-
- handlers[exception] = 0;
-}
-
-static void exception_hang(int vect)
-{
- printf("Unhandled exception at 0x%x ", vect & 0xff00);
-
- vect = ((vect >> 8) & 0xff);
- if (vect < ARRAY_SIZE(excp_table))
- printf("(%s)\n", excp_table[vect]);
- else
- printf("(%s)\n", excp_table[0]);
-
- printf("EPCR: 0x%08lx\n", mfspr(SPR_EPCR_BASE));
- printf("EEAR: 0x%08lx\n", mfspr(SPR_EEAR_BASE));
- printf("ESR: 0x%08lx\n", mfspr(SPR_ESR_BASE));
- hang();
-}
-
-void exception_handler(int vect)
-{
- int exception = vect >> 8;
-
- if (handlers[exception])
- handlers[exception]();
- else
- exception_hang(vect);
-}
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/types.h>
-#include <asm/ptrace.h>
-#include <asm/system.h>
-#include <asm/openrisc_exc.h>
-
-struct irq_action {
- interrupt_handler_t *handler;
- void *arg;
- int count;
-};
-
-static struct irq_action handlers[32];
-
-void interrupt_handler(void)
-{
- int irq;
-
- while ((irq = ffs(mfspr(SPR_PICSR)))) {
- if (handlers[--irq].handler) {
- handlers[irq].handler(handlers[irq].arg);
- handlers[irq].count++;
- } else {
- /* disable the interrupt */
- mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1 << irq));
- printf("Unhandled interrupt: %d\n", irq);
- }
- /* clear the interrupt */
- mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1 << irq));
- }
-}
-
-int interrupt_init(void)
-{
- /* install handler for external interrupt exception */
- exception_install_handler(EXC_EXT_IRQ, interrupt_handler);
- /* Enable interrupts in supervisor register */
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
-
- return 0;
-}
-
-void enable_interrupts(void)
-{
- /* Set interrupt enable bit in supervisor register */
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
- /* Enable timer exception */
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
-}
-
-int disable_interrupts(void)
-{
- /* Clear interrupt enable bit in supervisor register */
- mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
- /* Disable timer exception */
- mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_TEE);
-
- return 0;
-}
-
-void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
-{
- if (irq < 0 || irq > 31)
- return;
-
- handlers[irq].handler = handler;
- handlers[irq].arg = arg;
-}
-
-void irq_free_handler(int irq)
-{
- if (irq < 0 || irq > 31)
- return;
-
- handlers[irq].handler = 0;
- handlers[irq].arg = 0;
-}
-
-#if defined(CONFIG_CMD_IRQ)
-int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
-
- printf("\nInterrupt-Information:\n\n");
- printf("Nr Routine Arg Count\n");
- printf("-----------------------------\n");
-
- for (i = 0; i < 32; i++) {
- if (handlers[i].handler) {
- printf("%02d %08lx %08lx %d\n",
- i,
- (ulong)handlers[i].handler,
- (ulong)handlers[i].arg,
- handlers[i].count);
- }
- }
- printf("\n");
-
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- * (C) Copyright 2014, Franck Jullien <franck.jullien@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm-offsets.h>
-#include <asm/spr-defs.h>
-
-#define EXCEPTION_STACK_SIZE (128+128)
-
-#define HANDLE_EXCEPTION \
- l.addi r1, r1, -EXCEPTION_STACK_SIZE ;\
- l.sw 0x00(r1), r2 ;\
- l.sw 0x1c(r1), r9 ;\
- l.movhi r2,hi(_exception_handler) ;\
- l.ori r2,r2,lo(_exception_handler) ;\
- l.jalr r2 ;\
- l.nop ;\
- l.lwz r9, 0x1c(r1) ;\
- l.addi r1, r1, EXCEPTION_STACK_SIZE ;\
- l.rfe ;\
- l.nop
-
- .section .vectors, "ax"
- .global __reset
-
- /* reset */
- .org 0x100
-__reset:
- /* there is no guarantee r0 is hardwired to zero, clear it here */
- l.andi r0, r0, 0
- /* reset stack and frame pointers */
- l.andi r1, r0, 0
- l.andi r2, r0, 0
-
- /* set supervisor mode */
- l.ori r3,r0,SPR_SR_SM
- l.mtspr r0,r3,SPR_SR
-
- l.jal _cur
- l.nop
-_cur:
- l.ori r8, r9, 0 /* Get _cur current address */
-
- l.movhi r3, hi(_cur)
- l.ori r3, r3, lo(_cur)
- l.sfeq r8, r3 /* If we are running at the linked address */
- l.bf _no_vector_reloc /* there is not need for relocation */
- l.sub r8, r8, r3
-
- l.mfspr r4, r0, SPR_CPUCFGR
- l.andi r4, r4, SPR_CPUCFGR_EVBARP /* Exception Vector Base Address Register present ? */
- l.sfnei r4,0
- l.bnf _reloc_vectors
- l.movhi r5, 0 /* Destination */
-
- l.mfspr r4, r0, SPR_EVBAR
- l.add r5, r5, r4
-
-_reloc_vectors:
- /* Relocate vectors*/
- l.movhi r5, 0 /* Destination */
- l.movhi r6, hi(__start) /* Length */
- l.ori r6, r6, lo(__start)
- l.ori r3, r8, 0
-
-.L_relocvectors:
- l.lwz r7, 0(r3)
- l.sw 0(r5), r7
- l.addi r5, r5, 4
- l.sfeq r5, r6
- l.bnf .L_relocvectors
- l.addi r3, r3, 4
-
-_no_vector_reloc:
-
- /* Relocate u-boot */
- l.movhi r3,hi(__start) /* source start offset */
- l.ori r3,r3,lo(__start)
- l.add r3,r8,r3
-
- l.movhi r4,hi(_stext) /* dest start address */
- l.ori r4,r4,lo(_stext)
- l.movhi r5,hi(__end) /* dest end address */
- l.ori r5,r5,lo(__end)
-
-.L_reloc:
- l.lwz r6,0(r3)
- l.sw 0(r4),r6
- l.addi r3,r3,4
- l.sfltu r4,r5
- l.bf .L_reloc
- l.addi r4,r4,4 /* delay slot */
-
- l.movhi r4,hi(_start)
- l.ori r4,r4,lo(_start)
- l.jr r4
- l.nop
-
- /* bus error */
- .org 0x200
- HANDLE_EXCEPTION
-
- /* data page fault */
- .org 0x300
- HANDLE_EXCEPTION
-
- /* instruction page fault */
- .org 0x400
- HANDLE_EXCEPTION
-
- /* tick timer */
- .org 0x500
- HANDLE_EXCEPTION
-
- /* alignment */
- .org 0x600
- HANDLE_EXCEPTION
-
- /* illegal instruction */
- .org 0x700
- HANDLE_EXCEPTION
-
- /* external interrupt */
- .org 0x800
- HANDLE_EXCEPTION
-
- /* D-TLB miss */
- .org 0x900
- HANDLE_EXCEPTION
-
- /* I-TLB miss */
- .org 0xa00
- HANDLE_EXCEPTION
-
- /* range */
- .org 0xb00
- HANDLE_EXCEPTION
-
- /* system call */
- .org 0xc00
- HANDLE_EXCEPTION
-
- /* floating point */
- .org 0xd00
- HANDLE_EXCEPTION
-
- /* trap */
- .org 0xe00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0xf00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1100
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1200
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1300
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1400
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1500
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1600
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1700
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1800
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1900
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1a00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1b00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1c00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1d00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1e00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1f00
- HANDLE_EXCEPTION
-
- /* Startup routine */
- .text
- .global _start
-_start:
- /* Init stack and frame pointers */
- l.movhi r1, hi(CONFIG_SYS_INIT_SP_ADDR)
- l.ori r1, r1, lo(CONFIG_SYS_INIT_SP_ADDR)
- l.or r2, r0, r1
-
- /* clear BSS segments */
- l.movhi r4, hi(_bss_start)
- l.ori r4, r4, lo(_bss_start)
- l.movhi r5, hi(_bss_end)
- l.ori r5, r5, lo(_bss_end)
-.L_clear_bss:
- l.sw 0(r4), r0
- l.sfltu r4,r5
- l.bf .L_clear_bss
- l.addi r4,r4,4
-
- /* Reset registers before jumping to board_init */
- l.andi r3, r0, 0
- l.andi r4, r0, 0
- l.andi r5, r0, 0
- l.andi r6, r0, 0
- l.andi r7, r0, 0
- l.andi r8, r0, 0
- l.andi r9, r0, 0
- l.andi r10, r0, 0
- l.andi r11, r0, 0
- l.andi r12, r0, 0
- l.andi r13, r0, 0
- l.andi r14, r0, 0
- l.andi r15, r0, 0
- l.andi r17, r0, 0
- l.andi r18, r0, 0
- l.andi r19, r0, 0
- l.andi r20, r0, 0
- l.andi r21, r0, 0
- l.andi r22, r0, 0
- l.andi r23, r0, 0
- l.andi r24, r0, 0
- l.andi r25, r0, 0
- l.andi r26, r0, 0
- l.andi r27, r0, 0
- l.andi r28, r0, 0
- l.andi r29, r0, 0
- l.andi r30, r0, 0
- l.andi r31, r0, 0
-
- l.j board_init
- l.nop
-
- .size _start, .-_start
-
-/*
- * Store state onto stack and call the real exception handler
- */
- .section .text
- .extern exception_handler
- .type _exception_handler,@function
-
-_exception_handler:
- /* Store state (r2 and r9 already saved)*/
- l.sw 0x04(r1), r3
- l.sw 0x08(r1), r4
- l.sw 0x0c(r1), r5
- l.sw 0x10(r1), r6
- l.sw 0x14(r1), r7
- l.sw 0x18(r1), r8
- l.sw 0x20(r1), r10
- l.sw 0x24(r1), r11
- l.sw 0x28(r1), r12
- l.sw 0x2c(r1), r13
- l.sw 0x30(r1), r14
- l.sw 0x34(r1), r15
- l.sw 0x38(r1), r16
- l.sw 0x3c(r1), r17
- l.sw 0x40(r1), r18
- l.sw 0x44(r1), r19
- l.sw 0x48(r1), r20
- l.sw 0x4c(r1), r21
- l.sw 0x50(r1), r22
- l.sw 0x54(r1), r23
- l.sw 0x58(r1), r24
- l.sw 0x5c(r1), r25
- l.sw 0x60(r1), r26
- l.sw 0x64(r1), r27
- l.sw 0x68(r1), r28
- l.sw 0x6c(r1), r29
- l.sw 0x70(r1), r30
- l.sw 0x74(r1), r31
-
- /* Save return address */
- l.or r14, r0, r9
- /* Call exception handler with the link address as argument */
- l.jal exception_handler
- l.or r3, r0, r14
- /* Load return address */
- l.or r9, r0, r14
-
- /* Restore state */
- l.lwz r2, 0x00(r1)
- l.lwz r3, 0x04(r1)
- l.lwz r4, 0x08(r1)
- l.lwz r5, 0x0c(r1)
- l.lwz r6, 0x10(r1)
- l.lwz r7, 0x14(r1)
- l.lwz r8, 0x18(r1)
- l.lwz r10, 0x20(r1)
- l.lwz r11, 0x24(r1)
- l.lwz r12, 0x28(r1)
- l.lwz r13, 0x2c(r1)
- l.lwz r14, 0x30(r1)
- l.lwz r15, 0x34(r1)
- l.lwz r16, 0x38(r1)
- l.lwz r17, 0x3c(r1)
- l.lwz r18, 0x40(r1)
- l.lwz r19, 0x44(r1)
- l.lwz r20, 0x48(r1)
- l.lwz r21, 0x4c(r1)
- l.lwz r22, 0x50(r1)
- l.lwz r23, 0x54(r1)
- l.lwz r24, 0x58(r1)
- l.lwz r25, 0x5c(r1)
- l.lwz r26, 0x60(r1)
- l.lwz r27, 0x64(r1)
- l.lwz r28, 0x68(r1)
- l.lwz r29, 0x6c(r1)
- l.lwz r30, 0x70(r1)
- l.lwz r31, 0x74(r1)
- l.jr r9
- l.nop
+++ /dev/null
-#include <config.h>
-OUTPUT_ARCH(or1k)
-__DYNAMIC = 0;
-
-MEMORY
-{
- vectors : ORIGIN = 0, LENGTH = 0x2000
- ram : ORIGIN = CONFIG_SYS_MONITOR_BASE,
- LENGTH = CONFIG_SYS_MONITOR_LEN
-}
-
-SECTIONS
-{
- .vectors :
- {
- *(.vectors)
- } > vectors
-
- __start = .;
- .text : AT (__start) {
- _stext = .;
- *(.text)
- _etext = .;
- *(.lit)
- *(.shdata)
- _endtext = .;
- } > ram
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- } > ram
-
- .rodata : {
- *(.rodata);
- *(.rodata.*)
- } > ram
-
- .shbss :
- {
- *(.shbss)
- } > ram
-
- .talias :
- {
- } > ram
-
- .data : {
- sdata = .;
- _sdata = .;
- *(.data)
- edata = .;
- _edata = .;
- } > ram
-
- .bss :
- {
- _bss_start = .;
- *(.bss)
- *(COMMON)
- _bss_end = .;
- } > ram
- __end = .;
-
- /* No stack specification - done manually */
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_BITOPS_H
-#define __ASM_OPENRISC_BITOPS_H
-
-#define PLATFORM_FLS
-#include <asm/bitops/fls.h>
-#define PLATFORM_FFS
-#include <asm/bitops/ffs.h>
-
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#define hweight32(x) generic_hweight32(x)
-#define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
-
-#endif /* __ASM_GENERIC_BITOPS_H */
+++ /dev/null
-/*
- * OpenRISC Linux
- *
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_FFS_H
-#define __ASM_OPENRISC_FFS_H
-
-static inline int ffs(int x)
-{
- int ret;
-
- __asm__ ("l.ff1 %0,%1"
- : "=r" (ret)
- : "r" (x));
-
- return ret;
-}
-
-#endif /* __ASM_OPENRISC_FFS_H */
+++ /dev/null
-/*
- * OpenRISC Linux
- *
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_FLS_H
-#define __ASM_OPENRISC_FLS_H
-
-static inline int fls(int x)
-{
- int ret;
-
- __asm__ ("l.fl1 %0,%1"
- : "=r" (ret)
- : "r" (x));
-
- return ret;
-}
-
-#endif /* __ASM_OPENRISC_FLS_H */
+++ /dev/null
-#include <linux/byteorder/big_endian.h>
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_CACHE_H_
-#define __ASM_OPENRISC_CACHE_H_
-
-/*
- * Valid L1 data cache line sizes for the OpenRISC architecture are
- * 16 and 32 bytes.
- * If the board configuration has not specified one we default to the
- * largest of these values for alignment of DMA buffers.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN 32
-#endif
-
-#endif /* __ASM_OPENRISC_CACHE_H_ */
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_CONFIG_H_
-#define _ASM_CONFIG_H_
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-/* Architecture-specific global data */
-struct arch_global_data {
-};
-
-#include <asm-generic/global_data.h>
-
-/* OR32 GCC already has r10 set as fixed-use */
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r10")
-
-#endif /* __ASM_GBL_DATA_H */
+++ /dev/null
-/*
- * OpenRISC gpio driver
- *
- * Copyright (C) 2011 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * based on nios2 gpio driver
- * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
- *
- * when CONFIG_SYS_GPIO_BASE is not defined, board may provide
- * its own driver.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef CONFIG_SYS_GPIO_BASE
-#include <asm/io.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
-static inline int gpio_free(unsigned gpio)
-{
- return 0;
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
- return (readb(CONFIG_SYS_GPIO_BASE + gpio/8) >> gpio%8) & 0x1;
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
- u8 tmp = readb(CONFIG_SYS_GPIO_BASE + gpio/8);
-
- if (value)
- tmp |= (1 << gpio%8);
- else
- tmp &= ~(1 << gpio%8);
- writeb(tmp, CONFIG_SYS_GPIO_BASE + gpio/8);
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
- gpio_set_value(gpio + CONFIG_SYS_GPIO_WIDTH, 0);
-
- return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
- gpio_set_value(gpio + CONFIG_SYS_GPIO_WIDTH, 1);
- gpio_set_value(gpio, value);
-
- return 0;
-}
-
-static inline int gpio_is_valid(int number)
-{
- return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH;
-}
-#else
-extern int gpio_request(unsigned gpio, const char *label);
-extern int gpio_free(unsigned gpio);
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
-extern int gpio_get_value(unsigned gpio);
-extern void gpio_set_value(unsigned gpio, int value);
-extern int gpio_is_valid(int number);
-#endif /* CONFIG_SYS_GPIO_BASE */
+++ /dev/null
-/*
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_IO_H
-#define __ASM_OPENRISC_IO_H
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE (0)
-#define MAP_WRCOMBINE (0)
-#define MAP_WRBACK (0)
-#define MAP_WRTHROUGH (0)
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
- return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-/*
- * Change virtual addresses to physical addresses
- */
-static inline phys_addr_t virt_to_phys(void *vaddr)
-{
- return (phys_addr_t)(vaddr);
-}
-
-
-/*
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the openrisc architecture, we just read/write the
- * memory location directly.
- */
-#define readb(addr) (*(volatile unsigned char *) (addr))
-#define readw(addr) (*(volatile unsigned short *) (addr))
-#define readl(addr) (*(volatile unsigned int *) (addr))
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-
-#define writeb(b, addr) ((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) ((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) ((*(volatile unsigned int *) (addr)) = (b))
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-
-#define memset_io(a, b, c) memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
-
-/*
- * Again, OpenRISC does not require mem IO specific function.
- */
-
-
-#define IO_BASE 0x0
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define inb(port) readb((port + IO_BASE))
-#define outb(value, port) writeb((value), (port + IO_BASE))
-#define inb_p(port) inb((port))
-#define outb_p(value, port) outb((value), (port))
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p) __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p) p
-
-#define ioread8(addr) readb(addr)
-#define ioread16(addr) readw(addr)
-#define ioread32(addr) readl(addr)
-
-#define iowrite8(v, addr) writeb((v), (addr))
-#define iowrite16(v, addr) writew((v), (addr))
-#define iowrite32(v, addr) writel((v), (addr))
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _OPENRISC_EXC_H_
-#define _OPENRISC_EXC_H_
-
-#define EXC_RESET 0x01
-#define EXC_BUS_ERROR 0x02
-#define EXC_DATA_PAGE_FAULT 0x03
-#define EXC_INSTR_PAGE_FAULT 0x04
-#define EXC_TIMER 0x05
-#define EXC_ALIGNMENT 0x06
-#define EXC_ILLEGAL_INSTR 0x07
-#define EXC_EXT_IRQ 0x08
-#define EXC_DTLB_MISS 0x09
-#define EXC_ITLB_MISS 0x0a
-#define EXC_RANGE 0x0b
-#define EXC_SYSCALL 0x0c
-#define EXC_FLOAT_POINT 0x0d
-#define EXC_TRAP 0x0e
-
-void exception_install_handler(int exception, void (*handler)(void));
-void exception_free_handler(int exception);
-
-#endif
+++ /dev/null
-/*
- * Based on microblaze implementation:
- * Copyright (C) 2003 John Williams <jwilliams@itee.uq.edu.au>
- * Copyright (C) 2001,2002 NEC Corporation
- * Copyright (C) 2001,2002 Miles Bader <miles@gnu.org>
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file COPYING in the main directory of this
- * archive for more details.
- *
- * Written by Miles Bader <miles@gnu.org>
- * Microblaze port by John Williams
- */
-
-#ifndef __ASM_OPENRISC_POSIX_TYPES_H
-#define __ASM_OPENRISC_POSIX_TYPES_H
-
-typedef unsigned int __kernel_dev_t;
-typedef unsigned long __kernel_ino_t;
-typedef unsigned long long __kernel_ino64_t;
-typedef unsigned int __kernel_mode_t;
-typedef unsigned int __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef long long __kernel_loff_t;
-typedef int __kernel_pid_t;
-typedef unsigned short __kernel_ipc_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_daddr_t;
-typedef char *__kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-
-
-typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
- int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
-} __kernel_fsid_t;
-
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
-
-#undef __FD_SET
-#define __FD_SET(fd, fd_set) \
- __set_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
-#undef __FD_CLR
-#define __FD_CLR(fd, fd_set) \
- __clear_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
-#undef __FD_ISSET
-#define __FD_ISSET(fd, fd_set) \
- __test_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
-#undef __FD_ZERO
-#define __FD_ZERO(fd_set) \
- memset(fd_set, 0, sizeof(*(fd_set *)fd_set))
-
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-
-#endif /* __ASM_OPENRISC_POSIX_TYPES_H */
+++ /dev/null
-#ifndef __ASM_OPENRISC_PROCESSOR_H
-#define __ASM_OPENRISC_PROCESSOR_H
-
-#endif
+++ /dev/null
-/*
- * OpenRISC Linux
- *
- * Linux architectural port borrowing liberally from similar works of
- * others. All original copyrights apply as per the original source
- * declaration.
- *
- * OpenRISC implementation:
- * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- * et al.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_PTRACE_H
-#define __ASM_OPENRISC_PTRACE_H
-
-#include <asm/spr-defs.h>
-
-#ifndef __ASSEMBLY__
-/*
- * This is the layout of the regset returned by the GETREGSET ptrace call
- */
-struct user_regs_struct {
- /* GPR R0-R31... */
- unsigned long gpr[32];
- unsigned long pc;
- unsigned long sr;
- unsigned long pad1;
- unsigned long pad2;
-};
-#endif
-
-#ifdef __KERNEL__
-
-/*
- * Make kernel PTrace/register structures opaque to userspace... userspace can
- * access thread state via the regset mechanism. This allows us a bit of
- * flexibility in how we order the registers on the stack, permitting some
- * optimizations like packing call-clobbered registers together so that
- * they share a cacheline (not done yet, though... future optimization).
- */
-
-#ifndef __ASSEMBLY__
-/*
- * This struct describes how the registers are laid out on the kernel stack
- * during a syscall or other kernel entry.
- *
- * This structure should always be cacheline aligned on the stack.
- * FIXME: I don't think that's the case right now. The alignment is
- * taken care of elsewhere... head.S, process.c, etc.
- */
-
-struct pt_regs {
- union {
- struct {
- /* Named registers */
- long sr; /* Stored in place of r0 */
- long sp; /* r1 */
- };
- struct {
- /* Old style */
- long offset[2];
- long gprs[30];
- };
- struct {
- /* New style */
- long gpr[32];
- };
- };
- long pc;
- long orig_gpr11; /* For restarting system calls */
- long syscallno; /* Syscall number (used by strace) */
- long dummy; /* Cheap alignment fix */
-};
-#endif /* __ASSEMBLY__ */
-
-/* TODO: Rename this to REDZONE because that's what it is */
-#define STACK_FRAME_OVERHEAD 128 /* size of minimum stack frame */
-
-#define instruction_pointer(regs) ((regs)->pc)
-#define user_mode(regs) (((regs)->sr & SPR_SR_SM) == 0)
-#define user_stack_pointer(regs) ((unsigned long)(regs)->sp)
-#define profile_pc(regs) instruction_pointer(regs)
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-#define PT_SR 0
-#define PT_SP 4
-#define PT_GPR2 8
-#define PT_GPR3 12
-#define PT_GPR4 16
-#define PT_GPR5 20
-#define PT_GPR6 24
-#define PT_GPR7 28
-#define PT_GPR8 32
-#define PT_GPR9 36
-#define PT_GPR10 40
-#define PT_GPR11 44
-#define PT_GPR12 48
-#define PT_GPR13 52
-#define PT_GPR14 56
-#define PT_GPR15 60
-#define PT_GPR16 64
-#define PT_GPR17 68
-#define PT_GPR18 72
-#define PT_GPR19 76
-#define PT_GPR20 80
-#define PT_GPR21 84
-#define PT_GPR22 88
-#define PT_GPR23 92
-#define PT_GPR24 96
-#define PT_GPR25 100
-#define PT_GPR26 104
-#define PT_GPR27 108
-#define PT_GPR28 112
-#define PT_GPR29 116
-#define PT_GPR30 120
-#define PT_GPR31 124
-#define PT_PC 128
-#define PT_ORIG_GPR11 132
-#define PT_SYSCALLNO 136
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASM_OPENRISC_PTRACE_H */
+++ /dev/null
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_SECTIONS_H
-#define __ASM_OPENRISC_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
+++ /dev/null
-/*
- * SPR Definitions
- *
- * Copyright (C) 2000 Damjan Lampret
- * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
- * Copyright (C) 2008, 2010 Embecosm Limited
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- * et al.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * This file is part of OpenRISC 1000 Architectural Simulator.
- */
-
-#ifndef SPR_DEFS__H
-#define SPR_DEFS__H
-
-/* Definition of special-purpose registers (SPRs) */
-
-#define MAX_GRPS (32)
-#define MAX_SPRS_PER_GRP_BITS (11)
-#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
-#define MAX_SPRS (0x10000)
-
-/* Base addresses for the groups */
-#define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS)
-
-/* System control and status group */
-#define SPR_VR (SPRGROUP_SYS + 0)
-#define SPR_UPR (SPRGROUP_SYS + 1)
-#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
-#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
-#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
-#define SPR_DCCFGR (SPRGROUP_SYS + 5)
-#define SPR_ICCFGR (SPRGROUP_SYS + 6)
-#define SPR_DCFGR (SPRGROUP_SYS + 7)
-#define SPR_PCCFGR (SPRGROUP_SYS + 8)
-#define SPR_VR2 (SPRGROUP_SYS + 9)
-#define SPR_AVR (SPRGROUP_SYS + 10)
-#define SPR_EVBAR (SPRGROUP_SYS + 11)
-#define SPR_AECR (SPRGROUP_SYS + 12)
-#define SPR_AESR (SPRGROUP_SYS + 13)
-#define SPR_NPC (SPRGROUP_SYS + 16)
-#define SPR_SR (SPRGROUP_SYS + 17)
-#define SPR_PPC (SPRGROUP_SYS + 18)
-#define SPR_FPCSR (SPRGROUP_SYS + 20)
-#define SPR_EPCR_BASE (SPRGROUP_SYS + 32)
-#define SPR_EPCR_LAST (SPRGROUP_SYS + 47)
-#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
-#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
-#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
-#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
-#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
-
-/* Data MMU group */
-#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
-#define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
-#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
-#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
-#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
-#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
-
-/* Instruction MMU group */
-#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
-#define SPR_ITLBEIR (SPRGROUP_IMMU + 2)
-#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
-#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
-#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
-#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
-
-/* Data cache group */
-#define SPR_DCCR (SPRGROUP_DC + 0)
-#define SPR_DCBPR (SPRGROUP_DC + 1)
-#define SPR_DCBFR (SPRGROUP_DC + 2)
-#define SPR_DCBIR (SPRGROUP_DC + 3)
-#define SPR_DCBWR (SPRGROUP_DC + 4)
-#define SPR_DCBLR (SPRGROUP_DC + 5)
-#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
-#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
-
-/* Instruction cache group */
-#define SPR_ICCR (SPRGROUP_IC + 0)
-#define SPR_ICBPR (SPRGROUP_IC + 1)
-#define SPR_ICBIR (SPRGROUP_IC + 2)
-#define SPR_ICBLR (SPRGROUP_IC + 3)
-#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
-#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
-
-/* MAC group */
-#define SPR_MACLO (SPRGROUP_MAC + 1)
-#define SPR_MACHI (SPRGROUP_MAC + 2)
-
-/* Debug group */
-#define SPR_DVR(N) (SPRGROUP_D + (N))
-#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
-#define SPR_DMR1 (SPRGROUP_D + 16)
-#define SPR_DMR2 (SPRGROUP_D + 17)
-#define SPR_DWCR0 (SPRGROUP_D + 18)
-#define SPR_DWCR1 (SPRGROUP_D + 19)
-#define SPR_DSR (SPRGROUP_D + 20)
-#define SPR_DRR (SPRGROUP_D + 21)
-
-/* Performance counters group */
-#define SPR_PCCR(N) (SPRGROUP_PC + (N))
-#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
-
-/* Power management group */
-#define SPR_PMR (SPRGROUP_PM + 0)
-
-/* PIC group */
-#define SPR_PICMR (SPRGROUP_PIC + 0)
-#define SPR_PICPR (SPRGROUP_PIC + 1)
-#define SPR_PICSR (SPRGROUP_PIC + 2)
-
-/* Tick Timer group */
-#define SPR_TTMR (SPRGROUP_TT + 0)
-#define SPR_TTCR (SPRGROUP_TT + 1)
-
-/*
- * Bit definitions for the Version Register
- */
-#define SPR_VR_VER 0xff000000 /* Processor version */
-#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
-#define SPR_VR_RES 0x0000ffc0 /* Reserved */
-#define SPR_VR_REV 0x0000003f /* Processor revision */
-
-#define SPR_VR_VER_OFF 24
-#define SPR_VR_CFG_OFF 16
-#define SPR_VR_REV_OFF 0
-
-/*
- * Bit definitions for the Unit Present Register
- */
-#define SPR_UPR_UP 0x00000001 /* UPR present */
-#define SPR_UPR_DCP 0x00000002 /* Data cache present */
-#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
-#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
-#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
-#define SPR_UPR_MP 0x00000020 /* MAC present */
-#define SPR_UPR_DUP 0x00000040 /* Debug unit present */
-#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */
-#define SPR_UPR_PMP 0x00000100 /* Power management present */
-#define SPR_UPR_PICP 0x00000200 /* PIC present */
-#define SPR_UPR_TTP 0x00000400 /* Tick timer present */
-#define SPR_UPR_RES 0x00fe0000 /* Reserved */
-#define SPR_UPR_CUP 0xff000000 /* Context units present */
-
-/*
- * Bit definitions for the CPU configuration register
- */
-#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */
-#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */
-#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */
-#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */
-#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
-#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
-#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */
-#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */
-#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
-#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
-#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */
- /* Arithmetic Exception Status Register (AESR) presents */
-#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */
-
-/*
- * Bit definitions for the Debug configuration register and other
- * constants.
- */
-
-#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */
-#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */
-#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */
-#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */
-#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
-#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
-#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
-#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
-#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
-#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */
-
-#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
- 2 == n ? SPR_DCFGR_NDP2 : \
- 3 == n ? SPR_DCFGR_NDP3 : \
- 4 == n ? SPR_DCFGR_NDP4 : \
- 5 == n ? SPR_DCFGR_NDP5 : \
- 6 == n ? SPR_DCFGR_NDP6 : \
- 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
-#define MAX_MATCHPOINTS 8
-#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)
-
-/*
- * Bit definitions for the Supervision Register
- */
-#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
-#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
-#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
-#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
-#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
-#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
-#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
-#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
-#define SPR_SR_CE 0x00000100 /* CID Enable */
-#define SPR_SR_F 0x00000200 /* Condition Flag */
-#define SPR_SR_CY 0x00000400 /* Carry flag */
-#define SPR_SR_OV 0x00000800 /* Overflow flag */
-#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
-#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
-#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */
-#define SPR_SR_FO 0x00008000 /* Fixed one */
-#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
-#define SPR_SR_RES 0x0ffe0000 /* Reserved */
-#define SPR_SR_CID 0xf0000000 /* Context ID */
-
-/*
- * Bit definitions for the Data MMU Control Register
- */
-#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
-#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
-#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
-#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
-
-/*
- * Bit definitions for the Instruction MMU Control Register
- */
-#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
-#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
-#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
-#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
-
-/*
- * Bit definitions for the Data TLB Match Register
- */
-#define SPR_DTLBMR_V 0x00000001 /* Valid */
-#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
-#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
-#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
-#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
-
-/*
- * Bit definitions for the Data TLB Translate Register
- */
-#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
-#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
-#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
-#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
-#define SPR_DTLBTR_A 0x00000010 /* Accessed */
-#define SPR_DTLBTR_D 0x00000020 /* Dirty */
-#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
-#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
-#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
-#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
-#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
-
-/*
- * Bit definitions for the Instruction TLB Match Register
- */
-#define SPR_ITLBMR_V 0x00000001 /* Valid */
-#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
-#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
-#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
-#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
-
-/*
- * Bit definitions for the Instruction TLB Translate Register
- */
-#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
-#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
-#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
-#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
-#define SPR_ITLBTR_A 0x00000010 /* Accessed */
-#define SPR_ITLBTR_D 0x00000020 /* Dirty */
-#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
-#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
-#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
-
-/*
- * Bit definitions for Data Cache Control register
- */
-#define SPR_DCCR_EW 0x000000ff /* Enable ways */
-
-/*
- * Bit definitions for Insn Cache Control register
- */
-#define SPR_ICCR_EW 0x000000ff /* Enable ways */
-
-/*
- * Bit definitions for Data Cache Configuration Register
- */
-
-#define SPR_DCCFGR_NCW 0x00000007
-#define SPR_DCCFGR_NCS 0x00000078
-#define SPR_DCCFGR_CBS 0x00000080
-#define SPR_DCCFGR_CWS 0x00000100
-#define SPR_DCCFGR_CCRI 0x00000200
-#define SPR_DCCFGR_CBIRI 0x00000400
-#define SPR_DCCFGR_CBPRI 0x00000800
-#define SPR_DCCFGR_CBLRI 0x00001000
-#define SPR_DCCFGR_CBFRI 0x00002000
-#define SPR_DCCFGR_CBWBRI 0x00004000
-
-#define SPR_DCCFGR_NCW_OFF 0
-#define SPR_DCCFGR_NCS_OFF 3
-#define SPR_DCCFGR_CBS_OFF 7
-
-/*
- * Bit definitions for Instruction Cache Configuration Register
- */
-#define SPR_ICCFGR_NCW 0x00000007
-#define SPR_ICCFGR_NCS 0x00000078
-#define SPR_ICCFGR_CBS 0x00000080
-#define SPR_ICCFGR_CCRI 0x00000200
-#define SPR_ICCFGR_CBIRI 0x00000400
-#define SPR_ICCFGR_CBPRI 0x00000800
-#define SPR_ICCFGR_CBLRI 0x00001000
-
-#define SPR_ICCFGR_NCW_OFF 0
-#define SPR_ICCFGR_NCS_OFF 3
-#define SPR_ICCFGR_CBS_OFF 7
-
-/*
- * Bit definitions for Data MMU Configuration Register
- */
-#define SPR_DMMUCFGR_NTW 0x00000003
-#define SPR_DMMUCFGR_NTS 0x0000001C
-#define SPR_DMMUCFGR_NAE 0x000000E0
-#define SPR_DMMUCFGR_CRI 0x00000100
-#define SPR_DMMUCFGR_PRI 0x00000200
-#define SPR_DMMUCFGR_TEIRI 0x00000400
-#define SPR_DMMUCFGR_HTR 0x00000800
-
-#define SPR_DMMUCFGR_NTW_OFF 0
-#define SPR_DMMUCFGR_NTS_OFF 2
-
-/*
- * Bit definitions for Instruction MMU Configuration Register
- */
-#define SPR_IMMUCFGR_NTW 0x00000003
-#define SPR_IMMUCFGR_NTS 0x0000001C
-#define SPR_IMMUCFGR_NAE 0x000000E0
-#define SPR_IMMUCFGR_CRI 0x00000100
-#define SPR_IMMUCFGR_PRI 0x00000200
-#define SPR_IMMUCFGR_TEIRI 0x00000400
-#define SPR_IMMUCFGR_HTR 0x00000800
-
-#define SPR_IMMUCFGR_NTW_OFF 0
-#define SPR_IMMUCFGR_NTS_OFF 2
-
-/*
- * Bit definitions for Debug Control registers
- */
-#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
-#define SPR_DCR_CC 0x0000000e /* Compare condition */
-#define SPR_DCR_SC 0x00000010 /* Signed compare */
-#define SPR_DCR_CT 0x000000e0 /* Compare to */
-
-/* Bit results with SPR_DCR_CC mask */
-#define SPR_DCR_CC_MASKED 0x00000000
-#define SPR_DCR_CC_EQUAL 0x00000002
-#define SPR_DCR_CC_LESS 0x00000004
-#define SPR_DCR_CC_LESSE 0x00000006
-#define SPR_DCR_CC_GREAT 0x00000008
-#define SPR_DCR_CC_GREATE 0x0000000a
-#define SPR_DCR_CC_NEQUAL 0x0000000c
-
-/* Bit results with SPR_DCR_CT mask */
-#define SPR_DCR_CT_DISABLED 0x00000000
-#define SPR_DCR_CT_IFEA 0x00000020
-#define SPR_DCR_CT_LEA 0x00000040
-#define SPR_DCR_CT_SEA 0x00000060
-#define SPR_DCR_CT_LD 0x00000080
-#define SPR_DCR_CT_SD 0x000000a0
-#define SPR_DCR_CT_LSEA 0x000000c0
-#define SPR_DCR_CT_LSD 0x000000e0
-
-/*
- * Bit definitions for Debug Mode 1 register
- */
-#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */
-#define SPR_DMR1_CW0_AND 0x00000001
-#define SPR_DMR1_CW0_OR 0x00000002
-#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
-#define SPR_DMR1_CW1_AND 0x00000004
-#define SPR_DMR1_CW1_OR 0x00000008
-#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
-#define SPR_DMR1_CW2_AND 0x00000010
-#define SPR_DMR1_CW2_OR 0x00000020
-#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
-#define SPR_DMR1_CW3_AND 0x00000040
-#define SPR_DMR1_CW3_OR 0x00000080
-#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
-#define SPR_DMR1_CW4_AND 0x00000100
-#define SPR_DMR1_CW4_OR 0x00000200
-#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
-#define SPR_DMR1_CW5_AND 0x00000400
-#define SPR_DMR1_CW5_OR 0x00000800
-#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
-#define SPR_DMR1_CW6_AND 0x00001000
-#define SPR_DMR1_CW6_OR 0x00002000
-#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
-#define SPR_DMR1_CW7_AND 0x00004000
-#define SPR_DMR1_CW7_OR 0x00008000
-#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
-#define SPR_DMR1_CW8_AND 0x00010000
-#define SPR_DMR1_CW8_OR 0x00020000
-#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
-#define SPR_DMR1_CW9_AND 0x00040000
-#define SPR_DMR1_CW9_OR 0x00080000
-#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
-#define SPR_DMR1_RES1 0x00300000 /* Reserved */
-#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
-#define SPR_DMR1_BT 0x00800000 /* Branch trace */
-#define SPR_DMR1_RES2 0xff000000 /* Reserved */
-
-/*
- * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
- */
-#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
-#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
-#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */
-#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */
-#define SPR_DMR2_WGB 0x003ff000 /* Watch generating breakpoint */
-#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */
-#define SPR_DMR2_WBS 0xffc00000 /* Watchpoint status */
-#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */
-
-/*
- * Bit definitions for Debug watchpoint counter registers
- */
-#define SPR_DWCR_COUNT 0x0000ffff /* Count */
-#define SPR_DWCR_MATCH 0xffff0000 /* Match */
-#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */
-
-/*
- * Bit definitions for Debug stop register
- *
- */
-#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
-#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
-#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
-#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
-#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */
-#define SPR_DSR_AE 0x00000020 /* Alignment exception */
-#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
-#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
-#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
-#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
-#define SPR_DSR_RE 0x00000400 /* Range exception */
-#define SPR_DSR_SCE 0x00000800 /* System call exception */
-#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */
-#define SPR_DSR_TE 0x00002000 /* Trap exception */
-
-/*
- * Bit definitions for Debug reason register
- */
-#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
-#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
-#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
-#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
-#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
-#define SPR_DRR_AE 0x00000020 /* Alignment exception */
-#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
-#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
-#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
-#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
-#define SPR_DRR_RE 0x00000400 /* Range exception */
-#define SPR_DRR_SCE 0x00000800 /* System call exception */
-#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */
-#define SPR_DRR_TE 0x00002000 /* Trap exception */
-
-/*
- * Bit definitions for Performance counters mode registers
- */
-#define SPR_PCMR_CP 0x00000001 /* Counter present */
-#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
-#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
-#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
-#define SPR_PCMR_LA 0x00000010 /* Load access event */
-#define SPR_PCMR_SA 0x00000020 /* Store access event */
-#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
-#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
-#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
-#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
-#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
-#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
-#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
-#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
-#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
-#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
-
-/*
- * Bit definitions for the Power management register
- */
-#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
-#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
-#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
-#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
-#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
-
-/*
- * Bit definitions for PICMR
- */
-#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
-
-/*
- * Bit definitions for PICPR
- */
-#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
-
-/*
- * Bit definitions for PICSR
- */
-#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
-
-/*
- * Bit definitions for Tick Timer Control Register
- */
-#define SPR_TTCR_CNT 0xffffffff /* Count, time period */
-#define SPR_TTMR_TP 0x0fffffff /* Time period */
-#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
-#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
-#define SPR_TTMR_DI 0x00000000 /* Disabled */
-#define SPR_TTMR_RT 0x40000000 /* Restart tick */
-#define SPR_TTMR_SR 0x80000000 /* Single run */
-#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
-#define SPR_TTMR_M 0xc0000000 /* Tick mode */
-
-/*
- * Bit definitions for the FP Control Status Register
- */
-#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
-#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
-#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
-#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
-#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
-#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
-#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
-#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
-#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
-#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
-#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
-#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
- SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
- SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
-
-#define FPCSR_RM_RN (0<<1)
-#define FPCSR_RM_RZ (1<<1)
-#define FPCSR_RM_RIP (2<<1)
-#define FPCSR_RM_RIN (3<<1)
-
-/*
- * l.nop constants
- */
-#define NOP_NOP 0x0000 /* Normal nop instruction */
-#define NOP_EXIT 0x0001 /* End of simulation */
-#define NOP_REPORT 0x0002 /* Simple report */
-#define NOP_PUTC 0x0004 /* Simputc instruction */
-#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */
-#define NOP_GET_TICKS 0x0006 /* Get # ticks running */
-#define NOP_GET_PS 0x0007 /* Get picosecs/cycle */
-#define NOP_REPORT_FIRST 0x0400 /* Report with number */
-#define NOP_REPORT_LAST 0x03ff /* Report with number */
-
-#endif /* SPR_DEFS__H */
+++ /dev/null
-#ifndef __ASM_OPENRISC_STRING_H
-#define __ASM_OPENRISC_STRING_H
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_SYSTEM_H
-#define __ASM_OPENRISC_SYSTEM_H
-
-#include <asm/spr-defs.h>
-
-static inline unsigned long mfspr(unsigned long add)
-{
- unsigned long ret;
-
- __asm__ __volatile__ ("l.mfspr %0,r0,%1" : "=r" (ret) : "K" (add));
-
- return ret;
-}
-
-static inline void mtspr(unsigned long add, unsigned long val)
-{
- __asm__ __volatile__ ("l.mtspr r0,%1,%0" : : "K" (add), "r" (val));
-}
-
-#endif /* __ASM_OPENRISC_SYSTEM_H */
+++ /dev/null
-/*
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_TYPES_H
-#define _ASM_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue. However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#define BITS_PER_LONG 32
-
-/* Dma addresses are 32-bits wide. */
-
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_TYPES_H */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- ********************************************************************
- * NOTE: This header file defines an interface to U-Boot. Including
- * this (unmodified) header file in another file is considered normal
- * use of U-Boot, and does *not* fall under the heading of "derived
- * work".
- ********************************************************************
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_
-
-typedef struct bd_info {
- unsigned long bi_arch_number; /* unique id for this board */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
-} bd_t;
-
-#define IH_ARCH_DEFAULT IH_ARCH_OPENRISC
-
-#endif /* _U_BOOT_H_ */
+++ /dev/null
-#include <asm-generic/unaligned.h>
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-y += timer.o
+++ /dev/null
-/*
- * (C) Copyright 2011 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * Based on microblaze implementation by:
- * (C) Copyright 2007 Michal Simek
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Michal SIMEK <monstr@monstr.eu>
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <u-boot/zlib.h>
-#include <asm/byteorder.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int do_bootm_linux(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- void (*kernel) (unsigned int);
- ulong rd_data_start, rd_data_end;
-
- /*
- * allow the PREP bootm subcommand, it is required for bootm to work
- */
- if (flag & BOOTM_STATE_OS_PREP)
- return 0;
-
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
-
- int ret;
-
- char *of_flat_tree = NULL;
-#if defined(CONFIG_OF_LIBFDT)
- /* did generic code already find a device tree? */
- if (images->ft_len)
- of_flat_tree = images->ft_addr;
-#endif
-
- kernel = (void (*)(unsigned int))images->ep;
-
- /* find ramdisk */
- ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_OPENRISC,
- &rd_data_start, &rd_data_end);
- if (ret)
- return 1;
-
- show_boot_progress(15);
-
- if (!of_flat_tree && argc > 1)
- of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16);
-#ifdef DEBUG
- printf("## Transferring control to Linux (at address 0x%08lx) " \
- "ramdisk 0x%08lx, FDT 0x%08lx...\n",
- (ulong) kernel, rd_data_start, (ulong) of_flat_tree);
-#endif
- if (dcache_status() || icache_status())
- flush_cache((ulong)kernel, max(checkdcache(), checkicache()));
-
- /*
- * Linux Kernel Parameters (passing device tree):
- * r3: pointer to the fdt, followed by the board info data
- */
- kernel((unsigned int) of_flat_tree);
- /* does not return */
-
- return 1;
-}
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/openrisc_exc.h>
-
-static ulong timestamp;
-
-/* how many counter cycles in a jiffy */
-#define TIMER_COUNTER_CYCLES (CONFIG_SYS_CLK_FREQ/CONFIG_SYS_OPENRISC_TMR_HZ)
-/* how many ms elapses between each timer interrupt */
-#define TIMER_TIMESTAMP_INC (1000/CONFIG_SYS_OPENRISC_TMR_HZ)
-/* how many cycles per ms */
-#define TIMER_CYCLES_MS (CONFIG_SYS_CLK_FREQ/1000)
-/* how many cycles per us */
-#define TIMER_CYCLES_US (CONFIG_SYS_CLK_FREQ/1000000uL)
-
-void timer_isr(void)
-{
- timestamp += TIMER_TIMESTAMP_INC;
- mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
- (TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
-}
-
-int timer_init(void)
-{
- /* Install timer exception handler */
- exception_install_handler(EXC_TIMER, timer_isr);
-
- /* Set up the timer for the first expiration. */
- timestamp = 0;
-
- mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
- (TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
-
- /* Enable tick timer exception in supervisor register */
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
-
- return 0;
-}
-
-void reset_timer(void)
-{
- timestamp = 0;
-
- mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
- (TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
-}
-
-/*
- * The timer value in ms is calculated by taking the
- * value accumulated by full timer revolutions plus the value
- * accumulated in this period
- */
-ulong get_timer(ulong base)
-{
- return timestamp + mfspr(SPR_TTCR)/TIMER_CYCLES_MS - base;
-}
-
-void set_timer(ulong t)
-{
- reset_timer();
- timestamp = t;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
-
-void __udelay(ulong usec)
-{
- ulong elapsed = 0;
- ulong tick;
- ulong last_tick;
-
- last_tick = mfspr(SPR_TTCR);
- while ((elapsed / TIMER_CYCLES_US) < usec) {
- tick = mfspr(SPR_TTCR);
- if (tick >= last_tick)
- elapsed += (tick - last_tick);
- else
- elapsed += TIMER_COUNTER_CYCLES - (last_tick - tick);
- last_tick = tick;
- }
-}
+++ /dev/null
-if TARGET_OPENRISC_GENERIC
-
-config SYS_BOARD
- default "openrisc-generic"
-
-config SYS_VENDOR
- default "openrisc"
-
-config SYS_CONFIG_NAME
- default "openrisc-generic"
-
-endif
+++ /dev/null
-OPENRISC-GENERIC BOARD
-M: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-S: Maintained
-F: board/openrisc/openrisc-generic/
-F: include/configs/openrisc-generic.h
-F: configs/openrisc-generic_defconfig
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := openrisc-generic.o
+++ /dev/null
-#
-# (C) Copyright 2011, Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mhard-mul -mhard-div
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
+++ /dev/null
-/*
- * Based on nios2-generic.c:
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int board_early_init_f(void)
-{
- return 0;
-}
-
-int checkboard(void)
-{
- printf("BOARD: %s\n", CONFIG_BOARD_NAME);
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-
-#ifdef CONFIG_ETHOC
- rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-/* sim.cfg -- Simulator configuration script file
- Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
-
-This file is part of OpenRISC 1000 Architectural Simulator.
-It contains the default configuration and help about configuring
-the simulator.
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-/* INTRODUCTION
-
- The ork1sim has various parameters, that are set in configuration files
- like this one. The user can switch between configurations at startup by
- specifying the required configuration file with the -f <filename.cfg> option.
- If no configuration file is specified or1ksim searches for the default
- configuration file sim.cfg. First it searches for './sim.cfg'. If this
- file is not found, it searches for '~/or1k/sim.cfg'. If this file is
- not found too, it reverts to the built-in default configuration.
-
- NOTE: Users should not rely on the built-in configuration, since the
- default configuration may differ between version.
- Rather create a configuration file that sets all critical values.
-
- This file may contain (standard C) comments only - no // support.
-
- Configure files may be be included, using:
- include "file_name_to_include"
-
- Like normal configuration files, the included file is divided into
- sections. Each section is described in detail also.
-
- Some section have subsections. One example of such a subsection is:
-
- device <index>
- instance specific parameters...
- enddevice
-
- which creates a device instance.
-*/
-
-
-/* MEMORY SECTION
-
- This section specifies how the memory is generated and the blocks
- it consists of.
-
- type = random/unknown/pattern
- Specifies the initial memory values.
- 'random' generates random memory using seed 'random_seed'.
- 'pattern' fills memory with 'pattern'.
- 'unknown' does not specify how memory should be generated,
- leaving the memory in a undefined state. This is the fastest
- option.
-
- random_seed = <value>
- random seed for randomizer, used if type = 'random'.
-
- pattern = <value>
- pattern to fill memory, used if type = 'pattern'.
-
- nmemories = <value>
- number of memory instances connected
-
- baseaddr = <hex_value>
- memory start address
-
- size = <hex_value>
- memory size
-
- name = "<string>"
- memory block name
-
- ce = <value>
- chip enable index of the memory instance
-
- mc = <value>
- memory controller this memory is connected to
-
- delayr = <value>
- cycles, required for read access, -1 if instance does not support reading
-
- delayw = <value>
- cycles, required for write access, -1 if instance does not support writing
-
- log = "<filename>"
- filename, where to log memory accesses to, no log, if log command is not specified
-*/
-
-
-section memory
- pattern = 0x00
- type = unknown /* Fastest */
-
- name = "FLASH"
- ce = 0
- mc = 0
- baseaddr = 0xf0000000
- size = 0x01000000
- delayr = 1
- delayw = -1
-end
-
-section memory
- pattern = 0x00
- type = unknown /* Fastest */
-
- name = "RAM"
- ce = 1
- mc = 0
- baseaddr = 0x00000000
- size = 0x02000000
- delayr = 1
- delayw = 1
-end
-
-section memory
- pattern = 0x00
- type = unknown /* Fastest */
-
- name = "SRAM"
- mc = 0
- ce = 2
- baseaddr = 0xa4000000
- size = 0x00100000
- delayr = 1
- delayw = 2
-end
-
-
-/* IMMU SECTION
-
- This section configures the Instruction Memory Manangement Unit
-
- enabled = 0/1
- '0': disabled
- '1': enabled
- (NOTE: UPR bit is set)
-
- nsets = <value>
- number of ITLB sets; must be power of two
-
- nways = <value>
- number of ITLB ways
-
- pagesize = <value>
- instruction page size; must be power of two
-
- entrysize = <value>
- instruction entry size in bytes
-
- ustates = <value>
- number of ITLB usage states (2, 3, 4 etc., max is 4)
-
- hitdelay = <value>
- number of cycles immu hit costs
-
- missdelay = <value>
- number of cycles immu miss costs
-*/
-
-section immu
- enabled = 1
- nsets = 64
- nways = 1
- pagesize = 8192
- hitdelay = 0
- missdelay = 0
-end
-
-
-/* DMMU SECTION
-
- This section configures the Data Memory Manangement Unit
-
- enabled = 0/1
- '0': disabled
- '1': enabled
- (NOTE: UPR bit is set)
-
- nsets = <value>
- number of DTLB sets; must be power of two
-
- nways = <value>
- number of DTLB ways
-
- pagesize = <value>
- data page size; must be power of two
-
- entrysize = <value>
- data entry size in bytes
-
- ustates = <value>
- number of DTLB usage states (2, 3, 4 etc., max is 4)
-
- hitdelay = <value>
- number of cycles dmmu hit costs
-
- missdelay = <value>
- number of cycles dmmu miss costs
-*/
-
-section dmmu
- enabled = 1
- nsets = 64
- nways = 1
- pagesize = 8192
- hitdelay = 0
- missdelay = 0
-end
-
-
-/* IC SECTION
-
- This section configures the Instruction Cache
-
- enabled = 0/1
- '0': disabled
- '1': enabled
- (NOTE: UPR bit is set)
-
- nsets = <value>
- number of IC sets; must be power of two
-
- nways = <value>
- number of IC ways
-
- blocksize = <value>
- IC block size in bytes; must be power of two
-
- ustates = <value>
- number of IC usage states (2, 3, 4 etc., max is 4)
-
- hitdelay = <value>
- number of cycles ic hit costs
-
- missdelay = <value>
- number of cycles ic miss costs
-*/
-
-section ic
- enabled = 1
- nsets = 512
- nways = 1
- blocksize = 16
- hitdelay = 1
- missdelay = 1
-end
-
-
-/* DC SECTION
-
- This section configures the Data Cache
-
- enabled = 0/1
- '0': disabled
- '1': enabled
- (NOTE: UPR bit is set)
-
- nsets = <value>
- number of DC sets; must be power of two
-
- nways = <value>
- number of DC ways
-
- blocksize = <value>
- DC block size in bytes; must be power of two
-
- ustates = <value>
- number of DC usage states (2, 3, 4 etc., max is 4)
-
- load_hitdelay = <value>
- number of cycles dc load hit costs
-
- load_missdelay = <value>
- number of cycles dc load miss costs
-
- store_hitdelay = <value>
- number of cycles dc load hit costs
-
- store_missdelay = <value>
- number of cycles dc load miss costs
-*/
-
-section dc
- enabled = 1
- nsets = 512
- nways = 1
- blocksize = 16
- load_hitdelay = 1
- load_missdelay = 1
- store_hitdelay = 1
- store_missdelay = 1
-end
-
-
-/* SIM SECTION
-
- This section specifies how or1ksim should behave.
-
- verbose = 0/1
- '0': don't print extra messages
- '1': print extra messages
-
- debug = 0-9
- 0 : no debug messages
- 1-9: debug message level.
- higher numbers produce more messages
-
- profile = 0/1
- '0': don't generate profiling file 'sim.profile'
- '1': don't generate profiling file 'sim.profile'
-
- prof_fn = "<filename>"
- optional filename for the profiling file.
- valid only if 'profile' is set
-
- mprofile = 0/1
- '0': don't generate memory profiling file 'sim.mprofile'
- '1': generate memory profiling file 'sim.mprofile'
-
- mprof_fn = "<filename>"
- optional filename for the memory profiling file.
- valid only if 'mprofile' is set
-
- history = 0/1
- '0': don't track execution flow
- '1': track execution flow
- Execution flow can be tracked for the simulator's
- 'hist' command. Useful for back-trace debugging.
-
- iprompt = 0/1
- '0': start in <not interactive prompt> (so what do we start in ???)
- '1': start in interactive prompt.
-
- exe_log = 0/1
- '0': don't generate execution log.
- '1': generate execution log.
-
- exe_log = default/hardware/simple/software
- type of execution log, default is used when not specified
-
- exe_log_start = <value>
- index of first instruction to start logging, default = 0
-
- exe_log_end = <value>
- index of last instruction to end logging; not limited, if omitted
-
- exe_log_marker = <value>
- <value> specifies number of instructions before horizontal marker is
- printed; if zero, markers are disabled (default)
-
- exe_log_fn = "<filename>"
- filename for the exection log file.
- valid only if 'exe_log' is set
-
- clkcycle = <value>[ps|ns|us|ms]
- specifies time measurement for one cycle
-*/
-
-section sim
- verbose = 1
- debug = 0
- profile = 0
- history = 0
-
- clkcycle = 10ns
-end
-
-
-/* SECTION VAPI
-
- This section configures the Verification API, used for Advanced
- Core Verification.
-
- enabled = 0/1
- '0': disbable VAPI server
- '1': enable/start VAPI server
-
- server_port = <value>
- TCP/IP port to start VAPI server on
-
- log_enabled = 0/1
- '0': disable VAPI requests logging
- '1': enable VAPI requests logging
-
- hide_device_id = 0/1
- '0': don't log device id (for compatability with old version)
- '1': log device id
-
-
- vapi_fn = <filename>
- filename for the log file.
- valid only if log_enabled is set
-*/
-
-section VAPI
- enabled = 0
- server_port = 9998
- log_enabled = 0
- vapi_log_fn = "vapi.log"
-end
-
-
-/* CPU SECTION
-
- This section specifies various CPU parameters.
-
- ver = <value>
- rev = <value>
- specifies version and revision of the CPU used
-
- upr = <value>
- changes the upr register
-
- sr = <value>
- sets the initial Supervision Register value
- supervisor mode (SM) and fixed one (FO) set = 0x8001
- exception prefix high (EPH, vectors@0xf0000000) = 0x4000
- together, (SM | FO | EPH) = 0xc001
- superscalar = 0/1
- '0': CPU is scalar
- '1': CPU is superscalar
- (modify cpu/or32/execute.c to tune superscalar model)
-
- hazards = 0/1
- '0': don't track data hazards in superscalar CPU
- '1': track data hazards in superscalar CPU
- If tracked, data hazards can be displayed using the
- simulator's 'r' command.
-
- dependstats = 0/1
- '0': don't calculate inter-instruction dependencies.
- '1': calculate inter-instruction dependencies.
- If calculated, inter-instruction dependencies can be
- displayed using the simulator's 'stat' command.
-
- sbuf_len = <value>
- length of store buffer (<= 256), 0 = disabled
-*/
-
-section cpu
- ver = 0x12
- cfg = 0x00
- rev = 0x01
- sr = 0x8001 /*SPR_SR_FO | SPR_SR_SM | SPR_SR_EPH */
- /* upr = */
- superscalar = 0
- hazards = 0
- dependstats = 0
- sbuf_len = 0
-end
-
-
-/* PM SECTION
-
- This section specifies Power Management parameters
-
- enabled = 0/1
- '0': disable power management
- '1': enable power management
-*/
-
-section pm
- enabled = 0
-end
-
-
-/* BPB SECTION
-
- This section specifies how branch prediction should behave.
-
- enabled = 0/1
- '0': disable branch prediction
- '1': enable branch prediction
-
- btic = 0/1
- '0': disable branch target instruction cache model
- '1': enable branch target instruction cache model
-
- sbp_bf_fwd = 0/1
- Static branch prediction for 'l.bf'
- '0': don't use forward prediction
- '1': use forward prediction
-
- sbp_bnf_fwd = 0/1
- Static branch prediction for 'l.bnf'
- '0': don't use forward prediction
- '1': use forward prediction
-
- hitdelay = <value>
- number of cycles bpb hit costs
-
- missdelay = <value>
- number of cycles bpb miss costs
-*/
-
-section bpb
- enabled = 0
- btic = 0
- sbp_bf_fwd = 0
- sbp_bnf_fwd = 0
- hitdelay = 0
- missdelay = 0
-end
-
-
-/* DEBUG SECTION
-
- This sections specifies how the debug unit should behave.
-
- enabled = 0/1
- '0': disable debug unit
- '1': enable debug unit
-
- gdb_enabled = 0/1
- '0': don't start gdb server
- '1': start gdb server at port 'server_port'
-
- server_port = <value>
- TCP/IP port to start gdb server on
- valid only if gdb_enabled is set
-
- vapi_id = <hex_value>
- Used to create "fake" vapi log file containing the JTAG proxy messages.
-*/
-section debug
- enabled = 0
-/* gdb_enabled = 0 */
-/* server_port = 9999*/
- rsp_enabled = 1
- rsp_port = 50001
-end
-
-
-/* MC SECTION
-
- This section configures the memory controller
-
- enabled = 0/1
- '0': disable memory controller
- '1': enable memory controller
-
- baseaddr = <hex_value>
- address of first MC register
-
- POC = <hex_value>
- Power On Configuration register
-
- index = <value>
- Index of this memory controller amongst all the memory controllers
-*/
-
-section mc
- enabled = 0
- baseaddr = 0x93000000
- POC = 0x00000008 /* Power on configuration register */
- index = 0
-end
-
-
-/* UART SECTION
-
- This section configures the UARTs
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first UART register for this device
-
-
- channel = <channeltype>:<args>
-
- The channel parameter indicates the source of received UART characters
- and the sink for transmitted UART characters.
-
- The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
- (without quotes).
-
- A) To send/receive characters from a pair of files, use a file
- channel:
-
- channel=file:<rxfile>,<txfile>
-
- B) To create an interactive terminal window, use an xterm channel:
-
- channel=xterm:[<xterm_arg>]*
-
- C) To create a bidirectional tcp socket which one could, for example,
- access via telnet, use a tcp channel:
-
- channel=tcp:<port number>
-
- D) To cause the UART to read/write from existing numeric file
- descriptors, use an fd channel:
-
- channel=fd:<rx file descriptor num>,<tx file descriptor num>
-
- E) To connect the UART to a physical serial port, create a tty
- channel:
-
- channel=tty:device=/dev/ttyS0,baud=9600
-
- irq = <value>
- irq number for this device
-
- 16550 = 0/1
- '0': this device is a UART16450
- '1': this device is a UART16550
-
- jitter = <value>
- in msecs... time to block, -1 to disable it
-
- vapi_id = <hex_value>
- VAPI id of this instance
-*/
-
-section uart
- enabled = 1
- baseaddr = 0x90000000
- irq = 2
- /* channel = "file:uart0.rx,uart0.tx" */
- /* channel = "tcp:10084" */
- channel = "xterm:"
- jitter = -1 /* async behaviour */
- 16550 = 1
-end
-
-
-/* DMA SECTION
-
- This section configures the DMAs
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first DMA register for this device
-
- irq = <value>
- irq number for this device
-
- vapi_id = <hex_value>
- VAPI id of this instance
-*/
-
-section dma
- enabled = 1
- baseaddr = 0x9a000000
- irq = 11
-end
-
-
-/* ETHERNET SECTION
-
- This section configures the ETHERNETs
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first ethernet register for this device
-
- dma = <value>
- which controller is this ethernet "connected" to
-
- irq = <value>
- ethernet mac IRQ level
-
- rtx_type = <value>
- use 0 - file interface, 1 - socket interface
-
- rx_channel = <value>
- DMA channel used for RX
-
- tx_channel = <value>
- DMA channel used for TX
-
- rxfile = "<filename>"
- filename, where to read data from
-
- txfile = "<filename>"
- filename, where to write data to
-
- sockif = "<ifacename>"
- interface name of ethernet socket
-
- vapi_id = <hex_value>
- VAPI id of this instance
-*/
-
-section ethernet
- enabled = 1
- baseaddr = 0x92000000
- /* dma = 0 */
- irq = 4
- rtx_type = "tap"
- tap_dev = "tap0"
- /* tx_channel = 0 */
- /* rx_channel = 1 */
- rxfile = "eth0.rx"
- txfile = "eth0.tx"
- sockif = "eth0"
-end
-
-
-/* GPIO SECTION
-
- This section configures the GPIOs
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first GPIO register for this device
-
- irq = <value>
- irq number for this device
-
- base_vapi_id = <hex_value>
- first VAPI id of this instance
- GPIO uses 8 consecutive VAPI IDs
-*/
-
-section gpio
- enabled = 0
- baseaddr = 0x91000000
- irq = 3
- base_vapi_id = 0x0200
-end
-
-/* VGA SECTION
-
- This section configures the VGA/LCD controller
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first VGA register
-
- irq = <value>
- irq number for this device
-
- refresh_rate = <value>
- number of cycles between screen dumps
-
- filename = "<filename>"
- template name for generated names (e.g. "primary" produces "primary0023.bmp")
-*/
-
-section vga
- enabled = 0
- baseaddr = 0x97100000
- irq = 8
- refresh_rate = 100000
- filename = "primary"
-end
-
-
-/* TICK TIMER SECTION
-
- This section configures tick timer
-
- enabled = 0/1
- whether tick timer is enabled
-*/
-
-section pic
- enabled = 1
- edge_trigger = 1
-end
-
-/* FB SECTION
-
- This section configures the frame buffer
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- base address of frame buffer
-
- paladdr = <hex_value>
- base address of first palette entry
-
- refresh_rate = <value>
- number of cycles between screen dumps
-
- filename = "<filename>"
- template name for generated names (e.g. "primary" produces "primary0023.bmp")
-*/
-
-section fb
- enabled = 0
- baseaddr = 0x97000000
- refresh_rate = 1000000
- filename = "primary"
-end
-
-
-/* KBD SECTION
-
- This section configures the PS/2 compatible keyboard
-
- baseaddr = <hex_value>
- base address of the keyboard device
-
- rxfile = "<filename>"
- filename, where to read data from
-*/
-
-section kbd
- enabled = 0
- irq = 5
- baseaddr = 0x94000000
- rxfile = "kbd.rx"
-end
-
-
-/* ATA SECTION
-
- This section configures the ATA/ATAPI host controller
-
- baseaddr = <hex_value>
- address of first ATA register
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- irq = <value>
- irq number for this device
-
- debug = <value>
- debug level for ata models.
- 0: no debug messages
- 1: verbose messages
- 3: normal messages (more messages than verbose)
- 5: debug messages (normal debug messages)
- 7: flow control messages (debug statemachine flows)
- 9: low priority message (display everything the code does)
-
- dev_type0/1 = <value>
- ata device 0 type
- 0: NO_CONNeCT: none (not connected)
- 1: FILE : simulated harddisk
- 2: LOCAL : local system harddisk
-
- dev_file0/1 = "<filename>"
- filename for simulated ATA device
- valid only if dev_type0 == 1
-
- dev_size0/1 = <value>
- size of simulated hard-disk (in MBytes)
- valid only if dev_type0 == 1
-
- dev_packet0/1 = <value>
- 0: simulated ATA device does NOT implement PACKET command feature set
- 1: simulated ATA device does implement PACKET command feature set
-
- FIXME: irq number
-*/
-
-section ata
- enabled = 0
- baseaddr = 0x9e000000
- irq = 15
-
-end
print_num("flash size ", (ulong)bd->bi_flashsize);
print_num("flash offset ", (ulong)bd->bi_flashoffset);
-#elif defined(CONFIG_NIOS2) || defined(CONFIG_OPENRISC)
+#elif defined(CONFIG_NIOS2)
print_num("flash start", (ulong)bd->bi_flashstart);
print_num("flash size", (ulong)bd->bi_flashsize);
print_num("flash offset", (ulong)bd->bi_flashoffset);
return 0;
}
-#elif defined(CONFIG_OPENRISC)
-
-int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_mem(bd);
- print_bi_flash(bd);
- print_eth_ip_addr();
- print_baudrate();
-
- return 0;
-}
-
#elif defined(CONFIG_ARC)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+++ /dev/null
-CONFIG_OPENRISC=y
-CONFIG_TARGET_OPENRISC_GENERIC=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_NETDEVICES=y
-CONFIG_ETHOC=y
-CONFIG_SYS_NS16550=y
" lwi $r16, [$r16 + (%1)]\n" \
" jr $r16\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16");
-#elif defined(CONFIG_OPENRISC)
-/*
- * r10 holds the pointer to the global_data, r13 is a call-clobbered
- * register
- */
-#define EXPORT_FUNC(f, a, x, ...) \
- asm volatile ( \
-" .globl " #x "\n" \
-#x ":\n" \
-" l.lwz r13, %0(r10)\n" \
-" l.lwz r13, %1(r13)\n" \
-" l.jr r13\n" \
-" l.nop\n" \
- : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r13");
#elif defined(CONFIG_ARC)
/*
* r25 holds the pointer to the global_data. r10 is call clobbered.
+++ /dev/null
-/*
- * (C) Copyright 2011, Stefan Kristiansson, stefan.kristianssons@saunalahti.fi
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * BOARD/CPU
- */
-#define CONFIG_SYS_CLK_FREQ 50000000
-#define CONFIG_SYS_RESET_ADDR 0x00000100
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 0x02000000
-
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define CONFIG_SYS_UART_BASE 0x90000000
-#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_UART_BAUD 115200
-
-#define CONFIG_BOARD_NAME "OpenRISC Generic"
-
-#define CONFIG_SYS_MAX_FLASH_SECT 0
-
-/*
- * SERIAL
- */
-# define CONFIG_SYS_NS16550_SERIAL
-# define CONFIG_SYS_NS16550_REG_SIZE 1
-# define CONFIG_CONS_INDEX 1
-# define CONFIG_SYS_NS16550_COM1 (0x90000000)
-# define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
-
-#define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE}
-#define CONSOLE_ARG "console=console=ttyS0,115200\0"
-
-/*
- * Ethernet
- */
-#define CONFIG_SYS_ETHOC_BASE 0x92000000
-
-#define CONFIG_BOOTFILE "boot.img"
-#define CONFIG_LOADADDR 0x100000 /* 1MB mark */
-
-/*
- * TIMER
- */
-#define CONFIG_SYS_OPENRISC_TMR_HZ 100
-
-/*
- * Memory organisation:
- *
- * RAM start ---------------------------
- * | ... |
- * ---------------------------
- * | Stack |
- * ---------------------------
- * | Global data |
- * ---------------------------
- * | Environment |
- * ---------------------------
- * | Monitor |
- * RAM end ---------------------------
- */
-/* We're running in RAM */
-#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_SDRAM_SIZE - \
- CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment, 128KB */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
-
-/*
- * Global data object and stack pointer
- */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_ENV_ADDR \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_GBL_DATA_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_STACK_LENGTH 0x10000 /* 64KB */
-#define CONFIG_SYS_MALLOC_LEN 0x400000 /* 4MB */
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_INIT_SP_OFFSET \
- - CONFIG_SYS_STACK_LENGTH \
- - CONFIG_SYS_MALLOC_LEN)
-/*
- * MISC
- */
-#define CONFIG_SYS_LONGHELP /* Provide extended help */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
-#define CONFIG_SYS_MAXARGS 16 /* Max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + \
- 16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x2000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP_ADDR - 0x20000)
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_BSP
-
-#define CONFIG_LMB
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#endif /* __CONFIG_H */
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