static char *cpu_warning = "\n " \
"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
-static int check_CPU (long clock, uint pvr, uint immr)
+static int check_CPU(long clock, uint pvr, uint immr)
{
char *id_str =
NULL;
id_str =
"PC866x"; /* Unknown chip from MPC866 family */
break;
- case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
+ case 0x09000000:
+ pre = 'M'; mid = suf = ""; m = 1;
if (id_str == NULL)
id_str = "PC885"; /* 870/875/880/885 */
break;
- default: suf = NULL; break;
+ default:
+ suf = NULL;
+ break;
}
if (id_str == NULL)
id_str = "PC86x"; /* Unknown 86x chip */
if (suf)
- printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
+ printf("%c%s%sZPnn%s", pre, id_str, mid, suf);
else
- printf ("unknown M%s (0x%08x)", id_str, k);
+ printf("unknown M%s (0x%08x)", id_str, k);
- printf (" at %s MHz: ", strmhz (buf, clock));
+ printf(" at %s MHz: ", strmhz(buf, clock));
print_size(checkicache(), " I-Cache ");
print_size(checkdcache(), " D-Cache");
out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
- printf (" FEC present");
+ printf(" FEC present");
- if (!m) {
- puts (cpu_warning);
- }
+ if (!m)
+ puts(cpu_warning);
- putc ('\n');
+ putc('\n');
return 0;
}
/* ------------------------------------------------------------------------- */
-int checkcpu (void)
+int checkcpu(void)
{
ulong clock = gd->cpu_clk;
- uint immr = get_immr (0); /* Return full IMMR contents */
- uint pvr = get_pvr ();
+ uint immr = get_immr(0); /* Return full IMMR contents */
+ uint pvr = get_pvr();
- puts ("CPU: ");
+ puts("CPU: ");
- return check_CPU (clock, pvr, immr);
+ return check_CPU(clock, pvr, immr);
}
/* ------------------------------------------------------------------------- */
/* L1 i-cache */
-int checkicache (void)
+int checkicache(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
- u32 cacheon = rd_ic_cst () & IDC_ENABLED;
+ u32 cacheon = rd_ic_cst() & IDC_ENABLED;
/* probe in flash memoryarea */
u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
- wr_ic_cst (IDC_UNALL);
- wr_ic_cst (IDC_INVALL);
- wr_ic_cst (IDC_DISABLE);
+ wr_ic_cst(IDC_UNALL);
+ wr_ic_cst(IDC_INVALL);
+ wr_ic_cst(IDC_DISABLE);
__asm__ volatile ("isync");
- while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
- wr_ic_adr (k);
- wr_ic_cst (IDC_LDLCK);
+ while (!((m = rd_ic_cst()) & IDC_CERR2)) {
+ wr_ic_adr(k);
+ wr_ic_cst(IDC_LDLCK);
__asm__ volatile ("isync");
lines++;
- k += 0x10; /* the number of bytes in a cacheline */
+ k += 0x10; /* the number of bytes in a cacheline */
}
- wr_ic_cst (IDC_UNALL);
- wr_ic_cst (IDC_INVALL);
+ wr_ic_cst(IDC_UNALL);
+ wr_ic_cst(IDC_INVALL);
if (cacheon)
- wr_ic_cst (IDC_ENABLE);
+ wr_ic_cst(IDC_ENABLE);
else
- wr_ic_cst (IDC_DISABLE);
+ wr_ic_cst(IDC_DISABLE);
__asm__ volatile ("isync");
/* L1 d-cache */
/* call with cache disabled */
-int checkdcache (void)
+int checkdcache(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
- u32 cacheon = rd_dc_cst () & IDC_ENABLED;
+ u32 cacheon = rd_dc_cst() & IDC_ENABLED;
/* probe in flash memoryarea */
u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
- wr_dc_cst (IDC_UNALL);
- wr_dc_cst (IDC_INVALL);
- wr_dc_cst (IDC_DISABLE);
+ wr_dc_cst(IDC_UNALL);
+ wr_dc_cst(IDC_INVALL);
+ wr_dc_cst(IDC_DISABLE);
- while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
- wr_dc_adr (k);
- wr_dc_cst (IDC_LDLCK);
+ while (!((m = rd_dc_cst()) & IDC_CERR2)) {
+ wr_dc_adr(k);
+ wr_dc_cst(IDC_LDLCK);
lines++;
k += 0x10; /* the number of bytes in a cacheline */
}
- wr_dc_cst (IDC_UNALL);
- wr_dc_cst (IDC_INVALL);
+ wr_dc_cst(IDC_UNALL);
+ wr_dc_cst(IDC_INVALL);
if (cacheon)
- wr_dc_cst (IDC_ENABLE);
+ wr_dc_cst(IDC_ENABLE);
else
- wr_dc_cst (IDC_DISABLE);
+ wr_dc_cst(IDC_DISABLE);
return lines << 4;
};
/* ------------------------------------------------------------------------- */
-void upmconfig (uint upm, uint * table, uint size)
+void upmconfig(uint upm, uint *table, uint size)
{
uint i;
uint addr = 0;
/* ------------------------------------------------------------------------- */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong msr, addr;
/* Interrupts and MMU off */
__asm__ volatile ("mtspr 81, 0");
- __asm__ volatile ("mfmsr %0":"=r" (msr));
+ __asm__ volatile ("mfmsr %0" : "=r" (msr));
msr &= ~0x1030;
- __asm__ volatile ("mtmsr %0"::"r" (msr));
+ __asm__ volatile ("mtmsr %0" : : "r" (msr));
/*
* Trying to execute the next instruction at a non-existing address
addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
- * - sizeof (ulong) is usually a valid address. Better pick an address
- * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
+ * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
+ * Better pick an address known to be invalid on your system and assign
+ * it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
- addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
+ addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
#endif
- ((void (*)(void)) addr) ();
+ ((void (*)(void)) addr)();
return 1;
}
*
* See sections 14.2 and 14.6 of the User's Manual
*/
-unsigned long get_tbclk (void)
+unsigned long get_tbclk(void)
{
- uint immr = get_immr (0); /* Return full IMMR contents */
+ uint immr = get_immr(0); /* Return full IMMR contents */
immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
ulong oscclk, factor, pll;
if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
- return (gd->cpu_clk / 16);
+ return gd->cpu_clk / 16;
pll = in_be32(&immap->im_clkrst.car_plprcr);
* (PDF + 1) * 2^S
*
*/
- factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
- (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
+ factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
+ (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
oscclk = gd->cpu_clk / factor;
if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
factor > 2)
- return (oscclk / 4);
+ return oscclk / 4;
- return (oscclk / 16);
+ return oscclk / 16;
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
-void watchdog_reset (void)
+void watchdog_reset(void)
{
- int re_enable = disable_interrupts ();
+ int re_enable = disable_interrupts();
reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
if (re_enable)
- enable_interrupts ();
+ enable_interrupts();
}
#endif /* CONFIG_WATCHDOG */
out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
#if defined(CONFIG_WATCHDOG)
- reset_8xx_watchdog (immr);
+ reset_8xx_watchdog(immr);
#endif /* CONFIG_WATCHDOG */
/* SIUMCR - contains debug pin configuration (11-6) */
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
- return (0);
+ return 0;
}
void ft_cpu_setup(void *blob, bd_t *bd)
{
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", get_tbclk(), 1);
+ "timebase-frequency", get_tbclk(), 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "bus-frequency", bd->bi_busfreq, 1);
+ "bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "clock-frequency", bd->bi_intfreq, 1);
+ "clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
- gd->arch.brg_clk, 1);
+ gd->arch.brg_clk, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#define PKT_MAXBLR_SIZE 1520
#ifdef __GNUC__
-static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
+static char txbuf[DBUF_LENGTH] __aligned(8);
#else
#error txbuf must be aligned.
#endif
*/
struct common_buf_desc {
- cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
- cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
+ cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
+ cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
};
static struct common_buf_desc __iomem *rtx;
static int fec_send(struct eth_device *dev, void *packet, int length);
-static int fec_recv(struct eth_device* dev);
-static int fec_init(struct eth_device* dev, bd_t * bd);
-static void fec_halt(struct eth_device* dev);
+static int fec_recv(struct eth_device *dev);
+static int fec_init(struct eth_device *dev, bd_t *bd);
+static void fec_halt(struct eth_device *dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static void __mii_init(void);
#endif
int fec_initialize(bd_t *bis)
{
- struct eth_device* dev;
+ struct eth_device *dev;
struct ether_fcc_info_s *efis;
int i;
for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
-
dev = malloc(sizeof(*dev));
if (dev == NULL)
hang();
/* for FEC1 make sure that the name of the interface is the same
as the old one for compatibility reasons */
- if (i == 0) {
+ if (i == 0)
strcpy(dev->name, "FEC");
- } else {
- sprintf (dev->name, "FEC%d",
+ else
+ sprintf(dev->name, "FEC%d",
ether_fcc_info[i].ether_index + 1);
- }
efis = ðer_fcc_info[i];
udelay(1);
j++;
}
- if (j>=TOUT_LOOP) {
+ if (j >= TOUT_LOOP)
printf("TX not ready\n");
- }
out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
udelay(1);
j++;
}
- if (j>=TOUT_LOOP) {
+ if (j >= TOUT_LOOP)
printf("TX timeout\n");
- }
+
/* return only status bits */;
rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
return rc;
}
-static int fec_recv (struct eth_device *dev)
+static int fec_recv(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
fec_t __iomem *fecp =
#endif /* CONFIG_ETHER_ON_FEC1 */
} else if (fecidx == 1) {
-
#if defined(CONFIG_ETHER_ON_FEC2)
#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
#endif /* CONFIG_MPC885_FAMILY */
#endif /* CONFIG_ETHER_ON_FEC2 */
-
}
}
out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
(i < FEC_RESET_DELAY); ++i)
- udelay (1);
+ udelay(1);
if (i == FEC_RESET_DELAY)
return -1;
return 0;
}
-static int fec_init (struct eth_device *dev, bd_t * bd)
+static int fec_init(struct eth_device *dev, bd_t *bd)
{
struct ether_fcc_info_s *efis = dev->priv;
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
#endif
if (fec_reset(fecp) < 0)
- printf ("FEC_RESET_DELAY timeout\n");
+ printf("FEC_RESET_DELAY timeout\n");
/* We use strictly polling mode only
*/
out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
/*
- * Setup Buffers and Buffer Desriptors
+ * Setup Buffers and Buffer Descriptors
*/
rxIdx = 0;
txIdx = 0;
/*
* Setup the pin configuration of the FEC
*/
- fec_pin_init (efis->ether_index);
+ fec_pin_init(efis->ether_index);
rxIdx = 0;
txIdx = 0;
/*
* wait for the PHY to wake up after reset
*/
- efis->actual_phy_addr = mii_discover_phy (dev);
+ efis->actual_phy_addr = mii_discover_phy(dev);
if (efis->actual_phy_addr == -1) {
- printf ("Unable to discover phy!\n");
+ printf("Unable to discover phy!\n");
return -1;
}
#else
/*
* adapt the RMII speed to the speed of the phy
*/
- if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
- fec_100Mbps (dev);
- } else {
- fec_10Mbps (dev);
- }
+ if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
+ fec_100Mbps(dev);
+ else
+ fec_10Mbps(dev);
#endif
#if defined(CONFIG_MII)
/*
* adapt to the half/full speed settings
*/
- if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
- fec_full_duplex (dev);
- } else {
- fec_half_duplex (dev);
- }
+ if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
+ fec_full_duplex(dev);
+ else
+ fec_half_duplex(dev);
#endif
/* And last, try to fill Rx Buffer Descriptors */
}
-static void fec_halt(struct eth_device* dev)
+static void fec_halt(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
fec_t __iomem *fecp =
out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
(i < FEC_RESET_DELAY); ++i)
- udelay (1);
+ udelay(1);
if (i == FEC_RESET_DELAY) {
- printf ("FEC_RESET_DELAY timeout\n");
+ printf("FEC_RESET_DELAY timeout\n");
return;
}
}
mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
- return (mii_reply & 0xffff); /* data read from phy */
+ return mii_reply & 0xffff; /* data read from phy */
}
#endif
}
}
}
- if (phyaddr < 0) {
+ if (phyaddr < 0)
printf("No PHY device found.\n");
- }
+
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
if (fec_reset(fecp) < 0)
- printf ("FEC_RESET_DELAY timeout\n");
+ printf("FEC_RESET_DELAY timeout\n");
/* We use strictly polling mode only
*/
out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
}
-void mii_init (void)
+void mii_init(void)
{
int i;
DECLARE_GLOBAL_DATA_PTR;
-int
-do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_siuinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
return 0;
}
-int
-do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_memcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
return 0;
}
-int
-do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_carinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
car8xx_t __iomem *car = &immap->im_clkrst;
static int counter;
-static void
-header(void)
+static void header(void)
{
char *data = "\
-------------------------------- --------------------------------\
printf("%.79s\n", data);
}
-static void binary (char *label, uint value, int nbits)
+static void binary(char *label, uint value, int nbits)
{
uint mask = 1 << (nbits - 1);
int i, second = (counter++ % 2);
if (second)
- putc (' ');
- puts (label);
+ putc(' ');
+ puts(label);
for (i = 32 + 1; i != nbits; i--)
- putc (' ');
+ putc(' ');
while (mask != 0) {
if (value & mask)
- putc ('1');
+ putc('1');
else
- putc ('0');
+ putc('0');
mask >>= 1;
}
if (second)
- putc ('\n');
+ putc('\n');
}
#define PA_NBITS 16
#define PC_NBITS 12
#define PD_NBITS 13
-int
-do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_iopinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
iop8xx_t __iomem *iop = &immap->im_ioport;
uint __iomem *R;
counter = 0;
- header ();
+ header();
/*
* Ports A & B
binary("PA_DAT", in_be16(l++), PA_NBITS);
binary("PB_DAT", in_be32(R++), PB_NBITS);
- header ();
+ header();
/*
* Ports C & D
binary("PD_DAT", in_be16(r++), PD_NBITS);
binary("PC_INT", in_be16(l++), PC_NBITS);
- header ();
+ header();
return 0;
}
* this needs a clean up for smaller tighter code
* use *uint and set the address based on cmd + port
*/
-int
-do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_iopset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
uint rcode = 0;
iopin_t iopin;
- static uint port = 0;
- static uint pin = 0;
- static uint value = 0;
+ static uint port;
+ static uint pin;
+ static uint value;
static enum {
DIR,
PAR,
} cmd = DAT;
if (argc != 5) {
- puts ("iopset PORT PIN CMD VALUE\n");
+ puts("iopset PORT PIN CMD VALUE\n");
return 1;
}
port = argv[1][0] - 'A';
port -= 0x20;
if (port > 3)
rcode = 1;
- pin = simple_strtol (argv[2], NULL, 10);
+ pin = simple_strtol(argv[2], NULL, 10);
if (pin > 31)
rcode = 1;
cmd = INT;
break;
default:
- printf ("iopset: unknown command %s\n", argv[3]);
+ printf("iopset: unknown command %s\n", argv[3]);
rcode = 1;
}
if (argv[4][0] == '1')
switch (cmd) {
case DIR:
if (value)
- iopin_set_out (&iopin);
+ iopin_set_out(&iopin);
else
- iopin_set_in (&iopin);
+ iopin_set_in(&iopin);
break;
case PAR:
if (value)
- iopin_set_ded (&iopin);
+ iopin_set_ded(&iopin);
else
- iopin_set_gen (&iopin);
+ iopin_set_gen(&iopin);
break;
case SOR:
if (value)
- iopin_set_opt2 (&iopin);
+ iopin_set_opt2(&iopin);
else
- iopin_set_opt1 (&iopin);
+ iopin_set_opt1(&iopin);
break;
case ODR:
if (value)
- iopin_set_odr (&iopin);
+ iopin_set_odr(&iopin);
else
- iopin_set_act (&iopin);
+ iopin_set_act(&iopin);
break;
case DAT:
if (value)
- iopin_set_high (&iopin);
+ iopin_set_high(&iopin);
else
- iopin_set_low (&iopin);
+ iopin_set_low(&iopin);
break;
case INT:
if (value)
- iopin_set_falledge (&iopin);
+ iopin_set_falledge(&iopin);
else
- iopin_set_anyedge (&iopin);
+ iopin_set_anyedge(&iopin);
break;
}
-
}
return rcode;
}
-static void prbrg (int n, uint val)
+static void prbrg(int n, uint val)
{
uint extc = (val >> 14) & 3;
uint cd = (val & CPM_BRG_CD_MASK) >> 1;
ulong clock = gd->cpu_clk;
- printf ("BRG%d:", n);
+ printf("BRG%d:", n);
if (val & CPM_BRG_RST)
- puts (" RESET");
+ puts(" RESET");
else
- puts (" ");
+ puts(" ");
if (val & CPM_BRG_EN)
- puts (" ENABLED");
+ puts(" ENABLED");
else
- puts (" DISABLED");
+ puts(" DISABLED");
- printf (" EXTC=%d", extc);
+ printf(" EXTC=%d", extc);
if (val & CPM_BRG_ATB)
- puts (" ATB");
+ puts(" ATB");
else
- puts (" ");
+ puts(" ");
- printf (" DIVIDER=%4d", cd);
+ printf(" DIVIDER=%4d", cd);
if (extc == 0 && cd != 0) {
uint baudrate;
else
baudrate = clock / (cd + 1);
- printf ("=%6d bps", baudrate);
+ printf("=%6d bps", baudrate);
} else {
- puts (" ");
+ puts(" ");
}
if (val & CPM_BRG_DIV16)
- puts (" DIV16");
+ puts(" DIV16");
else
- puts (" ");
+ puts(" ");
- putc ('\n');
+ putc('\n');
}
-int
-do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_brginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immap->im_cpm;
static struct interrupt_action cpm_vecs[CPMVEC_NR];
static struct interrupt_action irq_vecs[NR_IRQS];
-static void cpm_interrupt_init (void);
-static void cpm_interrupt (void *regs);
+static void cpm_interrupt_init(void);
+static void cpm_interrupt(void *regs);
/************************************************************************/
-int interrupt_init_cpu (unsigned *decrementer_count)
+int interrupt_init_cpu(unsigned *decrementer_count)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
- *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
+ *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
/* disable all interrupts */
out_be32(&immr->im_siu_conf.sc_simask, 0);
/* Configure CPM interrupts */
- cpm_interrupt_init ();
+ cpm_interrupt_init();
- return (0);
+ return 0;
}
/************************************************************************/
/*
* Handle external interrupts
*/
-void external_interrupt (struct pt_regs *regs)
+void external_interrupt(struct pt_regs *regs)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
int irq;
}
if (irq_vecs[irq].handler != NULL) {
- irq_vecs[irq].handler (irq_vecs[irq].arg);
+ irq_vecs[irq].handler(irq_vecs[irq].arg);
} else {
- printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
- irq, vec);
+ printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
+ irq, vec);
/* turn off the bogus interrupt to avoid it from now */
simask &= ~v_bit;
}
/*
* CPM interrupt handler
*/
-static void cpm_interrupt (void *regs)
+static void cpm_interrupt(void *regs)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
uint vec;
(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
} else {
clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
- printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
+ printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
}
/*
* After servicing the interrupt,
* to do is ACK it and return. This is a no-op function so we don't
* need any special tests in the interrupt handler.
*/
-static void cpm_error_interrupt (void *dummy)
+static void cpm_error_interrupt(void *dummy)
{
}
/*
* Install and free an interrupt handler
*/
-void irq_install_handler (int vec, interrupt_handler_t * handler,
- void *arg)
+void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
vec &= 0xffff;
- if (cpm_vecs[vec].handler != NULL) {
- printf ("CPM interrupt 0x%x replacing 0x%x\n",
- (uint) handler,
- (uint) cpm_vecs[vec].handler);
- }
+ if (cpm_vecs[vec].handler != NULL)
+ printf("CPM interrupt 0x%x replacing 0x%x\n",
+ (uint)handler, (uint)cpm_vecs[vec].handler);
cpm_vecs[vec].handler = handler;
cpm_vecs[vec].arg = arg;
setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
} else {
/* SIU interrupt */
- if (irq_vecs[vec].handler != NULL) {
- printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
- vec,
- (uint) handler,
- (uint) cpm_vecs[vec].handler);
- }
+ if (irq_vecs[vec].handler != NULL)
+ printf("SIU interrupt %d 0x%x replacing 0x%x\n",
+ vec, (uint)handler, (uint)cpm_vecs[vec].handler);
irq_vecs[vec].handler = handler;
irq_vecs[vec].arg = arg;
setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
}
}
-void irq_free_handler (int vec)
+void irq_free_handler(int vec)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
/************************************************************************/
-static void cpm_interrupt_init (void)
+static void cpm_interrupt_init(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
uint cicr;
/*
* Install the error handler.
*/
- irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
+ irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
/*
* Install the cpm interrupt handler
*/
- irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
+ irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
}
/************************************************************************/
* with interrupts disabled.
* Trivial implementation - no need to be really accurate.
*/
-void timer_interrupt_cpu (struct pt_regs *regs)
+void timer_interrupt_cpu(struct pt_regs *regs)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
* other useful registers
*/
- printf ("\nSystem Configuration registers\n"
+ printf("\nSystem Configuration registers\n"
"\tIMMR\t0x%08X\n", get_immr(0));
printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
static void serial_setdivisor(cpm8xx_t __iomem *cp)
{
- int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
+ int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate;
- if(divisor/16>0x1000) {
+ if (divisor / 16 > 0x1000) {
/* bad divisor, assume 50MHz clock and 9600 baud */
- divisor=(50*1000*1000 + 8*9600)/16/9600;
+ divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
}
#ifdef CONFIG_SYS_BRGCLK_PRESCALE
* as serial console interface.
*/
-static void smc_setbrg (void)
+static void smc_setbrg(void)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &(im->im_cpm);
serial_setdivisor(cp);
}
-static int smc_init (void)
+static int smc_init(void)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
smc_t __iomem *sp;
out_8(&sp->smc_smce, 0xff);
/* Set up the baud rate generator */
- smc_setbrg ();
+ smc_setbrg();
/* Make the first buffer the only buffer. */
setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
/* Enable transmitter/receiver. */
setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
- return (0);
+ return 0;
}
-static void
-smc_putc(const char c)
+static void smc_putc(const char c)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
struct serialbuffer __iomem *rtx;
if (c == '\n')
- smc_putc ('\r');
+ smc_putc('\r');
rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
-static void
-smc_puts (const char *s)
+static void smc_puts(const char *s)
{
- while (*s) {
- smc_putc (*s++);
- }
+ while (*s)
+ smc_putc(*s++);
}
-static int
-smc_getc(void)
+static int smc_getc(void)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
/* Wait for character to show up. */
while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
/* the characters are read one by one,
* use the rxindex to know the next char to deliver
setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
}
out_be32(&rtx->rxindex, rxindex);
- return(c);
+ return c;
}
-static int
-smc_tstc(void)
+static int smc_tstc(void)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
}
-struct serial_device serial_smc_device =
-{
+struct serial_device serial_smc_device = {
.name = "serial_smc",
.start = smc_init,
.stop = NULL,
{
uint divider = 0;
- switch((sccr&SCCR_DFBRG11)>>11){
- case 0:
- divider = 1;
- break;
- case 1:
- divider = 4;
- break;
- case 2:
- divider = 16;
- break;
- case 3:
- divider = 64;
- break;
+ switch ((sccr & SCCR_DFBRG11) >> 11) {
+ case 0:
+ divider = 1;
+ break;
+ case 1:
+ divider = 4;
+ break;
+ case 2:
+ divider = 16;
+ break;
+ case 3:
+ divider = 64;
+ break;
}
- gd->arch.brg_clk = gd->cpu_clk/divider;
+ gd->arch.brg_clk = gd->cpu_clk / divider;
}
/*
* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
*/
-int get_clocks (void)
+int get_clocks(void)
{
- uint immr = get_immr (0); /* Return full IMMR contents */
+ uint immr = get_immr(0); /* Return full IMMR contents */
immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
uint sccr = in_be32(&immap->im_clkrst.car_sccr);
/*
get_brgclk(sccr);
- return (0);
+ return 0;
}
/* -------------------
* Function prototypes
* ------------------- */
-void spi_init (void);
-
-ssize_t spi_read (uchar *, int, uchar *, int);
-ssize_t spi_write (uchar *, int, uchar *, int);
-ssize_t spi_xfer (size_t);
+ssize_t spi_xfer(size_t);
/* -------------------
* Variables
* Initially we place the RX and TX buffers at a fixed location in DPRAM!
* ---------------------------------------------------------------------- */
static uchar *rxbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
[CONFIG_SYS_SPI_INIT_OFFSET];
static uchar *txbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
[CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
/* **************************************************************************
* return: ---
*
* *********************************************************************** */
-void spi_init_f (void)
+void spi_init_f(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
* PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
* PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
* PBODR[30] = 0 [0x00000002] -> active output: SPICLK
- * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
+ * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
* ---------------------------------------------- */
clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
* return: ---
*
* *********************************************************************** */
-void spi_init_r (void)
+void spi_init_r(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
/* Allocate memory for RX and TX buffers */
- rxbuf = (uchar *) malloc (MAX_BUFFER);
- txbuf = (uchar *) malloc (MAX_BUFFER);
+ rxbuf = (uchar *)malloc(MAX_BUFFER);
+ txbuf = (uchar *)malloc(MAX_BUFFER);
out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
/****************************************************************************
* Function: spi_write
**************************************************************************** */
-ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
{
int i;
*txbuf = SPI_EEPROM_RDSR; /* read status */
txbuf[1] = 0;
spi_xfer(2);
- if (!(rxbuf[1] & 1)) {
+ if (!(rxbuf[1] & 1))
break;
- }
udelay(1000);
}
- if (i >= 1000) {
- printf ("*** spi_write: Time out while writing!\n");
- }
+ if (i >= 1000)
+ printf("*** spi_write: Time out while writing!\n");
return len;
}
/****************************************************************************
* Function: spi_read
**************************************************************************** */
-ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
{
memset(rxbuf, 0, MAX_BUFFER);
memset(txbuf, 0, MAX_BUFFER);
/****************************************************************************
* Function: spi_xfer
**************************************************************************** */
-ssize_t spi_xfer (size_t count)
+ssize_t spi_xfer(size_t count)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
* Wait for SPI transmit to get out
* or time out (1 second = 1000 ms)
* -------------------------------- */
- for (tm=0; tm<1000; ++tm) {
+ for (tm = 0; tm < 1000; ++tm) {
if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
break;
if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
break;
- udelay (1000);
- }
- if (tm >= 1000) {
- printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
+ udelay(1000);
}
+ if (tm >= 1000)
+ printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
/* Clear CS for device */
setbits_be32(&cp->cp_pbdat, 0x0001);
if (cnt++ % 7 == 0)
printf("\n");
printf("%08lX ", i);
- if (cnt > 32) break;
+ if (cnt > 32)
+ break;
sp = (unsigned long *)*sp;
}
printf("\n");
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
- regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
- regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
- regs->msr&MSR_IR ? 1 : 0,
- regs->msr&MSR_DR ? 1 : 0);
+ regs->msr, regs->msr & MSR_EE ? 1 : 0,
+ regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
+ regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
+ regs->msr & MSR_DR ? 1 : 0);
printf("\n");
for (i = 0; i < 32; i++) {
if ((i % 8) == 0)
- {
printf("GPR%02d: ", i);
- }
printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7)
- {
printf("\n");
- }
}
}
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+ panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
}
void MachineCheckException(struct pt_regs *regs)
{
- unsigned long fixup;
+ unsigned long fixup = search_exception_table(regs->nip);
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
* the PCI exception handler.
*/
- if ((fixup = search_exception_table(regs->nip)) != 0) {
+ if (fixup != 0) {
regs->nip = fixup;
return;
}
printf("Machine check in kernel mode.\n");
printf("Caused by (from msr): ");
- printf("regs %p ",regs);
- switch( regs->msr & 0x000F0000) {
- case (0x80000000>>12):
+ printf("regs %p ", regs);
+ switch (regs->msr & 0x000F0000) {
+ case (0x80000000 >> 12):
printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
break;
- case (0x80000000>>13):
+ case (0x80000000 >> 13):
printf("Transfer error ack signal\n");
break;
- case (0x80000000>>14):
+ case (0x80000000 >> 14):
printf("Data parity signal\n");
break;
- case (0x80000000>>15):
+ case (0x80000000 >> 15):
printf("Address parity signal\n");
break;
default:
void DebugException(struct pt_regs *regs)
{
- printf("Debugger trap at @ %lx\n", regs->nip );
- show_regs(regs);
+ printf("Debugger trap at @ %lx\n", regs->nip);
+ show_regs(regs);
}
/* Probe an address by reading. If not present, return -1, otherwise
#define IOPIN_PORTC 2
#define IOPIN_PORTD 3
-static __inline__ void
-iopin_set_high(iopin_t *iopin)
+static inline void iopin_set_high(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ void
-iopin_set_low(iopin_t *iopin)
+static inline void iopin_set_low(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ uint
-iopin_is_high(iopin_t *iopin)
+static inline uint iopin_is_high(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ uint
-iopin_is_low(iopin_t *iopin)
+static inline uint iopin_is_low(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ void
-iopin_set_out(iopin_t *iopin)
+static inline void iopin_set_out(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ void
-iopin_set_in(iopin_t *iopin)
+static inline void iopin_set_in(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ uint
-iopin_is_out(iopin_t *iopin)
+static inline uint iopin_is_out(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ uint
-iopin_is_in(iopin_t *iopin)
+static inline uint iopin_is_in(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ void
-iopin_set_odr(iopin_t *iopin)
+static inline void iopin_set_odr(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ void
-iopin_set_act(iopin_t *iopin)
+static inline void iopin_set_act(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ uint
-iopin_is_odr(iopin_t *iopin)
+static inline uint iopin_is_odr(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ uint
-iopin_is_act(iopin_t *iopin)
+static inline uint iopin_is_act(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ void
-iopin_set_ded(iopin_t *iopin)
+static inline void iopin_set_ded(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ void
-iopin_set_gen(iopin_t *iopin)
+static inline void iopin_set_gen(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ uint
-iopin_is_ded(iopin_t *iopin)
+static inline uint iopin_is_ded(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ uint
-iopin_is_gen(iopin_t *iopin)
+static inline uint iopin_is_gen(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ void
-iopin_set_opt2(iopin_t *iopin)
+static inline void iopin_set_opt2(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ void
-iopin_set_opt1(iopin_t *iopin)
+static inline void iopin_set_opt1(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ uint
-iopin_is_opt2(iopin_t *iopin)
+static inline uint iopin_is_opt2(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ uint
-iopin_is_opt1(iopin_t *iopin)
+static inline uint iopin_is_opt1(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ void
-iopin_set_falledge(iopin_t *iopin)
+static inline void iopin_set_falledge(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ void
-iopin_set_anyedge(iopin_t *iopin)
+static inline void iopin_set_anyedge(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
}
}
-static __inline__ uint
-iopin_is_falledge(iopin_t *iopin)
+static inline uint iopin_is_falledge(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
return 0;
}
-static __inline__ uint
-iopin_is_anyedge(iopin_t *iopin)
+static inline uint iopin_is_anyedge(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
*
* This file contains structures and information for the communication
* processor channels. Some CPM control and status is available
- * throught the MPC8xx internal memory map. See immap.h for details.
+ * through the MPC8xx internal memory map. See immap.h for details.
* This file only contains what I need for the moment, not the total
* CPM capabilities. I (or someone else) will add definitions as they
* are needed. -- Dan
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
-#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
-#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x) ((x) &0xF)
+#define SPMODE_LEN(x) ((((x) - 1) & 0xF) << 4)
+#define SPMODE_PM(x) ((x) & 0xF)
/* HDLC parameter RAM.
*/
#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
-extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
+void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
/* CPM interrupt configuration vector.
*/
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
-#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
+#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
#define CICR_IEN ((uint)0x00000080) /* Int. enable */
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
projects / u-boot / commitdiff