reset_failed:
b reset_failed
-
+
/* set up the platform, once the cpu has been initialized */
.globl platformsetup
platformsetup:
* itself should be performed in cpu/arm<>/start.S
* This function affects only the core module or board settings
*/
-
+
#ifdef CONFIG_CM_INIT
/* CM has an initialization register
* - bits in it are wired into test-chip pins to force
* reset defaults
* - may need to change its contents for U-Boot
*/
-
+
/* set the desired CM specific value */
mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
-
+
#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
orr r2,r2,#CMMASK_INIT_102
#else
-
+
#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
!defined (CONFIG_CM940T)
-
+
#ifdef CONFIG_CM_MULTIPLE_SSRAM
/* set simple mapping */
and r2,r2,#CMMASK_MAP_SIMPLE
#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
-
+
#ifdef CONFIG_CM_TCRAM
/* disable TCRAM */
and r2,r2,#CMMASK_TCRAM_DISABLE
#endif /* #ifdef CONFIG_CM_TCRAM */
-
+
#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
defined (CONFIG_CM1136JF_S)
and r2,r2,#CMMASK_LE
-
+
#endif /* cpu with little endian initialization */
-
+
orr r2,r2,#CMMASK_CMxx6_COMMON
-
+
#endif /* CMxx6 code */
-
+
#endif /* ARM102xxE value */
/* read CM_INIT */
and r3,r1,r2
cmp r3,r2
beq init_reg_OK
-
+
/* lock for change */
mov r3, #CMVAL_LOCK
and r3,r3,#CMMASK_LOCK
str r1, [r0, #OS_INIT]
mov r1, #CMVAL_UNLOCK
str r1, [r0, #OS_LOCK]
-
+
/* soft reset so new values used */
b reset_cpu
-
+
init_reg_OK:
-
+
#endif /* CONFIG_CM_INIT */
-
+
mov pc, lr
-
+
#ifdef CONFIG_CM_SPD_DETECT
/* Fast memory is available for the DRAM data
* - ensure it has been transferred, then summarize the data
/* set up SDRAM info */
/* - based on example code from the CM User Guide */
mov r0, #CM_BASE
-
+
readspdbit:
ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
and r1, r1, #0x20 /* mask SPD bit (5) */
cmp r1, #0x20 /* test if set */
bne readspdbit
-
+
setupsdram:
add r0, r0, #OS_SPD /* address the copy of the SDP data */
ldrb r1, [r0, #3] /* number of row address lines */
bne not16
mov r6, #0x2 /* store size and CAS latency of 2 */
b writesize
-
+
not16:
cmp r5, #0x20 /* is it 32MB? */
bne not32
mov r6, #0x6
b writesize
-
+
not32:
cmp r5, #0x40 /* is it 64MB? */
bne not64
mov r6, #0xa
b writesize
-
+
not64:
cmp r5, #0x80 /* is it 128MB? */
bne not128
mov r6, #0xe
b writesize
-
+
not128:
/* if it is none of these sizes then it is either 256MB, or
* there is no SDRAM fitted so default to 256MB
*/
mov r6, #0x12
-
+
writesize:
mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
orr r2, r1, r2, ASL#12 /* OR in column address lines */
orr r3, r2, r3, ASL#16 /* OR in number of banks */
orr r6, r6, r3 /* OR in size and CAS latency */
str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
-
+
#endif /* #ifdef CONFIG_CM_SPD_DETECT */
-
+
ldmfd r13!,{r4-r6,pc} /* back to caller */
#ifdef CONFIG_CM_REMAP
.globl cm_remap
cm_remap:
stmfd r13!,{r4-r10,lr}
-
+
mov r0, #CM_BASE
ldr r1, [r0, #OS_CTRL]
orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
str r1, [r0, #OS_CTRL]
-
+
/* Now 0x00000000 is writeable, replace the vectors */
ldr r0, =_start /* r0 <- start of vectors */
ldr r2, =_armboot_start /* r2 <- past vectors */
sub r1,r1,r1 /* destination 0x00000000 */
-
+
copy_vec:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
ble copy_vec
-
+
ldmfd r13!,{r4-r10,pc} /* back to caller */
-
+
#endif /* #ifdef CONFIG_CM_REMAP */
#define CFG_MEMTEST_END 0x10000000
#define CFG_HZ 1000
#define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
-#define CFG_TIMERBASE 0x13000100 /* Timer1 */
+#define CFG_TIMERBASE 0x13000100 /* Timer1 */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
#undef CONFIG_INIT_CRITICAL
-#define CONFIG_CM_INIT 1
-#define CONFIG_CM_REMAP 1
+#define CONFIG_CM_INIT 1
+#define CONFIG_CM_REMAP 1
#undef CONFIG_CM_SPD_DETECT
/*
*/
#define CFG_PL010_SERIAL
#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 38400
+#define CONFIG_BAUDRATE 38400
#define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) }
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000
/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
/*#define CONFIG_NET_MULTI */
-/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
+/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
-#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
+#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
-#define CONFIG_BOOTCOMMAND ""
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
+#define CONFIG_BOOTCOMMAND ""
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define CFG_FLASH_BASE 0x24000000
+#define CFG_FLASH_BASE 0x24000000
/*-----------------------------------------------------------------------
* FLASH and environment organization
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
-#define CFG_MAX_FLASH_SECT 128
-#define CFG_ENV_SIZE 32768
+#define CFG_MAX_FLASH_SECT 128
+#define CFG_ENV_SIZE 32768
#define PHYS_FLASH_1 (CFG_FLASH_BASE)
/*#define CONFIG_PCI /--* include pci support */
#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define DEBUG
#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define INTEGRATOR_BOOT_ROM_BASE 0x20000000
-#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
+#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
/* PCI Base area */
#define INTEGRATOR_PCI_BASE 0x40000000
#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF
/* memory map as seen by the CPU on the local bus */
-#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */
+#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */
#define CPU_PCI_IO_SIZE 0x10000
#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */
#define CPU_PCI_CNFG_SIZE 0x1000000
-#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */
+#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */
/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
-#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */
+#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */
/* unused (128-16)M from B1000000-B7FFFFFF */
-#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
+#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
/* unused ((128-16)M - 64K) from XXX */
-#define PCI_V3_BASE 0x62000000
+#define PCI_V3_BASE 0x62000000
/* V3 PCI bridge controller */
#define V3_BASE 0x62000000 /* V360EPC registers */
#define PCI_ENET0_MEMADDR (PCI_MEM_BASE)
-#define V3_PCI_VENDOR 0x00000000
-#define V3_PCI_DEVICE 0x00000002
-#define V3_PCI_CMD 0x00000004
-#define V3_PCI_STAT 0x00000006
-#define V3_PCI_CC_REV 0x00000008
-#define V3_PCI_HDR_CF 0x0000000C
-#define V3_PCI_IO_BASE 0x00000010
-#define V3_PCI_BASE0 0x00000014
-#define V3_PCI_BASE1 0x00000018
-#define V3_PCI_SUB_VENDOR 0x0000002C
-#define V3_PCI_SUB_ID 0x0000002E
-#define V3_PCI_ROM 0x00000030
-#define V3_PCI_BPARAM 0x0000003C
-#define V3_PCI_MAP0 0x00000040
-#define V3_PCI_MAP1 0x00000044
-#define V3_PCI_INT_STAT 0x00000048
-#define V3_PCI_INT_CFG 0x0000004C
-#define V3_LB_BASE0 0x00000054
-#define V3_LB_BASE1 0x00000058
-#define V3_LB_MAP0 0x0000005E
-#define V3_LB_MAP1 0x00000062
-#define V3_LB_BASE2 0x00000064
-#define V3_LB_MAP2 0x00000066
-#define V3_LB_SIZE 0x00000068
-#define V3_LB_IO_BASE 0x0000006E
-#define V3_FIFO_CFG 0x00000070
-#define V3_FIFO_PRIORITY 0x00000072
-#define V3_FIFO_STAT 0x00000074
-#define V3_LB_ISTAT 0x00000076
-#define V3_LB_IMASK 0x00000077
-#define V3_SYSTEM 0x00000078
-#define V3_LB_CFG 0x0000007A
-#define V3_PCI_CFG 0x0000007C
-#define V3_DMA_PCI_ADR0 0x00000080
-#define V3_DMA_PCI_ADR1 0x00000090
-#define V3_DMA_LOCAL_ADR0 0x00000084
-#define V3_DMA_LOCAL_ADR1 0x00000094
-#define V3_DMA_LENGTH0 0x00000088
-#define V3_DMA_LENGTH1 0x00000098
-#define V3_DMA_CSR0 0x0000008B
-#define V3_DMA_CSR1 0x0000009B
-#define V3_DMA_CTLB_ADR0 0x0000008C
-#define V3_DMA_CTLB_ADR1 0x0000009C
-#define V3_DMA_DELAY 0x000000E0
-#define V3_MAIL_DATA 0x000000C0
-#define V3_PCI_MAIL_IEWR 0x000000D0
-#define V3_PCI_MAIL_IERD 0x000000D2
-#define V3_LB_MAIL_IEWR 0x000000D4
-#define V3_LB_MAIL_IERD 0x000000D6
-#define V3_MAIL_WR_STAT 0x000000D8
-#define V3_MAIL_RD_STAT 0x000000DA
-#define V3_QBA_MAP 0x000000DC
+#define V3_PCI_VENDOR 0x00000000
+#define V3_PCI_DEVICE 0x00000002
+#define V3_PCI_CMD 0x00000004
+#define V3_PCI_STAT 0x00000006
+#define V3_PCI_CC_REV 0x00000008
+#define V3_PCI_HDR_CF 0x0000000C
+#define V3_PCI_IO_BASE 0x00000010
+#define V3_PCI_BASE0 0x00000014
+#define V3_PCI_BASE1 0x00000018
+#define V3_PCI_SUB_VENDOR 0x0000002C
+#define V3_PCI_SUB_ID 0x0000002E
+#define V3_PCI_ROM 0x00000030
+#define V3_PCI_BPARAM 0x0000003C
+#define V3_PCI_MAP0 0x00000040
+#define V3_PCI_MAP1 0x00000044
+#define V3_PCI_INT_STAT 0x00000048
+#define V3_PCI_INT_CFG 0x0000004C
+#define V3_LB_BASE0 0x00000054
+#define V3_LB_BASE1 0x00000058
+#define V3_LB_MAP0 0x0000005E
+#define V3_LB_MAP1 0x00000062
+#define V3_LB_BASE2 0x00000064
+#define V3_LB_MAP2 0x00000066
+#define V3_LB_SIZE 0x00000068
+#define V3_LB_IO_BASE 0x0000006E
+#define V3_FIFO_CFG 0x00000070
+#define V3_FIFO_PRIORITY 0x00000072
+#define V3_FIFO_STAT 0x00000074
+#define V3_LB_ISTAT 0x00000076
+#define V3_LB_IMASK 0x00000077
+#define V3_SYSTEM 0x00000078
+#define V3_LB_CFG 0x0000007A
+#define V3_PCI_CFG 0x0000007C
+#define V3_DMA_PCI_ADR0 0x00000080
+#define V3_DMA_PCI_ADR1 0x00000090
+#define V3_DMA_LOCAL_ADR0 0x00000084
+#define V3_DMA_LOCAL_ADR1 0x00000094
+#define V3_DMA_LENGTH0 0x00000088
+#define V3_DMA_LENGTH1 0x00000098
+#define V3_DMA_CSR0 0x0000008B
+#define V3_DMA_CSR1 0x0000009B
+#define V3_DMA_CTLB_ADR0 0x0000008C
+#define V3_DMA_CTLB_ADR1 0x0000009C
+#define V3_DMA_DELAY 0x000000E0
+#define V3_MAIL_DATA 0x000000C0
+#define V3_PCI_MAIL_IEWR 0x000000D0
+#define V3_PCI_MAIL_IERD 0x000000D2
+#define V3_LB_MAIL_IEWR 0x000000D4
+#define V3_LB_MAIL_IERD 0x000000D6
+#define V3_MAIL_WR_STAT 0x000000D8
+#define V3_MAIL_RD_STAT 0x000000DA
+#define V3_QBA_MAP 0x000000DC
/* SYSTEM register bits */
-#define V3_SYSTEM_M_RST_OUT (1 << 15)
-#define V3_SYSTEM_M_LOCK (1 << 14)
+#define V3_SYSTEM_M_RST_OUT (1 << 15)
+#define V3_SYSTEM_M_LOCK (1 << 14)
/* PCI_CFG bits */
-#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
-#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
-#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
+#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
/* PCI MAP register bits (PCI -> Local bus) */
-#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
-#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
-#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10)
-#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8)
-#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
-#define V3_PCI_MAP_M_REG_EN (1 << 1)
-#define V3_PCI_MAP_M_ENABLE (1 << 0)
+#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10)
+#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
+#define V3_PCI_MAP_M_REG_EN (1 << 1)
+#define V3_PCI_MAP_M_ENABLE (1 << 0)
/* 9 => 512M window size */
-#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
+#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
/* A => 1024M window size */
-#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
+#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
/* LB_BASE register bits (Local bus -> PCI) */
-#define V3_LB_BASE_M_MAP_ADR 0xFFF00000
-#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9)
-#define V3_LB_BASE_M_ADR_SIZE 0x000000F0
-#define V3_LB_BASE_M_PREFETCH (1 << 3)
-#define V3_LB_BASE_M_ENABLE (1 << 0)
+#define V3_LB_BASE_M_MAP_ADR 0xFFF00000
+#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9)
+#define V3_LB_BASE_M_ADR_SIZE 0x000000F0
+#define V3_LB_BASE_M_PREFETCH (1 << 3)
+#define V3_LB_BASE_M_ENABLE (1 << 0)
/* PCI COMMAND REGISTER bits */
-#define V3_COMMAND_M_FBB_EN (1 << 9)
-#define V3_COMMAND_M_SERR_EN (1 << 8)
-#define V3_COMMAND_M_PAR_EN (1 << 6)
-#define V3_COMMAND_M_MASTER_EN (1 << 2)
-#define V3_COMMAND_M_MEM_EN (1 << 1)
-#define V3_COMMAND_M_IO_EN (1 << 0)
+#define V3_COMMAND_M_FBB_EN (1 << 9)
+#define V3_COMMAND_M_SERR_EN (1 << 8)
+#define V3_COMMAND_M_PAR_EN (1 << 6)
+#define V3_COMMAND_M_MASTER_EN (1 << 2)
+#define V3_COMMAND_M_MEM_EN (1 << 1)
+#define V3_COMMAND_M_IO_EN (1 << 0)
#define INTEGRATOR_SC_BASE 0x11000000
#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
/* CM registers common to all integrator/CP CMs */
#define OS_CTRL 0x0000000C
-#define CMMASK_REMAP 0x00000005 /* Set remap & led */
+#define CMMASK_REMAP 0x00000005 /* Set remap & led */
#define CMMASK_RESET 0x00000008
#define OS_LOCK 0x00000014
-#define CMVAL_LOCK 0x0000A000 /* Locking value */
-#define CMMASK_LOCK 0x0000005F /* Locking value */
+#define CMVAL_LOCK 0x0000A000 /* Locking value */
+#define CMMASK_LOCK 0x0000005F /* Locking value */
#define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */
#define OS_SDRAM 0x00000020
#define OS_INIT 0x00000024
#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
-#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
+#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
#ifdef CONFIG_CM_SPD_DETECT
#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
#endif
#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
-#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
- * - PLL test clock bypassed
- * - bus clock ratio 2
- * - little endian
- * - vectors at zero
- */
+#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
+ * - PLL test clock bypassed
+ * - bus clock ratio 2
+ * - little endian
+ * - vectors at zero
+ */
#endif /* CM1022xx */
-#define CMMASK_LE 0x00000008 /* little endian */
+#define CMMASK_LE 0x00000008 /* little endian */
#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
- * - divisor/ratio b00000001
- * bx
- * - HCLKDIV b000
- * bxx
- * - PLL BYPASS b00
- */
-#endif /* __CONFIG_H */
-
+ * - divisor/ratio b00000001
+ * bx
+ * - HCLKDIV b000
+ * bxx
+ * - PLL BYPASS b00
+ */
+#endif /* __CONFIG_H */
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