]> git.sur5r.net Git - u-boot/commitdiff
MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG
authorDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Wed, 27 Jul 2011 11:22:37 +0000 (13:22 +0200)
committerShinya Kuribayashi <skuribay@pobox.com>
Sun, 31 Jul 2011 14:26:41 +0000 (23:26 +0900)
This define is a board-specific config option and should be
renamed to follow the U-Boot naming convention. Additionally,
add an explaining comment for this option.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
arch/mips/cpu/mips32/start.S
include/configs/incaip.h

index 5d7467d02ad69b6285bba9d598eaf24879e1fe1a..e829b024c728fa4d4d3be7a973967b0ace846929 100644 (file)
 _start:
        RVECENT(reset,0)                        # U-boot entry point
        RVECENT(reset,1)                        # software reboot
-#ifdef CONFIG_INCA_IP
-       .word INFINEON_EBU_BOOTCFG              # EBU init code, fetched during
-       .word 0x00000000                        # booting phase of the flash
+#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+       /*
+        * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
+        * access external NOR flashes. If the board boots from NOR flash the
+        * internal BootROM does a blind read at address 0xB0000010 to read the
+        * initial configuration for that EBU in order to access the flash
+        * device with correct parameters. This config option is board-specific.
+        */
+       .word CONFIG_SYS_XWAY_EBU_BOOTCFG
+       .word 0x00000000
 #else
        RVECENT(romReserved,2)
 #endif
index 57eb2fa6ad451a4e37a605778838b0bd3910c4ee..0e5ad2b4d3a7865fd07a0154f309593531028d66 100644 (file)
@@ -41,7 +41,7 @@
 #define CONFIG_CPU_CLOCK_RATE  150000000
 #endif
 
-#define INFINEON_EBU_BOOTCFG   0x40C4  /* CMULT = 8 */
+#define CONFIG_SYS_XWAY_EBU_BOOTCFG    0x40C4  /* CMULT = 8 */
 
 #define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */