u64 ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
+ if (!(serdes1_prtcl_map & (1ULL << NONE)))
+ fsl_serdes_init();
+
ret |= (1ULL << device) & serdes1_prtcl_map;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
+ if (!(serdes2_prtcl_map & (1ULL << NONE)))
+ fsl_serdes_init();
+
ret |= (1ULL << device) & serdes2_prtcl_map;
#endif
serdes_prtcl_map |= (1ULL << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes_prtcl_map |= (1ULL << NONE);
+
return serdes_prtcl_map;
}
void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
- serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+ if (!(serdes1_prtcl_map & (1ULL << NONE)))
+ serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
- serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+ if (!(serdes2_prtcl_map & (1ULL << NONE)))
+ serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
+ if (!serdes1_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
+ if (!serdes2_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes2_prtcl_map[device];
#endif
u32 cfg;
int lane;
+ if (serdes_prtcl_map[NONE])
+ return;
+
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
else
serdes_prtcl_map[lane_prtcl] = 1;
}
+
+ /* Set the first element to indicate serdes has been initialized */
+ serdes_prtcl_map[NONE] = 1;
}
void fsl_serdes_init(void)
int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
+ if (!serdes1_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
+ if (!serdes2_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes2_prtcl_map[device];
#endif
u32 cfg;
int lane;
+ if (serdes_prtcl_map[NONE])
+ return;
+
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
#endif
}
}
+
+ /* Set the first element to indicate serdes has been initialized */
+ serdes_prtcl_map[NONE] = 1;
}
void fsl_serdes_init(void)
#ifdef CONFIG_LS2080A
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,
};
#elif defined(CONFIG_FSL_LSCH2)
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,
#include <config.h>
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl device)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes1_prtcl_map;
}
const struct serdes_config *ptr;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
enum srds_prtcl lane_prtcl = ptr->lanes[lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
+ if (!serdes1_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
+ if (!serdes2_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes2_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
+ if (!serdes3_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes3_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
+ if (!serdes4_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes4_prtcl_map[device];
#endif
u32 cfg;
int lane;
+ if (serdes_prtcl_map[NONE])
+ return;
+
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
struct ccsr_sfp_regs __iomem *sfp_regs =
else
serdes_prtcl_map[lane_prtcl] = 1;
}
+
+ /* Set the first element to indicate serdes has been initialized */
+ serdes_prtcl_map[NONE] = 1;
}
void fsl_serdes_init(void)
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return 0;
+ if (!(serdes_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes_prtcl_map;
}
if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
#endif
+ if (serdes_prtcl_map & (1 << NONE))
+ return;
/* Is serdes enabled at all? */
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
SRDS_RSTCTL_SDPD);
}
#endif
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes_prtcl_map |= (1 << NONE);
}
const char *serdes_clock_to_string(u32 clock)
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
u32 tmp;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
return;
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
serdes1_prtcl_map |= (1 << SGMII_TSEC4);
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
int lane;
u32 mask, val;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
/* Init SERDES Receiver electrical idle detection control for PCIe */
/* Lane 0 is always PCIe 1 */
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
return ret;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
MPC8610_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
MPC8641_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
#include <config.h>
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,