writel(umc_dataset[freq], dc_base + UMC_DATASET);
writel(0x00400020, dc_base + UMC_DCCGCTL);
- writel(0x00000003, dc_base + UMC_ACSCTLA);
+ writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
- writel(0x00010200, dc_base + UMC_ACSSETA);
+ writel(0x00010200, dc_base + UMC_ACSSETB);
writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
writel(0x00004444, dc_base + UMC_FLOWCTLC);
#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
-#define UMC_ACSCTLA 0x000000C0
-#define UMC_ACSSETA 0x000000C4
+#define UMC_ACSSETA 0x000000C0
+#define UMC_ACSSETB 0x000000C4
#define UMC_MEMCONF0A 0x00000200
#define UMC_MEMCONF0B 0x00000204
#define UMC_MEMCONFCH 0x00000240