]> git.sur5r.net Git - u-boot/commitdiff
sh: tmu: Changed TMU driver using array of structures
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Tue, 21 Aug 2012 04:14:46 +0000 (13:14 +0900)
committerNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Tue, 21 Aug 2012 06:00:33 +0000 (15:00 +0900)
This changed into access using array of structure from access to the register
using the definition of the register by macro.
And removed white space.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
15 files changed:
arch/sh/include/asm/clk.h
arch/sh/include/asm/cpu_sh7706.h
arch/sh/include/asm/cpu_sh7710.h
arch/sh/include/asm/cpu_sh7720.h
arch/sh/include/asm/cpu_sh7722.h
arch/sh/include/asm/cpu_sh7723.h
arch/sh/include/asm/cpu_sh7724.h
arch/sh/include/asm/cpu_sh7734.h
arch/sh/include/asm/cpu_sh7750.h
arch/sh/include/asm/cpu_sh7757.h
arch/sh/include/asm/cpu_sh7763.h
arch/sh/include/asm/cpu_sh7780.h
arch/sh/include/asm/cpu_sh7785.h
arch/sh/lib/time.c
include/sh_tmu.h [new file with mode: 0644]

index 9cac6b09f902221be043dee550e5c942e805bf48..2164bfb3a6c1fcfbe8c2c3caabe928eba1f7ead2 100644 (file)
@@ -27,9 +27,4 @@ static inline unsigned long get_peripheral_clk_rate(void)
        return CONFIG_SYS_CLK_FREQ;
 }
 
-static inline unsigned long get_tmu0_clk_rate(void)
-{
-       return CONFIG_SYS_CLK_FREQ;
-}
-
 #endif /* __ASM_SH_CLK_H__ */
index d093f88d4c821e9a76a8de01b57c0f0ea31a78cf..8066ff719bdae4a962cba6dc69af55e7f4844a35 100644 (file)
 #define SCIF0_BASE     SCSMR_2
 
 /* Timer */
-#define TSTR0          0xFFFFFE92
-#define TSTR           TSTR0
-#define TCNT0          0xFFFFFE98
-#define TCR0           0xFFFFFE9C
+#define TMU_BASE       0xFFFFFE90
 
 /* On chip oscillator circuits */
 #define        WTCNT   0xFFFFFF84
index e223f1ca16245a16f55742767ebdeebdaaee674b..e4ecef7f70dcd0846e12cf44939d8ea83de56340 100644 (file)
 #define SCIF1_BASE     SCSMR_1
 
 /* Timer */
-#define TSTR0          0xA412FE92
-#define TSTR           TSTR0
-#define TCNT0          0xa412FE98
-#define TCR0           0xa412FE9C
+#define TMU_BASE       0xA412FE90
 
 /* On chip oscillator circuits */
 #define FRQCR          0xA415FF80
index 1b393b88a607598503067e45e0dab4da37067e61..a8013cc96352b476fc1c3177de1cdab62d80189d 100644 (file)
 
 /*     TMU     */
 #define TMU_BASE       0xA412FE90
-#define TSTR           (TMU_BASE + 0x02)
-#define TCOR0          (TMU_BASE + 0x04)
-#define TCNT0          (TMU_BASE + 0x08)
-#define TCR0           (TMU_BASE + 0x0C)
-#define TCOR1          (TMU_BASE + 0x10)
-#define TCNT1          (TMU_BASE + 0x14)
-#define TCR1           (TMU_BASE + 0x18)
-#define TCOR2          (TMU_BASE + 0x1C)
-#define TCNT2          (TMU_BASE + 0x20)
-#define TCR2           (TMU_BASE + 0x24)
 
 /*     TPU     */
 #define TPU_BASE       0xA4480000
index 3157dcbf115a3b893717aa342d9af585b61db249..92dfe27cccca47ba9f4e6ad8ec2e20592fed1781 100644 (file)
 
 
 /*     TMU     */
-#define TSTR        0xFFD80004
-#define TCOR0       0xFFD80008
-#define TCNT0       0xFFD8000C
-#define TCR0        0xFFD80010
-#define TCOR1       0xFFD80014
-#define TCNT1       0xFFD80018
-#define TCR1        0xFFD8001C
-#define TCOR2       0xFFD80020
-#define TCNT2       0xFFD80024
-#define TCR2        0xFFD80028
+#define TMU_BASE       0xFFD80000
 
 /*     TPU     */
 #define TPU_TSTR    0xA4C90000
index 6dac6e9a0182ad65740a993434016e3b9fb825bf..2595f298daef9044978a302e4f115b5400865d1e 100644 (file)
 #define WTCNT          RWTCNT
 
 /* TMU */
-#define TSTR        0xFFD80004
-#define TCOR0       0xFFD80008
-#define TCNT0       0xFFD8000C
-#define TCR0        0xFFD80010
-#define TCOR1       0xFFD80014
-#define TCNT1       0xFFD80018
-#define TCR1        0xFFD8001C
-#define TCOR2       0xFFD80020
-#define TCNT2       0xFFD80024
-#define TCR2        0xFFD80028
+#define TMU_BASE       0xFFD80000
 
 /* TPU */
 
index 3bb51d3f18443d7b787bc619088c7c4382137e97..cd40b6d22c08b22d811054da1e8015610818c8bc 100644 (file)
 #define WTCNT          RWTCNT
 
 /* TMU */
-#define TSTR        0xFFD80004
-#define TCOR0       0xFFD80008
-#define TCNT0       0xFFD8000C
-#define TCR0        0xFFD80010
-#define TCOR1       0xFFD80014
-#define TCNT1       0xFFD80018
-#define TCR1        0xFFD8001C
-#define TCOR2       0xFFD80020
-#define TCNT2       0xFFD80024
-#define TCR2        0xFFD80028
+#define TMU_BASE       0xFFD80000
 
 /* TPU */
 
index 0f84b4f57ca2fb36d77ae23395ce222c78e783f9..179a35751c85de2f4df980c8e5559f9113fe894a 100644 (file)
@@ -36,9 +36,7 @@
 #define SCIF5_BASE  0xFFE45000
 
 /* Timer */
-#define TSTR   0xFFD80004
-#define TCNT0  0xFFD8000C
-#define TCR0   0xFFD80010
+#define TMU_BASE 0xFFD80000
 
 /* PFC */
 #define PMMR    (0xFFFC0000)
index b3e84244fd04db98a0a175523fd869cefe5993a5..88c4c8d58e6f826a9c2291be58b5164bd8563d6d 100644 (file)
 #define CLKSTPCLR      0xFE0A0008
 
 /*      TMU     */
-#define TSTR2  0xFE100004
-#define TCOR3  0xFE100008
-#define TCNT3  0xFE10000C
-#define TCR3   0xFE100010
-#define TCOR4  0xFE100014
-#define TCNT4  0xFE100018
-#define TCR4   0xFE10001C
-#define TOCR   0xFFD80000
-#define TSTR0  0xFFD80004
-#define TCOR0  0xFFD80008
-#define TCNT0  0xFFD8000C
-#define TCR0   0xFFD80010
-#define TCOR1  0xFFD80014
-#define TCNT1  0xFFD80018
-#define TCR1   0xFFD8001C
-#define TCOR2  0xFFD80020
-#define TCNT2  0xFFD80024
-#define TCR2   0xFFD80028
-#define TCPR2  0xFFD8002C
-#define TSTR   TSTR0
+#define TMU_BASE       0xFFD80000
 
 /*      SCI     */
 #define SCSMR1 0xFFE00000
index 17a6537bc32f73c0b96a7681f1cc0dba157d37da..43c1f07b92930e63bf5b4e0ca145b367e33733a9 100644 (file)
@@ -51,19 +51,7 @@ struct mmu_regs {
 #define SMR0           0xfe470000
 
 /* TMU0 */
-#define TSTR           0xFE430004
-#define TOCR           0xFE430000
-#define TSTR0          0xFE430004
-#define TCOR0          0xFE430008
-#define TCNT0          0xFE43000C
-#define TCR0           0xFE430010
-#define TCOR1          0xFE430014
-#define TCNT1          0xFE430018
-#define TCR1           0xFE43001C
-#define TCOR2          0xFE430020
-#define TCNT2          0xFE430024
-#define TCR2           0xFE430028
-#define TCPR2          0xFE43002C
+#define TMU_BASE    0xFE430000
 
 /* ETHER, GETHER MAC address */
 struct ether_mac_regs {
index 78b456b4b27c1436ad777df12bfe2a7e68cb54fd..36d70655c03db8cb01e4bcfc673e355d97ca93e5 100644 (file)
@@ -43,9 +43,6 @@
 #define WDTST          0xFFCC0000
 
 /* TMU */
-#define TSTR           0xFFD80004
-#define TCOR0          0xFFD80008
-#define TCNT0          0xFFD8000C
-#define TCR0           0xFFD80010
+#define TMU_BASE       0xFFD80000
 
 #endif /* _ASM_CPU_SH7763_H_ */
index e9c59fe245a81549ba14c7bd3f8ca2e90171688d..162aa688f3cbc7ecc4c18736043b22b080e0fa55 100644 (file)
 #define        MSTPCR  0xFFC80030
 
 /* Timer Unit */
-#define        TSTR    TSTR0
-#define        TOCR    0xFFD80000
-#define        TSTR0   0xFFD80004
-#define        TCOR0   0xFFD80008
-#define        TCNT0   0xFFD8000C
-#define        TCR0    0xFFD80010
-#define        TCOR1   0xFFD80014
-#define        TCNT1   0xFFD80018
-#define        TCR1    0xFFD8001C
-#define        TCOR2   0xFFD80020
-#define        TCNT2   0xFFD80024
-#define        TCR2    0xFFD80028
-#define        TCPR2   0xFFD8002C
-#define        TSTR1   0xFFDC0004
-#define        TCOR3   0xFFDC0008
-#define        TCNT3   0xFFDC000C
-#define        TCR3    0xFFDC0010
-#define        TCOR4   0xFFDC0014
-#define        TCNT4   0xFFDC0018
-#define        TCR4    0xFFDC001C
-#define        TCOR5   0xFFDC0020
-#define        TCNT5   0xFFDC0024
-#define        TCR5    0xFFDC0028
+#define TMU_BASE    0xFFD80000
 
 /* Timer/Counter */
 #define        CMTCFG  0xFFE30000
index 4a4dfc90420470487318ca47aaad7cb798fe2cb9..8e3839d1a2e147a67937a828d7c3c4393b08e9d2 100644 (file)
 #define        WDTBCNT 0xFFCC0018
 
 /* Timer Unit */
-#define        TSTR    TSTR0
-#define        TOCR    0xFFD80000
-#define        TSTR0   0xFFD80004
-#define        TCOR0   0xFFD80008
-#define        TCNT0   0xFFD8000C
-#define        TCR0    0xFFD80010
-#define        TCOR1   0xFFD80014
-#define        TCNT1   0xFFD80018
-#define        TCR1    0xFFD8001C
-#define        TCOR2   0xFFD80020
-#define        TCNT2   0xFFD80024
-#define        TCR2    0xFFD80028
-#define        TCPR2   0xFFD8002C
-#define        TSTR1   0xFFDC0004
-#define        TCOR3   0xFFDC0008
-#define        TCNT3   0xFFDC000C
-#define        TCR3    0xFFDC0010
-#define        TCOR4   0xFFDC0014
-#define        TCNT4   0xFFDC0018
-#define        TCR4    0xFFDC001C
-#define        TCOR5   0xFFDC0020
-#define        TCNT5   0xFFDC0024
-#define        TCR5    0xFFDC0028
+#define TMU_BASE       0xFFD80000
 
 /* Serial Communication        Interface with FIFO */
 #define        SCIF1_BASE      0xffeb0000
index a01596cace6eb2bb477b9fbb7e224a9f90239ee9..48404727c3dcd91f61625cc39eec709da0f0d905 100644 (file)
@@ -2,7 +2,7 @@
  * (C) Copyright 2009
  * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  *
- * (C) Copyright 2007-2010
+ * (C) Copyright 2007-2012
  * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * (C) Copyright 2003
@@ -32,6 +32,9 @@
 #include <asm/processor.h>
 #include <asm/clk.h>
 #include <asm/io.h>
+#include <sh_tmu.h>
+
+static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
 
 #define TMU_MAX_COUNTER (~0UL)
 
@@ -55,21 +58,21 @@ static inline unsigned long long usec_to_tick(unsigned long long usec)
        return usec;
 }
 
-static void tmu_timer_start (unsigned int timer)
+static void tmu_timer_start(unsigned int timer)
 {
        if (timer > 2)
                return;
-       writeb(readb(TSTR) | (1 << timer), TSTR);
+       writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
 }
 
-static void tmu_timer_stop (unsigned int timer)
+static void tmu_timer_stop(unsigned int timer)
 {
        if (timer > 2)
                return;
-       writeb(readb(TSTR) & ~(1 << timer), TSTR);
+       writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
 }
 
-int timer_init (void)
+int timer_init(void)
 {
        /* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
        u16 bit = 0;
@@ -91,7 +94,7 @@ int timer_init (void)
        default:
                break;
        }
-       writew(readw(TCR0) | bit, TCR0);
+       writew(readw(&tmu->tcr0) | bit, &tmu->tcr0);
 
        /* Calc clock rate */
        timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2);
@@ -105,9 +108,9 @@ int timer_init (void)
        return 0;
 }
 
-unsigned long long get_ticks (void)
+unsigned long long get_ticks(void)
 {
-       unsigned long tcnt = 0 - readl(TCNT0);
+       unsigned long tcnt = 0 - readl(&tmu->tcnt0);
 
        if (last_tcnt > tcnt) /* overflow */
                overflow_ticks++;
@@ -116,7 +119,7 @@ unsigned long long get_ticks (void)
        return (overflow_ticks << 32) | tcnt;
 }
 
-void __udelay (unsigned long usec)
+void __udelay(unsigned long usec)
 {
        unsigned long long tmp;
        ulong tmo;
@@ -128,13 +131,13 @@ void __udelay (unsigned long usec)
                 /*NOP*/;
 }
 
-unsigned long get_timer (unsigned long base)
+unsigned long get_timer(unsigned long base)
 {
        /* return msec */
        return tick_to_time(get_ticks()) - base;
 }
 
-unsigned long get_tbclk (void)
+unsigned long get_tbclk(void)
 {
        return timer_freq;
 }
diff --git a/include/sh_tmu.h b/include/sh_tmu.h
new file mode 100644 (file)
index 0000000..a55d141
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SH_TMU_H
+#define __SH_TMU_H
+
+#include <asm/types.h>
+
+#if defined(CONFIG_SH3)
+struct tmu_regs {
+       u8      tocr;
+       u8      reserved0;
+       u8      tstr;
+       u8      reserved1;
+       u32     tcor0;
+       u32     tcnt0;
+       u16     tcr0;
+       u16     reserved2;
+       u32     tcor1;
+       u32     tcnt1;
+       u16     tcr1;
+       u16     reserved3;
+       u32     tcor2;
+       u32     tcnt2;
+       u16     tcr2;
+       u16     reserved4;
+       u32     tcpr2;
+};
+#endif /* CONFIG_SH3 */
+
+#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+struct tmu_regs {
+       u32 reserved;
+       u8  tstr;
+       u8  reserved2[3];
+       u32 tcor0;
+       u32 tcnt0;
+       u16 tcr0;
+       u16 reserved3;
+       u32 tcor1;
+       u32 tcnt1;
+       u16 tcr1;
+       u16 reserved4;
+       u32 tcor2;
+       u32 tcnt2;
+       u16 tcr2;
+       u16 reserved5;
+};
+#endif /* CONFIG_SH4 */
+
+static inline unsigned long get_tmu0_clk_rate(void)
+{
+       return CONFIG_SYS_CLK_FREQ;
+}
+
+#endif /* __SH_TMU_H */