powerpc/mpc85xx: Skip zero values for DDR debug registers

Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.

Also add debug messages for workarounds and debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index 81961def1b7fa036a846e73c6bb5c4b9e141adae..0761d70080ae613a6a8fcd570f057cc28ab0ccdb 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -43,6 +43,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->eor, regs->ddr_eor);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+       debug("Workaround for ERRATUM_DDR111_DDR134\n");
        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
                cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
                cs_ea = regs->cs[i].bnds & 0xfff;
@@ -115,8 +116,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
        out_be32(&ddr->err_disable, regs->err_disable);
        out_be32(&ddr->err_int_en, regs->err_int_en);
-       for (i = 0; i < 32; i++)
-               out_be32(&ddr->debug[i], regs->debug[i]);
+       for (i = 0; i < 32; i++) {
+               if (regs->debug[i]) {
+                       debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
+                       out_be32(&ddr->debug[i], regs->debug[i]);
+               }
+       }
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
        out_be32(&ddr->debug[12], 0x00000015);
@@ -128,6 +133,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
        out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+       debug("Workaround for ERRATUM_DDR_A003\n");
        if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
                out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
                out_be32(&ddr->debug[2], 0x00000400);
@@ -209,6 +215,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
         * This erratum does not affect DDR3 mode, only for DDR2 mode.
         */
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
+       debug("Workaround for ERRATUM_DDR_115\n");
        if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
            && in_be32(&ddr->sdram_cfg) & 0x80000) {
                /* set DEBUG_1[31] */
@@ -216,6 +223,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        }
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+       debug("Workaround for ERRATUM_DDR111_DDR134\n");
        /*
         * This is the combined workaround for DDR111 and DDR134
         * following the published errata for MPC8572