..no_pllset:
 #endif /* CONFIG_BUBINGA */
 
-#ifdef CONFIG_TAIHU
-       mfdcr   r4, CPC0_BOOT
-       andi.   r5, r4, CPC0_BOOT_SEP@l
-       bne     strap_1                 /* serial eeprom present */
-       addis   r5,0,CPLD_REG0_ADDR@h
-       ori     r5,r5,CPLD_REG0_ADDR@l
-       andi.   r5, r5, 0x10
-       bne     _pci_66mhz
-#endif /* CONFIG_TAIHU */
-
        addis   r3,0,PLLMR0_DEFAULT@h   /* PLLMR0 default value */
        ori     r3,r3,PLLMR0_DEFAULT@l  /* */
        addis   r4,0,PLLMR1_DEFAULT@h   /* PLLMR1 default value */
        ori     r4,r4,PLLMR1_DEFAULT@l  /* */
 
-#ifdef CONFIG_TAIHU
-       b       1f
-_pci_66mhz:
-       addis   r3,0,PLLMR0_DEFAULT_PCI66@h
-       ori     r3,r3,PLLMR0_DEFAULT_PCI66@l
-       addis   r4,0,PLLMR1_DEFAULT_PCI66@h
-       ori     r4,r4,PLLMR1_DEFAULT_PCI66@l
-       b       1f
-strap_1:
-       mfdcr   r3, CPC0_PLLMR0
-       mfdcr   r4, CPC0_PLLMR1
-#endif /* CONFIG_TAIHU */
-
 1:
        b       pll_write               /* Write the CPC0_PLLMR with new value */