F: arch/arm/include/asm/arch-tegra*/
ARM TI
-M: Tom Rini <trini@ti.com>
+M: Tom Rini <trini@konsulko.com>
S: Maintained
T: git git://git.denx.de/u-boot-ti.git
F: arch/arm/cpu/arm926ejs/davinci/
M: Masahiro Yamada <yamada.m@jp.panasonic.com>
S: Maintained
T: git git://git.denx.de/u-boot-uniphier.git
-F: arch/arm/cpu/armv7/uniphier/
-F: arch/arm/include/asm/arch-uniphier/
+F: arch/arm/mach-uniphier/
F: configs/ph1_*_defconfig
N: uniphier
S: Maintained
T: git git://git.denx.de/u-boot-dfu.git
F: drivers/dfu/
+F: drivers/usb/gadget/
DRIVER MODEL
M: Simon Glass <sjg@chromium.org>
F: arch/x86/
THE REST
-M: Tom Rini <trini@ti.com>
+M: Tom Rini <trini@konsulko.com>
L: u-boot@lists.denx.de
Q: http://patchwork.ozlabs.org/project/uboot/list/
S: Maintained
source "arch/arm/mach-tegra/Kconfig"
-source "arch/arm/cpu/armv7/uniphier/Kconfig"
+source "arch/arm/mach-uniphier/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_TEGRA) += tegra
+machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_U8500) += u8500/
-obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
obj-$(CONFIG_VF610) += vf610/
obj-$(CONFIG_ZYNQ) += zynq/
obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-$(CONFIG_EXYNOS5420) += sec_boot.o
+
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
* MA 02111-1307 USA
*/
+#include <asm/arch/system.h>
+
#define DMC_OFFSET 0x10000
/*
int do_lowlevel_init(void);
void sdelay(unsigned long);
+
+enum l2_cache_params {
+ CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
+ CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
+ CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
+ CACHE_DATA_RAM_SETUP = (1 << 5),
+ CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
+ CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
+ CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
+ CACHE_TAG_RAM_SETUP = (1 << 9),
+ CACHE_ECC_AND_PARITY = (1 << 21),
+ CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
+};
+
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Configure L2CTLR to get timings that keep us from hanging/crashing.
+ *
+ * Must be inline here since low_power_start() is called without a
+ * stack (!).
+ */
+static inline void configure_l2_ctlr(void)
+{
+ uint32_t val;
+
+ mrc_l2_ctlr(val);
+
+ val |= CACHE_TAG_RAM_SETUP |
+ CACHE_DATA_RAM_SETUP |
+ CACHE_TAG_RAM_LATENCY_2_CYCLES |
+ CACHE_DATA_RAM_LATENCY_2_CYCLES;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ val |= CACHE_ECC_AND_PARITY |
+ CACHE_TAG_RAM_LATENCY_3_CYCLES |
+ CACHE_DATA_RAM_LATENCY_3_CYCLES;
+ }
+
+ mcr_l2_ctlr(val);
+}
+
+/*
+ * Configure L2ACTLR.
+ *
+ * Must be inline here since low_power_start() is called without a
+ * stack (!).
+ */
+static inline void configure_l2_actlr(void)
+{
+ uint32_t val;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ mrc_l2_aux_ctlr(val);
+ val |= CACHE_ENABLE_FORCE_L2_LOGIC |
+ CACHE_DISABLE_CLEAN_EVICT;
+ mcr_l2_aux_ctlr(val);
+ }
+}
+#endif
#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
#else
+
+#define CPU_CONFIG_STATUS_OFFSET 0x80
+#define CPU_RST_FLAG_VAL 0xFCBA0D10
#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
/* APLL_CON1 */
#include <asm/arch/tzpc.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/system.h>
+#include <asm/armv7.h>
#include "common_setup.h"
+#include "exynos5_setup.h"
/* These are the things we can do during low-level init */
enum {
DO_POWER = 1 << 4,
};
+#ifdef CONFIG_EXYNOS5420
+/*
+ * Power up secondary CPUs.
+ */
+static void secondary_cpu_start(void)
+{
+ v7_enable_smp(EXYNOS5420_INFORM_BASE);
+ svc32_mode_en();
+ branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
+}
+
+/*
+ * This is the entry point of hotplug-in and
+ * cluster switching.
+ */
+static void low_power_start(void)
+{
+ uint32_t val, reg_val;
+
+ reg_val = readl(EXYNOS5420_SPARE_BASE);
+ if (reg_val != CPU_RST_FLAG_VAL) {
+ writel(0x0, CONFIG_LOWPOWER_FLAG);
+ branch_bx(0x0);
+ }
+
+ reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
+ if (reg_val != (uint32_t)&low_power_start) {
+ /* Store jump address as low_power_start if not present */
+ writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
+ dsb();
+ sev();
+ }
+
+ /* Set the CPU to SVC32 mode */
+ svc32_mode_en();
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+ /* Read MIDR for Primary Part Number */
+ mrc_midr(val);
+ val = (val >> 4);
+ val &= 0xf;
+
+ if (val == 0xf) {
+ configure_l2_ctlr();
+ configure_l2_actlr();
+ v7_enable_l2_hazard_detect();
+ }
+#endif
+
+ /* Invalidate L1 & TLB */
+ val = 0x0;
+ mcr_tlb(val);
+ mcr_icache(val);
+
+ /* Disable MMU stuff and caches */
+ mrc_sctlr(val);
+
+ val &= ~((0x2 << 12) | 0x7);
+ val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
+ mcr_sctlr(val);
+
+ /* CPU state is hotplug or reset */
+ secondary_cpu_start();
+
+ /* Core should not enter into WFI here */
+ wfi();
+}
+
+/*
+ * Pointer to this function is stored in iRam which is used
+ * for jump and power down of a specific core.
+ */
+static void power_down_core(void)
+{
+ uint32_t tmp, core_id, core_config;
+
+ /* Get the unique core id */
+ /*
+ * Multiprocessor Affinity Register
+ * [11:8] Cluster ID
+ * [1:0] CPU ID
+ */
+ mrc_mpafr(core_id);
+ tmp = core_id & 0x3;
+ core_id = (core_id >> 6) & ~3;
+ core_id |= tmp;
+ core_id &= 0x3f;
+
+ /* Set the status of the core to low */
+ core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
+ core_config += EXYNOS5420_CPU_CONFIG_BASE;
+ writel(0x0, core_config);
+
+ /* Core enter WFI */
+ wfi();
+}
+
+/*
+ * Configurations for secondary cores are inapt at this stage.
+ * Reconfigure secondary cores. Shutdown and change the status
+ * of all cores except the primary core.
+ */
+static void secondary_cores_configure(void)
+{
+ /* Clear secondary boot iRAM base */
+ writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
+
+ /* set lowpower flag and address */
+ writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
+ writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
+ writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
+ /* Store jump address for power down */
+ writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
+
+ /* Need all core power down check */
+ dsb();
+ sev();
+}
+
+extern void relocate_wait_code(void);
+#endif
+
int do_lowlevel_init(void)
{
uint32_t reset_status;
arch_cpu_init();
+#ifndef CONFIG_SYS_L2CACHE_OFF
+ /*
+ * Init L2 cache parameters here for use by boot and resume
+ *
+ * These are here instead of in v7_outer_cache_enable() so that the
+ * L2 cache settings get properly set even at resume time or if we're
+ * running U-Boot with the cache off. The kernel still needs us to
+ * set these for it.
+ */
+ configure_l2_ctlr();
+ configure_l2_actlr();
+ dsb();
+ isb();
+#endif
+
+#ifdef CONFIG_EXYNOS5420
+ relocate_wait_code();
+
+ /* Reconfigure secondary cores */
+ secondary_cores_configure();
+#endif
+
reset_status = get_reset_status();
switch (reset_status) {
--- /dev/null
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Akshay Saraswat <akshay.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+ .globl relocate_wait_code
+relocate_wait_code:
+ adr r0, code_base @ r0: source address (start)
+ adr r1, code_end @ r1: source address (end)
+ ldr r2, =0x02073000 @ r2: target address
+1:
+ ldmia r0!, {r3-r6}
+ stmia r2!, {r3-r6}
+ cmp r0, r1
+ blt 1b
+ b code_end
+ .ltorg
+/*
+ * Secondary core waits here until Primary wake it up.
+ * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
+ * This is a workaround code which is supposed to act as a
+ * substitute/supplement to the iROM code.
+ *
+ * This workaround code is relocated to the address 0x02073000
+ * because that comes out to be the last 4KB of the iRAM
+ * (Base Address - 0x02020000, Limit Address - 0x020740000).
+ *
+ * U-boot and kernel are aware of this code and flags by the simple
+ * fact that we are implementing a workaround in the last 4KB
+ * of the iRAM and we have already defined these flag and address
+ * values in both kernel and U-boot for our use.
+ */
+code_base:
+ b 1f
+/*
+ * These addresses are being used as flags in u-boot and kernel.
+ *
+ * Jump address for resume and flag to check for resume/reset:
+ * Resume address - 0x2073008
+ * Resume flag - 0x207300C
+ *
+ * Jump address for cluster switching:
+ * Switch address - 0x2073018
+ *
+ * Jump address for core hotplug:
+ * Hotplug address - 0x207301C
+ *
+ * Jump address for C2 state (Reserved for future not being used right now):
+ * C2 address - 0x2073024
+ *
+ * Managed per core status for the active cluster:
+ * CPU0 state - 0x2073028
+ * CPU1 state - 0x207302C
+ * CPU2 state - 0x2073030
+ * CPU3 state - 0x2073034
+ *
+ * Managed per core GIC status for the active cluster:
+ * CPU0 gic state - 0x2073038
+ * CPU1 gic state - 0x207303C
+ * CPU2 gic state - 0x2073040
+ * CPU3 gic state - 0x2073044
+ *
+ * Logic of the code:
+ * Step-1: Read current CPU status.
+ * Step-2: If it's a resume then continue, else jump to step 4.
+ * Step-3: Clear inform1 PMU register and jump to inform0 value.
+ * Step-4: If it's a switch, C2 or reset, get the hotplug address.
+ * Step-5: If address is not available, enter WFE.
+ * Step-6: If address is available, jump to that address.
+ */
+ nop @ for backward compatibility
+ .word 0x0 @ REG0: RESUME_ADDR
+ .word 0x0 @ REG1: RESUME_FLAG
+ .word 0x0 @ REG2
+ .word 0x0 @ REG3
+_switch_addr:
+ .word 0x0 @ REG4: SWITCH_ADDR
+_hotplug_addr:
+ .word 0x0 @ REG5: CPU1_BOOT_REG
+ .word 0x0 @ REG6
+_c2_addr:
+ .word 0x0 @ REG7: REG_C2_ADDR
+_cpu_state:
+ .word 0x1 @ CPU0_STATE : RESET
+ .word 0x2 @ CPU1_STATE : SECONDARY RESET
+ .word 0x2 @ CPU2_STATE : SECONDARY RESET
+ .word 0x2 @ CPU3_STATE : SECONDARY RESET
+_gic_state:
+ .word 0x0 @ CPU0 - GICD_IGROUPR0
+ .word 0x0 @ CPU1 - GICD_IGROUPR0
+ .word 0x0 @ CPU2 - GICD_IGROUPR0
+ .word 0x0 @ CPU3 - GICD_IGROUPR0
+1:
+ adr r0, _cpu_state
+ mrc p15, 0, r7, c0, c0, 5 @ read MPIDR
+ and r7, r7, #0xf @ r7 = cpu id
+/* Read the current cpu state */
+ ldr r10, [r0, r7, lsl #2]
+svc_entry:
+ tst r10, #(1 << 4)
+ adrne r0, _switch_addr
+ bne wait_for_addr
+/* Clear INFORM1 */
+ ldr r0, =(0x10040000 + 0x804)
+ ldr r1, [r0]
+ cmp r1, #0x0
+ movne r1, #0x0
+ strne r1, [r0]
+/* Get INFORM0 */
+ ldrne r1, =(0x10040000 + 0x800)
+ ldrne pc, [r1]
+ tst r10, #(1 << 0)
+ ldrne pc, =0x23e00000
+ adr r0, _hotplug_addr
+wait_for_addr:
+ ldr r1, [r0]
+ cmp r1, #0x0
+ bxne r1
+ wfe
+ b wait_for_addr
+ .ltorg
+code_end:
+ mov pc, lr
#include <asm/io.h>
#include <asm/system.h>
-enum l2_cache_params {
- CACHE_TAG_RAM_SETUP = (1 << 9),
- CACHE_DATA_RAM_SETUP = (1 << 5),
- CACHE_TAG_RAM_LATENCY = (2 << 6),
- CACHE_DATA_RAM_LATENCY = (2 << 0)
-};
-
void reset_cpu(ulong addr)
{
writel(0x1, samsung_get_base_swreset());
dcache_enable();
}
#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-/*
- * Set L2 cache parameters
- */
-static void exynos5_set_l2cache_params(void)
-{
- unsigned int val = 0;
-
- asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
-
- val |= CACHE_TAG_RAM_SETUP |
- CACHE_DATA_RAM_SETUP |
- CACHE_TAG_RAM_LATENCY |
- CACHE_DATA_RAM_LATENCY;
-
- asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
-}
-
-/*
- * Sets L2 cache related parameters before enabling data cache
- */
-void v7_outer_cache_enable(void)
-{
- if (cpu_is_exynos5())
- exynos5_set_l2cache_params();
-}
-#endif
config TARGET_SILK
bool "Silk board"
+config TARGET_PORTER
+ bool "Porter board"
+
endchoice
config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
- depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK
default n
source "board/atmark-techno/armadillo-800eva/Kconfig"
source "board/kmc/kzm9g/Kconfig"
source "board/renesas/alt/Kconfig"
source "board/renesas/silk/Kconfig"
+source "board/renesas/porter/Kconfig"
endif
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
FN_MII_RXD2,
- /* IPSR8 - IPSR16 */
+ /* IPSR8 */
+ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
+ FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
+ FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
+ FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
+ FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
+ FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
+ FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
+ FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
+ FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
+ FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
+ FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+ FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+ FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
+ FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+ FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
+ FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+ FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
+ FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
+
+ /* IPSR9 */
+ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
+ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
+ FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
+ FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
+ FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+ FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
+ FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+ FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
+ FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
+ FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+ FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
+ FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
+ FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
+ FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+ FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
+ FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
+ FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
+ FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
+ FN_VI3_CLK_B,
+
+ /* IPSR10 */
+ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+ FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+ FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+ FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+ FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+ FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+ FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+ FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+ FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+ FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+ FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+ FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+ FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+ FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
+ FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+ FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
+ FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
+ FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+ FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+ FN_GLO_I0_B, FN_VI3_DATA6_B,
+
+ /* IPSR11 */
+ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+ FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
+ FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
+ FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
+ FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
+ FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
+ FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+ FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
+ FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+ FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+ FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
+ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
+ FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
+ FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+ FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
+ FN_MOUT0,
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
FN_SEL_SCIF1_4,
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
FN_SEL_I2C2_4,
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
-
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
+ VI1_DATA7_VI1_B7_MARK,
+
+ USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
+ USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
+ DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
+
+ D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
+ D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
+ VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
+ VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
+ VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
+ SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
+ VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
+ SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
+ VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
+ SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
+ SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
+ VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
+ D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
+ VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
+
+ D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
+ VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
+ SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
+ VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
+ SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
+ VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
+ D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
+ VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
+ D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
+ VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
+ SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
+ VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
+ D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
+ VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
+ A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
+
+ A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
+ PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
+ TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
+ A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
+ SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
+ A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
+ VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
+ A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
+ VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
+ A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
+ VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
+
+ A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
+ VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
+ A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
+ VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
+ A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
+ MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
+ VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
+ ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
+ ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
+ A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
+ AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
+ ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
+ VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
+
+ A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
+ A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
+ VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
+ VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
+ VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
+ VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
+ VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
+ VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
+ CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
+ VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
+ VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
+ MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
+ HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
+ VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
+ VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
+
+ EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
+ VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
+ EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
+ VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
+ INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
+ MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
+ VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
+ SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
+ CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
+ CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
+ VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
+ INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+ VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
+ WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
+ VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
+ IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+ VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
+ MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
+ VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
+ SSI_WS78_B_MARK,
+
DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
MII_RXD2_MARK,
+ VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
+ MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
+ AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
+ AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
+ AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
+ AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
+ MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
+ MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
+ MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
+ AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
+ SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
+ VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
+ MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
+ AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
+ AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
+ AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
+ SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
+ SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+
+ SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
+ SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+ SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
+ SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+ SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
+ GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
+ SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
+ MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
+ GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
+ SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
+ AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
+ AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
+ SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
+ SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
+ MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
+ AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
+ SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
+ SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
+ TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
+ SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
+ VI3_CLK_B_MARK,
+
+ SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
+ GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
+ SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
+ VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
+ VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
+ VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
+ TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
+ SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
+ VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
+ TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
+ SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
+ VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
+ TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
+ SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
+ VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
+ GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
+ MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
+ HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
+ VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
+ TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
+ VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
+ GLO_I0_B_MARK, VI3_DATA6_B_MARK,
+
+ SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
+ GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
+ TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
+ SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
+ MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
+ SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
+ MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
+ SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
+ VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
+ MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
+ RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
+ RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
+ MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
+ SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
+ SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
+ RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
+ MOUT0_MARK,
+
+ SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
+ SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
+ SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
+ SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
+ SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
+ MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
+ STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
+ CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
+ SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
+ SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
+ MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
+ SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
+ MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
+ SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
+ CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
+ IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
+ CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
+ IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
+ CAN_DEBUGOUT4_MARK,
+
+ SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
+ LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
+ SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
+ DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
+ BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
+ SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
+ LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
+ FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
+ CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
+ SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
+ CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
+ SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
+ LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
+ STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
+ TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
+ BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
+ FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
+ STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
+ CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
+ STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
+ SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
+ SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
+
+ AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
+ DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
+ REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
+ MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
+ SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
+ DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
+ TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
+ HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
+ LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
+ SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
+ MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
+ SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
+ DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+ SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
+ LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
+ CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
+ SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
+ MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
+ HRTS0_N_C_MARK,
+
+ SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
+ LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
+ DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
+ SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
+ SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
+ DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
+ DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
+ LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
+ LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
+ LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
+ DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
+ SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
+ SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
+ DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
+ DU2_DG6_MARK, LCDOUT14_MARK,
+
+ MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
+ DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
+ MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
+ ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
+ USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
+ TCLK1_B_MARK,
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+ PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
+ PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+ PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
+ PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
+ PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
+ PINMUX_DATA(AVS1_MARK, FN_AVS1),
+ PINMUX_DATA(AVS2_MARK, FN_AVS2),
+ PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
+ PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
+
PINMUX_IPSR_DATA(IP6_2_0, DACK0),
PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
+ PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
+ PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
+ PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
+ PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
+ PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
+ PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
+ PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
+ PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
+ PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
+ PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
+ PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
+ PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
+ PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
+ PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
+ PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
+ PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
+ PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
+ PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
+ PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
+ PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
+ PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
+ PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
+ PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
+ PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
+
+ PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
+ PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
+ PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
+ PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
+ PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
+ PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
+ PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
+ PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
+ PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
+ PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
+ PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
+ PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
+ PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
+ PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
+ PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
+ PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
+ PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
+ PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
+ PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
+ PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
+ PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
+ PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
+ PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
+ PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
+ PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
+
+ PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
+ PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
+ PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
+ PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
+ PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
+ PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
+ PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
+ PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
+ PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
+ PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
+ PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
+
+ PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
+ PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
+ PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
+ PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
+ PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
+ PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
+ PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
+ PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
+ PINMUX_IPSR_DATA(IP11_8_7, STM_N),
+ PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
+ PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
+ PINMUX_IPSR_DATA(IP11_10_9, MDATA),
+ PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
+ PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
+ PINMUX_IPSR_DATA(IP11_12_11, SDATA),
+ PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
+ PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
+ PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
+ PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
+ PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
+ PINMUX_IPSR_DATA(IP11_17_15, VSP),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
+ PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
+ PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
+ PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
+ PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
+ PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
+ PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
+ PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
+ PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
+ PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
+
};
static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO_GP_ALL(),
- /*IPSR0 - IPSR5*/
+ GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC_VBUS),
+ GPIO_FN(USB2_PWEN), GPIO_FN(USB2_OVC), GPIO_FN(AVS1), GPIO_FN(AVS2),
+ GPIO_FN(DU_DOTCLKIN0), GPIO_FN(DU_DOTCLKIN2),
+
+ /* IPSR0 - IPSR5 */
/*IPSR6*/
GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
- /*IPSR8 - IPSR16*/
+
+ /*IPSR8*/
+ GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(ATARD0_N), GPIO_FN(AVB_RXD3),
+ GPIO_FN(MII_RXD3), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(ATAWR0_N),
+ GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ATADIR0_N),
+ GPIO_FN(AVB_RXD5), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ATAG0_N),
+ GPIO_FN(AVB_RXD6), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(EX_WAIT1),
+ GPIO_FN(AVB_RXD7), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RX_ER),
+ GPIO_FN(MII_RX_ER), GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RX_CLK),
+ GPIO_FN(MII_RX_CLK), GPIO_FN(VI1_CLK), GPIO_FN(AVB_RX_DV),
+ GPIO_FN(MII_RX_DV), GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SCIFA1_SCK_D),
+ GPIO_FN(AVB_CRS), GPIO_FN(MII_CRS), GPIO_FN(VI1_DATA1_VI1_B1),
+ GPIO_FN(SCIFA1_RXD_D), GPIO_FN(AVB_MDC), GPIO_FN(MII_MDC),
+ GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SCIFA1_TXD_D), GPIO_FN(AVB_MDIO),
+ GPIO_FN(MII_MDIO), GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SCIFA1_CTS_N_D),
+ GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI1_DATA4_VI1_B4),
+ GPIO_FN(SCIFA1_RTS_N_D), GPIO_FN(AVB_MAGIC), GPIO_FN(MII_MAGIC),
+ GPIO_FN(VI1_DATA5_VI1_B5), GPIO_FN(AVB_PHY_INT),
+ GPIO_FN(VI1_DATA6_VI1_B6), GPIO_FN(AVB_GTXREFCLK),
+ GPIO_FN(SD0_CLK), GPIO_FN(VI1_DATA0_VI1_B0_B), GPIO_FN(SD0_CMD),
+ GPIO_FN(SCIFB1_SCK_B), GPIO_FN(VI1_DATA1_VI1_B1_B),
+
+ /*IPSR9*/
+ GPIO_FN(SD0_DAT0), GPIO_FN(SCIFB1_RXD_B), GPIO_FN(VI1_DATA2_VI1_B2_B),
+ GPIO_FN(SD0_DAT1), GPIO_FN(SCIFB1_TXD_B), GPIO_FN(VI1_DATA3_VI1_B3_B),
+ GPIO_FN(SD0_DAT2), GPIO_FN(SCIFB1_CTS_N_B), GPIO_FN(VI1_DATA4_VI1_B4_B),
+ GPIO_FN(SD0_DAT3), GPIO_FN(SCIFB1_RTS_N_B), GPIO_FN(VI1_DATA5_VI1_B5_B),
+ GPIO_FN(SD0_CD), GPIO_FN(MMC0_D6), GPIO_FN(TS_SDEN0_B),
+ GPIO_FN(USB0_EXTP), GPIO_FN(GLO_SCLK), GPIO_FN(VI1_DATA6_VI1_B6_B),
+ GPIO_FN(SCL1_B), GPIO_FN(SCL1_CIS_B), GPIO_FN(VI2_DATA6_VI2_B6_B),
+ GPIO_FN(SD0_WP), GPIO_FN(MMC0_D7), GPIO_FN(TS_SPSYNC0_B),
+ GPIO_FN(USB0_IDIN), GPIO_FN(GLO_SDATA), GPIO_FN(VI1_DATA7_VI1_B7_B),
+ GPIO_FN(SDA1_B), GPIO_FN(SDA1_CIS_B), GPIO_FN(VI2_DATA7_VI2_B7_B),
+ GPIO_FN(SD1_CLK), GPIO_FN(AVB_TX_EN), GPIO_FN(MII_TX_EN),
+ GPIO_FN(SD1_CMD), GPIO_FN(AVB_TX_ER), GPIO_FN(MII_TX_ER),
+ GPIO_FN(SCIFB0_SCK_B), GPIO_FN(SD1_DAT0), GPIO_FN(AVB_TX_CLK),
+ GPIO_FN(MII_TX_CLK), GPIO_FN(SCIFB0_RXD_B), GPIO_FN(SD1_DAT1),
+ GPIO_FN(AVB_LINK), GPIO_FN(MII_LINK), GPIO_FN(SCIFB0_TXD_B),
+ GPIO_FN(SD1_DAT2), GPIO_FN(AVB_COL), GPIO_FN(MII_COL),
+ GPIO_FN(SCIFB0_CTS_N_B), GPIO_FN(SD1_DAT3), GPIO_FN(AVB_RXD0),
+ GPIO_FN(MII_RXD0), GPIO_FN(SCIFB0_RTS_N_B), GPIO_FN(SD1_CD),
+ GPIO_FN(MMC1_D6), GPIO_FN(TS_SDEN1), GPIO_FN(USB1_EXTP),
+ GPIO_FN(GLO_SS), GPIO_FN(VI0_CLK_B), GPIO_FN(SCL2_D),
+ GPIO_FN(SCL2_CIS_D), GPIO_FN(SIM0_CLK_B), GPIO_FN(VI3_CLK_B),
+
+ /*IPSR10*/
+ GPIO_FN(SD1_WP), GPIO_FN(MMC1_D7), GPIO_FN(TS_SPSYNC1),
+ GPIO_FN(USB1_IDIN), GPIO_FN(GLO_RFON), GPIO_FN(VI1_CLK_B),
+ GPIO_FN(SDA2_D), GPIO_FN(SDA2_CIS_D), GPIO_FN(SIM0_D_B),
+ GPIO_FN(SD2_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(SIM0_CLK),
+ GPIO_FN(VI0_DATA0_VI0_B0_B), GPIO_FN(TS_SDEN0_C), GPIO_FN(GLO_SCLK_B),
+ GPIO_FN(VI3_DATA0_B), GPIO_FN(SD2_CMD), GPIO_FN(MMC0_CMD),
+ GPIO_FN(SIM0_D), GPIO_FN(VI0_DATA1_VI0_B1_B), GPIO_FN(SCIFB1_SCK_E),
+ GPIO_FN(SCK1_D), GPIO_FN(TS_SPSYNC0_C), GPIO_FN(GLO_SDATA_B),
+ GPIO_FN(VI3_DATA1_B), GPIO_FN(SD2_DAT0), GPIO_FN(MMC0_D0),
+ GPIO_FN(FMCLK_B), GPIO_FN(VI0_DATA2_VI0_B2_B), GPIO_FN(SCIFB1_RXD_E),
+ GPIO_FN(RX1_D), GPIO_FN(TS_SDAT0_C), GPIO_FN(GLO_SS_B),
+ GPIO_FN(VI3_DATA2_B), GPIO_FN(SD2_DAT1), GPIO_FN(MMC0_D1),
+ GPIO_FN(FMIN_B), GPIO_FN(RDS_DATA), GPIO_FN(VI0_DATA3_VI0_B3_B),
+ GPIO_FN(SCIFB1_TXD_E), GPIO_FN(TX1_D), GPIO_FN(TS_SCK0_C),
+ GPIO_FN(GLO_RFON_B), GPIO_FN(VI3_DATA3_B), GPIO_FN(SD2_DAT2),
+ GPIO_FN(MMC0_D2), GPIO_FN(BPFCLK_B), GPIO_FN(RDS_CLK),
+ GPIO_FN(VI0_DATA4_VI0_B4_B), GPIO_FN(HRX0_D), GPIO_FN(TS_SDEN1_B),
+ GPIO_FN(GLO_Q0_B), GPIO_FN(VI3_DATA4_B), GPIO_FN(SD2_DAT3),
+ GPIO_FN(MMC0_D3), GPIO_FN(SIM0_RST), GPIO_FN(VI0_DATA5_VI0_B5_B),
+ GPIO_FN(HTX0_D), GPIO_FN(TS_SPSYNC1_B), GPIO_FN(GLO_Q1_B),
+ GPIO_FN(VI3_DATA5_B), GPIO_FN(SD2_CD), GPIO_FN(MMC0_D4),
+ GPIO_FN(TS_SDAT0_B), GPIO_FN(USB2_EXTP), GPIO_FN(GLO_I0),
+ GPIO_FN(VI0_DATA6_VI0_B6_B), GPIO_FN(HCTS0_N_D), GPIO_FN(TS_SDAT1_B),
+ GPIO_FN(GLO_I0_B), GPIO_FN(VI3_DATA6_B),
+
+ /*IPSR11*/
+ GPIO_FN(SD2_WP), GPIO_FN(MMC0_D5), GPIO_FN(TS_SCK0_B),
+ GPIO_FN(USB2_IDIN), GPIO_FN(GLO_I1), GPIO_FN(VI0_DATA7_VI0_B7_B),
+ GPIO_FN(HRTS0_N_D), GPIO_FN(TS_SCK1_B), GPIO_FN(GLO_I1_B),
+ GPIO_FN(VI3_DATA7_B), GPIO_FN(SD3_CLK), GPIO_FN(MMC1_CLK),
+ GPIO_FN(SD3_CMD), GPIO_FN(MMC1_CMD), GPIO_FN(MTS_N), GPIO_FN(SD3_DAT0),
+ GPIO_FN(MMC1_D0), GPIO_FN(STM_N), GPIO_FN(SD3_DAT1), GPIO_FN(MMC1_D1),
+ GPIO_FN(MDATA), GPIO_FN(SD3_DAT2), GPIO_FN(MMC1_D2), GPIO_FN(SDATA),
+ GPIO_FN(SD3_DAT3), GPIO_FN(MMC1_D3), GPIO_FN(SCKZ), GPIO_FN(SD3_CD),
+ GPIO_FN(MMC1_D4), GPIO_FN(TS_SDAT1), GPIO_FN(VSP), GPIO_FN(GLO_Q0),
+ GPIO_FN(SIM0_RST_B), GPIO_FN(SD3_WP), GPIO_FN(MMC1_D5),
+ GPIO_FN(TS_SCK1), GPIO_FN(GLO_Q1), GPIO_FN(FMIN_C), GPIO_FN(RDS_DATA_B),
+ GPIO_FN(FMIN_E), GPIO_FN(RDS_DATA_D), GPIO_FN(FMIN_F),
+ GPIO_FN(RDS_DATA_E), GPIO_FN(MLB_CLK), GPIO_FN(SCL2_B),
+ GPIO_FN(SCL2_CIS_B), GPIO_FN(MLB_SIG), GPIO_FN(SCIFB1_RXD_D),
+ GPIO_FN(RX1_C), GPIO_FN(SDA2_B), GPIO_FN(SDA2_CIS_B), GPIO_FN(MLB_DAT),
+ GPIO_FN(SPV_EVEN), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(TX1_C),
+ GPIO_FN(BPFCLK_C), GPIO_FN(RDS_CLK_B), GPIO_FN(SSI_SCK0129),
+ GPIO_FN(CAN_CLK_B), GPIO_FN(MOUT0),
+
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, FN_IP14_24_22,
GP_5_0_FN, FN_IP14_21_19 }
},
-
- /*IPSR0 - IPSR5*/
+ /* IPSR0 - IPSR5 */
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
/* IP6_31_29 [3] */
FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
},
- /*IPSR8 - IPSR16*/
+ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+ 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2) {
+ /* IP8_31 [1] */
+ 0, 0,
+ /* IP8_30_29 [2] */
+ FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
+ /* IP8_28 [1] */
+ FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
+ /* IP8_27 [1] */
+ FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+ /* IP8_26 [1] */
+ FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
+ /* IP8_25_24 [2] */
+ FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+ FN_AVB_MAGIC, FN_MII_MAGIC,
+ /* IP8_23_22 [2] */
+ FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
+ /* IP8_21_20 [2] */
+ FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+ FN_MII_MDIO,
+ /* IP8_19_18 [2] */
+ FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+ /* IP8_17_16 [2] */
+ FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
+ /* IP8_15_14 [2] */
+ FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
+ /* IP8_13_12 [2] */
+ FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
+ /* IP8_11_10 [2] */
+ FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
+ /* IP8_9_8 [2] */
+ FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
+ /* IP8_7_6 [2] */
+ FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
+ /* IP8_5_4 [2] */
+ FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
+ /* IP8_3_2 [2] */
+ FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
+ /* IP8_1_0 [2] */
+ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+ 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
+ /* IP9_31_28 [4] */
+ FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
+ FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
+ FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
+ /* IP9_27_26 [2] */
+ FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
+ /* IP9_25_24 [2] */
+ FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+ /* IP9_23_22 [2] */
+ FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
+ /* IP9_21_20 [2] */
+ FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
+ /* IP9_19_18 [2] */
+ FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+ /* IP9_17_16 [2] */
+ FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
+ /* IP9_15_12 [4] */
+ FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+ FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
+ /* IP9_11_8 [4] */
+ FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+ FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
+ /* IP9_7_6 [2] */
+ FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
+ /* IP9_5_4 [2] */
+ FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
+ /* IP9_3_2 [2] */
+ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
+ /* IP9_1_0 [2] */
+ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+ 2, 4, 3, 4, 4, 4, 4, 3, 4) {
+ /* IP10_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP10_29_26 [4] */
+ FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+ FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+ FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
+ /* IP10_25_23 [3] */
+ FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+ FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
+ /* IP10_22_19 [4] */
+ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+ FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+ FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
+ /* IP10_18_15 [4] */
+ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+ FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+ FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+ 0, 0, 0, 0, 0, 0,
+ /* IP10_14_11 [4] */
+ FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+ FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+ FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+ 0, 0, 0, 0, 0, 0, 0,
+ /* IP10_10_7 [4] */
+ FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+ FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+ FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+ 0, 0, 0, 0, 0, 0, 0,
+ /* IP10_6_4 [3] */
+ FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+ FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+ FN_VI3_DATA0_B, 0,
+ /* IP10_3_0 [4] */
+ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+ FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+ FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+ 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
+ /* IP11_31_30 [2] */
+ FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
+ /* IP11_29_27 [3] */
+ FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+ FN_RDS_CLK_B, 0, 0,
+ /* IP11_26_24 [3] */
+ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
+ 0, 0, 0,
+ /* IP11_23_22 [2] */
+ FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
+ /* IP11_21_18 [4] */
+ FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+ FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+ FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
+ /* IP11_17_15 [3] */
+ FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+ FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
+ /* IP11_14_13 [2] */
+ FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
+ /* IP11_12_11 [2] */
+ FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
+ /* IP11_10_9 [2] */
+ FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
+ /* IP11_8_7 [2] */
+ FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
+ /* IP11_6_5 [2] */
+ FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
+ /* IP11_4 [1] */
+ FN_SD3_CLK, FN_MMC1_CLK,
+ /* IP11_3_0 [4] */
+ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+ FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+ 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
+ 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
+ /* SEL_SCIF1 [3] */
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+ FN_SEL_SCIF1_4, 0, 0, 0,
+ /* SEL_SCIFB [2] */
+ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
+ /* SEL_SCIFB2 [2] */
+ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
+ /* SEL_SCIFB1 [3] */
+ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
+ FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
+ FN_SEL_SCIFB1_6, 0,
+ /* SEL_SCIFA1 [2] */
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+ FN_SEL_SCIFA1_3,
+ /* SEL_SCIF0 [1] */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+ /* SEL_SCIFA [1] */
+ FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+ /* SEL_SOF1 [1] */
+ FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+ /* SEL_SSI7 [2] */
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
+ /* SEL_SSI6 [1] */
+ FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+ /* SEL_SSI5 [2] */
+ FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
+ /* SEL_VI3 [1] */
+ FN_SEL_VI3_0, FN_SEL_VI3_1,
+ /* SEL_VI2 [1] */
+ FN_SEL_VI2_0, FN_SEL_VI2_1,
+ /* SEL_VI1 [1] */
+ FN_SEL_VI1_0, FN_SEL_VI1_1,
+ /* SEL_VI0 [1] */
+ FN_SEL_VI0_0, FN_SEL_VI0_1,
+ /* SEL_TSIF1 [2] */
+ FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_LBS [1] */
+ FN_SEL_LBS_0, FN_SEL_LBS_1,
+ /* SEL_TSIF0 [2] */
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ /* SEL_SOF3 [1] */
+ FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+ /* SEL_SOF0 [1] */
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+ 2, 1, 1, 1, 1, 2, 1, 2, 1,
+ 2, 1, 1, 1, 3, 3, 2, 3, 2, 2) {
+ /* RESEVED [2] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_TMU1 [1] */
+ FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+ /* SEL_HSCIF1 [1] */
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+ /* SEL_SCIFCLK [1] */
+ FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+ /* SEL_CAN0 [2] */
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ /* SEL_CANCLK [1] */
+ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+ /* SEL_SCIFA2 [2] */
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
+ /* SEL_CAN1 [1] */
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+ /* RESEVED [2] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_ADI [1] */
+ FN_SEL_ADI_0, FN_SEL_ADI_1,
+ /* SEL_SSP [1] */
+ FN_SEL_SSP_0, FN_SEL_SSP_1,
+ /* SEL_FM [3] */
+ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+ FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
+ /* SEL_HSCIF0 [3] */
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+ FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
+ /* SEL_GPS [2] */
+ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
+ /* SEL_RDS [3] */
+ FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+ FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
+ /* SEL_SIM [2] */
+ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
+ /* SEL_SSI8 [2] */
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+ 1, 1, 2, 4, 4, 2, 2,
+ 4, 2, 3, 2, 3, 2) {
+ /* SEL_IICDVFS [1] */
+ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+ /* SEL_IIC0 [1] */
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* RESEVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_IEB [2] */
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+ /* RESEVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_IIC2 [3] */
+ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+ FN_SEL_IIC2_4, 0, 0, 0,
+ /* SEL_IIC1 [2] */
+ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
+ /* SEL_I2C2 [3] */
+ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+ FN_SEL_I2C2_4, 0, 0, 0,
+ /* SEL_I2C1 [2] */
+ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
+ },
{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
0, 0,
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */,
+ .last_gpio = GPIO_FN_MOUT0,
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
+ /* IPSR0 */
+ FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
+ FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
+ FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
+ FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
+ FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
+ FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
+ FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
+ FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
+
/*
- * From IPSR0 to IPSR5 have been removed because they does not use.
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
SD1_DATA2_MARK, SD1_DATA3_MARK,
+ /* IPSR0 */
+ SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
+ MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
+ SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
+ SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
+ MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
+ CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
+ CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
+ SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
+ SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
+ SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
+
/*
- * From IPSR0 to IPSR5 have been removed because they does not use.
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
+ /* IPSR0 */
+ PINMUX_IPSR_DATA(IP0_0, SD1_CD),
+ PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0),
+ PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
+ PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
+ PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0),
+ PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
+ PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
+ PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
+ PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
+ PINMUX_IPSR_DATA(IP0_12, MMC_D0),
+ PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
+ PINMUX_IPSR_DATA(IP0_13, MMC_D1),
+ PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
+ PINMUX_IPSR_DATA(IP0_14, MMC_D2),
+ PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
+ PINMUX_IPSR_DATA(IP0_15, MMC_D3),
+ PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
+ PINMUX_IPSR_DATA(IP0_16, MMC_D4),
+ PINMUX_IPSR_DATA(IP0_16, SD2_CD),
+ PINMUX_IPSR_DATA(IP0_17, MMC_D5),
+ PINMUX_IPSR_DATA(IP0_17, SD2_WP),
+ PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
+ PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0),
+ PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
+ PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0),
+ PINMUX_IPSR_DATA(IP0_23_22, D0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
+ PINMUX_IPSR_DATA(IP0_24, D1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_DATA(IP0_25, D2),
+ PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_DATA(IP0_27_26, D3),
+ PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
+ PINMUX_IPSR_DATA(IP0_29_28, D4),
+ PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
+ PINMUX_IPSR_DATA(IP0_31_30, D5),
+ PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
+
/*
- * From IPSR0 to IPSR5 have been removed because they does not use.
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
+ /* IPSR0 */
+ GPIO_FN(SD1_CD), GPIO_FN(CAN0_RX), GPIO_FN(SD1_WP), GPIO_FN(IRQ7),
+ GPIO_FN(CAN0_TX), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CLK), GPIO_FN(MMC_CMD),
+ GPIO_FN(SD2_CMD), GPIO_FN(MMC_D0), GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D1),
+ GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D2), GPIO_FN(SD2_DATA2),
+ GPIO_FN(MMC_D3), GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D4),
+ GPIO_FN(SD2_CD), GPIO_FN(MMC_D5), GPIO_FN(SD2_WP), GPIO_FN(MMC_D6),
+ GPIO_FN(SCIF0_RXD), GPIO_FN(I2C2_SCL_B), GPIO_FN(CAN1_RX),
+ GPIO_FN(MMC_D7), GPIO_FN(SCIF0_TXD), GPIO_FN(I2C2_SDA_B),
+ GPIO_FN(CAN1_TX), GPIO_FN(D0), GPIO_FN(SCIFA3_SCK_B), GPIO_FN(IRQ4),
+ GPIO_FN(D1), GPIO_FN(SCIFA3_RXD_B), GPIO_FN(D2), GPIO_FN(SCIFA3_TXD_B),
+ GPIO_FN(D3), GPIO_FN(I2C3_SCL_B), GPIO_FN(SCIF5_RXD_B), GPIO_FN(D4),
+ GPIO_FN(I2C3_SDA_B), GPIO_FN(SCIF5_TXD_B), GPIO_FN(D5),
+ GPIO_FN(SCIF4_RXD_B), GPIO_FN(I2C0_SCL_D),
+
/*
- * From IPSR0 to IPSR5 have been removed because they does not use
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
GP_6_1_FN, FN_SD0_CMD,
GP_6_0_FN, FN_SD0_CLK }
},
+ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+ 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+ 2, 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP0_31_30 [2] */
+ FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
+ /* IP0_29_28 [2] */
+ FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
+ /* IP0_27_26 [2] */
+ FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
+ /* IP0_25 [1] */
+ FN_D2, FN_SCIFA3_TXD_B,
+ /* IP0_24 [1] */
+ FN_D1, FN_SCIFA3_RXD_B,
+ /* IP0_23_22 [2] */
+ FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
+ /* IP0_21_20 [2] */
+ FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
+ /* IP0_19_18 [2] */
+ FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
+ /* IP0_17 [1] */
+ FN_MMC_D5, FN_SD2_WP,
+ /* IP0_16 [1] */
+ FN_MMC_D4, FN_SD2_CD,
+ /* IP0_15 [1] */
+ FN_MMC_D3, FN_SD2_DATA3,
+ /* IP0_14 [1] */
+ FN_MMC_D2, FN_SD2_DATA2,
+ /* IP0_13 [1] */
+ FN_MMC_D1, FN_SD2_DATA1,
+ /* IP0_12 [1] */
+ FN_MMC_D0, FN_SD2_DATA0,
+ /* IP0_11 [1] */
+ FN_MMC_CMD, FN_SD2_CMD,
+ /* IP0_10 [1] */
+ FN_MMC_CLK, FN_SD2_CLK,
+ /* IP0_9_8 [2] */
+ FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
+ /* IP0_7 [1] */
+ 0, 0,
+ /* IP0_6 [1] */
+ 0, 0,
+ /* IP0_5 [1] */
+ 0, 0,
+ /* IP0_4 [1] */
+ 0, 0,
+ /* IP0_3 [1] */
+ 0, 0,
+ /* IP0_2 [1] */
+ 0, 0,
+ /* IP0_1 [1] */
+ 0, 0,
+ /* IP0_0 [1] */
+ FN_SD1_CD, FN_CAN0_RX, }
+ },
/*
- * From IPSR0 to IPSR5 have been removed because they does not use.
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+++ /dev/null
-menu "Panasonic UniPhier platform"
- depends on ARCH_UNIPHIER
-
-config SYS_SOC
- default "uniphier"
-
-config SYS_CONFIG_NAME
- default "uniphier"
-
-config UNIPHIER_SMP
- bool
-
-choice
- prompt "UniPhier SoC select"
-
-config MACH_PH1_PRO4
- bool "PH1-Pro4"
- select UNIPHIER_SMP
-
-config MACH_PH1_LD4
- bool "PH1-LD4"
-
-config MACH_PH1_SLD8
- bool "PH1-sLD8"
-
-endchoice
-
-choice
- prompt "UniPhier Support Card select"
- optional
-
-config PFC_MICRO_SUPPORT_CARD
- bool "Support card with PFC CPLD"
- help
- This option provides support for the expansion board with PFC
- original address mapping.
-
- Say Y to use the on-board UART, Ether, LED devices.
-
-config DCC_MICRO_SUPPORT_CARD
- bool "Support card with DCC CPLD"
- help
- This option provides support for the expansion board with DCC-
- arranged address mapping that is compatible with legacy UniPhier
- reference boards.
-
- Say Y to use the on-board UART, Ether, LED devices.
-
-endchoice
-
-config SYS_MALLOC_F
- default y
-
-config SYS_MALLOC_F_LEN
- default 0x400
-
-config CMD_PINMON
- bool "Enable boot mode pins monitor command"
- default y
- help
- The command "pinmon" shows the state of the boot mode pins.
- The boot mode pins are latched when the system reset is deasserted
- and determine which device the system should load a boot image from.
-
-config CMD_DDRPHY_DUMP
- bool "Enable dump command of DDR PHY parameters"
- help
- The command "ddrphy" shows the resulting parameters of DDR PHY
- training; it is useful for the evaluation of DDR PHY training.
-
-choice
- prompt "DDR3 Frequency select"
-
-config DDR_FREQ_1600
- bool "DDR3 1600"
- depends on MACH_PH1_PRO4 || MACH_PH1_LD4
-
-config DDR_FREQ_1333
- bool "DDR3 1333"
- depends on MACH_PH1_LD4 || MACH_PH1_SLD8
-
-endchoice
-
-config DDR_FREQ
- int
- default 1333 if DDR_FREQ_1333
- default 1600 if DDR_FREQ_1600
-
-endmenu
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-
-obj-y += lowlevel_init.o
-obj-y += init_page_table.o
-obj-y += spl.o
-obj-y += ddrphy_training.o
-
-else
-
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
-obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
-obj-y += dram_init.o
-obj-y += board_common.o
-obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
-obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
-obj-y += reset.o
-obj-y += cache_uniphier.o
-obj-$(CONFIG_UNIPHIER_SMP) += smp.o
-obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
-obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
-
-endif
-
-obj-y += timer.o
-
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
-
-obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
-obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
-obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/led.h>
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- led_write(U, B, O, O);
-
- return 0;
-}
-
-#if CONFIG_NR_DRAM_BANKS >= 2
-void dram_init_banksize(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
- gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
-}
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/led.h>
-#include <asm/arch/board.h>
-
-void pin_init(void);
-
-int board_early_init_f(void)
-{
- led_write(U, 0, , );
-
- pin_init();
-
- led_write(U, 1, , );
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/board.h>
-
-int board_early_init_r(void)
-{
- uniphier_board_late_init();
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <../drivers/mtd/nand/denali.h>
-
-static void nand_denali_wp_disable(void)
-{
-#ifdef CONFIG_NAND_DENALI
- /*
- * Since the boot rom enables the write protection for NAND boot mode,
- * it must be disabled somewhere for "nand write", "nand erase", etc.
- * The workaround is here to not disturb the Denali NAND controller
- * driver just for a really SoC-specific thing.
- */
- void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
-
- writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
-#endif
-}
-
-int board_late_init(void)
-{
- puts("MODE: ");
-
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC1:
- printf("eMMC Boot\n");
- setenv("bootmode", "emmcboot");
- break;
- case BOOT_DEVICE_NAND:
- printf("NAND Boot\n");
- setenv("bootmode", "nandboot");
- nand_denali_wp_disable();
- break;
- case BOOT_DEVICE_NOR:
- printf("NOR Boot\n");
- setenv("bootmode", "norboot");
- break;
- default:
- printf("Unsupported Boot Mode\n");
- return -1;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/armv7.h>
-#include <asm/arch/ssc-regs.h>
-
-#ifdef CONFIG_UNIPHIER_L2CACHE_ON
-static void uniphier_cache_maint_all(u32 operation)
-{
- /* try until the command is successfully set */
- do {
- writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
- } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
- /* wait until the operation is completed */
- while (readl(SSCOLPQS) != SSCOLPQS_EF)
- ;
-
- /* clear the complete notification flag */
- writel(SSCOLPQS_EF, SSCOLPQS);
-
- writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
- readl(SSCOPE); /* need a read back to confirm */
-}
-
-void v7_outer_cache_flush_all(void)
-{
- uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_all(void)
-{
- uniphier_cache_maint_all(SSCOQM_CM_INV);
-}
-
-static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
-{
- /* try until the command is successfully set */
- do {
- writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
- writel(start, SSCOQAD);
- writel(size, SSCOQSZ);
-
- } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
- /* wait until the operation is completed */
- while (readl(SSCOLPQS) != SSCOLPQS_EF)
- ;
-
- /* clear the complete notification flag */
- writel(SSCOLPQS_EF, SSCOLPQS);
-}
-
-static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
-{
- u32 size;
-
- /*
- * If start address is not aligned to cache-line,
- * do cache operation for the first cache-line
- */
- start = start & ~(SSC_LINE_SIZE - 1);
-
- if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
- /* this means cache operation for all range */
- uniphier_cache_maint_all(operation);
- return;
- }
-
- /*
- * If end address is not aligned to cache-line,
- * do cache operation for the last cache-line
- */
- size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
-
- while (size) {
- u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
- SSC_RANGE_OP_MAX_SIZE : size;
- __uniphier_cache_maint_range(start, chunk_size, operation);
-
- start += chunk_size;
- size -= chunk_size;
- }
-
- writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
- readl(SSCOPE); /* need a read back to confirm */
-}
-
-void v7_outer_cache_flush_range(u32 start, u32 end)
-{
- uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_range(u32 start, u32 end)
-{
- uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
-}
-
-void v7_outer_cache_enable(void)
-{
- u32 tmp;
- tmp = readl(SSCC);
- tmp |= SSCC_ON;
- writel(tmp, SSCC);
-}
-#endif
-
-void v7_outer_cache_disable(void)
-{
- u32 tmp;
- tmp = readl(SSCC);
- tmp &= ~SSCC_ON;
- writel(tmp, SSCC);
-}
-
-void wakeup_secondary(void);
-
-void enable_caches(void)
-{
- uint32_t reg;
-
-#ifdef CONFIG_UNIPHIER_SMP
- /*
- * The secondary CPU must move to DDR,
- * before L2 disable.
- * On SPL, the Page Table is located on the L2.
- */
- wakeup_secondary();
-#endif
- /*
- * UniPhier SoCs must use L2 cache for init stack pointer.
- * We disable L2 and L1 in this order.
- * If CONFIG_SYS_DCACHE_OFF is not defined,
- * caches are enabled again with a new page table.
- */
-
- /* L2 disable */
- v7_outer_cache_disable();
-
- /* L1 disable */
- reg = get_cr();
- reg &= ~(CR_C | CR_M);
- set_cr(reg);
-
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-/* Select either decimal or hexadecimal */
-#if 1
-#define PRINTF_FORMAT "%2d"
-#else
-#define PRINTF_FORMAT "%02x"
-#endif
-/* field separator */
-#define FS " "
-
-static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
-{
- return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
-}
-
-static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
-{
- int ch, p, dx;
- struct ddrphy __iomem *phy;
-
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- printf("CH%dP%dDX%d:", ch, p, dx);
- (*callback)(&phy->dx[dx]);
- printf("\n");
- }
- }
- }
-}
-
-static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int i;
-
- for (i = 0; i < 10; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
-}
-
-void wbdl_dump(void)
-{
- printf("\n--- Write Bit Delay Line ---\n");
- printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
-
- dump_loop(&__wbdl_dump);
-}
-
-static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int i;
-
- for (i = 15; i < 24; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
-}
-
-void rbdl_dump(void)
-{
- printf("\n--- Read Bit Delay Line ---\n");
- printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
-
- dump_loop(&__rbdl_dump);
-}
-
-static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int rank;
- u32 lcdlr0 = readl(&dx->lcdlr[0]);
- u32 gtr = readl(&dx->gtr);
-
- for (rank = 0; rank < 4; rank++) {
- u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
- u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
-
- printf(FS PRINTF_FORMAT "%sT", wld,
- wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
- }
-}
-
-void wld_dump(void)
-{
- printf("\n--- Write Leveling Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
-
- dump_loop(&__wld_dump);
-}
-
-static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int rank;
- u32 lcdlr2 = readl(&dx->lcdlr[2]);
- u32 gtr = readl(&dx->gtr);
-
- for (rank = 0; rank < 4; rank++) {
- u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
- u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
-
- printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
- }
-}
-
-void dqsgd_dump(void)
-{
- printf("\n--- DQS Gating Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
-
- dump_loop(&__dqsgd_dump);
-}
-
-static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int i;
- u32 mdl = readl(&dx->mdlr);
- for (i = 0; i < 3; i++)
- printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
-}
-
-void mdl_dump(void)
-{
- printf("\n--- Master Delay Line ---\n");
- printf(" IPRD TPRD MDLD\n");
-
- dump_loop(&__mdl_dump);
-}
-
-#define REG_DUMP(x) \
- { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
- p - (u32 *)phy, #x, p, readl(p)); }
-
-void reg_dump(void)
-{
- int ch, p;
- struct ddrphy __iomem *phy;
-
- printf("\n--- DDR PHY registers ---\n");
-
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- printf("== Ch%d, PHY%d ==\n", ch, p);
- printf(" No: Name : Address : Data\n");
-
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
- REG_DUMP(ridr);
- REG_DUMP(pir);
- REG_DUMP(pgcr[0]);
- REG_DUMP(pgcr[1]);
- REG_DUMP(pgsr[0]);
- REG_DUMP(pgsr[1]);
- REG_DUMP(pllcr);
- REG_DUMP(ptr[0]);
- REG_DUMP(ptr[1]);
- REG_DUMP(ptr[2]);
- REG_DUMP(ptr[3]);
- REG_DUMP(ptr[4]);
- REG_DUMP(acmdlr);
- REG_DUMP(acbdlr);
- REG_DUMP(dxccr);
- REG_DUMP(dsgcr);
- REG_DUMP(dcr);
- REG_DUMP(dtpr[0]);
- REG_DUMP(dtpr[1]);
- REG_DUMP(dtpr[2]);
- REG_DUMP(mr0);
- REG_DUMP(mr1);
- REG_DUMP(mr2);
- REG_DUMP(mr3);
- REG_DUMP(dx[0].gcr);
- REG_DUMP(dx[0].gtr);
- REG_DUMP(dx[1].gcr);
- REG_DUMP(dx[1].gtr);
- }
- }
-}
-
-static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *cmd = argv[1];
-
- if (argc == 1)
- cmd = "all";
-
- if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
- wbdl_dump();
-
- if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
- rbdl_dump();
-
- if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
- wld_dump();
-
- if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
- dqsgd_dump();
-
- if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
- mdl_dump();
-
- if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
- reg_dump();
-
- return 0;
-}
-
-U_BOOT_CMD(
- ddr, 2, 1, do_ddr,
- "UniPhier DDR PHY parameters dumper",
- "- dump all of the followings\n"
- "ddr wbdl - dump Write Bit Delay\n"
- "ddr rbdl - dump Read Bit Delay\n"
- "ddr wld - dump Write Leveling\n"
- "ddr dqsgd - dump DQS Gating Delay\n"
- "ddr mdl - dump Master Delay Line\n"
- "ddr reg - dump registers\n"
-);
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/boot-device.h>
-#include <asm/arch/sbc-regs.h>
-
-static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int mode_sel, i;
-
- printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; boot_device_table[i].info; i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-
- return 0;
-}
-
-U_BOOT_CMD(
- pinmon, 1, 1, do_pinmon,
- "pin monitor",
- ""
-);
+++ /dev/null
-/*
- * Copyright (C) 2013-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-int print_cpuinfo(void)
-{
- u32 revision, type, model, rev, required_model = 1, required_rev = 1;
-
- revision = readl(SG_REVISION);
- type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT;
- model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT;
- rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT;
-
- puts("CPU: ");
-
- switch (type) {
- case 0x25:
- puts("PH1-sLD3 (MN2WS0220)");
- required_model = 2;
- break;
- case 0x26:
- puts("PH1-LD4 (MN2WS0250)");
- required_rev = 2;
- break;
- case 0x28:
- puts("PH1-Pro4 (MN2WS0230)");
- break;
- case 0x29:
- puts("PH1-sLD8 (MN2WS0270)");
- break;
- default:
- printf("Unknown Processor ID (0x%x)\n", revision);
- return -1;
- }
-
- if (model > 1)
- printf(" model %d", model);
-
- printf(" (rev. %d)\n", rev);
-
- if (model < required_model) {
- printf("Sorry, this model is not supported.\n");
- printf("Required model is %d.", required_model);
- return -1;
- } else if (rev < required_rev) {
- printf("Sorry, this revision is not supported.\n");
- printf("Required revision is %d.", required_rev);
- return -1;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
-{
- int dx;
- u32 __iomem tmp, *p;
-
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- p = &phy->dx[dx].gcr;
-
- tmp = readl(p);
- /* Specify the rank that should be write leveled */
- tmp &= ~DXGCR_WLRKEN_MASK;
- tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
- writel(tmp, p);
- }
-
- p = &phy->dtcr;
-
- tmp = readl(p);
- /* Specify the rank used during data bit deskew and eye centering */
- tmp &= ~DTCR_DTRANK_MASK;
- tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
- /* Use Multi-Purpose Register for DQS gate training */
- tmp |= DTCR_DTMPR;
- /* Specify the rank enabled for data-training */
- tmp &= ~DTCR_RNKEN_MASK;
- tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
- writel(tmp, p);
-}
-
-struct ddrphy_init_sequence {
- char *description;
- u32 init_flag;
- u32 done_flag;
- u32 err_flag;
-};
-
-static struct ddrphy_init_sequence init_sequence[] = {
- {
- "DRAM Initialization",
- PIR_DRAMRST | PIR_DRAMINIT,
- PGSR0_DIDONE,
- PGSR0_DIERR
- },
- {
- "Write Leveling",
- PIR_WL,
- PGSR0_WLDONE,
- PGSR0_WLERR
- },
- {
- "Read DQS Gate Training",
- PIR_QSGATE,
- PGSR0_QSGDONE,
- PGSR0_QSGERR
- },
- {
- "Write Leveling Adjustment",
- PIR_WLADJ,
- PGSR0_WLADONE,
- PGSR0_WLAERR
- },
- {
- "Read Bit Deskew",
- PIR_RDDSKW,
- PGSR0_RDDONE,
- PGSR0_RDERR
- },
- {
- "Write Bit Deskew",
- PIR_WRDSKW,
- PGSR0_WDDONE,
- PGSR0_WDERR
- },
- {
- "Read Eye Training",
- PIR_RDEYE,
- PGSR0_REDONE,
- PGSR0_REERR
- },
- {
- "Write Eye Training",
- PIR_WREYE,
- PGSR0_WEDONE,
- PGSR0_WEERR
- }
-};
-
-int ddrphy_training(struct ddrphy __iomem *phy)
-{
- int i;
- u32 pgsr0;
- u32 init_flag = PIR_INIT;
- u32 done_flag = PGSR0_IDONE;
- int timeout = 50000; /* 50 msec is long enough */
-#ifdef DISPLAY_ELAPSED_TIME
- ulong start = get_timer(0);
-#endif
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- init_flag |= init_sequence[i].init_flag;
- done_flag |= init_sequence[i].done_flag;
- }
-
- writel(init_flag, &phy->pir);
-
- do {
- if (--timeout < 0) {
-#ifndef CONFIG_SPL_BUILD
- printf("%s: error: timeout during DDR training\n",
- __func__);
-#endif
- return -1;
- }
- udelay(1);
- pgsr0 = readl(&phy->pgsr[0]);
- } while ((pgsr0 & done_flag) != done_flag);
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- if (pgsr0 & init_sequence[i].err_flag) {
-#ifndef CONFIG_SPL_BUILD
- printf("%s: error: %s failed\n", __func__,
- init_sequence[i].description);
-#endif
- return -1;
- }
- }
-
-#ifdef DISPLAY_ELAPSED_TIME
- printf("%s: info: elapsed time %ld msec\n", get_timer(start));
-#endif
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
- return 0;
-}
+++ /dev/null
-#include <config.h>
-#include <linux/linkage.h>
-
-/* page table */
-#define NR_SECTIONS 4096
-#define SECTION_SHIFT 20
-#define DEVICE 0x00002002 /* Non-shareable Device */
-#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
-
-#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
-#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT))
-
- .section ".rodata"
- .align 14
-ENTRY(init_page_table)
- section = 0
- .rept NR_SECTIONS
- .if section == TEXT_SECTION || section == STACK_SECTION
- attr = NORMAL
- .else
- attr = DEVICE
- .endif
- .word (section << SECTION_SHIFT) | attr
- section = section + 1
- .endr
-END(init_page_table)
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/system.h>
-#include <asm/arch/led.h>
-#include <asm/arch/arm-mpcore.h>
-#include <asm/arch/sbc-regs.h>
-
-ENTRY(lowlevel_init)
- mov r8, lr @ persevere link reg across call
-
- /*
- * The UniPhier Boot ROM loads SPL code to the L2 cache.
- * But CPUs can only do instruction fetch now because start.S has
- * cleared C and M bits.
- * First we need to turn on MMU and Dcache again to get back
- * data access to L2.
- */
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
- orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
- mcr p15, 0, r0, c1, c0, 0
-
-#ifdef CONFIG_DEBUG_LL
- bl setup_lowlevel_debug
-#endif
-
- /*
- * Now we are using the page table embedded in the Boot ROM.
- * It is not handy since it is not a straight mapped table for sLD3.
- * What we need to do next is to switch over to the page table in SPL.
- */
- ldr r3, =init_page_table @ page table must be 16KB aligned
-
- /* Disable MMU and Dcache before switching Page Table */
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
- bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
- mcr p15, 0, r0, c1, c0, 0
-
- bl enable_mmu
-
-#ifdef CONFIG_UNIPHIER_SMP
- /*
- * ACTLR (Auxiliary Control Register) for Cortex-A9
- * bit[9] Parity on
- * bit[8] Alloc in one way
- * bit[7] EXCL (Exclusive cache bit)
- * bit[6] SMP
- * bit[3] Write full line of zeros mode
- * bit[2] L1 Prefetch enable
- * bit[1] L2 prefetch enable
- * bit[0] FW (Cache and TLB maintenance broadcast)
- */
- mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
- orr r0, r0, #0x41 @ enable SMP, FW bit
- mcr p15, 0, r0, c1, c0, 1
-
- /* branch by CPU ID */
- mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
- and r0, r0, #0x3
- cmp r0, #0x0
- beq primary_cpu
- ldr r1, =ROM_BOOT_ROMRSV2
- mov r0, #0
- str r0, [r1]
-0: wfe
- ldr r0, [r1]
- cmp r0, #0
- beq 0b
- bx r0 @ r0: entry point of U-Boot main for the secondary CPU
-primary_cpu:
- ldr r1, =ROM_BOOT_ROMRSV2
- ldr r0, =_start @ entry for the secondary CPU
- str r0, [r1]
- ldr r0, [r1] @ make sure str is complete before sev
- sev @ kick the sedoncary CPU
- mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
- bfc r1, #0, #13 @ clear bit 12-0
- mov r0, #-1
- str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
- mov r0, #1 @ SCU enable
- str r0, [r1, #SCU_CTRL] @ SCU Control Register
-#endif
-
- bl setup_init_ram @ RAM area for temporary stack pointer
-
- mov lr, r8 @ restore link
- mov pc, lr @ back to my caller
-ENDPROC(lowlevel_init)
-
-ENTRY(enable_mmu)
- mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
- bic r0, r0, #0x37
- orr r0, r0, #0x20 @ disable TTBR1
- mcr p15, 0, r0, c2, c0, 2
-
- orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
- mcr p15, 0, r0, c2, c0, 0 @ TTBR0
-
- mov r0, #0
- mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
-
- mov r0, #-1 @ manager for all domains (No permission check)
- mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
-
- dsb
- isb
- /*
- * MMU on:
- * TLBs was already invalidated in "../start.S"
- * So, we don't need to invalidate it here.
- */
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
- orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
- mcr p15, 0, r0, c1, c0, 0
-
- mov pc, lr
-ENDPROC(enable_mmu)
-
-#include <asm/arch/ssc-regs.h>
-
-#define BOOT_RAM_SIZE (SSC_WAY_SIZE)
-#define BOOT_WAY_BITS (0x00000100) /* way 8 */
-
-ENTRY(setup_init_ram)
- /*
- * Touch to zero for the boot way
- */
-0:
- /*
- * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
- */
- ldr r0, = 0x00408006 @ touch to zero with address range
- ldr r1, = SSCOQM
- str r0, [r1]
- ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address
- ldr r1, = SSCOQAD
- str r0, [r1]
- ldr r0, = BOOT_RAM_SIZE
- ldr r1, = SSCOQSZ
- str r0, [r1]
- ldr r0, = BOOT_WAY_BITS
- ldr r1, = SSCOQWN
- str r0, [r1]
- ldr r1, = SSCOPPQSEF
- ldr r0, [r1]
- cmp r0, #0 @ check if the command is successfully set
- bne 0b @ try again if an error occurres
-
- ldr r1, = SSCOLPQS
-1:
- ldr r0, [r1]
- cmp r0, #0x4
- bne 1b @ wait until the operation is completed
- str r0, [r1] @ clear the complete notification flag
-
- mov pc, lr
-ENDPROC(setup_init_ram)
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
- pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/bcu-regs.h>
-
-#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-
-void bcu_init(void)
-{
- int shift;
-
- writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
- writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
-
- /* Specify DDR channel */
- shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
- writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-}
+++ /dev/null
-#include "../ph1-pro4/boot-mode.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
- tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
- | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
- | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8253c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a82dbc0, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
- writel(0x00000800, &phy->mr3);
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-}
+++ /dev/null
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <asm/arch/sg-regs.h>
-
-#define UART_CLK 36864000
-#include <asm/arch/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 85, 1, r0, r1
- set_pinsel 88, 1, r0, r1
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void pin_init(void)
-{
- u32 tmp;
-
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */
- sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */
-
- sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */
- sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */
-
- sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */
- sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */
-
- sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
- sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */
- sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */
- sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */
- sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */
- sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */
- sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */
- sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */
- sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */
- sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */
- sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */
- sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */
- sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */
- sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */
- sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */
- sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
- /* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
-#endif
-
- tmp = readl(SG_IECTRL);
- tmp |= 0x41;
- writel(tmp, SG_IECTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/platdevice.h>
-
-#define UART_MASTER_CLK 36864000
-
-SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
-SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
-SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
-SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
- {
- .base = 0x5a800100,
- },
- {
- .base = 0x5a810100,
- },
- {
- .base = 0x5a820100,
- },
-};
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-#undef DPLL_SSC_RATE_1PER
-
-static void dpll_init(void)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT (DPLLCTRL.bit[29:20])
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x000f0000;
-#if CONFIG_DDR_FREQ == 1600
- tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
- tmp |= 0x000d0000;
-#else
-# error "Unknown frequency"
-#endif
-
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~SC_DPLLCTRL_SSC_RATE;
-#else
- tmp |= SC_DPLLCTRL_SSC_RATE;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
- dpll_init();
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-}
+++ /dev/null
-#include "../ph1-pro4/pll_spectrum.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
- /* XECS1: sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-#if !defined(CONFIG_SPL_BUILD)
- /* XECS0: boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
- /* XECS3: peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0);
- writel(0x0400bc01, SBBASE1);
- writel(0x0800bf01, SBBASE3);
-
-#if !defined(CONFIG_SPL_BUILD)
- /* enable access to sub memory when boot swap is on */
- sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-#endif
- sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void sg_init(void)
-{
- u32 tmp;
-
- /* Set DDR size */
- tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
- tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
- tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
- writel(tmp, SG_MEMCONF);
-
- /* Input ports must be enabled before deasserting reset of cores */
- tmp = readl(SG_IECTRL);
- tmp |= 0x1;
- writel(tmp, SG_IECTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/umc-regs.h>
-#include <asm/arch/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
- if (freq == 1333) {
- writel(0x45990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958924, dramcont + UMC_CMDCTLB);
- writel(0x5101046A, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x27028B0A, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
- writel(0x000FF0FF, dramcont + UMC_INITCTLC);
- writel(0x00000b51, dramcont + UMC_DRMMR0);
- } else if (freq == 1600) {
- writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
- writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
- writel(0x5101387F, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x2F030D3F, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x43030D3F, dramcont + UMC_INITCTLB);
-
- writel(0x00FF00FF, dramcont + UMC_INITCTLC);
- writel(0x00000d71, dramcont + UMC_DRMMR0);
- }
-
- writel(0x00000006, dramcont + UMC_DRMMR1);
-
- if (freq == 1333)
- writel(0x00000290, dramcont + UMC_DRMMR2);
- else if (freq == 1600)
- writel(0x00000298, dramcont + UMC_DRMMR2);
-
- writel(0x00000800, dramcont + UMC_DRMMR3);
-
- if (freq == 1333) {
- if (size == 1)
- writel(0x00240512, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x00350512, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0006, dramcont + UMC_SPCCTLB);
- writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
- } else if (freq == 1600) {
- if (size == 1)
- writel(0x002B0617, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x003F0617, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0008, dramcont + UMC_SPCCTLB);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
- }
-
- writel(0x04060806, dramcont + UMC_WDATACTL_D0);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x00000003, dramcont + 0x7000);
- writel(0x0000000f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000071, dramcont + 0x8008);
- writel(0x0000003b, dramcont + UMC_DICGCTLA);
- writel(0x020a0808, dramcont + UMC_DICGCTLB);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00000000, dramcont + UMC_SPCSETD);
- writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 1);
- ddrphy_training(phy1_0);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int umc_init(void)
-{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
- (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
- CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += sbc_init.o sg_init.o pll_init.o clkrst_init.o \
- pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/boot-device.h>
-#include <asm/arch/sg-regs.h>
-#include <asm/arch/sbc-regs.h>
-
-struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- { /* sentinel */ }
-};
-
-int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 spl_boot_device(void)
-{
- int boot_mode;
-
- if (boot_is_swapped())
- return BOOT_DEVICE_NOR;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
- tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
- | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
- | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8363c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a878400, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
- writel(0x00000000, &phy->mr3);
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-}
+++ /dev/null
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-#define UART_CLK 73728000
-#include <asm/arch/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- ldr r0, =SC_CLKCTRL
- ldr r1, [r0]
- orr r1, r1, #SC_CLKCTRL_CLK_PERI
- str r1, [r0]
-
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 127, 0, r0, r1
- set_pinsel 128, 0, r0, r1
-
- ldr r0, =SG_LOADPINCTRL
- mov r1, #1
- str r1, [r0]
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */
- sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */
- sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */
- sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */
- sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */
- sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */
- sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */
- sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */
- sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */
- sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */
- sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */
- sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */
- sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */
- sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */
- sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */
- sg_set_pinsel(48, 0); /* NFALE -> NFALE */
- sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */
- sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */
- sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */
- sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */
- sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */
- sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/platdevice.h>
-
-#define UART_MASTER_CLK 73728000
-
-SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
-SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
-SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
-SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
- {
- .base = 0x5a800100,
- },
- {
- .base = 0x5a810100,
- },
-};
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-#undef DPLL_SSC_RATE_1PER
-
-static void dpll_init(void)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT ( DPLLCTRL.bit[29:20] )
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~(0x000f0000);
-#if CONFIG_DDR_FREQ == 1600
- tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
- tmp |= 0x000d0000;
-#else
-# error "Unsupported frequency"
-#endif
-
- /*
- * Set Moduration rate
- * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
- */
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~0x00008000;
-#else
- tmp |= 0x00008000;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void stop_mpll(void)
-{
- u32 tmp;
-
- tmp = readl(SC_MPLLOSCCTL);
-
- if (!(tmp & SC_MPLLOSCCTL_MPLLST))
- return; /* already stopped */
-
- tmp &= ~SC_MPLLOSCCTL_MPLLEN;
- writel(tmp, SC_MPLLOSCCTL);
-
- while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST)
- ;
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- /* Set VPLL27A & VPLL27B */
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-#if defined(CONFIG_MACH_PH1_PRO4)
- /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
- return;
-#endif
-
- /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Unset VPLA_K_LD and VPLB_K_LD bit */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set VPLA_M and VPLB_M to 0x20 */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
- /* Set VPLA_K and VPLB_K for AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* wait 1 usec */
- udelay(1);
-
- /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Unset VPLA_SNRST and VPLB_SNRST bit */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
- dpll_init();
- stop_mpll();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 1 usec in vpll_init() so 1 usec can be saved here.
- */
- udelay(499);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void enable_dpll_ssc(void)
-{
- u32 tmp;
-
- tmp = readl(SC_DPLLCTRL);
- tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
- *
- * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
- * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x3effffff: memory bank (31MB)
- * 0x03f00000-0x3fffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-#if !defined(CONFIG_SPL_BUILD)
- /* XECS0: boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
- /* XECS1: sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
- /* XECS3: peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
- writel(0x0000bc01, SBBASE0); /* boot memory */
- writel(0x0400bc01, SBBASE1); /* sub memory */
- writel(0x0800bf01, SBBASE3); /* peripherals */
-
-#if !defined(CONFIG_SPL_BUILD)
- sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
-#endif
- sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
- writel(0x00000001, SG_LOADPINCTRL);
-
-#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void sg_init(void)
-{
- u32 tmp;
-
- /* Set DDR size */
- tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
- tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
- tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
- writel(tmp, SG_MEMCONF);
-
- /* Input ports must be enabled before deasserting reset of cores */
- tmp = readl(SG_IECTRL);
- tmp |= 1 << 6;
- writel(tmp, SG_IECTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/umc-regs.h>
-#include <asm/arch/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000001, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x07ffffff, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
-
- writel(0x03010100, ssif_base + UMC_HDMCHSEL);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DVCCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
- writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_HDMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_HDDRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_GIORST);
- writel(0x00000001, ssif_base + UMC_HD2RST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_DVCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_VPERST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
- writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
- writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
- writel(0x5101387f, dramcont + UMC_INITCTLA);
- writel(0x43030d3f, dramcont + UMC_INITCTLB);
- writel(0x00ff00ff, dramcont + UMC_INITCTLC);
- writel(0x00000d71, dramcont + UMC_DRMMR0);
- writel(0x00000006, dramcont + UMC_DRMMR1);
- writel(0x00000298, dramcont + UMC_DRMMR2);
- writel(0x00000000, dramcont + UMC_DRMMR3);
- writel(0x003f0617, dramcont + UMC_SPCCTLA);
- writel(0x00ff0008, dramcont + UMC_SPCCTLB);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
- writel(0x04060802, dramcont + UMC_WDATACTL_D0);
- writel(0x04060802, dramcont + UMC_WDATACTL_D1);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x0000000f, dramcont + 0x7000);
- writel(0x0000000f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000071, dramcont + 0x8008);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x00000000, dramcont + 0x0060);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00010000, dramcont + UMC_SPCSETD);
- writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
- void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000103, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_1, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_1, 1);
- ddrphy_training(phy0_1);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 0);
- ddrphy_training(phy1_0);
-
- writel(0x00000103, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_1, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_1, 1);
- ddrphy_training(phy1_1);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int umc_init(void)
-{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
- (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
- ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
- (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
-/* OK */
-#else
- #error Unsupported DDR configuration.
-#endif
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
- pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
+++ /dev/null
-#include "../ph1-ld4/bcu_init.c"
+++ /dev/null
-#include "../ph1-pro4/boot-mode.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
- tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
- | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
- | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8363c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a878400, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
-#ifdef CONFIG_DDR_STANDARD
- writel(0x00000000, &phy->mr3);
-#else
- writel(0x00000800, &phy->mr3);
-#endif
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-}
+++ /dev/null
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <asm/arch/sg-regs.h>
-
-#define UART_CLK 80000000
-#include <asm/arch/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 70, 3, r0, r1
- set_pinsel 71, 3, r0, r1
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */
- sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */
-
- sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */
- sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */
-
- sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */
- sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */
-
- sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
- sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
-#endif
-
-#ifdef CONFIG_SYS_I2C_UNIPHIER
- {
- u32 tmp;
- tmp = readl(SG_IECTRL);
- tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
- writel(tmp, SG_IECTRL);
- }
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */
- sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */
- sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */
- sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */
- sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */
- sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */
- sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */
- sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */
- sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */
- sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */
- sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */
- sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */
- sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */
- sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */
- sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
- /* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/platdevice.h>
-
-#define UART_MASTER_CLK 80000000
-
-SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
-SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
-SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
-SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
- {
- .base = 0x5a800100,
- },
- {
- .base = 0x5a810100,
- },
- {
- .base = 0x5a820100,
- },
-};
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-static void dpll_init(void)
-{
- u32 tmp;
- /*
- * Set DPLL SSC parameters for DPLLCTRL3
- * [23] DIVN_TEST 0x1
- * [22:16] DIVN 0x50
- * [10] FREFSEL_TEST 0x1
- * [9:8] FREFSEL 0x2
- * [4] ICPD_TEST 0x1
- * [3:0] ICPD 0xb
- */
- tmp = readl(SC_DPLLCTRL3);
- tmp &= ~0x00ff0717;
- tmp |= 0x00d0061b;
- writel(tmp, SC_DPLLCTRL3);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL
- * <-1%> <-2%>
- * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
- * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x3ff07fff;
-#ifdef CONFIG_DPLL_SSC_RATE_1PER
- tmp |= 0x084018bf;
-#else
- tmp |= 0x084031a6;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL2
- * [31:29] SSC_STEP 0
- * [27] SSC_REG_REF 1
- * [26:20] SSC_M 79 (0x4f)
- * [19:0] SSC_K 964689 (0xeb851)
- */
- tmp = readl(SC_DPLLCTRL2);
- tmp &= ~0xefffffff;
- tmp |= 0x0cfeb851;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
- dpll_init();
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-}
+++ /dev/null
-#include "../ph1-ld4/pll_spectrum.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
-#if !defined(CONFIG_SPL_BUILD)
- /* XECS0 : dummy */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
- /* XECS1 : boot memory (always boot swap = on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
- /* XECS4 : sub memory */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
-
- /* XECS5 : peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0); /* boot memory */
- writel(0x0900bfff, SBBASE1); /* dummy */
- writel(0x0400bc01, SBBASE4); /* sub memory */
- writel(0x0800bf01, SBBASE5); /* peripherals */
-
- sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
- sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
-
- /* dummy read to assure write process */
- readl(SG_PINCTRL(33));
-}
+++ /dev/null
-#include "../ph1-ld4/sg_init.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/umc-regs.h>
-#include <asm/arch/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
-#ifdef CONFIG_DDR_STANDARD
- writel(0x55990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958944, dramcont + UMC_CMDCTLB);
-#else
- writel(0x45990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958924, dramcont + UMC_CMDCTLB);
-#endif
-
- writel(0x5101046A, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x27028B0A, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
- writel(0x00FF00FF, dramcont + UMC_INITCTLC);
- writel(0x00000b51, dramcont + UMC_DRMMR0);
- writel(0x00000006, dramcont + UMC_DRMMR1);
- writel(0x00000290, dramcont + UMC_DRMMR2);
-
-#ifdef CONFIG_DDR_STANDARD
- writel(0x00000000, dramcont + UMC_DRMMR3);
-#else
- writel(0x00000800, dramcont + UMC_DRMMR3);
-#endif
-
- if (size == 1)
- writel(0x00240512, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x00350512, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0006, dramcont + UMC_SPCCTLB);
- writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
- writel(0x04060806, dramcont + UMC_WDATACTL_D0);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x00000003, dramcont + 0x7000);
- writel(0x0000004f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000077, dramcont + 0x8008);
- writel(0x0000003b, dramcont + UMC_DICGCTLA);
- writel(0x020a0808, dramcont + UMC_DICGCTLB);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00000000, dramcont + UMC_SPCSETD);
- writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 1);
- ddrphy_training(phy1_0);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int umc_init(void)
-{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
- (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
- CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/board.h>
-
-int misc_init_f(void)
-{
- return check_support_card();
-}
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void reset_cpu(unsigned long ignored)
-{
- u32 tmp;
-
- writel(5, SC_IRQTIMSET); /* default value */
-
- tmp = readl(SC_SLFRSTSEL);
- tmp &= ~0x3; /* mask [1:0] */
- tmp |= 0x0; /* XRST reboot */
- writel(tmp, SC_SLFRSTSEL);
-
- tmp = readl(SC_SLFRSTCTL);
- tmp |= 0x1;
- writel(tmp, SC_SLFRSTCTL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/system.h>
-#include <asm/arch/led.h>
-#include <asm/arch/sbc-regs.h>
-
-/* Entry point of U-Boot main program for the secondary CPU */
-LENTRY(secondary_entry)
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
- bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable
- mcr p15, 0, r0, c1, c0, 0
- mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
- mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
- dsb
- led_write(C,0,,)
- ldr r1, =ROM_BOOT_ROMRSV2
- mov r0, #0
- str r0, [r1]
-0: wfe
- ldr r4, [r1] @ r4: entry point for secondary CPUs
- cmp r4, #0
- beq 0b
- led_write(C, P, U, 1)
- bx r4 @ secondary CPUs jump to linux
-ENDPROC(secondary_entry)
-
-ENTRY(wakeup_secondary)
- ldr r1, =ROM_BOOT_ROMRSV2
-0: ldr r0, [r1]
- cmp r0, #0
- bne 0b
-
- /* set entry address and send event to the secondary CPU */
- ldr r0, =secondary_entry
- str r0, [r1]
- ldr r0, [r1] @ make sure store is complete
- mov r0, #0x100
-0: subs r0, r0, #1 @ I don't know the reason, but without this wait
- bne 0b @ fails to wake up the secondary CPU
- sev
-
- /* wait until the secondary CPU reach to secondary_entry */
-0: ldr r0, [r1]
- cmp r0, #0
- bne 0b
- bx lr
-ENDPROC(wakeup_secondary)
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/compiler.h>
-#include <asm/arch/led.h>
-#include <asm/arch/board.h>
-
-void __weak bcu_init(void)
-{
-};
-void sbc_init(void);
-void sg_init(void);
-void pll_init(void);
-void pin_init(void);
-void clkrst_init(void);
-int umc_init(void);
-void enable_dpll_ssc(void);
-
-void spl_board_init(void)
-{
- bcu_init();
-
- sbc_init();
-
- sg_init();
-
- uniphier_board_reset();
-
- pll_init();
-
- uniphier_board_init();
-
- led_write(L, 0, , );
-
- clkrst_init();
-
- led_write(L, 1, , );
-
- {
- int res;
-
- res = umc_init();
- if (res < 0) {
- while (1)
- ;
- }
- }
- led_write(L, 2, , );
-
- enable_dpll_ssc();
-
- led_write(L, 3, , );
-}
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/board.h>
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-
-#define PFC_MICRO_SUPPORT_CARD_RESET \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
-#define PFC_MICRO_SUPPORT_CARD_REVISION \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
-/*
- * 0: reset deassert, 1: reset
- *
- * bit[0]: LAN, I2C, LED
- * bit[1]: UART
- */
-void support_card_reset_deassert(void)
-{
- writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
-}
-
-void support_card_reset(void)
-{
- writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
-}
-
-static int support_card_show_revision(void)
-{
- u32 revision;
-
- revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
- printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-
-#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
-#define DCC_MICRO_SUPPORT_CARD_RESET_UART \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
-#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
-#define DCC_MICRO_SUPPORT_CARD_REVISION \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
-
-void support_card_reset_deassert(void)
-{
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-void support_card_reset(void)
-{
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-static int support_card_show_revision(void)
-{
- u32 revision;
-
- revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
-
- if (revision >= 0x67) {
- printf("(DCC CPLD version 3.%d.%d)\n",
- revision >> 4, revision & 0xf);
- return 0;
- } else {
- printf("(DCC CPLD unknown version)\n");
- return -1;
- }
-}
-#endif
-
-int check_support_card(void)
-{
- printf("SC: Micro Support Card ");
- return support_card_show_revision();
-}
-
-void support_card_init(void)
-{
- /*
- * After power on, we need to keep the LAN controller in reset state
- * for a while. (200 usec)
- * Fortunatelly, enough wait time is already inserted in pll_init()
- * function. So we do not have to wait here.
- */
- support_card_reset_deassert();
-}
-
-#if defined(CONFIG_SMC911X)
-#include <netdev.h>
-
-int board_eth_init(bd_t *bis)
-{
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-
-#include <mtd/cfi_flash.h>
-#include <asm/arch/sbc-regs.h>
-
-struct memory_bank {
- phys_addr_t base;
- unsigned long size;
-};
-
-static int mem_is_flash(const struct memory_bank *mem)
-{
- const int loop = 128;
- u32 *scratch_addr;
- u32 saved_value;
- int ret = 1;
- int i;
-
- /* just in case, use the tail of the memory bank */
- scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
- sizeof(u32) * loop, MAP_NOCACHE);
-
- for (i = 0; i < loop; i++, scratch_addr++) {
- saved_value = readl(scratch_addr);
- writel(~saved_value, scratch_addr);
- if (readl(scratch_addr) != saved_value) {
- /* We assume no memory or SRAM here. */
- writel(saved_value, scratch_addr);
- ret = 0;
- break;
- }
- }
-
- unmap_physmem(scratch_addr, MAP_NOCACHE);
-
- return ret;
-}
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
- /* {address, size} */
-static const struct memory_bank memory_banks_boot_swap_off[] = {
- {0x02000000, 0x01f00000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
- {0x00000000, 0x01f00000},
-};
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-static const struct memory_bank memory_banks_boot_swap_off[] = {
- {0x04000000, 0x02000000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
- {0x00000000, 0x02000000},
- {0x04000000, 0x02000000},
-};
-#endif
-
-static const struct memory_bank
-*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
-
-phys_addr_t cfi_flash_bank_addr(int i)
-{
- return flash_banks_list[i]->base;
-}
-
-unsigned long cfi_flash_bank_size(int i)
-{
- return flash_banks_list[i]->size;
-}
-
-static void detect_num_flash_banks(void)
-{
- const struct memory_bank *memory_bank, *end;
-
- cfi_flash_num_flash_banks = 0;
-
- if (boot_is_swapped()) {
- memory_bank = memory_banks_boot_swap_on;
- end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
- } else {
- memory_bank = memory_banks_boot_swap_off;
- end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
- }
-
- for (; memory_bank < end; memory_bank++) {
- if (cfi_flash_num_flash_banks >=
- CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
- break;
-
- if (mem_is_flash(memory_bank)) {
- flash_banks_list[cfi_flash_num_flash_banks] =
- memory_bank;
-
- debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
- memory_bank->base, memory_bank->size);
- cfi_flash_num_flash_banks++;
- }
- }
-
- debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
-}
-#else /* ONFIG_SYS_NO_FLASH */
-void detect_num_flash_banks(void)
-{
-};
-#endif /* ONFIG_SYS_NO_FLASH */
-
-void support_card_late_init(void)
-{
- detect_num_flash_banks();
-}
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/arm-mpcore.h>
-
-#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
-#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
-
-static void *get_global_timer_base(void)
-{
- void *val;
-
- asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory");
-
- return val + GLOBAL_TIMER_OFFSET;
-}
-
-unsigned long timer_read_counter(void)
-{
- /*
- * ARM 64bit Global Timer is too much for our purpose.
- * We use only lower 32 bit of the timer counter.
- */
- return readl(get_global_timer_base() + GTIMER_CNT_L);
-}
-
-int timer_init(void)
-{
- /* enable timer */
- writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL);
-
- return 0;
-}
/*
* Device Tree Source for UniPhier PH1-LD4 SoC
*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
};
usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
i2c3 = &i2c3;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ usb0 = &usb0;
};
};
&usb0 {
status = "okay";
};
-
-&usb1 {
- status = "okay";
-};
/*
* Device Tree Source for UniPhier PH1-Pro4 SoC
*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
status = "ok";
};
- usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ usb2: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
- usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ usb3: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
+ usb0: usb@65a00000 {
+ compatible = "panasonic,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ };
+
+ usb1: usb@65c00000 {
+ compatible = "panasonic,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ };
+
nand: nand@68000000 {
compatible = "denali,denali-nand-dt";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
/*
* Device Tree Source for UniPhier PH1-sLD3 SoC
*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
};
usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
usb3: usb@5a830100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a830100 0x100>;
};
/*
* Device Tree Source for UniPhier PH1-sLD8 SoC
*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
};
usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
- compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
#define EXYNOS5420_CLOCK_BASE 0x10010000
#define EXYNOS5420_POWER_BASE 0x10040000
#define EXYNOS5420_SWRESET 0x10040400
+#define EXYNOS5420_INFORM_BASE 0x10040800
+#define EXYNOS5420_SPARE_BASE 0x10040900
+#define EXYNOS5420_CPU_CONFIG_BASE 0x10042000
+#define EXYNOS5420_CPU_STATUS_BASE 0x10042004
#define EXYNOS5420_SYSREG_BASE 0x10050000
#define EXYNOS5420_TZPC_BASE 0x100E0000
#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
#define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
+
#ifndef __ASSEMBLY__
#include <asm/io.h>
/* CPU detection macros */
#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
+/*
+ * Data Synchronization Barrier acts as a special kind of memory barrier.
+ * No instruction in program order after this instruction executes until
+ * this instruction completes. This instruction completes when:
+ * - All explicit memory accesses before this instruction complete.
+ * - All Cache, Branch predictor and TLB maintenance operations before
+ * this instruction complete.
+ */
+#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
+
+/*
+ * This instruction causes an event to be signaled to all cores
+ * within a multiprocessor system. If SEV is implemented,
+ * WFE must also be implemented.
+ */
+#define sev() __asm__ __volatile__ ("sev\n\t" : : );
+/*
+ * If the Event Register is not set, WFE suspends execution until
+ * one of the following events occurs:
+ * - an IRQ interrupt, unless masked by the CPSR I-bit
+ * - an FIQ interrupt, unless masked by the CPSR F-bit
+ * - an Imprecise Data abort, unless masked by the CPSR A-bit
+ * - a Debug Entry request, if Debug is enabled
+ * - an Event signaled by another processor using the SEV instruction.
+ * If the Event Register is set, WFE clears it and returns immediately.
+ * If WFE is implemented, SEV must also be implemented.
+ */
+#define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
+
+/* Move 0xd3 value to CPSR register to enable SVC mode */
+#define svc32_mode_en() __asm__ __volatile__ \
+ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \
+ "msr cpsr_c, #0x13|0xC0\n\t" : : )
+
+/* Set program counter with the given value */
+#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
+
+/* Branch to the given location */
+#define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x))
+
+/* Read Main Id register */
+#define mrc_midr(x) __asm__ __volatile__ \
+ ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
+
+/* Read Multiprocessor Affinity Register */
+#define mrc_mpafr(x) __asm__ __volatile__ \
+ ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
+
+/* Read System Control Register */
+#define mrc_sctlr(x) __asm__ __volatile__ \
+ ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
+
+/* Read Auxiliary Control Register */
+#define mrc_auxr(x) __asm__ __volatile__ \
+ ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
+
+/* Read L2 Control register */
+#define mrc_l2_ctlr(x) __asm__ __volatile__ \
+ ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
+
+/* Read L2 Auxilliary Control register */
+#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \
+ ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
+
+/* Write System Control Register */
+#define mcr_sctlr(x) __asm__ __volatile__ \
+ ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
+
+/* Write Auxiliary Control Register */
+#define mcr_auxr(x) __asm__ __volatile__ \
+ ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
+
+/* Invalidate all instruction caches to PoU */
+#define mcr_icache(x) __asm__ __volatile__ \
+ ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x))
+
+/* Invalidate unified TLB */
+#define mcr_tlb(x) __asm__ __volatile__ \
+ ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x))
+
+/* Write L2 Control register */
+#define mcr_l2_ctlr(x) __asm__ __volatile__ \
+ ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
+
+/* Write L2 Auxilliary Control register */
+#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \
+ ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x))
+
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0,
GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3,
+ /* IPSR0 */
+ GPIO_FN_SD1_CD, GPIO_FN_CAN0_RX, GPIO_FN_SD1_WP, GPIO_FN_IRQ7,
+ GPIO_FN_CAN0_TX, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CLK, GPIO_FN_MMC_CMD,
+ GPIO_FN_SD2_CMD, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D1,
+ GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA2,
+ GPIO_FN_MMC_D3, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D4,
+ GPIO_FN_SD2_CD, GPIO_FN_MMC_D5, GPIO_FN_SD2_WP, GPIO_FN_MMC_D6,
+ GPIO_FN_SCIF0_RXD, GPIO_FN_I2C2_SCL_B, GPIO_FN_CAN1_RX, GPIO_FN_MMC_D7,
+ GPIO_FN_SCIF0_TXD, GPIO_FN_I2C2_SDA_B, GPIO_FN_CAN1_TX, GPIO_FN_D0,
+ GPIO_FN_SCIFA3_SCK_B, GPIO_FN_IRQ4, GPIO_FN_D1, GPIO_FN_SCIFA3_RXD_B,
+ GPIO_FN_D2, GPIO_FN_SCIFA3_TXD_B, GPIO_FN_D3, GPIO_FN_I2C3_SCL_B,
+ GPIO_FN_SCIF5_RXD_B, GPIO_FN_D4, GPIO_FN_I2C3_SDA_B,
+ GPIO_FN_SCIF5_TXD_B, GPIO_FN_D5, GPIO_FN_SCIF4_RXD_B,
+ GPIO_FN_I2C0_SCL_D,
+
/*
- * From IPSR0 to IPSR5 have been removed because they does not use.
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2,
GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK,
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
+ /* IPSR9 */
+ GPIO_FN_MSIOF0_TXD, GPIO_FN_SCIF5_TXD, GPIO_FN_I2C2_SDA_C,
+ GPIO_FN_DU1_DR3, GPIO_FN_RIF1_D1_B, GPIO_FN_TS_SPSYNC_D, GPIO_FN_FMIN_C,
+ GPIO_FN_RDS_DATA, GPIO_FN_MSIOF0_SCK, GPIO_FN_IRQ0, GPIO_FN_TS_SDATA,
+ GPIO_FN_DU1_DR4, GPIO_FN_RIF1_SYNC, GPIO_FN_TPUTO1_C,
+ GPIO_FN_MSIOF0_SYNC, GPIO_FN_PWM1, GPIO_FN_TS_SCK, GPIO_FN_DU1_DR5,
+ GPIO_FN_RIF1_CLK, GPIO_FN_BPFCLK_B, GPIO_FN_MSIOF0_SS1,
+ GPIO_FN_SCIFA0_RXD, GPIO_FN_TS_SDEN, GPIO_FN_DU1_DR6, GPIO_FN_RIF1_D0,
+ GPIO_FN_FMCLK_B, GPIO_FN_RDS_CLK_B, GPIO_FN_MSIOF0_SS2,
+ GPIO_FN_SCIFA0_TXD, GPIO_FN_TS_SPSYNC, GPIO_FN_DU1_DR7, GPIO_FN_RIF1_D1,
+ GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA_B, GPIO_FN_HSCIF1_HRX,
+ GPIO_FN_I2C4_SCL, GPIO_FN_PWM6, GPIO_FN_DU1_DG0, GPIO_FN_HSCIF1_HTX,
+ GPIO_FN_I2C4_SDA, GPIO_FN_TPUTO1, GPIO_FN_DU1_DG1, GPIO_FN_HSCIF1_HSCK,
+ GPIO_FN_PWM2, GPIO_FN_IETX, GPIO_FN_DU1_DG2, GPIO_FN_REMOCON_B,
+ GPIO_FN_SPEEDIN_B, GPIO_FN_VSP_B, GPIO_FN_HSCIF1_HCTS_N,
+ GPIO_FN_SCIFA4_RXD, GPIO_FN_IECLK, GPIO_FN_DU1_DG3, GPIO_FN_SSI_SCK1_B,
+ GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_CC50_STATE32,
+ GPIO_FN_HSCIF1_HRTS_N, GPIO_FN_SCIFA4_TXD, GPIO_FN_IERX,
+ GPIO_FN_DU1_DG4, GPIO_FN_SSI_WS1_B, GPIO_FN_CAN_STEP0,
+ GPIO_FN_CC50_STATE33, GPIO_FN_SCIF1_SCK, GPIO_FN_PWM3, GPIO_FN_TCLK2,
+ GPIO_FN_DU1_DG5, GPIO_FN_SSI_SDATA1_B, GPIO_FN_CAN_TXCLK,
+ GPIO_FN_CC50_STATE34,
+
+ /* IPSR10 */
+ GPIO_FN_SCIF1_RXD, GPIO_FN_IIC0_SCL, GPIO_FN_DU1_DG6,
+ GPIO_FN_SSI_SCK2_B, GPIO_FN_CAN_DEBUGOUT0, GPIO_FN_CC50_STATE35,
+ GPIO_FN_SCIF1_TXD, GPIO_FN_IIC0_SDA, GPIO_FN_DU1_DG7, GPIO_FN_SSI_WS2_B,
+ GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_CC50_STATE36, GPIO_FN_SCIF2_RXD,
+ GPIO_FN_IIC1_SCL, GPIO_FN_DU1_DB0, GPIO_FN_SSI_SDATA2_B,
+ GPIO_FN_USB0_EXTLP, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_CC50_STATE37,
+ GPIO_FN_SCIF2_TXD, GPIO_FN_IIC1_SDA, GPIO_FN_DU1_DB1,
+ GPIO_FN_SSI_SCK9_B, GPIO_FN_USB0_OVC1, GPIO_FN_CAN_DEBUGOUT3,
+ GPIO_FN_CC50_STATE38, GPIO_FN_SCIF2_SCK, GPIO_FN_IRQ1, GPIO_FN_DU1_DB2,
+ GPIO_FN_SSI_WS9_B, GPIO_FN_USB0_IDIN, GPIO_FN_CAN_DEBUGOUT4,
+ GPIO_FN_CC50_STATE39, GPIO_FN_SCIF3_SCK, GPIO_FN_IRQ2, GPIO_FN_BPFCLK_D,
+ GPIO_FN_DU1_DB3, GPIO_FN_SSI_SDATA9_B, GPIO_FN_TANS2,
+ GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_CC50_OSCOUT, GPIO_FN_SCIF3_RXD,
+ GPIO_FN_I2C1_SCL_E, GPIO_FN_FMCLK_D, GPIO_FN_DU1_DB4,
+ GPIO_FN_AUDIO_CLKA_C, GPIO_FN_SSI_SCK4_B, GPIO_FN_CAN_DEBUGOUT6,
+ GPIO_FN_RDS_CLK_C, GPIO_FN_SCIF3_TXD, GPIO_FN_I2C1_SDA_E,
+ GPIO_FN_FMIN_D, GPIO_FN_DU1_DB5, GPIO_FN_AUDIO_CLKB_C,
+ GPIO_FN_SSI_WS4_B, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_RDS_DATA_C,
+ GPIO_FN_I2C2_SCL, GPIO_FN_SCIFA5_RXD, GPIO_FN_DU1_DB6,
+ GPIO_FN_AUDIO_CLKC_C, GPIO_FN_SSI_SDATA4_B, GPIO_FN_CAN_DEBUGOUT8,
+ GPIO_FN_I2C2_SDA, GPIO_FN_SCIFA5_TXD, GPIO_FN_DU1_DB7,
+ GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SCK5,
+ GPIO_FN_SCIFA3_SCK, GPIO_FN_CAN_DEBUGOUT10,
+ GPIO_FN_DU1_DOTCLKIN,
/* IPSR11 */
GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C,
GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B,
GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B,
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
+ /* IPSR12 */
+ GPIO_FN_SSI_SCK34, GPIO_FN_MSIOF1_SYNC_B, GPIO_FN_SCIFA1_SCK_C,
+ GPIO_FN_ADICHS0_B, GPIO_FN_AD_NCS_N_B, GPIO_FN_DREQ1_N_B,
+ GPIO_FN_SSI_WS34, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_SCIFA1_RXD_C,
+ GPIO_FN_ADICHS1_B, GPIO_FN_CAN1_RX_C, GPIO_FN_DACK1_B,
+ GPIO_FN_SSI_SDATA3, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_SCIFA1_TXD_C,
+ GPIO_FN_ADICHS2_B, GPIO_FN_CAN1_TX_C, GPIO_FN_DREQ2_N, GPIO_FN_SSI_SCK4,
+ GPIO_FN_MLB_CK, GPIO_FN_IETX_B, GPIO_FN_IRD_TX, GPIO_FN_SSI_WS4,
+ GPIO_FN_MLB_SIG, GPIO_FN_IECLK_B, GPIO_FN_IRD_RX, GPIO_FN_SSI_SDATA4,
+ GPIO_FN_MLB_DAT, GPIO_FN_IERX_B, GPIO_FN_IRD_SCK, GPIO_FN_SSI_SDATA8,
+ GPIO_FN_SCIF1_SCK_B, GPIO_FN_PWM1_B, GPIO_FN_IRQ9, GPIO_FN_REMOCON,
+ GPIO_FN_DACK2, GPIO_FN_ETH_MDIO_B, GPIO_FN_SSI_SCK1,
+ GPIO_FN_SCIF1_RXD_B, GPIO_FN_IIC1_SCL_C, GPIO_FN_VI1_CLK,
+ GPIO_FN_CAN0_RX_D, GPIO_FN_AVB_AVTP_CAPTURE, GPIO_FN_ETH_CRS_DV_B,
+ GPIO_FN_SSI_WS1, GPIO_FN_SCIF1_TXD_B, GPIO_FN_IIC1_SDA_C,
+ GPIO_FN_VI1_DATA0, GPIO_FN_CAN0_TX_D, GPIO_FN_AVB_AVTP_MATCH,
+ GPIO_FN_ETH_RX_ER_B, GPIO_FN_SSI_SDATA1, GPIO_FN_HSCIF1_HRX_B,
+ GPIO_FN_VI1_DATA1, GPIO_FN_SDATA, GPIO_FN_ATAG0_N, GPIO_FN_ETH_RXD0_B,
+ GPIO_FN_SSI_SCK2, GPIO_FN_HSCIF1_HTX_B, GPIO_FN_VI1_DATA2,
+ GPIO_FN_MDATA, GPIO_FN_ATAWR0_N, GPIO_FN_ETH_RXD1_B,
+
+ /* IPSR13 */
+ GPIO_FN_SSI_WS2, GPIO_FN_HSCIF1_HCTS_N_B, GPIO_FN_SCIFA0_RXD_D,
+ GPIO_FN_VI1_DATA3, GPIO_FN_SCKZ, GPIO_FN_ATACS00_N, GPIO_FN_ETH_LINK_B,
+ GPIO_FN_SSI_SDATA2, GPIO_FN_HSCIF1_HRTS_N_B, GPIO_FN_SCIFA0_TXD_D,
+ GPIO_FN_VI1_DATA4, GPIO_FN_STM_N, GPIO_FN_ATACS10_N,
+ GPIO_FN_ETH_REFCLK_B, GPIO_FN_SSI_SCK9, GPIO_FN_SCIF2_SCK_B,
+ GPIO_FN_PWM2_B, GPIO_FN_VI1_DATA5, GPIO_FN_MTS_N, GPIO_FN_EX_WAIT1,
+ GPIO_FN_ETH_TXD1_B, GPIO_FN_SSI_WS9, GPIO_FN_SCIF2_RXD_B,
+ GPIO_FN_I2C3_SCL_E, GPIO_FN_VI1_DATA6, GPIO_FN_ATARD0_N,
+ GPIO_FN_ETH_TX_EN_B, GPIO_FN_SSI_SDATA9, GPIO_FN_SCIF2_TXD_B,
+ GPIO_FN_I2C3_SDA_E, GPIO_FN_VI1_DATA7, GPIO_FN_ATADIR0_N,
+ GPIO_FN_ETH_MAGIC_B, GPIO_FN_AUDIO_CLKA, GPIO_FN_I2C0_SCL_B,
+ GPIO_FN_SCIFA4_RXD_D, GPIO_FN_VI1_CLKENB, GPIO_FN_TS_SDATA_C,
+ GPIO_FN_RIF0_SYNC_B, GPIO_FN_ETH_TXD0_B, GPIO_FN_AUDIO_CLKB,
+ GPIO_FN_I2C0_SDA_B, GPIO_FN_SCIFA4_TXD_D, GPIO_FN_VI1_FIELD,
+ GPIO_FN_TS_SCK_C, GPIO_FN_RIF0_CLK_B, GPIO_FN_BPFCLK_E,
+ GPIO_FN_ETH_MDC_B, GPIO_FN_AUDIO_CLKC, GPIO_FN_I2C4_SCL_B,
+ GPIO_FN_SCIFA5_RXD_D, GPIO_FN_VI1_HSYNC_N, GPIO_FN_TS_SDEN_C,
+ GPIO_FN_RIF0_D0_B, GPIO_FN_FMCLK_E, GPIO_FN_RDS_CLK_D,
+ GPIO_FN_AUDIO_CLKOUT, GPIO_FN_I2C4_SDA_B, GPIO_FN_SCIFA5_TXD_D,
+ GPIO_FN_VI1_VSYNC_N, GPIO_FN_TS_SPSYNC_C, GPIO_FN_RIF0_D1_B,
+ GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D,
};
#endif /* __ASM_R8A7794_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_ARM_MPCORE_H
-#define ARCH_ARM_MPCORE_H
-
-/* Snoop Control Unit */
-#define SCU_OFFSET 0x00
-
-/* SCU Control Register */
-#define SCU_CTRL 0x00
-/* SCU Configuration Register */
-#define SCU_CONF 0x04
-/* SCU CPU Power Status Register */
-#define SCU_PWR_STATUS 0x08
-/* SCU Invalidate All Registers in Secure State */
-#define SCU_INV_ALL 0x0C
-/* SCU Filtering Start Address Register */
-#define SCU_FILTER_START 0x40
-/* SCU Filtering End Address Register */
-#define SCU_FILTER_END 0x44
-/* SCU Access Control Register */
-#define SCU_SAC 0x50
-/* SCU Non-secure Access Control Register */
-#define SCU_SNSAC 0x54
-
-/* Global Timer */
-#define GLOBAL_TIMER_OFFSET 0x200
-
-/* Global Timer Counter Registers */
-#define GTIMER_CNT_L 0x00
-#define GTIMER_CNT_H 0x04
-/* Global Timer Control Register */
-#define GTIMER_CTRL 0x08
-/* Global Timer Interrupt Status Register */
-#define GTIMER_STAT 0x0C
-/* Comparator Value Registers */
-#define GTIMER_CMP_L 0x10
-#define GTIMER_CMP_H 0x14
-/* Auto-increment Register */
-#define GTIMER_INC 0x18
-
-#endif /* ARCH_ARM_MPCORE_H */
+++ /dev/null
-/*
- * UniPhier BCU (Bus Control Unit) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_BCU_REGS_H
-#define ARCH_BCU_REGS_H
-
-#define BCU_BASE 0x50080000
-
-#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4)
-#define BCSCR0 (BCSCR(0))
-#define BCSCR1 (BCSCR(1))
-#define BCSCR2 (BCSCR(2))
-#define BCSCR3 (BCSCR(3))
-#define BCSCR4 (BCSCR(4))
-#define BCSCR5 (BCSCR(5))
-
-#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4)
-#define BCIPPCCHR0 (BCIPPCCHR(0))
-#define BCIPPCCHR1 (BCIPPCCHR(1))
-#define BCIPPCCHR2 (BCIPPCCHR(2))
-#define BCIPPCCHR3 (BCIPPCCHR(3))
-#define BCIPPCCHR4 (BCIPPCCHR(4))
-#define BCIPPCCHR5 (BCIPPCCHR(5))
-
-#endif /* ARCH_BCU_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_BOARD_H
-#define ARCH_BOARD_H
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
- defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-void support_card_reset(void);
-void support_card_init(void);
-void support_card_late_init(void);
-int check_support_card(void);
-#else
-#define support_card_reset() do {} while (0)
-#define support_card_init() do {} while (0)
-#define support_card_late_init() do {} while (0)
-static inline int check_support_card(void)
-{
- return 0;
-}
-#endif
-
-static inline void uniphier_board_reset(void)
-{
- support_card_reset();
-}
-
-static inline void uniphier_board_init(void)
-{
- support_card_init();
-}
-
-static inline void uniphier_board_late_init(void)
-{
- support_card_late_init();
-}
-
-#endif /* ARCH_BOARD_H */
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_BOOT_DEVICE_H_
-#define _ASM_BOOT_DEVICE_H_
-
-int get_boot_mode_sel(void);
-
-struct boot_device_info {
- u32 type;
- char *info;
-};
-
-extern struct boot_device_info boot_device_table[];
-
-#endif /* _ASM_BOOT_DEVICE_H_ */
+++ /dev/null
-/*
- * UniPhier DDR PHY registers
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_DDRPHY_REGS_H
-#define ARCH_DDRPHY_REGS_H
-
-#include <linux/compiler.h>
-
-#ifndef __ASSEMBLY__
-
-struct ddrphy {
- u32 ridr; /* Revision Identification Register */
- u32 pir; /* PHY Initialixation Register */
- u32 pgcr[2]; /* PHY General Configuration Register */
- u32 pgsr[2]; /* PHY General Status Register */
- u32 pllcr; /* PLL Control Register */
- u32 ptr[5]; /* PHY Timing Register */
- u32 acmdlr; /* AC Master Delay Line Register */
- u32 acbdlr; /* AC Bit Delay Line Register */
- u32 aciocr; /* AC I/O Configuration Register */
- u32 dxccr; /* DATX8 Common Configuration Register */
- u32 dsgcr; /* DDR System General Configuration Register */
- u32 dcr; /* DRAM Configuration Register */
- u32 dtpr[3]; /* DRAM Timing Parameters Register */
- u32 mr0; /* Mode Register 0 */
- u32 mr1; /* Mode Register 1 */
- u32 mr2; /* Mode Register 2 */
- u32 mr3; /* Mode Register 3 */
- u32 odtcr; /* ODT Configuration Register */
- u32 dtcr; /* Data Training Configuration Register */
- u32 dtar[4]; /* Data Training Address Register */
- u32 dtdr[2]; /* Data Training Data Register */
- u32 dtedr[2]; /* Data Training Eye Data Register */
- u32 rsv0[13]; /* Reserved */
- u32 dcuar; /* DCU Address Register */
- u32 dcudr; /* DCU Data Register */
- u32 dcurr; /* DCU Run Register */
- u32 dculr; /* DCU Loop Register */
- u32 dcugcr; /* DCU General Configuration Register */
- u32 dcutpr; /* DCU Timing Parameters Register */
- u32 dcusr[2]; /* DCU Status Register */
- u32 rsv1[8]; /* Reserved */
- u32 bistrr; /* BIST Run Register */
- u32 bistwcr; /* BIST Word Count Register */
- u32 bistmskr[3]; /* BIST Mask Register */
- u32 bistlsr; /* BIST LFSR Sed Register */
- u32 bistar[3]; /* BIST Address Register */
- u32 bistudpr; /* BIST User Data Pattern Register */
- u32 bistgsr; /* BIST General Status Register */
- u32 bistwer; /* BIST Word Error Register */
- u32 bistber[4]; /* BIST Bit Error Register */
- u32 bistwcsr; /* BIST Word Count Status Register */
- u32 bistfwr[3]; /* BIST Fail Word Register */
- u32 rsv2[10]; /* Reserved */
- u32 gpr[2]; /* General Purpose Register */
- struct ddrphy_zq { /* ZQ */
- u32 cr[2]; /* Impedance Control Register */
- u32 sr[2]; /* Impedance Status Register */
- } zq[4];
- struct ddrphy_datx8 { /* DATX8 */
- u32 gcr; /* General Configuration Register */
- u32 gsr[2]; /* General Status Register */
- u32 bdlr[5]; /* Bit Delay Line Register */
- u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
- u32 mdlr; /* Master Delay Line Register */
- u32 gtr; /* General Timing Register */
- u32 rsv[3]; /* Reserved */
- } dx[9];
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define PIR_INIT (1 << 0) /* Initialization Trigger */
-#define PIR_ZCAL (1 << 1) /* Impedance Calibration */
-#define PIR_PLLINIT (1 << 4) /* PLL Initialization */
-#define PIR_DCAL (1 << 5) /* DDL Calibration */
-#define PIR_PHYRST (1 << 6) /* PHY Reset */
-#define PIR_DRAMRST (1 << 7) /* DRAM Reset */
-#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */
-#define PIR_WL (1 << 9) /* Write Leveling */
-#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */
-#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */
-#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */
-#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */
-#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */
-#define PIR_WREYE (1 << 15) /* Write Data Eye Training */
-#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */
-#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */
-#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */
-#define PIR_INITBYP (1 << 31) /* Initialization Bypass */
-
-#define PGSR0_IDONE (1 << 0) /* Initialization Done */
-#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */
-#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */
-#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */
-#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */
-#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */
-#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */
-#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */
-#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */
-#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */
-#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */
-#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */
-#define PGSR0_IERR (1 << 16) /* Initialization Error */
-#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */
-#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */
-#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */
-#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */
-#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */
-#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */
-#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */
-#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */
-#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */
-#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */
-#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */
-#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
-#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
-#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */
-
-#define DXCCR_DQSRES_OPEN (0 << 5)
-#define DXCCR_DQSRES_688_OHM (1 << 5)
-#define DXCCR_DQSRES_611_OHM (2 << 5)
-#define DXCCR_DQSRES_550_OHM (3 << 5)
-#define DXCCR_DQSRES_500_OHM (4 << 5)
-#define DXCCR_DQSRES_458_OHM (5 << 5)
-#define DXCCR_DQSRES_393_OHM (6 << 5)
-#define DXCCR_DQSRES_344_OHM (7 << 5)
-
-#define DXCCR_DQSNRES_OPEN (0 << 9)
-#define DXCCR_DQSNRES_688_OHM (1 << 9)
-#define DXCCR_DQSNRES_611_OHM (2 << 9)
-#define DXCCR_DQSNRES_550_OHM (3 << 9)
-#define DXCCR_DQSNRES_500_OHM (4 << 9)
-#define DXCCR_DQSNRES_458_OHM (5 << 9)
-#define DXCCR_DQSNRES_393_OHM (6 << 9)
-#define DXCCR_DQSNRES_344_OHM (7 << 9)
-
-#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
-#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
-#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */
-#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */
-#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT))
-
-#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
-#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
-
-/* SoC-specific parameters */
-#define NR_DATX8_PER_DDRPHY 2
-
-#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
-#define NR_DDRPHY_PER_CH 1
-#else
-#define NR_DDRPHY_PER_CH 2
-#endif
-
-#define NR_DDRCH 2
-
-#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
-
-#ifndef __ASSEMBLY__
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
-int ddrphy_training(struct ddrphy __iomem *phy);
-#endif
-
-#endif /* ARCH_DDRPHY_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/serial_reg.h>
-
-#if !defined(CONFIG_DEBUG_SEMIHOSTING)
-#include CONFIG_DEBUG_LL_INCLUDE
-#endif
-
-#define BAUDRATE 115200
-#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
-#define DIVISOR DIV_ROUND(UART_CLK, 16 * BAUDRATE)
-
- .macro init_debug_uart, ra, rb, rc
- addruart \ra, \rb, \rc
- mov \rb, #UART_LCR_WLEN8
- strb \rb, [\ra, #0x11]
- ldr \rb, =DIVISOR
- str \rb, [\ra, #0x24]
- .endm
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PLAT_UNIPHIER_EHCI_H
-#define __PLAT_UNIPHIER_EHCI_H
-
-#include <linux/types.h>
-#include <asm/io.h>
-#include "mio-regs.h"
-
-struct uniphier_ehci_platform_data {
- unsigned long base;
-};
-
-extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[];
-
-static inline void uniphier_ehci_reset(int index, int on)
-{
- u32 tmp;
-
- tmp = readl(MIO_USB_RSTCTRL(index));
- if (on)
- tmp &= ~MIO_USB_RSTCTRL_XRST;
- else
- tmp |= MIO_USB_RSTCTRL_XRST;
- writel(tmp, MIO_USB_RSTCTRL(index));
-}
-
-#endif /* __PLAT_UNIPHIER_EHCI_H */
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_LED_H
-#define ARCH_LED_H
-
-#include <config.h>
-
-#define LED_CHAR_0 0x7e
-#define LED_CHAR_1 0x0c
-#define LED_CHAR_2 0xb6
-#define LED_CHAR_3 0x9e
-#define LED_CHAR_4 0xcc
-#define LED_CHAR_5 0xda
-#define LED_CHAR_6 0xfa
-#define LED_CHAR_7 0x4e
-#define LED_CHAR_8 0xfe
-#define LED_CHAR_9 0xde
-
-#define LED_CHAR_A 0xee
-#define LED_CHAR_B 0xf8
-#define LED_CHAR_C 0x72
-#define LED_CHAR_D 0xbc
-#define LED_CHAR_E 0xf2
-#define LED_CHAR_F 0xe2
-#define LED_CHAR_G 0x7a
-#define LED_CHAR_H 0xe8
-#define LED_CHAR_I 0x08
-#define LED_CHAR_J 0x3c
-#define LED_CHAR_K 0xea
-#define LED_CHAR_L 0x70
-#define LED_CHAR_M 0x6e
-#define LED_CHAR_N 0xa8
-#define LED_CHAR_O 0xb8
-#define LED_CHAR_P 0xe6
-#define LED_CHAR_Q 0xce
-#define LED_CHAR_R 0xa0
-#define LED_CHAR_S 0xc8
-#define LED_CHAR_T 0x8c
-#define LED_CHAR_U 0x7c
-#define LED_CHAR_V 0x54
-#define LED_CHAR_W 0xfc
-#define LED_CHAR_X 0xec
-#define LED_CHAR_Y 0xdc
-#define LED_CHAR_Z 0xa4
-
-#define LED_CHAR_SPACE 0x00
-#define LED_CHAR_DOT 0x01
-
-#define LED_CHAR_ (LED_CHAR_SPACE)
-
-/** Macro to translate 4 characters into integer to display led */
-#define LED_C2I(C0, C1, C2, C3) \
- (~( \
- (LED_CHAR_##C0 << 24) | \
- (LED_CHAR_##C1 << 16) | \
- (LED_CHAR_##C2 << 8) | \
- (LED_CHAR_##C3) \
- ))
-
-#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
-
-#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE
-
-#ifdef __ASSEMBLY__
-
-#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3)
-.macro raw_led_write data
- ldr r0, =\data
- ldr r1, =LED_ADDR
- str r0, [r1]
-.endm
-
-#else /* __ASSEMBLY__ */
-
-#include <asm/io.h>
-
-#define led_write(C0, C1, C2, C3) \
-do { \
- raw_led_write(LED_C2I(C0, C1, C2, C3)); \
-} while (0)
-
-static inline void raw_led_write(u32 data)
-{
- writel(data, LED_ADDR);
-}
-
-#endif /* __ASSEMBLY__ */
-
-#else /* CONFIG_SUPPORT_CARD_LED_BASE */
-
-#define led_write(C0, C1, C2, C3)
-#define raw_led_write(x)
-
-#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
-
-#endif /* ARCH_LED_H */
+++ /dev/null
-/*
- * UniPhier MIO (Media I/O) registers
- *
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_MIO_REGS_H
-#define ARCH_MIO_REGS_H
-
-#define MIO_BASE 0x59810000
-
-#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020)
-#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110)
-#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114)
-
-#define MIO_USB_RSTCTRL_XRST (0x1 << 0)
-
-#endif /* ARCH_MIO_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_PLATDEVICE_H
-#define ARCH_PLATDEVICE_H
-
-#include <dm/platdata.h>
-#include <dm/platform_data/serial-uniphier.h>
-
-#define SERIAL_DEVICE(n, ba, clk) \
-static struct uniphier_serial_platform_data serial_device##n = { \
- .base = ba, \
- .uartclk = clk \
-}; \
-U_BOOT_DEVICE(serial##n) = { \
- .name = DRIVER_NAME, \
- .platdata = &serial_device##n \
-};
-
-#include <asm/arch/ehci-uniphier.h>
-
-#endif /* ARCH_PLATDEVICE_H */
+++ /dev/null
-/*
- * UniPhier SBC (System Bus Controller) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SBC_REGS_H
-#define ARCH_SBC_REGS_H
-
-#define SBBASE_BASE 0x58c00100
-#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
-
-#define SBBASE0 (SBBASE(0))
-#define SBBASE1 (SBBASE(1))
-#define SBBASE2 (SBBASE(2))
-#define SBBASE3 (SBBASE(3))
-#define SBBASE4 (SBBASE(4))
-#define SBBASE5 (SBBASE(5))
-#define SBBASE6 (SBBASE(6))
-#define SBBASE7 (SBBASE(7))
-
-#define SBBASE_BANK_ENABLE (0x00000001)
-
-#define SBCTRL_BASE 0x58c00200
-#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
-
-#define SBCTRL00 SBCTRL(0, 0)
-#define SBCTRL01 SBCTRL(0, 1)
-#define SBCTRL02 SBCTRL(0, 2)
-#define SBCTRL03 SBCTRL(0, 3)
-#define SBCTRL04 (SBCTRL_BASE + 0x100)
-
-#define SBCTRL10 SBCTRL(1, 0)
-#define SBCTRL11 SBCTRL(1, 1)
-#define SBCTRL12 SBCTRL(1, 2)
-#define SBCTRL13 SBCTRL(1, 3)
-#define SBCTRL14 (SBCTRL_BASE + 0x110)
-
-#define SBCTRL20 SBCTRL(2, 0)
-#define SBCTRL21 SBCTRL(2, 1)
-#define SBCTRL22 SBCTRL(2, 2)
-#define SBCTRL23 SBCTRL(2, 3)
-#define SBCTRL24 (SBCTRL_BASE + 0x120)
-
-#define SBCTRL30 SBCTRL(3, 0)
-#define SBCTRL31 SBCTRL(3, 1)
-#define SBCTRL32 SBCTRL(3, 2)
-#define SBCTRL33 SBCTRL(3, 3)
-#define SBCTRL34 (SBCTRL_BASE + 0x130)
-
-#define SBCTRL40 SBCTRL(4, 0)
-#define SBCTRL41 SBCTRL(4, 1)
-#define SBCTRL42 SBCTRL(4, 2)
-#define SBCTRL43 SBCTRL(4, 3)
-#define SBCTRL44 (SBCTRL_BASE + 0x140)
-
-#define SBCTRL50 SBCTRL(5, 0)
-#define SBCTRL51 SBCTRL(5, 1)
-#define SBCTRL52 SBCTRL(5, 2)
-#define SBCTRL53 SBCTRL(5, 3)
-#define SBCTRL54 (SBCTRL_BASE + 0x150)
-
-#define SBCTRL60 SBCTRL(6, 0)
-#define SBCTRL61 SBCTRL(6, 1)
-#define SBCTRL62 SBCTRL(6, 2)
-#define SBCTRL63 SBCTRL(6, 3)
-#define SBCTRL64 (SBCTRL_BASE + 0x160)
-
-#define SBCTRL70 SBCTRL(7, 0)
-#define SBCTRL71 SBCTRL(7, 1)
-#define SBCTRL72 SBCTRL(7, 2)
-#define SBCTRL73 SBCTRL(7, 3)
-#define SBCTRL74 (SBCTRL_BASE + 0x170)
-
-/* slower but LED works */
-#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
-#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
-
-/* faster but LED does not work */
-#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
-/* NOR flash needs more wait counts than SRAM */
-#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
-
-#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
-
-#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
-
-#define PC0CTRL 0x598000c0
-#define ROM_BOOT_ROMRSV2 0x59801208
-
-#ifndef __ASSEMBLY__
-#include <asm/io.h>
-static inline int boot_is_swapped(void)
-{
- return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
-}
-#endif
-
-#endif /* ARCH_SBC_REGS_H */
+++ /dev/null
-/*
- * UniPhier SC (System Control) block registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SC_REGS_H
-#define ARCH_SC_REGS_H
-
-#define SC_BASE_ADDR 0x61840000
-
-#define SC_MPLLOSCCTL (SC_BASE_ADDR | 0x1184)
-#define SC_MPLLOSCCTL_MPLLEN (0x1 << 0)
-#define SC_MPLLOSCCTL_MPLLST (0x1 << 1)
-
-#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
-#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
-#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
-#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
-
-#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
-#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
-
-#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
-#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
-#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
-
-#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
-
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
-#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
-#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
-
-#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
-#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
-#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
-
-#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
-#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
-#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
-#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
-#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
-
-#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
-#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
-
-#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
-#define SC_CLKCTRL_CLK_ETHER (0x1 << 12)
-#define SC_CLKCTRL_CLK_MIO (0x1 << 11)
-#define SC_CLKCTRL_CLK_UMC (0x1 << 4)
-#define SC_CLKCTRL_CLK_NAND (0x1 << 2)
-#define SC_CLKCTRL_CLK_SBC (0x1 << 1)
-#define SC_CLKCTRL_CLK_PERI (0x1 << 0)
-
-/* System reset control register */
-#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
-#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
-#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
-
-#endif /* ARCH_SC_REGS_H */
+++ /dev/null
-/*
- * UniPhier SG (SoC Glue) block registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SG_REGS_H
-#define ARCH_SG_REGS_H
-
-/* Base Address */
-#define SG_CTRL_BASE 0x5f800000
-#define SG_DBG_BASE 0x5f900000
-
-/* Revision */
-#define SG_REVISION (SG_CTRL_BASE | 0x0000)
-#define SG_REVISION_TYPE_SHIFT 16
-#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
-#define SG_REVISION_MODEL_SHIFT 8
-#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
-#define SG_REVISION_REV_SHIFT 0
-#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
-
-/* Memory Configuration */
-#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
-
-#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
-#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
-#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
-#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
-#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
-#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
-#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
-
-#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
-#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
-#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
-#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
-#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
-#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
-#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
-
-#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
-#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
-#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
-#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
-#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
-#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
-
-#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
-
-/* Pin Control */
-#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
-
-#if defined(CONFIG_MACH_PH1_PRO4)
-# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
-#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
-# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
-#endif
-
-#if defined(CONFIG_MACH_PH1_PRO4)
-#define SG_PINSELBITS 4
-#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
-#define SG_PINSELBITS 8
-#endif
-
-#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
-#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \
- ((n) * (SG_PINSELBITS) % 32)))
-#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32))
-
-/* Only for PH1-Pro4 */
-#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
-
-/* Input Enable */
-#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
-
-/* Pin Monitor */
-#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
-
-#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
-#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
-#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
-#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
-
-#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
-
-#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
-
-#ifdef __ASSEMBLY__
-
- .macro set_pinsel, n, value, ra, rd
- ldr \ra, =SG_PINSEL_ADDR(\n)
- ldr \rd, [\ra]
- and \rd, \rd, #SG_PINSEL_MASK(\n)
- orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
- str \rd, [\ra]
- .endm
-
-#else
-
-#include <linux/types.h>
-#include <linux/sizes.h>
-#include <asm/io.h>
-
-static inline void sg_set_pinsel(int n, int value)
-{
- writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
- | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
-}
-
-static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
-{
- int size_mb = size / num;
- u32 ret;
-
- switch (size_mb) {
- case SZ_64M:
- ret = SG_MEMCONF_CH0_SZ_64M;
- break;
- case SZ_128M:
- ret = SG_MEMCONF_CH0_SZ_128M;
- break;
- case SZ_256M:
- ret = SG_MEMCONF_CH0_SZ_256M;
- break;
- case SZ_512M:
- ret = SG_MEMCONF_CH0_SZ_512M;
- break;
- case SZ_1G:
- ret = SG_MEMCONF_CH0_SZ_1G;
- break;
- default:
- BUG();
- break;
- }
-
- switch (num) {
- case 1:
- ret |= SG_MEMCONF_CH0_NUM_1;
- break;
- case 2:
- ret |= SG_MEMCONF_CH0_NUM_2;
- break;
- default:
- BUG();
- break;
- }
- return ret;
-}
-
-static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
-{
- int size_mb = size / num;
- u32 ret;
-
- switch (size_mb) {
- case SZ_64M:
- ret = SG_MEMCONF_CH1_SZ_64M;
- break;
- case SZ_128M:
- ret = SG_MEMCONF_CH1_SZ_128M;
- break;
- case SZ_256M:
- ret = SG_MEMCONF_CH1_SZ_256M;
- break;
- case SZ_512M:
- ret = SG_MEMCONF_CH1_SZ_512M;
- break;
- case SZ_1G:
- ret = SG_MEMCONF_CH1_SZ_1G;
- break;
- default:
- BUG();
- break;
- }
-
- switch (num) {
- case 1:
- ret |= SG_MEMCONF_CH1_NUM_1;
- break;
- case 2:
- ret |= SG_MEMCONF_CH1_NUM_2;
- break;
- default:
- BUG();
- break;
- }
- return ret;
-}
-
-static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
-{
- int size_mb = size / num;
- u32 ret;
-
- switch (size_mb) {
- case SZ_64M:
- ret = SG_MEMCONF_CH2_SZ_64M;
- break;
- case SZ_128M:
- ret = SG_MEMCONF_CH2_SZ_128M;
- break;
- case SZ_256M:
- ret = SG_MEMCONF_CH2_SZ_256M;
- break;
- case SZ_512M:
- ret = SG_MEMCONF_CH2_SZ_512M;
- break;
- default:
- BUG();
- break;
- }
-
- switch (num) {
- case 1:
- ret |= SG_MEMCONF_CH2_NUM_1;
- break;
- case 2:
- ret |= SG_MEMCONF_CH2_NUM_2;
- break;
- default:
- BUG();
- break;
- }
- return ret;
-}
-#endif /* __ASSEMBLY__ */
-
-#endif /* ARCH_SG_REGS_H */
+++ /dev/null
-/*
- * UniPhier System Cache (L2 Cache) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SSC_REGS_H
-#define ARCH_SSC_REGS_H
-
-#define SSCC 0x500c0000
-#define SSCC_BST (0x1 << 20)
-#define SSCC_ACT (0x1 << 19)
-#define SSCC_WTG (0x1 << 18)
-#define SSCC_PRD (0x1 << 17)
-#define SSCC_WBWA (0x1 << 16)
-#define SSCC_EX (0x1 << 13)
-#define SSCC_ON (0x1 << 0)
-
-#define SSCLPDAWCR 0x500c0030
-
-#define SSCOPE 0x506c0244
-#define SSCOPE_CM_SYNC 0x00000008
-
-#define SSCOQM 0x506c0248
-#define SSCOQM_TID_MASK (0x3 << 21)
-#define SSCOQM_TID_BY_WAY (0x2 << 21)
-#define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
-#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
-#define SSCOQM_S_MASK (0x3 << 17)
-#define SSCOQM_S_WAY (0x2 << 17)
-#define SSCOQM_S_ALL (0x1 << 17)
-#define SSCOQM_S_ADDRESS (0x0 << 17)
-#define SSCOQM_CE (0x1 << 15)
-#define SSCOQM_CW (0x1 << 14)
-#define SSCOQM_CM_MASK (0x7)
-#define SSCOQM_CM_DIRT_TOUCH (0x7)
-#define SSCOQM_CM_ZERO_TOUCH (0x6)
-#define SSCOQM_CM_NORM_TOUCH (0x5)
-#define SSCOQM_CM_PREF_FETCH (0x4)
-#define SSCOQM_CM_SSC_FETCH (0x3)
-#define SSCOQM_CM_WB_INV (0x2)
-#define SSCOQM_CM_WB (0x1)
-#define SSCOQM_CM_INV (0x0)
-
-#define SSCOQAD 0x506c024c
-#define SSCOQSZ 0x506c0250
-#define SSCOQWN 0x506c0258
-
-#define SSCOPPQSEF 0x506c025c
-#define SSCOPPQSEF_FE (0x1 << 1)
-#define SSCOPPQSEF_OE (0x1 << 0)
-
-#define SSCOLPQS 0x506c0260
-#define SSCOLPQS_EF (0x1 << 2)
-#define SSCOLPQS_EST (0x1 << 1)
-#define SSCOLPQS_QST (0x1 << 0)
-
-#define SSCOQCE0 0x506c0270
-
-#define SSC_LINE_SIZE 128
-#define SSC_NUM_ENTRIES 256
-#define SSC_WAY_SIZE ((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES))
-#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
-
-#endif /* ARCH_SSC_REGS_H */
+++ /dev/null
-/*
- * UniPhier UMC (Universal Memory Controller) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_UMC_REGS_H
-#define ARCH_UMC_REGS_H
-
-#define UMC_BASE 0x5b800000
-
-/* SSIF registers */
-#define UMC_SSIF_BASE UMC_BASE
-
-#define UMC_CPURST 0x00000700
-#define UMC_IDSRST 0x0000070C
-#define UMC_IXMRST 0x00000714
-#define UMC_HDMRST 0x00000718
-#define UMC_MDMRST 0x0000071C
-#define UMC_HDDRST 0x00000720
-#define UMC_MDDRST 0x00000724
-#define UMC_SIORST 0x00000728
-#define UMC_GIORST 0x0000072C
-#define UMC_HD2RST 0x00000734
-#define UMC_VIORST 0x0000073C
-#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
-#define UMC_DVCRST 0x00000748 /* Pro4 */
-#define UMC_RGLRST 0x00000750
-#define UMC_VPERST 0x00000758
-#define UMC_AIORST 0x00000764
-#define UMC_DMDRST 0x00000770
-
-#define UMC_HDMCHSEL 0x00000898
-#define UMC_MDMCHSEL 0x0000089C
-#define UMC_DVCCHSEL 0x000008C8
-#define UMC_DMDCHSEL 0x000008F0
-
-#define UMC_CLKEN_SSIF_FETCH 0x0000C060
-#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
-#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
-#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
-#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
-#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
-#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
-#define UMC_CLKEN_SSIF_WC 0x0000C07C
-#define UMC_CLKEN_SSIF_RC 0x0000C080
-#define UMC_CLKEN_SSIF_DST 0x0000C084
-
-/* CA registers */
-#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
-
-/* DRAM controller registers */
-#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
-
-#define UMC_CMDCTLA 0x00000000
-#define UMC_CMDCTLB 0x00000004
-#define UMC_INITCTLA 0x00000008
-#define UMC_INITCTLB 0x0000000C
-#define UMC_INITCTLC 0x00000010
-#define UMC_INITSET 0x00000014
-#define UMC_INITSTAT 0x00000018
-#define UMC_DRMMR0 0x0000001C
-#define UMC_DRMMR1 0x00000020
-#define UMC_DRMMR2 0x00000024
-#define UMC_DRMMR3 0x00000028
-#define UMC_SPCCTLA 0x00000030
-#define UMC_SPCCTLB 0x00000034
-#define UMC_SPCSETA 0x00000038
-#define UMC_SPCSETB 0x0000003C
-#define UMC_SPCSETC 0x00000040
-#define UMC_SPCSETD 0x00000044
-#define UMC_SPCSTATA 0x00000050
-#define UMC_SPCSTATB 0x00000054
-#define UMC_SPCSTATC 0x00000058
-#define UMC_ACSSETA 0x00000060
-#define UMC_FLOWCTLA 0x00000400
-#define UMC_FLOWCTLB 0x00000404
-#define UMC_FLOWCTLC 0x00000408
-#define UMC_FLOWCTLG 0x00000508
-#define UMC_RDATACTL_D0 0x00000600
-#define UMC_WDATACTL_D0 0x00000604
-#define UMC_RDATACTL_D1 0x00000608
-#define UMC_WDATACTL_D1 0x0000060C
-#define UMC_DATASET 0x00000610
-#define UMC_DCCGCTL 0x00000720
-#define UMC_DICGCTLA 0x00000724
-#define UMC_DICGCTLB 0x00000728
-#define UMC_DIOCTLA 0x00000C00
-#define UMC_DFICUPDCTLA 0x00000C20
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-static inline void umc_polling(u32 address, u32 expval, u32 mask)
-{
- u32 nmask = ~mask;
- u32 data;
- do {
- data = readl(address) & nmask;
- } while (data != expval);
-}
-
-static inline void umc_dram_init_start(void __iomem *dramcont)
-{
- writel(0x00000002, dramcont + UMC_INITSET);
-}
-
-static inline void umc_dram_init_poll(void __iomem *dramcont)
-{
- while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
- ;
-}
-
-#endif
-
-#endif
#ifndef __ASSEMBLY__
#include <linux/types.h>
+#include <asm/io.h>
/*
* CP15 Barrier instructions
#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
+/*
+ * Workaround for ARM errata # 798870
+ * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
+ * stalled for 1024 cycles to verify that its hazard condition still exists.
+ */
+static inline void v7_enable_l2_hazard_detect(void)
+{
+ uint32_t val;
+
+ /* L2ACTLR[7]: Enable hazard detect timeout */
+ asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
+ val |= (1 << 7);
+ asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
+}
+
+/*
+ * Workaround for ARM errata # 799270
+ * Ensure that the L2 logic has been used within the previous 256 cycles
+ * before modifying the ACTLR.SMP bit. This is required during boot before
+ * MMU has been enabled, or during a specified reset or power down sequence.
+ */
+static inline void v7_enable_smp(uint32_t address)
+{
+ uint32_t temp, val;
+
+ /* Read auxiliary control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
+
+ /* Enable SMP */
+ val |= (1 << 6);
+
+ /* Dummy read to assure L2 access */
+ temp = readl(address);
+ temp &= 0;
+ val |= temp;
+
+ /* Write auxiliary control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
+
+ CP15DSB;
+ CP15ISB;
+}
+
+void v7_en_l2_hazard_detect(void);
void v7_outer_cache_enable(void);
void v7_outer_cache_disable(void);
void v7_outer_cache_flush_all(void);
--- /dev/null
+menu "Panasonic UniPhier platform"
+ depends on ARCH_UNIPHIER
+
+config SYS_SOC
+ default "uniphier"
+
+config SYS_CONFIG_NAME
+ default "uniphier"
+
+config UNIPHIER_SMP
+ bool
+
+choice
+ prompt "UniPhier SoC select"
+
+config MACH_PH1_PRO4
+ bool "PH1-Pro4"
+ select UNIPHIER_SMP
+
+config MACH_PH1_LD4
+ bool "PH1-LD4"
+
+config MACH_PH1_SLD8
+ bool "PH1-sLD8"
+
+endchoice
+
+choice
+ prompt "UniPhier Support Card select"
+ optional
+
+config PFC_MICRO_SUPPORT_CARD
+ bool "Support card with PFC CPLD"
+ help
+ This option provides support for the expansion board with PFC
+ original address mapping.
+
+ Say Y to use the on-board UART, Ether, LED devices.
+
+config DCC_MICRO_SUPPORT_CARD
+ bool "Support card with DCC CPLD"
+ help
+ This option provides support for the expansion board with DCC-
+ arranged address mapping that is compatible with legacy UniPhier
+ reference boards.
+
+ Say Y to use the on-board UART, Ether, LED devices.
+
+endchoice
+
+config SYS_MALLOC_F
+ default y
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
+config CMD_PINMON
+ bool "Enable boot mode pins monitor command"
+ default y
+ help
+ The command "pinmon" shows the state of the boot mode pins.
+ The boot mode pins are latched when the system reset is deasserted
+ and determine which device the system should load a boot image from.
+
+config CMD_DDRPHY_DUMP
+ bool "Enable dump command of DDR PHY parameters"
+ help
+ The command "ddrphy" shows the resulting parameters of DDR PHY
+ training; it is useful for the evaluation of DDR PHY training.
+
+choice
+ prompt "DDR3 Frequency select"
+
+config DDR_FREQ_1600
+ bool "DDR3 1600"
+ depends on MACH_PH1_PRO4 || MACH_PH1_LD4
+
+config DDR_FREQ_1333
+ bool "DDR3 1333"
+ depends on MACH_PH1_LD4 || MACH_PH1_SLD8
+
+endchoice
+
+config DDR_FREQ
+ int
+ default 1333 if DDR_FREQ_1333
+ default 1600 if DDR_FREQ_1600
+
+endmenu
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+
+obj-y += lowlevel_init.o
+obj-y += init_page_table.o
+obj-y += spl.o
+obj-y += memconf.o
+obj-y += ddrphy_training.o
+
+else
+
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
+obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
+obj-y += dram_init.o
+obj-y += board_common.o
+obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
+obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
+obj-y += reset.o
+obj-y += cache_uniphier.o
+obj-$(CONFIG_UNIPHIER_SMP) += smp.o
+obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
+obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
+
+endif
+
+obj-y += timer.o
+
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
+
+obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
+obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
+obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mach/led.h>
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ led_write(U, B, O, O);
+
+ return 0;
+}
+
+#if CONFIG_NR_DRAM_BANKS >= 2
+void dram_init_banksize(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
+ gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
+ gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/led.h>
+#include <mach/board.h>
+
+void pin_init(void);
+void clkrst_init(void);
+
+int board_early_init_f(void)
+{
+ led_write(U, 0, , );
+
+ pin_init();
+
+ led_write(U, 1, , );
+
+ clkrst_init();
+
+ led_write(U, 2, , );
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mach/board.h>
+
+int board_early_init_r(void)
+{
+ uniphier_board_late_init();
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <../drivers/mtd/nand/denali.h>
+
+static void nand_denali_wp_disable(void)
+{
+#ifdef CONFIG_NAND_DENALI
+ /*
+ * Since the boot rom enables the write protection for NAND boot mode,
+ * it must be disabled somewhere for "nand write", "nand erase", etc.
+ * The workaround is here to not disturb the Denali NAND controller
+ * driver just for a really SoC-specific thing.
+ */
+ void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+
+ writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
+#endif
+}
+
+int board_late_init(void)
+{
+ puts("MODE: ");
+
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC1:
+ printf("eMMC Boot\n");
+ setenv("bootmode", "emmcboot");
+ break;
+ case BOOT_DEVICE_NAND:
+ printf("NAND Boot\n");
+ setenv("bootmode", "nandboot");
+ nand_denali_wp_disable();
+ break;
+ case BOOT_DEVICE_NOR:
+ printf("NOR Boot\n");
+ setenv("bootmode", "norboot");
+ break;
+ default:
+ printf("Unsupported Boot Mode\n");
+ return -1;
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7.h>
+#include <mach/ssc-regs.h>
+
+#ifdef CONFIG_UNIPHIER_L2CACHE_ON
+static void uniphier_cache_maint_all(u32 operation)
+{
+ /* try until the command is successfully set */
+ do {
+ writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
+ } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
+
+ /* wait until the operation is completed */
+ while (readl(SSCOLPQS) != SSCOLPQS_EF)
+ ;
+
+ /* clear the complete notification flag */
+ writel(SSCOLPQS_EF, SSCOLPQS);
+
+ writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
+ readl(SSCOPE); /* need a read back to confirm */
+}
+
+void v7_outer_cache_flush_all(void)
+{
+ uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
+}
+
+void v7_outer_cache_inval_all(void)
+{
+ uniphier_cache_maint_all(SSCOQM_CM_INV);
+}
+
+static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
+{
+ /* try until the command is successfully set */
+ do {
+ writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
+ writel(start, SSCOQAD);
+ writel(size, SSCOQSZ);
+
+ } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
+
+ /* wait until the operation is completed */
+ while (readl(SSCOLPQS) != SSCOLPQS_EF)
+ ;
+
+ /* clear the complete notification flag */
+ writel(SSCOLPQS_EF, SSCOLPQS);
+}
+
+static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
+{
+ u32 size;
+
+ /*
+ * If start address is not aligned to cache-line,
+ * do cache operation for the first cache-line
+ */
+ start = start & ~(SSC_LINE_SIZE - 1);
+
+ if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
+ /* this means cache operation for all range */
+ uniphier_cache_maint_all(operation);
+ return;
+ }
+
+ /*
+ * If end address is not aligned to cache-line,
+ * do cache operation for the last cache-line
+ */
+ size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
+
+ while (size) {
+ u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
+ SSC_RANGE_OP_MAX_SIZE : size;
+ __uniphier_cache_maint_range(start, chunk_size, operation);
+
+ start += chunk_size;
+ size -= chunk_size;
+ }
+
+ writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
+ readl(SSCOPE); /* need a read back to confirm */
+}
+
+void v7_outer_cache_flush_range(u32 start, u32 end)
+{
+ uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
+}
+
+void v7_outer_cache_inval_range(u32 start, u32 end)
+{
+ uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
+}
+
+void v7_outer_cache_enable(void)
+{
+ u32 tmp;
+ tmp = readl(SSCC);
+ tmp |= SSCC_ON;
+ writel(tmp, SSCC);
+}
+#endif
+
+void v7_outer_cache_disable(void)
+{
+ u32 tmp;
+ tmp = readl(SSCC);
+ tmp &= ~SSCC_ON;
+ writel(tmp, SSCC);
+}
+
+void wakeup_secondary(void);
+
+void enable_caches(void)
+{
+ uint32_t reg;
+
+#ifdef CONFIG_UNIPHIER_SMP
+ /*
+ * The secondary CPU must move to DDR,
+ * before L2 disable.
+ * On SPL, the Page Table is located on the L2.
+ */
+ wakeup_secondary();
+#endif
+ /*
+ * UniPhier SoCs must use L2 cache for init stack pointer.
+ * We disable L2 and L1 in this order.
+ * If CONFIG_SYS_DCACHE_OFF is not defined,
+ * caches are enabled again with a new page table.
+ */
+
+ /* L2 disable */
+ v7_outer_cache_disable();
+
+ /* L1 disable */
+ reg = get_cr();
+ reg &= ~(CR_C | CR_M);
+ set_cr(reg);
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/ddrphy-regs.h>
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS " "
+
+static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
+{
+ return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
+}
+
+static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
+{
+ int ch, p, dx;
+ struct ddrphy __iomem *phy;
+
+ for (ch = 0; ch < NR_DDRCH; ch++) {
+ for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
+ phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ printf("CH%dP%dDX%d:", ch, p, dx);
+ (*callback)(&phy->dx[dx]);
+ printf("\n");
+ }
+ }
+ }
+}
+
+static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int i;
+
+ for (i = 0; i < 10; i++)
+ printf(FS PRINTF_FORMAT, read_bdl(dx, i));
+
+ printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
+}
+
+void wbdl_dump(void)
+{
+ printf("\n--- Write Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
+
+ dump_loop(&__wbdl_dump);
+}
+
+static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int i;
+
+ for (i = 15; i < 24; i++)
+ printf(FS PRINTF_FORMAT, read_bdl(dx, i));
+
+ printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
+}
+
+void rbdl_dump(void)
+{
+ printf("\n--- Read Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
+
+ dump_loop(&__rbdl_dump);
+}
+
+static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int rank;
+ u32 lcdlr0 = readl(&dx->lcdlr[0]);
+ u32 gtr = readl(&dx->gtr);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+ u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "%sT", wld,
+ wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+ }
+}
+
+void wld_dump(void)
+{
+ printf("\n--- Write Leveling Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__wld_dump);
+}
+
+static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int rank;
+ u32 lcdlr2 = readl(&dx->lcdlr[2]);
+ u32 gtr = readl(&dx->gtr);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+ u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+ }
+}
+
+void dqsgd_dump(void)
+{
+ printf("\n--- DQS Gating Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__dqsgd_dump);
+}
+
+static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int i;
+ u32 mdl = readl(&dx->mdlr);
+ for (i = 0; i < 3; i++)
+ printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+void mdl_dump(void)
+{
+ printf("\n--- Master Delay Line ---\n");
+ printf(" IPRD TPRD MDLD\n");
+
+ dump_loop(&__mdl_dump);
+}
+
+#define REG_DUMP(x) \
+ { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
+ p - (u32 *)phy, #x, p, readl(p)); }
+
+void reg_dump(void)
+{
+ int ch, p;
+ struct ddrphy __iomem *phy;
+
+ printf("\n--- DDR PHY registers ---\n");
+
+ for (ch = 0; ch < NR_DDRCH; ch++) {
+ for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
+ printf("== Ch%d, PHY%d ==\n", ch, p);
+ printf(" No: Name : Address : Data\n");
+
+ phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+
+ REG_DUMP(ridr);
+ REG_DUMP(pir);
+ REG_DUMP(pgcr[0]);
+ REG_DUMP(pgcr[1]);
+ REG_DUMP(pgsr[0]);
+ REG_DUMP(pgsr[1]);
+ REG_DUMP(pllcr);
+ REG_DUMP(ptr[0]);
+ REG_DUMP(ptr[1]);
+ REG_DUMP(ptr[2]);
+ REG_DUMP(ptr[3]);
+ REG_DUMP(ptr[4]);
+ REG_DUMP(acmdlr);
+ REG_DUMP(acbdlr);
+ REG_DUMP(dxccr);
+ REG_DUMP(dsgcr);
+ REG_DUMP(dcr);
+ REG_DUMP(dtpr[0]);
+ REG_DUMP(dtpr[1]);
+ REG_DUMP(dtpr[2]);
+ REG_DUMP(mr0);
+ REG_DUMP(mr1);
+ REG_DUMP(mr2);
+ REG_DUMP(mr3);
+ REG_DUMP(dx[0].gcr);
+ REG_DUMP(dx[0].gtr);
+ REG_DUMP(dx[1].gcr);
+ REG_DUMP(dx[1].gtr);
+ }
+ }
+}
+
+static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *cmd = argv[1];
+
+ if (argc == 1)
+ cmd = "all";
+
+ if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+ wbdl_dump();
+
+ if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+ rbdl_dump();
+
+ if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+ wld_dump();
+
+ if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+ dqsgd_dump();
+
+ if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+ mdl_dump();
+
+ if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+ reg_dump();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ddr, 2, 1, do_ddr,
+ "UniPhier DDR PHY parameters dumper",
+ "- dump all of the followings\n"
+ "ddr wbdl - dump Write Bit Delay\n"
+ "ddr rbdl - dump Read Bit Delay\n"
+ "ddr wld - dump Write Leveling\n"
+ "ddr dqsgd - dump DQS Gating Delay\n"
+ "ddr mdl - dump Master Delay Line\n"
+ "ddr reg - dump registers\n"
+);
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mach/boot-device.h>
+#include <mach/sbc-regs.h>
+
+static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int mode_sel, i;
+
+ printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; boot_device_table[i].info; i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ pinmon, 1, 1, do_pinmon,
+ "pin monitor",
+ ""
+);
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sg-regs.h>
+
+int print_cpuinfo(void)
+{
+ u32 revision, type, model, rev, required_model = 1, required_rev = 1;
+
+ revision = readl(SG_REVISION);
+ type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT;
+ model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT;
+ rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT;
+
+ puts("CPU: ");
+
+ switch (type) {
+ case 0x25:
+ puts("PH1-sLD3 (MN2WS0220)");
+ required_model = 2;
+ break;
+ case 0x26:
+ puts("PH1-LD4 (MN2WS0250)");
+ required_rev = 2;
+ break;
+ case 0x28:
+ puts("PH1-Pro4 (MN2WS0230)");
+ break;
+ case 0x29:
+ puts("PH1-sLD8 (MN2WS0270)");
+ break;
+ default:
+ printf("Unknown Processor ID (0x%x)\n", revision);
+ return -1;
+ }
+
+ if (model > 1)
+ printf(" model %d", model);
+
+ printf(" (rev. %d)\n", rev);
+
+ if (model < required_model) {
+ printf("Sorry, this model is not supported.\n");
+ printf("Required model is %d.", required_model);
+ return -1;
+ } else if (rev < required_rev) {
+ printf("Sorry, this revision is not supported.\n");
+ printf("Required revision is %d.", required_rev);
+ return -1;
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/ddrphy-regs.h>
+
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
+{
+ int dx;
+ u32 __iomem tmp, *p;
+
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ p = &phy->dx[dx].gcr;
+
+ tmp = readl(p);
+ /* Specify the rank that should be write leveled */
+ tmp &= ~DXGCR_WLRKEN_MASK;
+ tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
+ writel(tmp, p);
+ }
+
+ p = &phy->dtcr;
+
+ tmp = readl(p);
+ /* Specify the rank used during data bit deskew and eye centering */
+ tmp &= ~DTCR_DTRANK_MASK;
+ tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
+ /* Use Multi-Purpose Register for DQS gate training */
+ tmp |= DTCR_DTMPR;
+ /* Specify the rank enabled for data-training */
+ tmp &= ~DTCR_RNKEN_MASK;
+ tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
+ writel(tmp, p);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static struct ddrphy_init_sequence init_sequence[] = {
+ {
+ "DRAM Initialization",
+ PIR_DRAMRST | PIR_DRAMINIT,
+ PGSR0_DIDONE,
+ PGSR0_DIERR
+ },
+ {
+ "Write Leveling",
+ PIR_WL,
+ PGSR0_WLDONE,
+ PGSR0_WLERR
+ },
+ {
+ "Read DQS Gate Training",
+ PIR_QSGATE,
+ PGSR0_QSGDONE,
+ PGSR0_QSGERR
+ },
+ {
+ "Write Leveling Adjustment",
+ PIR_WLADJ,
+ PGSR0_WLADONE,
+ PGSR0_WLAERR
+ },
+ {
+ "Read Bit Deskew",
+ PIR_RDDSKW,
+ PGSR0_RDDONE,
+ PGSR0_RDERR
+ },
+ {
+ "Write Bit Deskew",
+ PIR_WRDSKW,
+ PGSR0_WDDONE,
+ PGSR0_WDERR
+ },
+ {
+ "Read Eye Training",
+ PIR_RDEYE,
+ PGSR0_REDONE,
+ PGSR0_REERR
+ },
+ {
+ "Write Eye Training",
+ PIR_WREYE,
+ PGSR0_WEDONE,
+ PGSR0_WEERR
+ }
+};
+
+int ddrphy_training(struct ddrphy __iomem *phy)
+{
+ int i;
+ u32 pgsr0;
+ u32 init_flag = PIR_INIT;
+ u32 done_flag = PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+#ifdef DISPLAY_ELAPSED_TIME
+ ulong start = get_timer(0);
+#endif
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ init_flag |= init_sequence[i].init_flag;
+ done_flag |= init_sequence[i].done_flag;
+ }
+
+ writel(init_flag, &phy->pir);
+
+ do {
+ if (--timeout < 0) {
+#ifndef CONFIG_SPL_BUILD
+ printf("%s: error: timeout during DDR training\n",
+ __func__);
+#endif
+ return -1;
+ }
+ udelay(1);
+ pgsr0 = readl(&phy->pgsr[0]);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ if (pgsr0 & init_sequence[i].err_flag) {
+#ifndef CONFIG_SPL_BUILD
+ printf("%s: error: %s failed\n", __func__,
+ init_sequence[i].description);
+#endif
+ return -1;
+ }
+ }
+
+#ifdef DISPLAY_ELAPSED_TIME
+ printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_ARM_MPCORE_H
+#define ARCH_ARM_MPCORE_H
+
+/* Snoop Control Unit */
+#define SCU_OFFSET 0x00
+
+/* SCU Control Register */
+#define SCU_CTRL 0x00
+/* SCU Configuration Register */
+#define SCU_CONF 0x04
+/* SCU CPU Power Status Register */
+#define SCU_PWR_STATUS 0x08
+/* SCU Invalidate All Registers in Secure State */
+#define SCU_INV_ALL 0x0C
+/* SCU Filtering Start Address Register */
+#define SCU_FILTER_START 0x40
+/* SCU Filtering End Address Register */
+#define SCU_FILTER_END 0x44
+/* SCU Access Control Register */
+#define SCU_SAC 0x50
+/* SCU Non-secure Access Control Register */
+#define SCU_SNSAC 0x54
+
+/* Global Timer */
+#define GLOBAL_TIMER_OFFSET 0x200
+
+/* Global Timer Counter Registers */
+#define GTIMER_CNT_L 0x00
+#define GTIMER_CNT_H 0x04
+/* Global Timer Control Register */
+#define GTIMER_CTRL 0x08
+/* Global Timer Interrupt Status Register */
+#define GTIMER_STAT 0x0C
+/* Comparator Value Registers */
+#define GTIMER_CMP_L 0x10
+#define GTIMER_CMP_H 0x14
+/* Auto-increment Register */
+#define GTIMER_INC 0x18
+
+#endif /* ARCH_ARM_MPCORE_H */
--- /dev/null
+/*
+ * UniPhier BCU (Bus Control Unit) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_BCU_REGS_H
+#define ARCH_BCU_REGS_H
+
+#define BCU_BASE 0x50080000
+
+#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4)
+#define BCSCR0 (BCSCR(0))
+#define BCSCR1 (BCSCR(1))
+#define BCSCR2 (BCSCR(2))
+#define BCSCR3 (BCSCR(3))
+#define BCSCR4 (BCSCR(4))
+#define BCSCR5 (BCSCR(5))
+
+#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4)
+#define BCIPPCCHR0 (BCIPPCCHR(0))
+#define BCIPPCCHR1 (BCIPPCCHR(1))
+#define BCIPPCCHR2 (BCIPPCCHR(2))
+#define BCIPPCCHR3 (BCIPPCCHR(3))
+#define BCIPPCCHR4 (BCIPPCCHR(4))
+#define BCIPPCCHR5 (BCIPPCCHR(5))
+
+#endif /* ARCH_BCU_REGS_H */
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_BOARD_H
+#define ARCH_BOARD_H
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
+ defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+void support_card_reset(void);
+void support_card_init(void);
+void support_card_late_init(void);
+int check_support_card(void);
+#else
+#define support_card_reset() do {} while (0)
+#define support_card_init() do {} while (0)
+#define support_card_late_init() do {} while (0)
+static inline int check_support_card(void)
+{
+ return 0;
+}
+#endif
+
+static inline void uniphier_board_reset(void)
+{
+ support_card_reset();
+}
+
+static inline void uniphier_board_init(void)
+{
+ support_card_init();
+}
+
+static inline void uniphier_board_late_init(void)
+{
+ support_card_late_init();
+}
+
+#endif /* ARCH_BOARD_H */
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_BOOT_DEVICE_H_
+#define _ASM_BOOT_DEVICE_H_
+
+int get_boot_mode_sel(void);
+
+struct boot_device_info {
+ u32 type;
+ char *info;
+};
+
+extern struct boot_device_info boot_device_table[];
+
+#endif /* _ASM_BOOT_DEVICE_H_ */
--- /dev/null
+/*
+ * UniPhier DDR PHY registers
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_REGS_H
+#define ARCH_DDRPHY_REGS_H
+
+#include <linux/compiler.h>
+
+#ifndef __ASSEMBLY__
+
+struct ddrphy {
+ u32 ridr; /* Revision Identification Register */
+ u32 pir; /* PHY Initialixation Register */
+ u32 pgcr[2]; /* PHY General Configuration Register */
+ u32 pgsr[2]; /* PHY General Status Register */
+ u32 pllcr; /* PLL Control Register */
+ u32 ptr[5]; /* PHY Timing Register */
+ u32 acmdlr; /* AC Master Delay Line Register */
+ u32 acbdlr; /* AC Bit Delay Line Register */
+ u32 aciocr; /* AC I/O Configuration Register */
+ u32 dxccr; /* DATX8 Common Configuration Register */
+ u32 dsgcr; /* DDR System General Configuration Register */
+ u32 dcr; /* DRAM Configuration Register */
+ u32 dtpr[3]; /* DRAM Timing Parameters Register */
+ u32 mr0; /* Mode Register 0 */
+ u32 mr1; /* Mode Register 1 */
+ u32 mr2; /* Mode Register 2 */
+ u32 mr3; /* Mode Register 3 */
+ u32 odtcr; /* ODT Configuration Register */
+ u32 dtcr; /* Data Training Configuration Register */
+ u32 dtar[4]; /* Data Training Address Register */
+ u32 dtdr[2]; /* Data Training Data Register */
+ u32 dtedr[2]; /* Data Training Eye Data Register */
+ u32 rsv0[13]; /* Reserved */
+ u32 dcuar; /* DCU Address Register */
+ u32 dcudr; /* DCU Data Register */
+ u32 dcurr; /* DCU Run Register */
+ u32 dculr; /* DCU Loop Register */
+ u32 dcugcr; /* DCU General Configuration Register */
+ u32 dcutpr; /* DCU Timing Parameters Register */
+ u32 dcusr[2]; /* DCU Status Register */
+ u32 rsv1[8]; /* Reserved */
+ u32 bistrr; /* BIST Run Register */
+ u32 bistwcr; /* BIST Word Count Register */
+ u32 bistmskr[3]; /* BIST Mask Register */
+ u32 bistlsr; /* BIST LFSR Sed Register */
+ u32 bistar[3]; /* BIST Address Register */
+ u32 bistudpr; /* BIST User Data Pattern Register */
+ u32 bistgsr; /* BIST General Status Register */
+ u32 bistwer; /* BIST Word Error Register */
+ u32 bistber[4]; /* BIST Bit Error Register */
+ u32 bistwcsr; /* BIST Word Count Status Register */
+ u32 bistfwr[3]; /* BIST Fail Word Register */
+ u32 rsv2[10]; /* Reserved */
+ u32 gpr[2]; /* General Purpose Register */
+ struct ddrphy_zq { /* ZQ */
+ u32 cr[2]; /* Impedance Control Register */
+ u32 sr[2]; /* Impedance Status Register */
+ } zq[4];
+ struct ddrphy_datx8 { /* DATX8 */
+ u32 gcr; /* General Configuration Register */
+ u32 gsr[2]; /* General Status Register */
+ u32 bdlr[5]; /* Bit Delay Line Register */
+ u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
+ u32 mdlr; /* Master Delay Line Register */
+ u32 gtr; /* General Timing Register */
+ u32 rsv[3]; /* Reserved */
+ } dx[9];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define PIR_INIT (1 << 0) /* Initialization Trigger */
+#define PIR_ZCAL (1 << 1) /* Impedance Calibration */
+#define PIR_PLLINIT (1 << 4) /* PLL Initialization */
+#define PIR_DCAL (1 << 5) /* DDL Calibration */
+#define PIR_PHYRST (1 << 6) /* PHY Reset */
+#define PIR_DRAMRST (1 << 7) /* DRAM Reset */
+#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */
+#define PIR_WL (1 << 9) /* Write Leveling */
+#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */
+#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */
+#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */
+#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */
+#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */
+#define PIR_WREYE (1 << 15) /* Write Data Eye Training */
+#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */
+#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */
+#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */
+#define PIR_INITBYP (1 << 31) /* Initialization Bypass */
+
+#define PGSR0_IDONE (1 << 0) /* Initialization Done */
+#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */
+#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */
+#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */
+#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */
+#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */
+#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */
+#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */
+#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */
+#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */
+#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */
+#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */
+#define PGSR0_IERR (1 << 16) /* Initialization Error */
+#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */
+#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */
+#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */
+#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */
+#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */
+#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */
+#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */
+#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */
+#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */
+#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */
+#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */
+#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
+#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
+#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */
+
+#define DXCCR_DQSRES_OPEN (0 << 5)
+#define DXCCR_DQSRES_688_OHM (1 << 5)
+#define DXCCR_DQSRES_611_OHM (2 << 5)
+#define DXCCR_DQSRES_550_OHM (3 << 5)
+#define DXCCR_DQSRES_500_OHM (4 << 5)
+#define DXCCR_DQSRES_458_OHM (5 << 5)
+#define DXCCR_DQSRES_393_OHM (6 << 5)
+#define DXCCR_DQSRES_344_OHM (7 << 5)
+
+#define DXCCR_DQSNRES_OPEN (0 << 9)
+#define DXCCR_DQSNRES_688_OHM (1 << 9)
+#define DXCCR_DQSNRES_611_OHM (2 << 9)
+#define DXCCR_DQSNRES_550_OHM (3 << 9)
+#define DXCCR_DQSNRES_500_OHM (4 << 9)
+#define DXCCR_DQSNRES_458_OHM (5 << 9)
+#define DXCCR_DQSNRES_393_OHM (6 << 9)
+#define DXCCR_DQSNRES_344_OHM (7 << 9)
+
+#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
+#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
+#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */
+#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */
+#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT))
+
+#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
+
+/* SoC-specific parameters */
+#define NR_DATX8_PER_DDRPHY 2
+
+#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define NR_DDRPHY_PER_CH 1
+#else
+#define NR_DDRPHY_PER_CH 2
+#endif
+
+#define NR_DDRCH 2
+
+#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
+
+#ifndef __ASSEMBLY__
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
+int ddrphy_training(struct ddrphy __iomem *phy);
+#endif
+
+#endif /* ARCH_DDRPHY_REGS_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/serial_reg.h>
+
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
+
+#define BAUDRATE 115200
+#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
+#define DIVISOR DIV_ROUND(UART_CLK, 16 * BAUDRATE)
+
+ .macro init_debug_uart, ra, rb, rc
+ addruart \ra, \rb, \rc
+ mov \rb, #UART_LCR_WLEN8
+ strb \rb, [\ra, #0x11]
+ ldr \rb, =DIVISOR
+ str \rb, [\ra, #0x24]
+ .endm
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_LED_H
+#define ARCH_LED_H
+
+#include <config.h>
+
+#define LED_CHAR_0 0x7e
+#define LED_CHAR_1 0x0c
+#define LED_CHAR_2 0xb6
+#define LED_CHAR_3 0x9e
+#define LED_CHAR_4 0xcc
+#define LED_CHAR_5 0xda
+#define LED_CHAR_6 0xfa
+#define LED_CHAR_7 0x4e
+#define LED_CHAR_8 0xfe
+#define LED_CHAR_9 0xde
+
+#define LED_CHAR_A 0xee
+#define LED_CHAR_B 0xf8
+#define LED_CHAR_C 0x72
+#define LED_CHAR_D 0xbc
+#define LED_CHAR_E 0xf2
+#define LED_CHAR_F 0xe2
+#define LED_CHAR_G 0x7a
+#define LED_CHAR_H 0xe8
+#define LED_CHAR_I 0x08
+#define LED_CHAR_J 0x3c
+#define LED_CHAR_K 0xea
+#define LED_CHAR_L 0x70
+#define LED_CHAR_M 0x6e
+#define LED_CHAR_N 0xa8
+#define LED_CHAR_O 0xb8
+#define LED_CHAR_P 0xe6
+#define LED_CHAR_Q 0xce
+#define LED_CHAR_R 0xa0
+#define LED_CHAR_S 0xc8
+#define LED_CHAR_T 0x8c
+#define LED_CHAR_U 0x7c
+#define LED_CHAR_V 0x54
+#define LED_CHAR_W 0xfc
+#define LED_CHAR_X 0xec
+#define LED_CHAR_Y 0xdc
+#define LED_CHAR_Z 0xa4
+
+#define LED_CHAR_SPACE 0x00
+#define LED_CHAR_DOT 0x01
+
+#define LED_CHAR_ (LED_CHAR_SPACE)
+
+/** Macro to translate 4 characters into integer to display led */
+#define LED_C2I(C0, C1, C2, C3) \
+ (~( \
+ (LED_CHAR_##C0 << 24) | \
+ (LED_CHAR_##C1 << 16) | \
+ (LED_CHAR_##C2 << 8) | \
+ (LED_CHAR_##C3) \
+ ))
+
+#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
+
+#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE
+
+#ifdef __ASSEMBLY__
+
+#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3)
+.macro raw_led_write data
+ ldr r0, =\data
+ ldr r1, =LED_ADDR
+ str r0, [r1]
+.endm
+
+#else /* __ASSEMBLY__ */
+
+#include <asm/io.h>
+
+#define led_write(C0, C1, C2, C3) \
+do { \
+ raw_led_write(LED_C2I(C0, C1, C2, C3)); \
+} while (0)
+
+static inline void raw_led_write(u32 data)
+{
+ writel(data, LED_ADDR);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#else /* CONFIG_SUPPORT_CARD_LED_BASE */
+
+#define led_write(C0, C1, C2, C3)
+#define raw_led_write(x)
+
+#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
+
+#endif /* ARCH_LED_H */
--- /dev/null
+/*
+ * UniPhier MIO (Media I/O) registers
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_MIO_REGS_H
+#define ARCH_MIO_REGS_H
+
+#define MIO_BASE 0x59810000
+
+#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020)
+#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110)
+#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114)
+
+#define MIO_USB_RSTCTRL_XRST (0x1 << 0)
+
+#endif /* ARCH_MIO_REGS_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_PLATDEVICE_H
+#define ARCH_PLATDEVICE_H
+
+#include <dm/platdata.h>
+#include <dm/platform_data/serial-uniphier.h>
+
+#define SERIAL_DEVICE(n, ba, clk) \
+static struct uniphier_serial_platform_data serial_device##n = { \
+ .base = ba, \
+ .uartclk = clk \
+}; \
+U_BOOT_DEVICE(serial##n) = { \
+ .name = DRIVER_NAME, \
+ .platdata = &serial_device##n \
+};
+
+#endif /* ARCH_PLATDEVICE_H */
--- /dev/null
+/*
+ * UniPhier SBC (System Bus Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SBC_REGS_H
+#define ARCH_SBC_REGS_H
+
+#define SBBASE_BASE 0x58c00100
+#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
+
+#define SBBASE0 (SBBASE(0))
+#define SBBASE1 (SBBASE(1))
+#define SBBASE2 (SBBASE(2))
+#define SBBASE3 (SBBASE(3))
+#define SBBASE4 (SBBASE(4))
+#define SBBASE5 (SBBASE(5))
+#define SBBASE6 (SBBASE(6))
+#define SBBASE7 (SBBASE(7))
+
+#define SBBASE_BANK_ENABLE (0x00000001)
+
+#define SBCTRL_BASE 0x58c00200
+#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
+
+#define SBCTRL00 SBCTRL(0, 0)
+#define SBCTRL01 SBCTRL(0, 1)
+#define SBCTRL02 SBCTRL(0, 2)
+#define SBCTRL03 SBCTRL(0, 3)
+#define SBCTRL04 (SBCTRL_BASE + 0x100)
+
+#define SBCTRL10 SBCTRL(1, 0)
+#define SBCTRL11 SBCTRL(1, 1)
+#define SBCTRL12 SBCTRL(1, 2)
+#define SBCTRL13 SBCTRL(1, 3)
+#define SBCTRL14 (SBCTRL_BASE + 0x110)
+
+#define SBCTRL20 SBCTRL(2, 0)
+#define SBCTRL21 SBCTRL(2, 1)
+#define SBCTRL22 SBCTRL(2, 2)
+#define SBCTRL23 SBCTRL(2, 3)
+#define SBCTRL24 (SBCTRL_BASE + 0x120)
+
+#define SBCTRL30 SBCTRL(3, 0)
+#define SBCTRL31 SBCTRL(3, 1)
+#define SBCTRL32 SBCTRL(3, 2)
+#define SBCTRL33 SBCTRL(3, 3)
+#define SBCTRL34 (SBCTRL_BASE + 0x130)
+
+#define SBCTRL40 SBCTRL(4, 0)
+#define SBCTRL41 SBCTRL(4, 1)
+#define SBCTRL42 SBCTRL(4, 2)
+#define SBCTRL43 SBCTRL(4, 3)
+#define SBCTRL44 (SBCTRL_BASE + 0x140)
+
+#define SBCTRL50 SBCTRL(5, 0)
+#define SBCTRL51 SBCTRL(5, 1)
+#define SBCTRL52 SBCTRL(5, 2)
+#define SBCTRL53 SBCTRL(5, 3)
+#define SBCTRL54 (SBCTRL_BASE + 0x150)
+
+#define SBCTRL60 SBCTRL(6, 0)
+#define SBCTRL61 SBCTRL(6, 1)
+#define SBCTRL62 SBCTRL(6, 2)
+#define SBCTRL63 SBCTRL(6, 3)
+#define SBCTRL64 (SBCTRL_BASE + 0x160)
+
+#define SBCTRL70 SBCTRL(7, 0)
+#define SBCTRL71 SBCTRL(7, 1)
+#define SBCTRL72 SBCTRL(7, 2)
+#define SBCTRL73 SBCTRL(7, 3)
+#define SBCTRL74 (SBCTRL_BASE + 0x170)
+
+/* slower but LED works */
+#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
+#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
+#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
+#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
+
+/* faster but LED does not work */
+#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
+#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
+#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
+
+#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
+
+#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
+
+#define PC0CTRL 0x598000c0
+#define ROM_BOOT_ROMRSV2 0x59801208
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+static inline int boot_is_swapped(void)
+{
+ return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
+}
+#endif
+
+#endif /* ARCH_SBC_REGS_H */
--- /dev/null
+/*
+ * UniPhier SC (System Control) block registers
+ *
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SC_REGS_H
+#define ARCH_SC_REGS_H
+
+#define SC_BASE_ADDR 0x61840000
+
+#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
+#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
+#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
+#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
+
+#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
+#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
+
+#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
+#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
+#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
+
+#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
+
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
+#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
+#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
+
+#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
+#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
+#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
+
+#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
+#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
+#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
+#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
+#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
+#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
+#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
+#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
+
+#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
+#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
+
+#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
+
+#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
+#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
+#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
+#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
+#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
+#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
+#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
+#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
+#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
+#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
+
+/* System reset control register */
+#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
+#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
+#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
+
+#endif /* ARCH_SC_REGS_H */
--- /dev/null
+/*
+ * UniPhier SG (SoC Glue) block registers
+ *
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SG_REGS_H
+#define ARCH_SG_REGS_H
+
+/* Base Address */
+#define SG_CTRL_BASE 0x5f800000
+#define SG_DBG_BASE 0x5f900000
+
+/* Revision */
+#define SG_REVISION (SG_CTRL_BASE | 0x0000)
+#define SG_REVISION_TYPE_SHIFT 16
+#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
+#define SG_REVISION_MODEL_SHIFT 8
+#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
+#define SG_REVISION_REV_SHIFT 0
+#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
+
+/* Memory Configuration */
+#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
+
+#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
+#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
+#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
+#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
+
+#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
+#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
+#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
+#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
+
+#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
+#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
+#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
+#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
+#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
+
+#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
+
+/* Pin Control */
+#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
+#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
+#endif
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define SG_PINSELBITS 4
+#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define SG_PINSELBITS 8
+#endif
+
+#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
+#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \
+ ((n) * (SG_PINSELBITS) % 32)))
+#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32))
+
+/* Only for PH1-Pro4 */
+#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
+
+/* Input Enable */
+#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
+
+/* Pin Monitor */
+#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
+
+#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
+
+#ifdef __ASSEMBLY__
+
+ .macro set_pinsel, n, value, ra, rd
+ ldr \ra, =SG_PINSEL_ADDR(\n)
+ ldr \rd, [\ra]
+ and \rd, \rd, #SG_PINSEL_MASK(\n)
+ orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
+ str \rd, [\ra]
+ .endm
+
+#else
+
+#include <linux/types.h>
+#include <asm/io.h>
+
+static inline void sg_set_pinsel(int n, int value)
+{
+ writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
+ | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* ARCH_SG_REGS_H */
--- /dev/null
+/*
+ * UniPhier System Cache (L2 Cache) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SSC_REGS_H
+#define ARCH_SSC_REGS_H
+
+#define SSCC 0x500c0000
+#define SSCC_BST (0x1 << 20)
+#define SSCC_ACT (0x1 << 19)
+#define SSCC_WTG (0x1 << 18)
+#define SSCC_PRD (0x1 << 17)
+#define SSCC_WBWA (0x1 << 16)
+#define SSCC_EX (0x1 << 13)
+#define SSCC_ON (0x1 << 0)
+
+#define SSCLPDAWCR 0x500c0030
+
+#define SSCOPE 0x506c0244
+#define SSCOPE_CM_SYNC 0x00000008
+
+#define SSCOQM 0x506c0248
+#define SSCOQM_TID_MASK (0x3 << 21)
+#define SSCOQM_TID_BY_WAY (0x2 << 21)
+#define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
+#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
+#define SSCOQM_S_MASK (0x3 << 17)
+#define SSCOQM_S_WAY (0x2 << 17)
+#define SSCOQM_S_ALL (0x1 << 17)
+#define SSCOQM_S_ADDRESS (0x0 << 17)
+#define SSCOQM_CE (0x1 << 15)
+#define SSCOQM_CW (0x1 << 14)
+#define SSCOQM_CM_MASK (0x7)
+#define SSCOQM_CM_DIRT_TOUCH (0x7)
+#define SSCOQM_CM_ZERO_TOUCH (0x6)
+#define SSCOQM_CM_NORM_TOUCH (0x5)
+#define SSCOQM_CM_PREF_FETCH (0x4)
+#define SSCOQM_CM_SSC_FETCH (0x3)
+#define SSCOQM_CM_WB_INV (0x2)
+#define SSCOQM_CM_WB (0x1)
+#define SSCOQM_CM_INV (0x0)
+
+#define SSCOQAD 0x506c024c
+#define SSCOQSZ 0x506c0250
+#define SSCOQWN 0x506c0258
+
+#define SSCOPPQSEF 0x506c025c
+#define SSCOPPQSEF_FE (0x1 << 1)
+#define SSCOPPQSEF_OE (0x1 << 0)
+
+#define SSCOLPQS 0x506c0260
+#define SSCOLPQS_EF (0x1 << 2)
+#define SSCOLPQS_EST (0x1 << 1)
+#define SSCOLPQS_QST (0x1 << 0)
+
+#define SSCOQCE0 0x506c0270
+
+#define SSC_LINE_SIZE 128
+#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
+
+#endif /* ARCH_SSC_REGS_H */
--- /dev/null
+/*
+ * UniPhier UMC (Universal Memory Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_UMC_REGS_H
+#define ARCH_UMC_REGS_H
+
+#define UMC_BASE 0x5b800000
+
+/* SSIF registers */
+#define UMC_SSIF_BASE UMC_BASE
+
+#define UMC_CPURST 0x00000700
+#define UMC_IDSRST 0x0000070C
+#define UMC_IXMRST 0x00000714
+#define UMC_HDMRST 0x00000718
+#define UMC_MDMRST 0x0000071C
+#define UMC_HDDRST 0x00000720
+#define UMC_MDDRST 0x00000724
+#define UMC_SIORST 0x00000728
+#define UMC_GIORST 0x0000072C
+#define UMC_HD2RST 0x00000734
+#define UMC_VIORST 0x0000073C
+#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
+#define UMC_DVCRST 0x00000748 /* Pro4 */
+#define UMC_RGLRST 0x00000750
+#define UMC_VPERST 0x00000758
+#define UMC_AIORST 0x00000764
+#define UMC_DMDRST 0x00000770
+
+#define UMC_HDMCHSEL 0x00000898
+#define UMC_MDMCHSEL 0x0000089C
+#define UMC_DVCCHSEL 0x000008C8
+#define UMC_DMDCHSEL 0x000008F0
+
+#define UMC_CLKEN_SSIF_FETCH 0x0000C060
+#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
+#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
+#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
+#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
+#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
+#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
+#define UMC_CLKEN_SSIF_WC 0x0000C07C
+#define UMC_CLKEN_SSIF_RC 0x0000C080
+#define UMC_CLKEN_SSIF_DST 0x0000C084
+
+/* CA registers */
+#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
+
+/* DRAM controller registers */
+#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
+
+#define UMC_CMDCTLA 0x00000000
+#define UMC_CMDCTLB 0x00000004
+#define UMC_INITCTLA 0x00000008
+#define UMC_INITCTLB 0x0000000C
+#define UMC_INITCTLC 0x00000010
+#define UMC_INITSET 0x00000014
+#define UMC_INITSTAT 0x00000018
+#define UMC_DRMMR0 0x0000001C
+#define UMC_DRMMR1 0x00000020
+#define UMC_DRMMR2 0x00000024
+#define UMC_DRMMR3 0x00000028
+#define UMC_SPCCTLA 0x00000030
+#define UMC_SPCCTLB 0x00000034
+#define UMC_SPCSETA 0x00000038
+#define UMC_SPCSETB 0x0000003C
+#define UMC_SPCSETC 0x00000040
+#define UMC_SPCSETD 0x00000044
+#define UMC_SPCSTATA 0x00000050
+#define UMC_SPCSTATB 0x00000054
+#define UMC_SPCSTATC 0x00000058
+#define UMC_ACSSETA 0x00000060
+#define UMC_FLOWCTLA 0x00000400
+#define UMC_FLOWCTLB 0x00000404
+#define UMC_FLOWCTLC 0x00000408
+#define UMC_FLOWCTLG 0x00000508
+#define UMC_RDATACTL_D0 0x00000600
+#define UMC_WDATACTL_D0 0x00000604
+#define UMC_RDATACTL_D1 0x00000608
+#define UMC_WDATACTL_D1 0x0000060C
+#define UMC_DATASET 0x00000610
+#define UMC_DCCGCTL 0x00000720
+#define UMC_DICGCTLA 0x00000724
+#define UMC_DICGCTLB 0x00000728
+#define UMC_DIOCTLA 0x00000C00
+#define UMC_DFICUPDCTLA 0x00000C20
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+static inline void umc_polling(u32 address, u32 expval, u32 mask)
+{
+ u32 nmask = ~mask;
+ u32 data;
+ do {
+ data = readl(address) & nmask;
+ } while (data != expval);
+}
+
+static inline void umc_dram_init_start(void __iomem *dramcont)
+{
+ writel(0x00000002, dramcont + UMC_INITSET);
+}
+
+static inline void umc_dram_init_poll(void __iomem *dramcont)
+{
+ while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
+ ;
+}
+
+#endif
+
+#endif
--- /dev/null
+#include <config.h>
+#include <linux/linkage.h>
+
+/* page table */
+#define NR_SECTIONS 4096
+#define SECTION_SHIFT 20
+#define DEVICE 0x00002002 /* Non-shareable Device */
+#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
+
+#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
+#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT))
+
+ .section ".rodata"
+ .align 14
+ENTRY(init_page_table)
+ section = 0
+ .rept NR_SECTIONS
+ .if section == TEXT_SECTION || section == STACK_SECTION
+ attr = NORMAL
+ .else
+ attr = DEVICE
+ .endif
+ .word (section << SECTION_SHIFT) | attr
+ section = section + 1
+ .endr
+END(init_page_table)
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <linux/sizes.h>
+#include <asm/system.h>
+#include <mach/led.h>
+#include <mach/arm-mpcore.h>
+#include <mach/sbc-regs.h>
+#include <mach/ssc-regs.h>
+
+ENTRY(lowlevel_init)
+ mov r8, lr @ persevere link reg across call
+
+ /*
+ * The UniPhier Boot ROM loads SPL code to the L2 cache.
+ * But CPUs can only do instruction fetch now because start.S has
+ * cleared C and M bits.
+ * First we need to turn on MMU and Dcache again to get back
+ * data access to L2.
+ */
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
+ orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
+ mcr p15, 0, r0, c1, c0, 0
+
+#ifdef CONFIG_DEBUG_LL
+ bl setup_lowlevel_debug
+#endif
+
+ /*
+ * Now we are using the page table embedded in the Boot ROM.
+ * It is not handy since it is not a straight mapped table for sLD3.
+ * What we need to do next is to switch over to the page table in SPL.
+ */
+ ldr r3, =init_page_table @ page table must be 16KB aligned
+
+ /* Disable MMU and Dcache before switching Page Table */
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
+ bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
+ mcr p15, 0, r0, c1, c0, 0
+
+ bl enable_mmu
+
+#ifdef CONFIG_UNIPHIER_SMP
+ /*
+ * ACTLR (Auxiliary Control Register) for Cortex-A9
+ * bit[9] Parity on
+ * bit[8] Alloc in one way
+ * bit[7] EXCL (Exclusive cache bit)
+ * bit[6] SMP
+ * bit[3] Write full line of zeros mode
+ * bit[2] L1 Prefetch enable
+ * bit[1] L2 prefetch enable
+ * bit[0] FW (Cache and TLB maintenance broadcast)
+ */
+ mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
+ orr r0, r0, #0x41 @ enable SMP, FW bit
+ mcr p15, 0, r0, c1, c0, 1
+
+ /* branch by CPU ID */
+ mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
+ and r0, r0, #0x3
+ cmp r0, #0x0
+ beq primary_cpu
+ ldr r1, =ROM_BOOT_ROMRSV2
+ mov r0, #0
+ str r0, [r1]
+0: wfe
+ ldr r0, [r1]
+ cmp r0, #0
+ beq 0b
+ bx r0 @ r0: entry point of U-Boot main for the secondary CPU
+primary_cpu:
+ ldr r1, =ROM_BOOT_ROMRSV2
+ ldr r0, =_start @ entry for the secondary CPU
+ str r0, [r1]
+ ldr r0, [r1] @ make sure str is complete before sev
+ sev @ kick the sedoncary CPU
+ mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
+ bfc r1, #0, #13 @ clear bit 12-0
+ mov r0, #-1
+ str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
+ mov r0, #1 @ SCU enable
+ str r0, [r1, #SCU_CTRL] @ SCU Control Register
+#endif
+
+ bl setup_init_ram @ RAM area for temporary stack pointer
+
+ mov lr, r8 @ restore link
+ mov pc, lr @ back to my caller
+ENDPROC(lowlevel_init)
+
+ENTRY(enable_mmu)
+ mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
+ bic r0, r0, #0x37
+ orr r0, r0, #0x20 @ disable TTBR1
+ mcr p15, 0, r0, c2, c0, 2
+
+ orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
+ mcr p15, 0, r0, c2, c0, 0 @ TTBR0
+
+ mov r0, #0
+ mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
+
+ mov r0, #-1 @ manager for all domains (No permission check)
+ mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
+
+ dsb
+ isb
+ /*
+ * MMU on:
+ * TLBs was already invalidated in "../start.S"
+ * So, we don't need to invalidate it here.
+ */
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
+ orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
+ mcr p15, 0, r0, c1, c0, 0
+
+ mov pc, lr
+ENDPROC(enable_mmu)
+
+/*
+ * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
+ * It is large enough for tmp RAM.
+ */
+#define BOOT_RAM_SIZE (SZ_32K)
+#define BOOT_WAY_BITS (0x00000100) /* way 8 */
+
+ENTRY(setup_init_ram)
+ /*
+ * Touch to zero for the boot way
+ */
+0:
+ /*
+ * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
+ */
+ ldr r0, = 0x00408006 @ touch to zero with address range
+ ldr r1, = SSCOQM
+ str r0, [r1]
+ ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address
+ ldr r1, = SSCOQAD
+ str r0, [r1]
+ ldr r0, = BOOT_RAM_SIZE
+ ldr r1, = SSCOQSZ
+ str r0, [r1]
+ ldr r0, = BOOT_WAY_BITS
+ ldr r1, = SSCOQWN
+ str r0, [r1]
+ ldr r1, = SSCOPPQSEF
+ ldr r0, [r1]
+ cmp r0, #0 @ check if the command is successfully set
+ bne 0b @ try again if an error occurres
+
+ ldr r1, = SSCOLPQS
+1:
+ ldr r0, [r1]
+ cmp r0, #0x4
+ bne 1b @ wait until the operation is completed
+ str r0, [r1] @ clear the complete notification flag
+
+ mov pc, lr
+ENDPROC(setup_init_ram)
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <mach/sg-regs.h>
+
+static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
+{
+ int size_mb = size / num;
+ u32 ret;
+
+ switch (size_mb) {
+ case SZ_64M:
+ ret = SG_MEMCONF_CH0_SZ_64M;
+ break;
+ case SZ_128M:
+ ret = SG_MEMCONF_CH0_SZ_128M;
+ break;
+ case SZ_256M:
+ ret = SG_MEMCONF_CH0_SZ_256M;
+ break;
+ case SZ_512M:
+ ret = SG_MEMCONF_CH0_SZ_512M;
+ break;
+ case SZ_1G:
+ ret = SG_MEMCONF_CH0_SZ_1G;
+ break;
+ default:
+ BUG();
+ break;
+ }
+
+ switch (num) {
+ case 1:
+ ret |= SG_MEMCONF_CH0_NUM_1;
+ break;
+ case 2:
+ ret |= SG_MEMCONF_CH0_NUM_2;
+ break;
+ default:
+ BUG();
+ break;
+ }
+ return ret;
+}
+
+static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
+{
+ int size_mb = size / num;
+ u32 ret;
+
+ switch (size_mb) {
+ case SZ_64M:
+ ret = SG_MEMCONF_CH1_SZ_64M;
+ break;
+ case SZ_128M:
+ ret = SG_MEMCONF_CH1_SZ_128M;
+ break;
+ case SZ_256M:
+ ret = SG_MEMCONF_CH1_SZ_256M;
+ break;
+ case SZ_512M:
+ ret = SG_MEMCONF_CH1_SZ_512M;
+ break;
+ case SZ_1G:
+ ret = SG_MEMCONF_CH1_SZ_1G;
+ break;
+ default:
+ BUG();
+ break;
+ }
+
+ switch (num) {
+ case 1:
+ ret |= SG_MEMCONF_CH1_NUM_1;
+ break;
+ case 2:
+ ret |= SG_MEMCONF_CH1_NUM_2;
+ break;
+ default:
+ BUG();
+ break;
+ }
+ return ret;
+}
+
+void memconf_init(void)
+{
+ u32 tmp;
+
+ /* Set DDR size */
+ tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
+ tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
+ tmp |= SG_MEMCONF_SPARSEMEM;
+#endif
+ writel(tmp, SG_MEMCONF);
+}
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
+obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
+ pll_spectrum.o umc_init.o ddrphy_init.o
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
+else
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+endif
+
+obj-y += boot-mode.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/bcu-regs.h>
+
+#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
+
+void bcu_init(void)
+{
+ int shift;
+
+ writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
+ writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
+
+ /* Specify DDR channel */
+ shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
+ writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+}
--- /dev/null
+#include "../ph1-pro4/boot-mode.c"
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <mach/sc-regs.h>
+
+void clkrst_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <mach/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8253c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a82dbc0, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+ writel(0x00000800, &phy->mr3);
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+}
--- /dev/null
+#include "../ph1-pro4/early_clkrst_init.c"
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <mach/sg-regs.h>
+
+#define UART_CLK 36864000
+#include <mach/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ init_debug_uart r0, r1, r2
+
+ /* UART Port 0 */
+ set_pinsel 85, 1, r0, r1
+ set_pinsel 88, 1, r0, r1
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sg-regs.h>
+
+void pin_init(void)
+{
+ u32 tmp;
+
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+ sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */
+ sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */
+
+ sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */
+ sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */
+
+ sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */
+ sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */
+
+ sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
+ sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
+#endif
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */
+ sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */
+ sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */
+ sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */
+ sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */
+ sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */
+ sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */
+ sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */
+ sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */
+ sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */
+ sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */
+ sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */
+ sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */
+ sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */
+ sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */
+ sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */
+ sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */
+ sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */
+ /* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
+ /* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
+#endif
+
+ tmp = readl(SG_IECTRL);
+ tmp |= 0x41;
+ writel(tmp, SG_IECTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/platdevice.h>
+
+#define UART_MASTER_CLK 36864000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+#undef DPLL_SSC_RATE_1PER
+
+static void dpll_init(void)
+{
+ u32 tmp;
+
+ /*
+ * Set Frequency
+ * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+ * to FOUT (DPLLCTRL.bit[29:20])
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~0x000f0000;
+#if CONFIG_DDR_FREQ == 1600
+ tmp |= 0x000c0000;
+#elif CONFIG_DDR_FREQ == 1333
+ tmp |= 0x000d0000;
+#else
+# error "Unknown frequency"
+#endif
+
+#if defined(DPLL_SSC_RATE_1PER)
+ tmp &= ~SC_DPLLCTRL_SSC_RATE;
+#else
+ tmp |= SC_DPLLCTRL_SSC_RATE;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ tmp = readl(SC_DPLLCTRL2);
+ tmp |= SC_DPLLCTRL2_NRSTDS;
+ writel(tmp, SC_DPLLCTRL2);
+}
+
+static void upll_init(void)
+{
+ u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+ tmp = readl(SC_UPLLCTRL);
+ tmp &= ~0x18000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x0228f5c0;
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x02328000;
+ }
+ }
+
+ writel(tmp, SC_UPLLCTRL);
+
+ /* set 1 to K_LD(UPLLCTRL.bit[27]) */
+ tmp |= 0x08000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* set 1 to SNRT(UPLLCTRL.bit[28]) */
+ tmp |= 0x10000000;
+ writel(tmp, SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 1 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Set 0 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* Set 1 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* set 0 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+void pll_init(void)
+{
+ dpll_init();
+ upll_init();
+ vpll_init();
+
+ /*
+ * Wait 500 usec until dpll get stable
+ * We wait 10 usec in upll_init() and vpll_init()
+ * so 20 usec can be saved here.
+ */
+ udelay(480);
+}
--- /dev/null
+#include "../ph1-pro4/pll_spectrum.c"
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+void sbc_init(void)
+{
+ u32 tmp;
+
+ /* system bus output enable */
+ tmp = readl(PC0CTRL);
+ tmp &= 0xfffffcff;
+ writel(tmp, PC0CTRL);
+
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
+ *
+ * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
+ * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x00000000-0x01ffffff: mask ROM
+ * 0x02000000-0x03efffff: memory bank (31MB)
+ * 0x03f00000-0x03ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+void sbc_init(void)
+{
+ u32 tmp;
+
+ /* system bus output enable */
+ tmp = readl(PC0CTRL);
+ tmp &= 0xfffffcff;
+ writel(tmp, PC0CTRL);
+
+ /* XECS1: sub/boot memory (boot swap = off/on) */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+ /* XECS0: boot/sub memory (boot swap = off/on) */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+
+ /* XECS3: peripherals */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
+
+ /* base address regsiters */
+ writel(0x0000bc01, SBBASE0);
+ writel(0x0400bc01, SBBASE1);
+ writel(0x0800bf01, SBBASE3);
+
+ /* enable access to sub memory when boot swap is on */
+ if (boot_is_swapped())
+ sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
+
+ sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <mach/sg-regs.h>
+
+void sg_init(void)
+{
+ u32 tmp;
+
+ /* Input ports must be enabled before deasserting reset of cores */
+ tmp = readl(SG_IECTRL);
+ tmp |= 0x1;
+ writel(tmp, SG_IECTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/umc-regs.h>
+#include <mach/ddrphy-regs.h>
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
+{
+ if (freq == 1333) {
+ writel(0x45990b11, dramcont + UMC_CMDCTLA);
+ writel(0x16958924, dramcont + UMC_CMDCTLB);
+ writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+ if (size == 1)
+ writel(0x27028B0A, dramcont + UMC_INITCTLB);
+ else if (size == 2)
+ writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+ writel(0x000FF0FF, dramcont + UMC_INITCTLC);
+ writel(0x00000b51, dramcont + UMC_DRMMR0);
+ } else if (freq == 1600) {
+ writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
+ writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
+ writel(0x5101387F, dramcont + UMC_INITCTLA);
+
+ if (size == 1)
+ writel(0x2F030D3F, dramcont + UMC_INITCTLB);
+ else if (size == 2)
+ writel(0x43030D3F, dramcont + UMC_INITCTLB);
+
+ writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+ writel(0x00000d71, dramcont + UMC_DRMMR0);
+ }
+
+ writel(0x00000006, dramcont + UMC_DRMMR1);
+
+ if (freq == 1333)
+ writel(0x00000290, dramcont + UMC_DRMMR2);
+ else if (freq == 1600)
+ writel(0x00000298, dramcont + UMC_DRMMR2);
+
+ writel(0x00000800, dramcont + UMC_DRMMR3);
+
+ if (freq == 1333) {
+ if (size == 1)
+ writel(0x00240512, dramcont + UMC_SPCCTLA);
+ else if (size == 2)
+ writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+ writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+ writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+ } else if (freq == 1600) {
+ if (size == 1)
+ writel(0x002B0617, dramcont + UMC_SPCCTLA);
+ else if (size == 2)
+ writel(0x003F0617, dramcont + UMC_SPCCTLA);
+
+ writel(0x00ff0008, dramcont + UMC_SPCCTLB);
+ writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+ }
+
+ writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+ writel(0x04a02000, dramcont + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dramcont + UMC_DCCGCTL);
+ writel(0x00000003, dramcont + 0x7000);
+ writel(0x0000000f, dramcont + 0x8000);
+ writel(0x000000c3, dramcont + 0x8004);
+ writel(0x00000071, dramcont + 0x8008);
+ writel(0x0000003b, dramcont + UMC_DICGCTLA);
+ writel(0x020a0808, dramcont + UMC_DICGCTLB);
+ writel(0x00000004, dramcont + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+ writel(0x00200000, dramcont + UMC_FLOWCTLB);
+ writel(0x00004444, dramcont + UMC_FLOWCTLC);
+ writel(0x200a0a00, dramcont + UMC_SPCSETB);
+ writel(0x00000000, dramcont + UMC_SPCSETD);
+ writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+ void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+ void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+ void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+ void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+ void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+
+ umc_dram_init_start(dramcont0);
+ umc_dram_init_start(dramcont1);
+ umc_dram_init_poll(dramcont0);
+ umc_dram_init_poll(dramcont1);
+
+ writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+ ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
+ writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+ ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 1);
+ ddrphy_training(phy1_0);
+
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+
+int umc_init(void)
+{
+ return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
+ CONFIG_SDRAM1_SIZE / 0x08000000);
+}
+
+#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
+ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
+ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
+/* OK */
+#else
+#error Unsupported DDR configuration.
+#endif
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
+obj-y += sg_init.o pll_init.o early_clkrst_init.o \
+ pll_spectrum.o umc_init.o ddrphy_init.o
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
+else
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+endif
+
+obj-y += boot-mode.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <mach/boot-device.h>
+#include <mach/sg-regs.h>
+#include <mach/sbc-regs.h>
+
+struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ { /* sentinel */ }
+};
+
+int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 spl_boot_device(void)
+{
+ int boot_mode;
+
+ if (boot_is_swapped())
+ return BOOT_DEVICE_NOR;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <mach/sc-regs.h>
+
+void clkrst_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
+ SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp = readl(SC_RSTCTRL2);
+ tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
+ writel(tmp, SC_RSTCTRL2);
+ readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+ SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <mach/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a878400, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+ writel(0x00000000, &phy->mr3);
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <mach/sc-regs.h>
+
+void early_clkrst_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+
+ tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
+ if (spl_boot_device() != BOOT_DEVICE_NAND)
+ tmp &= ~SC_RSTCTRL_NRST_NAND;
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+#define UART_CLK 73728000
+#include <mach/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ init_debug_uart r0, r1, r2
+
+ /* UART Port 0 */
+ set_pinsel 127, 0, r0, r1
+ set_pinsel 128, 0, r0, r1
+
+ ldr r0, =SG_LOADPINCTRL
+ mov r1, #1
+ str r1, [r0]
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sg-regs.h>
+
+void pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+ sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */
+ sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */
+ sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */
+ sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */
+ sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */
+ sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */
+ sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */
+ sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */
+#endif
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */
+ sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */
+ sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */
+ sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */
+ sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */
+ sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */
+ sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */
+ sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */
+ sg_set_pinsel(48, 0); /* NFALE -> NFALE */
+ sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */
+ sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */
+ sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */
+ sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */
+ sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(180, 0); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(181, 0); /* USB0OD -> USB0OD */
+ sg_set_pinsel(182, 0); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(183, 0); /* USB1OD -> USB1OD */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */
+ sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */
+#endif
+
+ writel(1, SG_LOADPINCTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/platdevice.h>
+
+#define UART_MASTER_CLK 73728000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+#undef DPLL_SSC_RATE_1PER
+
+static void dpll_init(void)
+{
+ u32 tmp;
+
+ /*
+ * Set Frequency
+ * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+ * to FOUT ( DPLLCTRL.bit[29:20] )
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~(0x000f0000);
+#if CONFIG_DDR_FREQ == 1600
+ tmp |= 0x000c0000;
+#elif CONFIG_DDR_FREQ == 1333
+ tmp |= 0x000d0000;
+#else
+# error "Unsupported frequency"
+#endif
+
+ /*
+ * Set Moduration rate
+ * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
+ */
+#if defined(DPLL_SSC_RATE_1PER)
+ tmp &= ~0x00008000;
+#else
+ tmp |= 0x00008000;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ tmp = readl(SC_DPLLCTRL2);
+ tmp |= SC_DPLLCTRL2_NRSTDS;
+ writel(tmp, SC_DPLLCTRL2);
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ /* Set VPLL27A & VPLL27B */
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+ /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
+ return;
+#endif
+
+ /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Unset VPLA_K_LD and VPLB_K_LD bit */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set VPLA_M and VPLB_M to 0x20 */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
+ /* Set VPLA_K and VPLB_K for AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066666;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066666;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* wait 1 usec */
+ udelay(1);
+
+ /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Unset VPLA_SNRST and VPLB_SNRST bit */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+void pll_init(void)
+{
+ dpll_init();
+ vpll_init();
+
+ /*
+ * Wait 500 usec until dpll get stable
+ * We wait 1 usec in vpll_init() so 1 usec can be saved here.
+ */
+ udelay(499);
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sc-regs.h>
+
+void enable_dpll_ssc(void)
+{
+ u32 tmp;
+
+ tmp = readl(SC_DPLLCTRL);
+ tmp |= SC_DPLLCTRL_SSC_EN;
+ writel(tmp, SC_DPLLCTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+void sbc_init(void)
+{
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
+ *
+ * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
+ * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x00000000-0x01ffffff: mask ROM
+ * 0x02000000-0x03efffff: memory bank (31MB)
+ * 0x03f00000-0x03ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+void sbc_init(void)
+{
+ /* XECS0: boot/sub memory (boot swap = off/on) */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+
+ /* XECS1: sub/boot memory (boot swap = off/on) */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+ /* XECS3: peripherals */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
+
+ writel(0x0000bc01, SBBASE0); /* boot memory */
+ writel(0x0400bc01, SBBASE1); /* sub memory */
+ writel(0x0800bf01, SBBASE3); /* peripherals */
+
+ /* enable access to sub memory when boot swap is on */
+ if (boot_is_swapped())
+ sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
+
+ sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
+ writel(0x00000001, SG_LOADPINCTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <mach/sg-regs.h>
+
+void sg_init(void)
+{
+ u32 tmp;
+
+ /* Input ports must be enabled before deasserting reset of cores */
+ tmp = readl(SG_IECTRL);
+ tmp |= 1 << 6;
+ writel(tmp, SG_IECTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/umc-regs.h>
+#include <mach/ddrphy-regs.h>
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000001, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x07ffffff, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+
+ writel(0x03010100, ssif_base + UMC_HDMCHSEL);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DVCCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+ writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_HDMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_HDDRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_GIORST);
+ writel(0x00000001, ssif_base + UMC_HD2RST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_DVCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_VPERST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
+{
+ writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
+ writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
+ writel(0x5101387f, dramcont + UMC_INITCTLA);
+ writel(0x43030d3f, dramcont + UMC_INITCTLB);
+ writel(0x00ff00ff, dramcont + UMC_INITCTLC);
+ writel(0x00000d71, dramcont + UMC_DRMMR0);
+ writel(0x00000006, dramcont + UMC_DRMMR1);
+ writel(0x00000298, dramcont + UMC_DRMMR2);
+ writel(0x00000000, dramcont + UMC_DRMMR3);
+ writel(0x003f0617, dramcont + UMC_SPCCTLA);
+ writel(0x00ff0008, dramcont + UMC_SPCCTLB);
+ writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+ writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
+ writel(0x04060802, dramcont + UMC_WDATACTL_D0);
+ writel(0x04060802, dramcont + UMC_WDATACTL_D1);
+ writel(0x04a02000, dramcont + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dramcont + UMC_DCCGCTL);
+ writel(0x0000000f, dramcont + 0x7000);
+ writel(0x0000000f, dramcont + 0x8000);
+ writel(0x000000c3, dramcont + 0x8004);
+ writel(0x00000071, dramcont + 0x8008);
+ writel(0x00000004, dramcont + UMC_FLOWCTLG);
+ writel(0x00000000, dramcont + 0x0060);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+ writel(0x00200000, dramcont + UMC_FLOWCTLB);
+ writel(0x00004444, dramcont + UMC_FLOWCTLC);
+ writel(0x200a0a00, dramcont + UMC_SPCSETB);
+ writel(0x00010000, dramcont + UMC_SPCSETD);
+ writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+ void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+ void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+ void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+ void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+ void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+ void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
+
+ umc_dram_init_start(dramcont0);
+ umc_dram_init_start(dramcont1);
+ umc_dram_init_poll(dramcont0);
+ umc_dram_init_poll(dramcont1);
+
+ writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+ ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
+ writel(0x00000103, dramcont0 + UMC_DIOCTLA);
+
+ ddrphy_init(phy0_1, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_1, 1);
+ ddrphy_training(phy0_1);
+
+ writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+ ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 0);
+ ddrphy_training(phy1_0);
+
+ writel(0x00000103, dramcont1 + UMC_DIOCTLA);
+
+ ddrphy_init(phy1_1, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_1, 1);
+ ddrphy_training(phy1_1);
+
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+
+int umc_init(void)
+{
+ return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
+ CONFIG_SDRAM1_SIZE / 0x08000000);
+}
+
+#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
+ (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
+ ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
+ (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
+/* OK */
+#else
+ #error Unsupported DDR configuration.
+#endif
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
+obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
+ pll_spectrum.o umc_init.o ddrphy_init.o
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
+else
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+endif
+
+obj-y += boot-mode.o
--- /dev/null
+#include "../ph1-ld4/bcu_init.c"
--- /dev/null
+#include "../ph1-pro4/boot-mode.c"
--- /dev/null
+#include "../ph1-ld4/clkrst_init.c"
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <mach/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a878400, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x00000000, &phy->mr3);
+#else
+ writel(0x00000800, &phy->mr3);
+#endif
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+}
--- /dev/null
+#include "../ph1-ld4/early_clkrst_init.c"
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <mach/sg-regs.h>
+
+#define UART_CLK 80000000
+#include <mach/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ init_debug_uart r0, r1, r2
+
+ /* UART Port 0 */
+ set_pinsel 70, 3, r0, r1
+ set_pinsel 71, 3, r0, r1
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sg-regs.h>
+
+void pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+ sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */
+ sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */
+
+ sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */
+ sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */
+
+ sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */
+ sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */
+
+ sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
+ sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
+#endif
+
+#ifdef CONFIG_SYS_I2C_UNIPHIER
+ {
+ u32 tmp;
+ tmp = readl(SG_IECTRL);
+ tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
+ writel(tmp, SG_IECTRL);
+ }
+#endif
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */
+ sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */
+ sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */
+ sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */
+ sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */
+ sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */
+ sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */
+ sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */
+ sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */
+ sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */
+ sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */
+ sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */
+ sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */
+ sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */
+ sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */
+ sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */
+ sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */
+ sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */
+ /* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
+ /* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/platdevice.h>
+
+#define UART_MASTER_CLK 80000000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+static void dpll_init(void)
+{
+ u32 tmp;
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL3
+ * [23] DIVN_TEST 0x1
+ * [22:16] DIVN 0x50
+ * [10] FREFSEL_TEST 0x1
+ * [9:8] FREFSEL 0x2
+ * [4] ICPD_TEST 0x1
+ * [3:0] ICPD 0xb
+ */
+ tmp = readl(SC_DPLLCTRL3);
+ tmp &= ~0x00ff0717;
+ tmp |= 0x00d0061b;
+ writel(tmp, SC_DPLLCTRL3);
+
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL
+ * <-1%> <-2%>
+ * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
+ * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~0x3ff07fff;
+#ifdef CONFIG_DPLL_SSC_RATE_1PER
+ tmp |= 0x084018bf;
+#else
+ tmp |= 0x084031a6;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL2
+ * [31:29] SSC_STEP 0
+ * [27] SSC_REG_REF 1
+ * [26:20] SSC_M 79 (0x4f)
+ * [19:0] SSC_K 964689 (0xeb851)
+ */
+ tmp = readl(SC_DPLLCTRL2);
+ tmp &= ~0xefffffff;
+ tmp |= 0x0cfeb851;
+ writel(tmp, SC_DPLLCTRL2);
+}
+
+static void upll_init(void)
+{
+ u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+ tmp = readl(SC_UPLLCTRL);
+ tmp &= ~0x18000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x0228f5c0;
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x02328000;
+ }
+ }
+
+ writel(tmp, SC_UPLLCTRL);
+
+ /* set 1 to K_LD(UPLLCTRL.bit[27]) */
+ tmp |= 0x08000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* set 1 to SNRT(UPLLCTRL.bit[28]) */
+ tmp |= 0x10000000;
+ writel(tmp, SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 1 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Set 0 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* Set 1 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* set 0 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+void pll_init(void)
+{
+ dpll_init();
+ upll_init();
+ vpll_init();
+
+ /*
+ * Wait 500 usec until dpll get stable
+ * We wait 10 usec in upll_init() and vpll_init()
+ * so 20 usec can be saved here.
+ */
+ udelay(480);
+}
--- /dev/null
+#include "../ph1-ld4/pll_spectrum.c"
--- /dev/null
+#include "../ph1-ld4/sbc_init.c"
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+void sbc_init(void)
+{
+ u32 tmp;
+
+ /* system bus output enable */
+ tmp = readl(PC0CTRL);
+ tmp &= 0xfffffcff;
+ writel(tmp, PC0CTRL);
+
+ /*
+ * SBCTRL0* does not need settings because PH1-sLD8 has no support for
+ * XECS0. The boot swap must be enabled to boot from the support card.
+ */
+
+ if (boot_is_swapped()) {
+ /* XECS1 : boot memory if boot swap is on */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+ }
+
+ /* XECS4 : sub memory */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
+
+ /* XECS5 : peripherals */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
+
+ /* base address regsiters */
+ writel(0x0000bc01, SBBASE0); /* boot memory */
+ writel(0x0900bfff, SBBASE1); /* dummy */
+ writel(0x0400bc01, SBBASE4); /* sub memory */
+ writel(0x0800bf01, SBBASE5); /* peripherals */
+
+ sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
+ sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
+
+ /* dummy read to assure write process */
+ readl(SG_PINCTRL(0));
+}
--- /dev/null
+#include "../ph1-ld4/sg_init.c"
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/umc-regs.h>
+#include <mach/ddrphy-regs.h>
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
+{
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x55990b11, dramcont + UMC_CMDCTLA);
+ writel(0x16958944, dramcont + UMC_CMDCTLB);
+#else
+ writel(0x45990b11, dramcont + UMC_CMDCTLA);
+ writel(0x16958924, dramcont + UMC_CMDCTLB);
+#endif
+
+ writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+ if (size == 1)
+ writel(0x27028B0A, dramcont + UMC_INITCTLB);
+ else if (size == 2)
+ writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+ writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+ writel(0x00000b51, dramcont + UMC_DRMMR0);
+ writel(0x00000006, dramcont + UMC_DRMMR1);
+ writel(0x00000290, dramcont + UMC_DRMMR2);
+
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x00000000, dramcont + UMC_DRMMR3);
+#else
+ writel(0x00000800, dramcont + UMC_DRMMR3);
+#endif
+
+ if (size == 1)
+ writel(0x00240512, dramcont + UMC_SPCCTLA);
+ else if (size == 2)
+ writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+ writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+ writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+ writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+ writel(0x04a02000, dramcont + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dramcont + UMC_DCCGCTL);
+ writel(0x00000003, dramcont + 0x7000);
+ writel(0x0000004f, dramcont + 0x8000);
+ writel(0x000000c3, dramcont + 0x8004);
+ writel(0x00000077, dramcont + 0x8008);
+ writel(0x0000003b, dramcont + UMC_DICGCTLA);
+ writel(0x020a0808, dramcont + UMC_DICGCTLB);
+ writel(0x00000004, dramcont + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+ writel(0x00200000, dramcont + UMC_FLOWCTLB);
+ writel(0x00004444, dramcont + UMC_FLOWCTLC);
+ writel(0x200a0a00, dramcont + UMC_SPCSETB);
+ writel(0x00000000, dramcont + UMC_SPCSETD);
+ writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+ void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+ void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+ void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+ void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+ void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+
+ umc_dram_init_start(dramcont0);
+ umc_dram_init_start(dramcont1);
+ umc_dram_init_poll(dramcont0);
+ umc_dram_init_poll(dramcont1);
+
+ writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+ ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
+ writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+ ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 1);
+ ddrphy_training(phy1_0);
+
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+
+int umc_init(void)
+{
+ return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
+ CONFIG_SDRAM1_SIZE / 0x08000000);
+}
+
+#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
+ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
+ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
+/* OK */
+#else
+#error Unsupported DDR configuration.
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/board.h>
+
+int misc_init_f(void)
+{
+ return check_support_card();
+}
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sc-regs.h>
+
+void reset_cpu(unsigned long ignored)
+{
+ u32 tmp;
+
+ writel(5, SC_IRQTIMSET); /* default value */
+
+ tmp = readl(SC_SLFRSTSEL);
+ tmp &= ~0x3; /* mask [1:0] */
+ tmp |= 0x0; /* XRST reboot */
+ writel(tmp, SC_SLFRSTSEL);
+
+ tmp = readl(SC_SLFRSTCTL);
+ tmp |= 0x1;
+ writel(tmp, SC_SLFRSTCTL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <mach/led.h>
+#include <mach/sbc-regs.h>
+
+/* Entry point of U-Boot main program for the secondary CPU */
+LENTRY(secondary_entry)
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
+ bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable
+ mcr p15, 0, r0, c1, c0, 0
+ mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
+ dsb
+ led_write(C,0,,)
+ ldr r1, =ROM_BOOT_ROMRSV2
+ mov r0, #0
+ str r0, [r1]
+0: wfe
+ ldr r4, [r1] @ r4: entry point for secondary CPUs
+ cmp r4, #0
+ beq 0b
+ led_write(C, P, U, 1)
+ bx r4 @ secondary CPUs jump to linux
+ENDPROC(secondary_entry)
+
+ENTRY(wakeup_secondary)
+ ldr r1, =ROM_BOOT_ROMRSV2
+0: ldr r0, [r1]
+ cmp r0, #0
+ bne 0b
+
+ /* set entry address and send event to the secondary CPU */
+ ldr r0, =secondary_entry
+ str r0, [r1]
+ ldr r0, [r1] @ make sure store is complete
+ mov r0, #0x100
+0: subs r0, r0, #1 @ I don't know the reason, but without this wait
+ bne 0b @ fails to wake up the secondary CPU
+ sev
+
+ /* wait until the secondary CPU reach to secondary_entry */
+0: ldr r0, [r1]
+ cmp r0, #0
+ bne 0b
+ bx lr
+ENDPROC(wakeup_secondary)
--- /dev/null
+/*
+ * Copyright (C) 2013-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/led.h>
+#include <mach/board.h>
+
+void __weak bcu_init(void)
+{
+};
+void sbc_init(void);
+void sg_init(void);
+void pll_init(void);
+void pin_init(void);
+void memconf_init(void);
+void early_clkrst_init(void);
+int umc_init(void);
+void enable_dpll_ssc(void);
+
+void spl_board_init(void)
+{
+ bcu_init();
+
+ sbc_init();
+
+ sg_init();
+
+ uniphier_board_reset();
+
+ pll_init();
+
+ uniphier_board_init();
+
+ led_write(L, 0, , );
+
+ memconf_init();
+
+ led_write(L, 1, , );
+
+ early_clkrst_init();
+
+ led_write(L, 2, , );
+
+ {
+ int res;
+
+ res = umc_init();
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+ led_write(L, 3, , );
+
+ enable_dpll_ssc();
+
+ led_write(L, 4, , );
+}
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/board.h>
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+
+#define PFC_MICRO_SUPPORT_CARD_RESET \
+ ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
+#define PFC_MICRO_SUPPORT_CARD_REVISION \
+ ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
+/*
+ * 0: reset deassert, 1: reset
+ *
+ * bit[0]: LAN, I2C, LED
+ * bit[1]: UART
+ */
+void support_card_reset_deassert(void)
+{
+ writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
+}
+
+void support_card_reset(void)
+{
+ writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
+}
+
+static int support_card_show_revision(void)
+{
+ u32 revision;
+
+ revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
+ printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+
+#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \
+ ((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
+#define DCC_MICRO_SUPPORT_CARD_RESET_UART \
+ ((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
+#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \
+ ((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
+#define DCC_MICRO_SUPPORT_CARD_REVISION \
+ ((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
+
+void support_card_reset_deassert(void)
+{
+ writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
+ writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
+ writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
+}
+
+void support_card_reset(void)
+{
+ writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
+ writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
+ writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
+}
+
+static int support_card_show_revision(void)
+{
+ u32 revision;
+
+ revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
+
+ if (revision >= 0x67) {
+ printf("(DCC CPLD version 3.%d.%d)\n",
+ revision >> 4, revision & 0xf);
+ return 0;
+ } else {
+ printf("(DCC CPLD unknown version)\n");
+ return -1;
+ }
+}
+#endif
+
+int check_support_card(void)
+{
+ printf("SC: Micro Support Card ");
+ return support_card_show_revision();
+}
+
+void support_card_init(void)
+{
+ /*
+ * After power on, we need to keep the LAN controller in reset state
+ * for a while. (200 usec)
+ * Fortunatelly, enough wait time is already inserted in pll_init()
+ * function. So we do not have to wait here.
+ */
+ support_card_reset_deassert();
+}
+
+#if defined(CONFIG_SMC911X)
+#include <netdev.h>
+
+int board_eth_init(bd_t *bis)
+{
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+
+#include <mtd/cfi_flash.h>
+#include <mach/sbc-regs.h>
+
+struct memory_bank {
+ phys_addr_t base;
+ unsigned long size;
+};
+
+static int mem_is_flash(const struct memory_bank *mem)
+{
+ const int loop = 128;
+ u32 *scratch_addr;
+ u32 saved_value;
+ int ret = 1;
+ int i;
+
+ /* just in case, use the tail of the memory bank */
+ scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
+ sizeof(u32) * loop, MAP_NOCACHE);
+
+ for (i = 0; i < loop; i++, scratch_addr++) {
+ saved_value = readl(scratch_addr);
+ writel(~saved_value, scratch_addr);
+ if (readl(scratch_addr) != saved_value) {
+ /* We assume no memory or SRAM here. */
+ writel(saved_value, scratch_addr);
+ ret = 0;
+ break;
+ }
+ }
+
+ unmap_physmem(scratch_addr, MAP_NOCACHE);
+
+ return ret;
+}
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+ /* {address, size} */
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+ {0x02000000, 0x01f00000},
+};
+
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+ {0x00000000, 0x01f00000},
+};
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+ {0x04000000, 0x02000000},
+};
+
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+ {0x00000000, 0x02000000},
+ {0x04000000, 0x02000000},
+};
+#endif
+
+static const struct memory_bank
+*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
+
+phys_addr_t cfi_flash_bank_addr(int i)
+{
+ return flash_banks_list[i]->base;
+}
+
+unsigned long cfi_flash_bank_size(int i)
+{
+ return flash_banks_list[i]->size;
+}
+
+static void detect_num_flash_banks(void)
+{
+ const struct memory_bank *memory_bank, *end;
+
+ cfi_flash_num_flash_banks = 0;
+
+ if (boot_is_swapped()) {
+ memory_bank = memory_banks_boot_swap_on;
+ end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
+ } else {
+ memory_bank = memory_banks_boot_swap_off;
+ end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
+ }
+
+ for (; memory_bank < end; memory_bank++) {
+ if (cfi_flash_num_flash_banks >=
+ CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
+ break;
+
+ if (mem_is_flash(memory_bank)) {
+ flash_banks_list[cfi_flash_num_flash_banks] =
+ memory_bank;
+
+ debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
+ memory_bank->base, memory_bank->size);
+ cfi_flash_num_flash_banks++;
+ }
+ }
+
+ debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
+}
+#else /* ONFIG_SYS_NO_FLASH */
+void detect_num_flash_banks(void)
+{
+};
+#endif /* ONFIG_SYS_NO_FLASH */
+
+void support_card_late_init(void)
+{
+ detect_num_flash_banks();
+}
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/arm-mpcore.h>
+
+#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
+#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
+
+static void *get_global_timer_base(void)
+{
+ void *val;
+
+ asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory");
+
+ return val + GLOBAL_TIMER_OFFSET;
+}
+
+unsigned long timer_read_counter(void)
+{
+ /*
+ * ARM 64bit Global Timer is too much for our purpose.
+ * We use only lower 32 bit of the timer counter.
+ */
+ return readl(get_global_timer_base() + GTIMER_CNT_L);
+}
+
+int timer_init(void)
+{
+ /* enable timer */
+ writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL);
+
+ return 0;
+}
default "sh3" if CPU_SH3
default "sh4" if CPU_SH4
+config USE_PRIVATE_LIBGCC
+ default y
+
source "board/alphaproject/ap_sh4a_4a/Kconfig"
source "board/espt/Kconfig"
source "board/mpr2/Kconfig"
endif
obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashiftrt.o ashiftlt.o lshiftrt.o \
- ashldi3.o ashrsi3.o lshrdi3.o movmem.o
+udivsi3-y := udivsi3_i4i-Os.o
+
+ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y)
+udivsi3-$(CONFIG_CPU_SH3) := udivsi3_i4i.o
+udivsi3-$(CONFIG_CPU_SH4) := udivsi3_i4i.o
+endif
+udivsi3-y += udivsi3.o
+
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += movmem.o ashldi3.o ashrdi3.o lshrdi3.o \
+ ashlsi3.o ashrsi3.o ashiftrt.o lshrsi3.o \
+ udiv_qrnnd.o $(udivsi3-y)
+++ /dev/null
-/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
- 2004, 2005, 2006
- Free Software Foundation, Inc.
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-!! libgcc routines for the Renesas / SuperH SH CPUs.
-!! Contributed by Steve Chamberlain.
-!! sac@cygnus.com
-
-!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
-!! recoded in assembly by Toshiyasu Morita
-!! tm@netcom.com
-
-/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
- ELF local label prefixes by J"orn Rennecke
- amylaar@cygnus.com */
-
-!
-! GLOBAL(ashlsi3)
-!
-! Entry:
-!
-! r4: Value to shift
-! r5: Shifts
-!
-! Exit:
-!
-! r0: Result
-!
-! Destroys:
-!
-! (none)
-!
- .global __ashlsi3
- .align 2
-__ashlsi3:
- mov #31,r0
- and r0,r5
- mova __ashlsi3_table,r0
- mov.b @(r0,r5),r5
-#ifdef __sh1__
- add r5,r0
- jmp @r0
-#else
- braf r5
-#endif
- mov r4,r0
-
- .align 2
-__ashlsi3_table:
- .byte __ashlsi3_0-__ashlsi3_table
- .byte __ashlsi3_1-__ashlsi3_table
- .byte __ashlsi3_2-__ashlsi3_table
- .byte __ashlsi3_3-__ashlsi3_table
- .byte __ashlsi3_4-__ashlsi3_table
- .byte __ashlsi3_5-__ashlsi3_table
- .byte __ashlsi3_6-__ashlsi3_table
- .byte __ashlsi3_7-__ashlsi3_table
- .byte __ashlsi3_8-__ashlsi3_table
- .byte __ashlsi3_9-__ashlsi3_table
- .byte __ashlsi3_10-__ashlsi3_table
- .byte __ashlsi3_11-__ashlsi3_table
- .byte __ashlsi3_12-__ashlsi3_table
- .byte __ashlsi3_13-__ashlsi3_table
- .byte __ashlsi3_14-__ashlsi3_table
- .byte __ashlsi3_15-__ashlsi3_table
- .byte __ashlsi3_16-__ashlsi3_table
- .byte __ashlsi3_17-__ashlsi3_table
- .byte __ashlsi3_18-__ashlsi3_table
- .byte __ashlsi3_19-__ashlsi3_table
- .byte __ashlsi3_20-__ashlsi3_table
- .byte __ashlsi3_21-__ashlsi3_table
- .byte __ashlsi3_22-__ashlsi3_table
- .byte __ashlsi3_23-__ashlsi3_table
- .byte __ashlsi3_24-__ashlsi3_table
- .byte __ashlsi3_25-__ashlsi3_table
- .byte __ashlsi3_26-__ashlsi3_table
- .byte __ashlsi3_27-__ashlsi3_table
- .byte __ashlsi3_28-__ashlsi3_table
- .byte __ashlsi3_29-__ashlsi3_table
- .byte __ashlsi3_30-__ashlsi3_table
- .byte __ashlsi3_31-__ashlsi3_table
-
-__ashlsi3_6:
- shll2 r0
-__ashlsi3_4:
- shll2 r0
-__ashlsi3_2:
- rts
- shll2 r0
-
-__ashlsi3_7:
- shll2 r0
-__ashlsi3_5:
- shll2 r0
-__ashlsi3_3:
- shll2 r0
-__ashlsi3_1:
- rts
- shll r0
-
-__ashlsi3_14:
- shll2 r0
-__ashlsi3_12:
- shll2 r0
-__ashlsi3_10:
- shll2 r0
-__ashlsi3_8:
- rts
- shll8 r0
-
-__ashlsi3_15:
- shll2 r0
-__ashlsi3_13:
- shll2 r0
-__ashlsi3_11:
- shll2 r0
-__ashlsi3_9:
- shll8 r0
- rts
- shll r0
-
-__ashlsi3_22:
- shll2 r0
-__ashlsi3_20:
- shll2 r0
-__ashlsi3_18:
- shll2 r0
-__ashlsi3_16:
- rts
- shll16 r0
-
-__ashlsi3_23:
- shll2 r0
-__ashlsi3_21:
- shll2 r0
-__ashlsi3_19:
- shll2 r0
-__ashlsi3_17:
- shll16 r0
- rts
- shll r0
-
-__ashlsi3_30:
- shll2 r0
-__ashlsi3_28:
- shll2 r0
-__ashlsi3_26:
- shll2 r0
-__ashlsi3_24:
- shll16 r0
- rts
- shll8 r0
-
-__ashlsi3_31:
- shll2 r0
-__ashlsi3_29:
- shll2 r0
-__ashlsi3_27:
- shll2 r0
-__ashlsi3_25:
- shll16 r0
- shll8 r0
- rts
- shll r0
-
-__ashlsi3_0:
- rts
- nop
--- /dev/null
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+ 2004, 2005, 2006
+ Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+ ELF local label prefixes by J"orn Rennecke
+ amylaar@cygnus.com */
+
+!
+! GLOBAL(ashlsi3)
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+ .global __ashlsi3
+ .align 2
+__ashlsi3:
+ mov #31,r0
+ and r0,r5
+ mova __ashlsi3_table,r0
+ mov.b @(r0,r5),r5
+#ifdef __sh1__
+ add r5,r0
+ jmp @r0
+#else
+ braf r5
+#endif
+ mov r4,r0
+
+ .align 2
+__ashlsi3_table:
+ .byte __ashlsi3_0-__ashlsi3_table
+ .byte __ashlsi3_1-__ashlsi3_table
+ .byte __ashlsi3_2-__ashlsi3_table
+ .byte __ashlsi3_3-__ashlsi3_table
+ .byte __ashlsi3_4-__ashlsi3_table
+ .byte __ashlsi3_5-__ashlsi3_table
+ .byte __ashlsi3_6-__ashlsi3_table
+ .byte __ashlsi3_7-__ashlsi3_table
+ .byte __ashlsi3_8-__ashlsi3_table
+ .byte __ashlsi3_9-__ashlsi3_table
+ .byte __ashlsi3_10-__ashlsi3_table
+ .byte __ashlsi3_11-__ashlsi3_table
+ .byte __ashlsi3_12-__ashlsi3_table
+ .byte __ashlsi3_13-__ashlsi3_table
+ .byte __ashlsi3_14-__ashlsi3_table
+ .byte __ashlsi3_15-__ashlsi3_table
+ .byte __ashlsi3_16-__ashlsi3_table
+ .byte __ashlsi3_17-__ashlsi3_table
+ .byte __ashlsi3_18-__ashlsi3_table
+ .byte __ashlsi3_19-__ashlsi3_table
+ .byte __ashlsi3_20-__ashlsi3_table
+ .byte __ashlsi3_21-__ashlsi3_table
+ .byte __ashlsi3_22-__ashlsi3_table
+ .byte __ashlsi3_23-__ashlsi3_table
+ .byte __ashlsi3_24-__ashlsi3_table
+ .byte __ashlsi3_25-__ashlsi3_table
+ .byte __ashlsi3_26-__ashlsi3_table
+ .byte __ashlsi3_27-__ashlsi3_table
+ .byte __ashlsi3_28-__ashlsi3_table
+ .byte __ashlsi3_29-__ashlsi3_table
+ .byte __ashlsi3_30-__ashlsi3_table
+ .byte __ashlsi3_31-__ashlsi3_table
+
+__ashlsi3_6:
+ shll2 r0
+__ashlsi3_4:
+ shll2 r0
+__ashlsi3_2:
+ rts
+ shll2 r0
+
+__ashlsi3_7:
+ shll2 r0
+__ashlsi3_5:
+ shll2 r0
+__ashlsi3_3:
+ shll2 r0
+__ashlsi3_1:
+ rts
+ shll r0
+
+__ashlsi3_14:
+ shll2 r0
+__ashlsi3_12:
+ shll2 r0
+__ashlsi3_10:
+ shll2 r0
+__ashlsi3_8:
+ rts
+ shll8 r0
+
+__ashlsi3_15:
+ shll2 r0
+__ashlsi3_13:
+ shll2 r0
+__ashlsi3_11:
+ shll2 r0
+__ashlsi3_9:
+ shll8 r0
+ rts
+ shll r0
+
+__ashlsi3_22:
+ shll2 r0
+__ashlsi3_20:
+ shll2 r0
+__ashlsi3_18:
+ shll2 r0
+__ashlsi3_16:
+ rts
+ shll16 r0
+
+__ashlsi3_23:
+ shll2 r0
+__ashlsi3_21:
+ shll2 r0
+__ashlsi3_19:
+ shll2 r0
+__ashlsi3_17:
+ shll16 r0
+ rts
+ shll r0
+
+__ashlsi3_30:
+ shll2 r0
+__ashlsi3_28:
+ shll2 r0
+__ashlsi3_26:
+ shll2 r0
+__ashlsi3_24:
+ shll16 r0
+ rts
+ shll8 r0
+
+__ashlsi3_31:
+ shll2 r0
+__ashlsi3_29:
+ shll2 r0
+__ashlsi3_27:
+ shll2 r0
+__ashlsi3_25:
+ shll16 r0
+ shll8 r0
+ rts
+ shll r0
+
+__ashlsi3_0:
+ rts
+ nop
--- /dev/null
+#include "libgcc.h"
+
+long long __ashrdi3(long long u, word_type b)
+{
+ DWunion uu, w;
+ word_type bm;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+ bm = 32 - b;
+
+ if (bm <= 0) {
+ /* w.s.high = 1..1 or 0..0 */
+ w.s.high =
+ uu.s.high >> 31;
+ w.s.low = uu.s.high >> -bm;
+ } else {
+ const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+ w.s.high = uu.s.high >> b;
+ w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
+++ /dev/null
-/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
- 2004, 2005, 2006
- Free Software Foundation, Inc.
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-!! libgcc routines for the Renesas / SuperH SH CPUs.
-!! Contributed by Steve Chamberlain.
-!! sac@cygnus.com
-
-!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
-!! recoded in assembly by Toshiyasu Morita
-!! tm@netcom.com
-
-/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
- ELF local label prefixes by J"orn Rennecke
- amylaar@cygnus.com */
-
-!
-! __lshrsi3)
-!
-! Entry:
-!
-! r4: Value to shift
-! r5: Shifts
-!
-! Exit:
-!
-! r0: Result
-!
-! Destroys:
-!
-! (none)
-!
- .global __lshrsi3
- .align 2
-__lshrsi3:
- mov #31,r0
- and r0,r5
- mova __lshrsi3_table,r0
- mov.b @(r0,r5),r5
-#ifdef __sh1__
- add r5,r0
- jmp @r0
-#else
- braf r5
-#endif
- mov r4,r0
-
- .align 2
-__lshrsi3_table:
- .byte __lshrsi3_0-__lshrsi3_table
- .byte __lshrsi3_1-__lshrsi3_table
- .byte __lshrsi3_2-__lshrsi3_table
- .byte __lshrsi3_3-__lshrsi3_table
- .byte __lshrsi3_4-__lshrsi3_table
- .byte __lshrsi3_5-__lshrsi3_table
- .byte __lshrsi3_6-__lshrsi3_table
- .byte __lshrsi3_7-__lshrsi3_table
- .byte __lshrsi3_8-__lshrsi3_table
- .byte __lshrsi3_9-__lshrsi3_table
- .byte __lshrsi3_10-__lshrsi3_table
- .byte __lshrsi3_11-__lshrsi3_table
- .byte __lshrsi3_12-__lshrsi3_table
- .byte __lshrsi3_13-__lshrsi3_table
- .byte __lshrsi3_14-__lshrsi3_table
- .byte __lshrsi3_15-__lshrsi3_table
- .byte __lshrsi3_16-__lshrsi3_table
- .byte __lshrsi3_17-__lshrsi3_table
- .byte __lshrsi3_18-__lshrsi3_table
- .byte __lshrsi3_19-__lshrsi3_table
- .byte __lshrsi3_20-__lshrsi3_table
- .byte __lshrsi3_21-__lshrsi3_table
- .byte __lshrsi3_22-__lshrsi3_table
- .byte __lshrsi3_23-__lshrsi3_table
- .byte __lshrsi3_24-__lshrsi3_table
- .byte __lshrsi3_25-__lshrsi3_table
- .byte __lshrsi3_26-__lshrsi3_table
- .byte __lshrsi3_27-__lshrsi3_table
- .byte __lshrsi3_28-__lshrsi3_table
- .byte __lshrsi3_29-__lshrsi3_table
- .byte __lshrsi3_30-__lshrsi3_table
- .byte __lshrsi3_31-__lshrsi3_table
-
-__lshrsi3_6:
- shlr2 r0
-__lshrsi3_4:
- shlr2 r0
-__lshrsi3_2:
- rts
- shlr2 r0
-
-__lshrsi3_7:
- shlr2 r0
-__lshrsi3_5:
- shlr2 r0
-__lshrsi3_3:
- shlr2 r0
-__lshrsi3_1:
- rts
- shlr r0
-
-__lshrsi3_14:
- shlr2 r0
-__lshrsi3_12:
- shlr2 r0
-__lshrsi3_10:
- shlr2 r0
-__lshrsi3_8:
- rts
- shlr8 r0
-
-__lshrsi3_15:
- shlr2 r0
-__lshrsi3_13:
- shlr2 r0
-__lshrsi3_11:
- shlr2 r0
-__lshrsi3_9:
- shlr8 r0
- rts
- shlr r0
-
-__lshrsi3_22:
- shlr2 r0
-__lshrsi3_20:
- shlr2 r0
-__lshrsi3_18:
- shlr2 r0
-__lshrsi3_16:
- rts
- shlr16 r0
-
-__lshrsi3_23:
- shlr2 r0
-__lshrsi3_21:
- shlr2 r0
-__lshrsi3_19:
- shlr2 r0
-__lshrsi3_17:
- shlr16 r0
- rts
- shlr r0
-
-__lshrsi3_30:
- shlr2 r0
-__lshrsi3_28:
- shlr2 r0
-__lshrsi3_26:
- shlr2 r0
-__lshrsi3_24:
- shlr16 r0
- rts
- shlr8 r0
-
-__lshrsi3_31:
- shlr2 r0
-__lshrsi3_29:
- shlr2 r0
-__lshrsi3_27:
- shlr2 r0
-__lshrsi3_25:
- shlr16 r0
- shlr8 r0
- rts
- shlr r0
-
-__lshrsi3_0:
- rts
- nop
--- /dev/null
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+ 2004, 2005, 2006
+ Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+ ELF local label prefixes by J"orn Rennecke
+ amylaar@cygnus.com */
+
+!
+! __lshrsi3)
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+ .global __lshrsi3
+ .align 2
+__lshrsi3:
+ mov #31,r0
+ and r0,r5
+ mova __lshrsi3_table,r0
+ mov.b @(r0,r5),r5
+#ifdef __sh1__
+ add r5,r0
+ jmp @r0
+#else
+ braf r5
+#endif
+ mov r4,r0
+
+ .align 2
+__lshrsi3_table:
+ .byte __lshrsi3_0-__lshrsi3_table
+ .byte __lshrsi3_1-__lshrsi3_table
+ .byte __lshrsi3_2-__lshrsi3_table
+ .byte __lshrsi3_3-__lshrsi3_table
+ .byte __lshrsi3_4-__lshrsi3_table
+ .byte __lshrsi3_5-__lshrsi3_table
+ .byte __lshrsi3_6-__lshrsi3_table
+ .byte __lshrsi3_7-__lshrsi3_table
+ .byte __lshrsi3_8-__lshrsi3_table
+ .byte __lshrsi3_9-__lshrsi3_table
+ .byte __lshrsi3_10-__lshrsi3_table
+ .byte __lshrsi3_11-__lshrsi3_table
+ .byte __lshrsi3_12-__lshrsi3_table
+ .byte __lshrsi3_13-__lshrsi3_table
+ .byte __lshrsi3_14-__lshrsi3_table
+ .byte __lshrsi3_15-__lshrsi3_table
+ .byte __lshrsi3_16-__lshrsi3_table
+ .byte __lshrsi3_17-__lshrsi3_table
+ .byte __lshrsi3_18-__lshrsi3_table
+ .byte __lshrsi3_19-__lshrsi3_table
+ .byte __lshrsi3_20-__lshrsi3_table
+ .byte __lshrsi3_21-__lshrsi3_table
+ .byte __lshrsi3_22-__lshrsi3_table
+ .byte __lshrsi3_23-__lshrsi3_table
+ .byte __lshrsi3_24-__lshrsi3_table
+ .byte __lshrsi3_25-__lshrsi3_table
+ .byte __lshrsi3_26-__lshrsi3_table
+ .byte __lshrsi3_27-__lshrsi3_table
+ .byte __lshrsi3_28-__lshrsi3_table
+ .byte __lshrsi3_29-__lshrsi3_table
+ .byte __lshrsi3_30-__lshrsi3_table
+ .byte __lshrsi3_31-__lshrsi3_table
+
+__lshrsi3_6:
+ shlr2 r0
+__lshrsi3_4:
+ shlr2 r0
+__lshrsi3_2:
+ rts
+ shlr2 r0
+
+__lshrsi3_7:
+ shlr2 r0
+__lshrsi3_5:
+ shlr2 r0
+__lshrsi3_3:
+ shlr2 r0
+__lshrsi3_1:
+ rts
+ shlr r0
+
+__lshrsi3_14:
+ shlr2 r0
+__lshrsi3_12:
+ shlr2 r0
+__lshrsi3_10:
+ shlr2 r0
+__lshrsi3_8:
+ rts
+ shlr8 r0
+
+__lshrsi3_15:
+ shlr2 r0
+__lshrsi3_13:
+ shlr2 r0
+__lshrsi3_11:
+ shlr2 r0
+__lshrsi3_9:
+ shlr8 r0
+ rts
+ shlr r0
+
+__lshrsi3_22:
+ shlr2 r0
+__lshrsi3_20:
+ shlr2 r0
+__lshrsi3_18:
+ shlr2 r0
+__lshrsi3_16:
+ rts
+ shlr16 r0
+
+__lshrsi3_23:
+ shlr2 r0
+__lshrsi3_21:
+ shlr2 r0
+__lshrsi3_19:
+ shlr2 r0
+__lshrsi3_17:
+ shlr16 r0
+ rts
+ shlr r0
+
+__lshrsi3_30:
+ shlr2 r0
+__lshrsi3_28:
+ shlr2 r0
+__lshrsi3_26:
+ shlr2 r0
+__lshrsi3_24:
+ shlr16 r0
+ rts
+ shlr8 r0
+
+__lshrsi3_31:
+ shlr2 r0
+__lshrsi3_29:
+ shlr2 r0
+__lshrsi3_27:
+ shlr2 r0
+__lshrsi3_25:
+ shlr16 r0
+ shlr8 r0
+ rts
+ shlr r0
+
+__lshrsi3_0:
+ rts
+ nop
--- /dev/null
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+ 2004, 2005, 2006
+ Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+ ELF local label prefixes by J"orn Rennecke
+ amylaar@cygnus.com */
+
+ /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */
+ /* n1 < d, but n1 might be larger than d1. */
+ .global __udiv_qrnnd_16
+ .balign 8
+__udiv_qrnnd_16:
+ div0u
+ cmp/hi r6,r0
+ bt .Lots
+ .rept 16
+ div1 r6,r0
+ .endr
+ extu.w r0,r1
+ bt 0f
+ add r6,r0
+0: rotcl r1
+ mulu.w r1,r5
+ xtrct r4,r0
+ swap.w r0,r0
+ sts macl,r2
+ cmp/hs r2,r0
+ sub r2,r0
+ bt 0f
+ addc r5,r0
+ add #-1,r1
+ bt 0f
+1: add #-1,r1
+ rts
+ add r5,r0
+ .balign 8
+.Lots:
+ sub r5,r0
+ swap.w r4,r1
+ xtrct r0,r1
+ clrt
+ mov r1,r0
+ addc r5,r0
+ mov #-1,r1
+ bf/s 1b
+ shlr16 r1
+0: rts
+ nop
--- /dev/null
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+ 2004, 2005
+ Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+ .balign 4
+ .global __udivsi3
+ .type __udivsi3, @function
+div8:
+ div1 r5,r4
+div7:
+ div1 r5,r4; div1 r5,r4; div1 r5,r4
+ div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
+
+divx4:
+ div1 r5,r4; rotcl r0
+ div1 r5,r4; rotcl r0
+ div1 r5,r4; rotcl r0
+ rts; div1 r5,r4
+
+__udivsi3:
+ sts.l pr,@-r15
+ extu.w r5,r0
+ cmp/eq r5,r0
+ bf/s large_divisor
+ div0u
+ swap.w r4,r0
+ shlr16 r4
+ bsr div8
+ shll16 r5
+ bsr div7
+ div1 r5,r4
+ xtrct r4,r0
+ xtrct r0,r4
+ bsr div8
+ swap.w r4,r4
+ bsr div7
+ div1 r5,r4
+ lds.l @r15+,pr
+ xtrct r4,r0
+ swap.w r0,r0
+ rotcl r0
+ rts
+ shlr16 r5
+
+large_divisor:
+ mov #0,r0
+ xtrct r4,r0
+ xtrct r0,r4
+ bsr divx4
+ rotcl r0
+ bsr divx4
+ rotcl r0
+ bsr divx4
+ rotcl r0
+ bsr divx4
+ rotcl r0
+ lds.l @r15+,pr
+ rts
+ rotcl r0
--- /dev/null
+/* Copyright (C) 2006 Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Moderately Space-optimized libgcc routines for the Renesas SH /
+ STMicroelectronics ST40 CPUs.
+ Contributed by J"orn Rennecke joern.rennecke@st.com. */
+
+/* Size: 186 bytes jointly for udivsi3_i4i and sdivsi3_i4i
+ sh4-200 run times:
+ udiv small divisor: 55 cycles
+ udiv large divisor: 52 cycles
+ sdiv small divisor, positive result: 59 cycles
+ sdiv large divisor, positive result: 56 cycles
+ sdiv small divisor, negative result: 65 cycles (*)
+ sdiv large divisor, negative result: 62 cycles (*)
+ (*): r2 is restored in the rts delay slot and has a lingering latency
+ of two more cycles. */
+ .balign 4
+ .global __udivsi3_i4i
+ .global __udivsi3_i4
+ .set __udivsi3_i4, __udivsi3_i4i
+ .type __udivsi3_i4i, @function
+ .type __sdivsi3_i4i, @function
+__udivsi3_i4i:
+ sts pr,r1
+ mov.l r4,@-r15
+ extu.w r5,r0
+ cmp/eq r5,r0
+ swap.w r4,r0
+ shlr16 r4
+ bf/s large_divisor
+ div0u
+ mov.l r5,@-r15
+ shll16 r5
+sdiv_small_divisor:
+ div1 r5,r4
+ bsr div6
+ div1 r5,r4
+ div1 r5,r4
+ bsr div6
+ div1 r5,r4
+ xtrct r4,r0
+ xtrct r0,r4
+ bsr div7
+ swap.w r4,r4
+ div1 r5,r4
+ bsr div7
+ div1 r5,r4
+ xtrct r4,r0
+ mov.l @r15+,r5
+ swap.w r0,r0
+ mov.l @r15+,r4
+ jmp @r1
+ rotcl r0
+div7:
+ div1 r5,r4
+div6:
+ div1 r5,r4; div1 r5,r4; div1 r5,r4
+ div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
+
+divx3:
+ rotcl r0
+ div1 r5,r4
+ rotcl r0
+ div1 r5,r4
+ rotcl r0
+ rts
+ div1 r5,r4
+
+large_divisor:
+ mov.l r5,@-r15
+sdiv_large_divisor:
+ xor r4,r0
+ .rept 4
+ rotcl r0
+ bsr divx3
+ div1 r5,r4
+ .endr
+ mov.l @r15+,r5
+ mov.l @r15+,r4
+ jmp @r1
+ rotcl r0
+
+ .global __sdivsi3_i4i
+ .global __sdivsi3_i4
+ .global __sdivsi3
+ .set __sdivsi3_i4, __sdivsi3_i4i
+ .set __sdivsi3, __sdivsi3_i4i
+__sdivsi3_i4i:
+ mov.l r4,@-r15
+ cmp/pz r5
+ mov.l r5,@-r15
+ bt/s pos_divisor
+ cmp/pz r4
+ neg r5,r5
+ extu.w r5,r0
+ bt/s neg_result
+ cmp/eq r5,r0
+ neg r4,r4
+pos_result:
+ swap.w r4,r0
+ bra sdiv_check_divisor
+ sts pr,r1
+pos_divisor:
+ extu.w r5,r0
+ bt/s pos_result
+ cmp/eq r5,r0
+ neg r4,r4
+neg_result:
+ mova negate_result,r0
+ ;
+ mov r0,r1
+ swap.w r4,r0
+ lds r2,macl
+ sts pr,r2
+sdiv_check_divisor:
+ shlr16 r4
+ bf/s sdiv_large_divisor
+ div0u
+ bra sdiv_small_divisor
+ shll16 r5
+ .balign 4
+negate_result:
+ neg r0,r0
+ jmp @r2
+ sts macl,r2
--- /dev/null
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+ 2004, 2005, 2006
+ Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+ ELF local label prefixes by J"orn Rennecke
+ amylaar@cygnus.com */
+
+/* This code used shld, thus is not suitable for SH1 / SH2. */
+
+/* Signed / unsigned division without use of FPU, optimized for SH4.
+ Uses a lookup table for divisors in the range -128 .. +128, and
+ div1 with case distinction for larger divisors in three more ranges.
+ The code is lumped together with the table to allow the use of mova. */
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define L_LSB 0
+#define L_LSWMSB 1
+#define L_MSWLSB 2
+#else
+#define L_LSB 3
+#define L_LSWMSB 2
+#define L_MSWLSB 1
+#endif
+
+ .balign 4
+ .global __udivsi3_i4i
+ .global __udivsi3_i4
+ .set __udivsi3_i4, __udivsi3_i4i
+ .type __udivsi3_i4i, @function
+__udivsi3_i4i:
+ mov.w c128_w, r1
+ div0u
+ mov r4,r0
+ shlr8 r0
+ cmp/hi r1,r5
+ extu.w r5,r1
+ bf udiv_le128
+ cmp/eq r5,r1
+ bf udiv_ge64k
+ shlr r0
+ mov r5,r1
+ shll16 r5
+ mov.l r4,@-r15
+ div1 r5,r0
+ mov.l r1,@-r15
+ div1 r5,r0
+ div1 r5,r0
+ bra udiv_25
+ div1 r5,r0
+
+div_le128:
+ mova div_table_ix,r0
+ bra div_le128_2
+ mov.b @(r0,r5),r1
+udiv_le128:
+ mov.l r4,@-r15
+ mova div_table_ix,r0
+ mov.b @(r0,r5),r1
+ mov.l r5,@-r15
+div_le128_2:
+ mova div_table_inv,r0
+ mov.l @(r0,r1),r1
+ mov r5,r0
+ tst #0xfe,r0
+ mova div_table_clz,r0
+ dmulu.l r1,r4
+ mov.b @(r0,r5),r1
+ bt/s div_by_1
+ mov r4,r0
+ mov.l @r15+,r5
+ sts mach,r0
+ /* clrt */
+ addc r4,r0
+ mov.l @r15+,r4
+ rotcr r0
+ rts
+ shld r1,r0
+
+div_by_1_neg:
+ neg r4,r0
+div_by_1:
+ mov.l @r15+,r5
+ rts
+ mov.l @r15+,r4
+
+div_ge64k:
+ bt/s div_r8
+ div0u
+ shll8 r5
+ bra div_ge64k_2
+ div1 r5,r0
+udiv_ge64k:
+ cmp/hi r0,r5
+ mov r5,r1
+ bt udiv_r8
+ shll8 r5
+ mov.l r4,@-r15
+ div1 r5,r0
+ mov.l r1,@-r15
+div_ge64k_2:
+ div1 r5,r0
+ mov.l zero_l,r1
+ .rept 4
+ div1 r5,r0
+ .endr
+ mov.l r1,@-r15
+ div1 r5,r0
+ mov.w m256_w,r1
+ div1 r5,r0
+ mov.b r0,@(L_LSWMSB,r15)
+ xor r4,r0
+ and r1,r0
+ bra div_ge64k_end
+ xor r4,r0
+div_r8:
+ shll16 r4
+ bra div_r8_2
+ shll8 r4
+udiv_r8:
+ mov.l r4,@-r15
+ shll16 r4
+ clrt
+ shll8 r4
+ mov.l r5,@-r15
+div_r8_2:
+ rotcl r4
+ mov r0,r1
+ div1 r5,r1
+ mov r4,r0
+ rotcl r0
+ mov r5,r4
+ div1 r5,r1
+ .rept 5
+ rotcl r0; div1 r5,r1
+ .endr
+ rotcl r0
+ mov.l @r15+,r5
+ div1 r4,r1
+ mov.l @r15+,r4
+ rts
+ rotcl r0
+
+ .global __sdivsi3_i4i
+ .global __sdivsi3_i4
+ .global __sdivsi3
+ .set __sdivsi3_i4, __sdivsi3_i4i
+ .set __sdivsi3, __sdivsi3_i4i
+ .type __sdivsi3_i4i, @function
+ /* This is link-compatible with a __sdivsi3 call,
+ but we effectively clobber only r1. */
+__sdivsi3_i4i:
+ mov.l r4,@-r15
+ cmp/pz r5
+ mov.w c128_w, r1
+ bt/s pos_divisor
+ cmp/pz r4
+ mov.l r5,@-r15
+ neg r5,r5
+ bt/s neg_result
+ cmp/hi r1,r5
+ neg r4,r4
+pos_result:
+ extu.w r5,r0
+ bf div_le128
+ cmp/eq r5,r0
+ mov r4,r0
+ shlr8 r0
+ bf/s div_ge64k
+ cmp/hi r0,r5
+ div0u
+ shll16 r5
+ div1 r5,r0
+ div1 r5,r0
+ div1 r5,r0
+udiv_25:
+ mov.l zero_l,r1
+ div1 r5,r0
+ div1 r5,r0
+ mov.l r1,@-r15
+ .rept 3
+ div1 r5,r0
+ .endr
+ mov.b r0,@(L_MSWLSB,r15)
+ xtrct r4,r0
+ swap.w r0,r0
+ .rept 8
+ div1 r5,r0
+ .endr
+ mov.b r0,@(L_LSWMSB,r15)
+div_ge64k_end:
+ .rept 8
+ div1 r5,r0
+ .endr
+ mov.l @r15+,r4 ! zero-extension and swap using LS unit.
+ extu.b r0,r0
+ mov.l @r15+,r5
+ or r4,r0
+ mov.l @r15+,r4
+ rts
+ rotcl r0
+
+div_le128_neg:
+ tst #0xfe,r0
+ mova div_table_ix,r0
+ mov.b @(r0,r5),r1
+ mova div_table_inv,r0
+ bt/s div_by_1_neg
+ mov.l @(r0,r1),r1
+ mova div_table_clz,r0
+ dmulu.l r1,r4
+ mov.b @(r0,r5),r1
+ mov.l @r15+,r5
+ sts mach,r0
+ /* clrt */
+ addc r4,r0
+ mov.l @r15+,r4
+ rotcr r0
+ shld r1,r0
+ rts
+ neg r0,r0
+
+pos_divisor:
+ mov.l r5,@-r15
+ bt/s pos_result
+ cmp/hi r1,r5
+ neg r4,r4
+neg_result:
+ extu.w r5,r0
+ bf div_le128_neg
+ cmp/eq r5,r0
+ mov r4,r0
+ shlr8 r0
+ bf/s div_ge64k_neg
+ cmp/hi r0,r5
+ div0u
+ mov.l zero_l,r1
+ shll16 r5
+ div1 r5,r0
+ mov.l r1,@-r15
+ .rept 7
+ div1 r5,r0
+ .endr
+ mov.b r0,@(L_MSWLSB,r15)
+ xtrct r4,r0
+ swap.w r0,r0
+ .rept 8
+ div1 r5,r0
+ .endr
+ mov.b r0,@(L_LSWMSB,r15)
+div_ge64k_neg_end:
+ .rept 8
+ div1 r5,r0
+ .endr
+ mov.l @r15+,r4 ! zero-extension and swap using LS unit.
+ extu.b r0,r1
+ mov.l @r15+,r5
+ or r4,r1
+div_r8_neg_end:
+ mov.l @r15+,r4
+ rotcl r1
+ rts
+ neg r1,r0
+
+div_ge64k_neg:
+ bt/s div_r8_neg
+ div0u
+ shll8 r5
+ mov.l zero_l,r1
+ .rept 6
+ div1 r5,r0
+ .endr
+ mov.l r1,@-r15
+ div1 r5,r0
+ mov.w m256_w,r1
+ div1 r5,r0
+ mov.b r0,@(L_LSWMSB,r15)
+ xor r4,r0
+ and r1,r0
+ bra div_ge64k_neg_end
+ xor r4,r0
+
+c128_w:
+ .word 128
+
+div_r8_neg:
+ clrt
+ shll16 r4
+ mov r4,r1
+ shll8 r1
+ mov r5,r4
+ .rept 7
+ rotcl r1; div1 r5,r0
+ .endr
+ mov.l @r15+,r5
+ rotcl r1
+ bra div_r8_neg_end
+ div1 r4,r0
+
+m256_w:
+ .word 0xff00
+/* This table has been generated by divtab-sh4.c. */
+ .balign 4
+div_table_clz:
+ .byte 0
+ .byte 1
+ .byte 0
+ .byte -1
+ .byte -1
+ .byte -2
+ .byte -2
+ .byte -2
+ .byte -2
+ .byte -3
+ .byte -3
+ .byte -3
+ .byte -3
+ .byte -3
+ .byte -3
+ .byte -3
+ .byte -3
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -4
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -5
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+ .byte -6
+/* Lookup table translating positive divisor to index into table of
+ normalized inverse. N.B. the '0' entry is also the last entry of the
+ previous table, and causes an unaligned access for division by zero. */
+div_table_ix:
+ .byte -6
+ .byte -128
+ .byte -128
+ .byte 0
+ .byte -128
+ .byte -64
+ .byte 0
+ .byte 64
+ .byte -128
+ .byte -96
+ .byte -64
+ .byte -32
+ .byte 0
+ .byte 32
+ .byte 64
+ .byte 96
+ .byte -128
+ .byte -112
+ .byte -96
+ .byte -80
+ .byte -64
+ .byte -48
+ .byte -32
+ .byte -16
+ .byte 0
+ .byte 16
+ .byte 32
+ .byte 48
+ .byte 64
+ .byte 80
+ .byte 96
+ .byte 112
+ .byte -128
+ .byte -120
+ .byte -112
+ .byte -104
+ .byte -96
+ .byte -88
+ .byte -80
+ .byte -72
+ .byte -64
+ .byte -56
+ .byte -48
+ .byte -40
+ .byte -32
+ .byte -24
+ .byte -16
+ .byte -8
+ .byte 0
+ .byte 8
+ .byte 16
+ .byte 24
+ .byte 32
+ .byte 40
+ .byte 48
+ .byte 56
+ .byte 64
+ .byte 72
+ .byte 80
+ .byte 88
+ .byte 96
+ .byte 104
+ .byte 112
+ .byte 120
+ .byte -128
+ .byte -124
+ .byte -120
+ .byte -116
+ .byte -112
+ .byte -108
+ .byte -104
+ .byte -100
+ .byte -96
+ .byte -92
+ .byte -88
+ .byte -84
+ .byte -80
+ .byte -76
+ .byte -72
+ .byte -68
+ .byte -64
+ .byte -60
+ .byte -56
+ .byte -52
+ .byte -48
+ .byte -44
+ .byte -40
+ .byte -36
+ .byte -32
+ .byte -28
+ .byte -24
+ .byte -20
+ .byte -16
+ .byte -12
+ .byte -8
+ .byte -4
+ .byte 0
+ .byte 4
+ .byte 8
+ .byte 12
+ .byte 16
+ .byte 20
+ .byte 24
+ .byte 28
+ .byte 32
+ .byte 36
+ .byte 40
+ .byte 44
+ .byte 48
+ .byte 52
+ .byte 56
+ .byte 60
+ .byte 64
+ .byte 68
+ .byte 72
+ .byte 76
+ .byte 80
+ .byte 84
+ .byte 88
+ .byte 92
+ .byte 96
+ .byte 100
+ .byte 104
+ .byte 108
+ .byte 112
+ .byte 116
+ .byte 120
+ .byte 124
+ .byte -128
+/* 1/64 .. 1/127, normalized. There is an implicit leading 1 in bit 32. */
+ .balign 4
+zero_l:
+ .long 0x0
+ .long 0xF81F81F9
+ .long 0xF07C1F08
+ .long 0xE9131AC0
+ .long 0xE1E1E1E2
+ .long 0xDAE6076C
+ .long 0xD41D41D5
+ .long 0xCD856891
+ .long 0xC71C71C8
+ .long 0xC0E07039
+ .long 0xBACF914D
+ .long 0xB4E81B4F
+ .long 0xAF286BCB
+ .long 0xA98EF607
+ .long 0xA41A41A5
+ .long 0x9EC8E952
+ .long 0x9999999A
+ .long 0x948B0FCE
+ .long 0x8F9C18FA
+ .long 0x8ACB90F7
+ .long 0x86186187
+ .long 0x81818182
+ .long 0x7D05F418
+ .long 0x78A4C818
+ .long 0x745D1746
+ .long 0x702E05C1
+ .long 0x6C16C16D
+ .long 0x68168169
+ .long 0x642C8591
+ .long 0x60581606
+ .long 0x5C9882BA
+ .long 0x58ED2309
+div_table_inv:
+ .long 0x55555556
+ .long 0x51D07EAF
+ .long 0x4E5E0A73
+ .long 0x4AFD6A06
+ .long 0x47AE147B
+ .long 0x446F8657
+ .long 0x41414142
+ .long 0x3E22CBCF
+ .long 0x3B13B13C
+ .long 0x38138139
+ .long 0x3521CFB3
+ .long 0x323E34A3
+ .long 0x2F684BDB
+ .long 0x2C9FB4D9
+ .long 0x29E4129F
+ .long 0x27350B89
+ .long 0x24924925
+ .long 0x21FB7813
+ .long 0x1F7047DD
+ .long 0x1CF06ADB
+ .long 0x1A7B9612
+ .long 0x18118119
+ .long 0x15B1E5F8
+ .long 0x135C8114
+ .long 0x11111112
+ .long 0xECF56BF
+ .long 0xC9714FC
+ .long 0xA6810A7
+ .long 0x8421085
+ .long 0x624DD30
+ .long 0x4104105
+ .long 0x2040811
+ /* maximum error: 0.987342 scaled: 0.921875*/
dcache_disable();
icache_disable();
- /* arch number of vpac270 */
+ /* arch number of balloon3 */
gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
/* adress of boot parameters */
#include <common.h>
#include <malloc.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#define ETHER_MSTP813 (1 << 13)
#define IIC1_MSTP323 (1 << 23)
#define MMC0_MSTP315 (1 << 15)
+#define SDHI0_MSTP314 (1 << 14)
+#define SDHI1_MSTP312 (1 << 12)
+
+#define SD1CKCR 0xE6150078
+#define SD1_97500KHZ 0x7
int board_early_init_f(void)
{
/* MMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
#endif
+
+#ifdef CONFIG_SH_SDHI
+ /* SDHI0, 1 */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD1 to the 97.5MHz as well.
+ */
+ writel(SD1_97500KHZ, SD1CKCR);
+#endif
return 0;
}
int board_mmc_init(bd_t *bis)
{
- int ret = 0;
+ int ret = -ENODEV;
#ifdef CONFIG_SH_MMCIF
gpio_request(GPIO_GP_4_31, NULL);
ret = mmcif_mmc_init();
#endif
+
+#ifdef CONFIG_SH_SDHI
+ gpio_request(GPIO_FN_SD0_DATA0, NULL);
+ gpio_request(GPIO_FN_SD0_DATA1, NULL);
+ gpio_request(GPIO_FN_SD0_DATA2, NULL);
+ gpio_request(GPIO_FN_SD0_DATA3, NULL);
+ gpio_request(GPIO_FN_SD0_CLK, NULL);
+ gpio_request(GPIO_FN_SD0_CMD, NULL);
+ gpio_request(GPIO_FN_SD0_CD, NULL);
+ gpio_request(GPIO_FN_SD1_DATA0, NULL);
+ gpio_request(GPIO_FN_SD1_DATA1, NULL);
+ gpio_request(GPIO_FN_SD1_DATA2, NULL);
+ gpio_request(GPIO_FN_SD1_DATA3, NULL);
+ gpio_request(GPIO_FN_SD1_CLK, NULL);
+ gpio_request(GPIO_FN_SD1_CMD, NULL);
+ gpio_request(GPIO_FN_SD1_CD, NULL);
+
+ /* SDHI 0 */
+ gpio_request(GPIO_GP_2_26, NULL);
+ gpio_request(GPIO_GP_2_29, NULL);
+ gpio_direction_output(GPIO_GP_2_26, 1);
+ gpio_direction_output(GPIO_GP_2_29, 1);
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+ SH_SDHI_QUIRK_16BIT_BUF);
+ if (ret)
+ return ret;
+
+ /* SDHI 1 */
+ gpio_request(GPIO_GP_4_26, NULL);
+ gpio_request(GPIO_GP_4_29, NULL);
+ gpio_direction_output(GPIO_GP_4_26, 1);
+ gpio_direction_output(GPIO_GP_4_29, 1);
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
+#endif
return ret;
}
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}
+
+static const struct sh_serial_platdata serial_platdata = {
+ .base = SCIF2_BASE,
+ .type = PORT_SCIF,
+ .clk = 14745600,
+ .clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(alt_serials) = {
+ .name = "serial_sh",
+ .platdata = &serial_platdata,
+};
#include <common.h>
#include <malloc.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#define SCIF0_MSTP721 (1 << 21)
#define ETHER_MSTP813 (1 << 13)
+#define SDHI0_MSTP314 (1 << 14)
+#define SDHI1_MSTP312 (1 << 12)
+#define SDHI2_MSTP311 (1 << 11)
+
+#define SD1CKCR 0xE6150078
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
int board_early_init_f(void)
{
/* TMU0 */
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+ /* SDHI */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
+ SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
+ writel(SD_97500KHZ, SD1CKCR);
+ writel(SD_97500KHZ, SD2CKCR);
+
return 0;
}
return ret;
}
+int board_mmc_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+
+#ifdef CONFIG_SH_SDHI
+ gpio_request(GPIO_FN_SD0_DATA0, NULL);
+ gpio_request(GPIO_FN_SD0_DATA1, NULL);
+ gpio_request(GPIO_FN_SD0_DATA2, NULL);
+ gpio_request(GPIO_FN_SD0_DATA3, NULL);
+ gpio_request(GPIO_FN_SD0_CLK, NULL);
+ gpio_request(GPIO_FN_SD0_CMD, NULL);
+ gpio_request(GPIO_FN_SD0_CD, NULL);
+ gpio_request(GPIO_FN_SD2_DATA0, NULL);
+ gpio_request(GPIO_FN_SD2_DATA1, NULL);
+ gpio_request(GPIO_FN_SD2_DATA2, NULL);
+ gpio_request(GPIO_FN_SD2_DATA3, NULL);
+ gpio_request(GPIO_FN_SD2_CLK, NULL);
+ gpio_request(GPIO_FN_SD2_CMD, NULL);
+ gpio_request(GPIO_FN_SD2_CD, NULL);
+
+ /* SDHI 0 */
+ gpio_request(GPIO_GP_7_17, NULL);
+ gpio_request(GPIO_GP_2_12, NULL);
+ gpio_direction_output(GPIO_GP_7_17, 1); /* power on */
+ gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+ SH_SDHI_QUIRK_16BIT_BUF);
+ if (ret)
+ return ret;
+
+ /* SDHI 1 */
+ gpio_request(GPIO_GP_7_18, NULL);
+ gpio_request(GPIO_GP_2_13, NULL);
+ gpio_direction_output(GPIO_GP_7_18, 1); /* power on */
+ gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
+ if (ret)
+ return ret;
+
+ /* SDHI 2 */
+ gpio_request(GPIO_GP_7_19, NULL);
+ gpio_request(GPIO_GP_2_26, NULL);
+ gpio_direction_output(GPIO_GP_7_19, 1); /* power on */
+ gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
+#endif
+ return ret;
+}
+
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}
+
+static const struct sh_serial_platdata serial_platdata = {
+ .base = SCIF0_BASE,
+ .type = PORT_SCIF,
+ .clk = 14745600,
+ .clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(gose_serials) = {
+ .name = "serial_sh",
+ .platdata = &serial_platdata,
+};
#include <common.h>
#include <malloc.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#define SCIF0_MSTP721 (1 << 21)
#define ETHER_MSTP813 (1 << 13)
+#define SDHI0_MSTP314 (1 << 14)
+#define SDHI1_MSTP312 (1 << 12)
+#define SDHI2_MSTP311 (1 << 11)
+
+#define SD1CKCR 0xE6150078
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
int board_early_init_f(void)
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+ /* SDHI */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
+ SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD1 and SD2 to the 97.5MHz as well.
+ */
+ writel(SD_97500KHZ, SD1CKCR);
+ writel(SD_97500KHZ, SD2CKCR);
+
return 0;
}
#endif
}
+int board_mmc_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+
+#ifdef CONFIG_SH_SDHI
+ gpio_request(GPIO_FN_SD0_DATA0, NULL);
+ gpio_request(GPIO_FN_SD0_DATA1, NULL);
+ gpio_request(GPIO_FN_SD0_DATA2, NULL);
+ gpio_request(GPIO_FN_SD0_DATA3, NULL);
+ gpio_request(GPIO_FN_SD0_CLK, NULL);
+ gpio_request(GPIO_FN_SD0_CMD, NULL);
+ gpio_request(GPIO_FN_SD0_CD, NULL);
+ gpio_request(GPIO_FN_SD2_DATA0, NULL);
+ gpio_request(GPIO_FN_SD2_DATA1, NULL);
+ gpio_request(GPIO_FN_SD2_DATA2, NULL);
+ gpio_request(GPIO_FN_SD2_DATA3, NULL);
+ gpio_request(GPIO_FN_SD2_CLK, NULL);
+ gpio_request(GPIO_FN_SD2_CMD, NULL);
+ gpio_request(GPIO_FN_SD2_CD, NULL);
+
+ /* SDHI 0 */
+ gpio_request(GPIO_GP_7_17, NULL);
+ gpio_request(GPIO_GP_2_12, NULL);
+ gpio_direction_output(GPIO_GP_7_17, 1); /* power on */
+ gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+ SH_SDHI_QUIRK_16BIT_BUF);
+ if (ret)
+ return ret;
+
+ /* SDHI 1 */
+ gpio_request(GPIO_GP_7_18, NULL);
+ gpio_request(GPIO_GP_2_13, NULL);
+ gpio_direction_output(GPIO_GP_7_18, 1); /* power on */
+ gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
+ if (ret)
+ return ret;
+
+ /* SDHI 2 */
+ gpio_request(GPIO_GP_7_19, NULL);
+ gpio_request(GPIO_GP_2_26, NULL);
+ gpio_direction_output(GPIO_GP_7_19, 1); /* power on */
+ gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
+#endif
+ return ret;
+}
+
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}
+
+static const struct sh_serial_platdata serial_platdata = {
+ .base = SCIF0_BASE,
+ .type = PORT_SCIF,
+ .clk = 14745600,
+ .clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(koelsch_serials) = {
+ .name = "serial_sh",
+ .platdata = &serial_platdata,
+};
#include <common.h>
#include <malloc.h>
#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
#include <miiphy.h>
#include <i2c.h>
#include <mmc.h>
#define ETHER_MSTP813 (1 << 13)
#define MMC1_MSTP305 (1 << 5)
+#define MSTPSR3 0xE6150048
+#define SMSTPCR3 0xE615013C
+#define SDHI0_MSTP314 (1 << 14)
+#define SDHI1_MSTP313 (1 << 13)
+#define SDHI2_MSTP312 (1 << 12)
+
+#define SD2CKCR 0xE6150078
+#define SD2_97500KHZ 0x7
+
int board_early_init_f(void)
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
/* eMMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
+ /* SDHI0, 2 */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD2_97500KHZ, SD2CKCR);
return 0;
}
int board_mmc_init(bd_t *bis)
{
- int ret = 0;
+ int ret = -ENODEV;
#ifdef CONFIG_SH_MMCIF
gpio_request(GPIO_FN_MMC1_D0, NULL);
ret = mmcif_mmc_init();
#endif
+
+#ifdef CONFIG_SH_SDHI
+ gpio_request(GPIO_FN_SD0_DAT0, NULL);
+ gpio_request(GPIO_FN_SD0_DAT1, NULL);
+ gpio_request(GPIO_FN_SD0_DAT2, NULL);
+ gpio_request(GPIO_FN_SD0_DAT3, NULL);
+ gpio_request(GPIO_FN_SD0_CLK, NULL);
+ gpio_request(GPIO_FN_SD0_CMD, NULL);
+ gpio_request(GPIO_FN_SD0_CD, NULL);
+ gpio_request(GPIO_FN_SD2_DAT0, NULL);
+ gpio_request(GPIO_FN_SD2_DAT1, NULL);
+ gpio_request(GPIO_FN_SD2_DAT2, NULL);
+ gpio_request(GPIO_FN_SD2_DAT3, NULL);
+ gpio_request(GPIO_FN_SD2_CLK, NULL);
+ gpio_request(GPIO_FN_SD2_CMD, NULL);
+ gpio_request(GPIO_FN_SD2_CD, NULL);
+
+ /*
+ * SDHI 0
+ * need JP3 set to pin-1 side on board.
+ */
+ gpio_request(GPIO_GP_5_24, NULL);
+ gpio_request(GPIO_GP_5_29, NULL);
+ gpio_direction_output(GPIO_GP_5_24, 1); /* power on */
+ gpio_direction_output(GPIO_GP_5_29, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+ SH_SDHI_QUIRK_16BIT_BUF);
+ if (ret)
+ return ret;
+
+ /* SDHI 2 */
+ gpio_request(GPIO_GP_5_25, NULL);
+ gpio_request(GPIO_GP_5_30, NULL);
+ gpio_direction_output(GPIO_GP_5_25, 1); /* power on */
+ gpio_direction_output(GPIO_GP_5_30, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
+#endif
return ret;
}
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}
+
+static const struct sh_serial_platdata serial_platdata = {
+ .base = SCIF0_BASE,
+ .type = PORT_SCIF,
+ .clk = 14745600,
+ .clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(lager_serials) = {
+ .name = "serial_sh",
+ .platdata = &serial_platdata,
+};
--- /dev/null
+if TARGET_PORTER
+
+config SYS_BOARD
+ default "porter"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "porter"
+
+endif
--- /dev/null
+PORTER BOARD
+M: Cogent Embedded, Inc. <source@cogentembedded.com>
+S: Maintained
+F: board/renesas/porter/
+F: include/configs/porter.h
+F: configs/porter_defconfig
--- /dev/null
+#
+# board/renesas/porter/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+# Copyright (C) 2015 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := porter.o qos.o ../rcar-gen2-common/common.o
--- /dev/null
+/*
+ * board/renesas/porter/porter.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* CPU frequency setting. Set to 1.5GHz */
+ stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+ /* QoS */
+ qos_init();
+}
+
+#define TMU0_MSTP125 (1 << 25)
+#define SDHI0_MSTP314 (1 << 14)
+#define SDHI2_MSTP311 (1 << 11)
+#define SCIF0_MSTP721 (1 << 21)
+#define ETHER_MSTP813 (1 << 13)
+
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
+int board_early_init_f(void)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ /* SCIF0 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+ /* SDHI */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP311);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD_97500KHZ, SD2CKCR);
+
+ return 0;
+}
+
+/* LSI pin pull-up control */
+#define PUPR5 0xe6060114
+#define PUPR5_ETH 0x3FFC0000
+#define PUPR5_ETH_MAGIC (1 << 27)
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7791_pinmux_init();
+
+ /* Ether Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ0, NULL);
+
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
+ gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
+
+ gpio_direction_output(GPIO_GP_5_22, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_5_22, 1);
+ udelay(1);
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+ int ret = -ENODEV;
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+
+#ifdef CONFIG_SH_SDHI
+ gpio_request(GPIO_FN_SD0_DATA0, NULL);
+ gpio_request(GPIO_FN_SD0_DATA1, NULL);
+ gpio_request(GPIO_FN_SD0_DATA2, NULL);
+ gpio_request(GPIO_FN_SD0_DATA3, NULL);
+ gpio_request(GPIO_FN_SD0_CLK, NULL);
+ gpio_request(GPIO_FN_SD0_CMD, NULL);
+ gpio_request(GPIO_FN_SD0_CD, NULL);
+ gpio_request(GPIO_FN_SD2_DATA0, NULL);
+ gpio_request(GPIO_FN_SD2_DATA1, NULL);
+ gpio_request(GPIO_FN_SD2_DATA2, NULL);
+ gpio_request(GPIO_FN_SD2_DATA3, NULL);
+ gpio_request(GPIO_FN_SD2_CLK, NULL);
+ gpio_request(GPIO_FN_SD2_CMD, NULL);
+ gpio_request(GPIO_FN_SD2_CD, NULL);
+
+ /* SDHI 0 */
+ gpio_request(GPIO_GP_2_12, NULL);
+ gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+ SH_SDHI_QUIRK_16BIT_BUF);
+ if (ret)
+ return ret;
+
+ /* SDHI 2 */
+ gpio_request(GPIO_GP_2_26, NULL);
+ gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
+#endif
+ return ret;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+/* porter has KSZ8041RNLI */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+ u8 val;
+
+ i2c_set_bus_num(2); /* PowerIC connected to ch2 */
+ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ val |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
+
+static const struct sh_serial_platdata serial_platdata = {
+ .base = SCIF0_BASE,
+ .type = PORT_SCIF,
+ .clk = CONFIG_P_CLK_FREQ,
+};
+
+U_BOOT_DEVICE(porter_serials) = {
+ .name = "serial_sh",
+ .platdata = &serial_platdata,
+};
--- /dev/null
+/*
+ * board/renesas/porter/qos.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+enum {
+ DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+ DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+ DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+ DBSC3_15,
+ DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_1_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_1_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_1_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_1_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_1_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_1_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_1_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_1_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_1_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_1_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_1_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_1_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_1_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_1_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_1_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_1_QOS_R15_BASE,
+};
+
+static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_1_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_1_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_1_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_1_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_1_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_1_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_1_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_1_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_1_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_1_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_1_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_1_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_1_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_1_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_1_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_1_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+ writel(0x20042004, DBSC3_1_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ if (IS_R8A7791_ES2()) {
+ /* Linear All mode */
+ /* writel(0x00000000, &s3c->s3cadsplcr); */
+ /* Linear Linear 0x7000 to 0x7800 mode */
+ writel(0x00BF1B0C, &s3c->s3cadsplcr);
+ /* Split Linear 0x6800 t 0x7000 mode */
+ /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */
+ /* Ssplit All mode */
+ /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */
+ writel(0x1F0B0908, &s3c->s3crorr);
+ writel(0x1F0C0A08, &s3c->s3cworr);
+ } else {
+ writel(0x00FF1B1D, &s3c->s3cadsplcr);
+ writel(0x1F0D0C0C, &s3c->s3crorr);
+ writel(0x1F0D0C0A, &s3c->s3cworr);
+ }
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20DC, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20DC, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20FA, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20FA, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00001FB0, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000201E, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002050, &qos_addr->dbtmval2);
+ writel(0x0000203A, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000203C, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC1 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00001FB0, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000201E, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC1 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002050, &qos_addr->dbtmval2);
+ writel(0x0000203A, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000203C, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* CCI-400 -QoS */
+ writel(0x20001000, CCI_400_MAXOT_1);
+ writel(0x20001000, CCI_400_MAXOT_2);
+ writel(0x0000000C, CCI_400_QOSCNTL_1);
+ writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxwtcr);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000C, &mxi_qos->vspdu1);
+ writel(0x0000000E, &mxi_qos->du0);
+ writel(0x0000000D, &mxi_qos->du1);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002299, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000206E, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ if (IS_R8A7791_ES2())
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ else
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2())
+ writel(0x00002001, &axi_qos->qosthres2);
+ else
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000000, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
--- /dev/null
+/*
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
#include <common.h>
#include <malloc.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#define ETHER_MSTP813 (1 << 13)
#define IIC1_MSTP323 (1 << 23)
#define MMC0_MSTP315 (1 << 15)
+#define SDHI1_MSTP312 (1 << 12)
+
+#define SD1CKCR 0xE6150078
+#define SD1_97500KHZ 0x7
int board_early_init_f(void)
{
/* MMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
#endif
+
+#ifdef CONFIG_SH_SDHI
+ /* SDHI1 */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312);
+
+ /*
+ * Set SD1 to the 97.5MHz
+ */
+ writel(SD1_97500KHZ, SD1CKCR);
+#endif
return 0;
}
+/* LSI pin pull-up control */
+#define PUPR3 0xe606010C
+#define PUPR3_ETH 0x006FF800
+#define PUPR1 0xe6060104
+#define PUPR1_DREQ0_N (1 << 20)
int board_init(void)
{
/* adress of boot parameters */
gpio_request(GPIO_FN_IRQ8, NULL);
/* PHY reset */
+ mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH);
gpio_request(GPIO_GP_1_24, NULL);
+ mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N);
+
gpio_direction_output(GPIO_GP_1_24, 0);
mdelay(20);
gpio_set_value(GPIO_GP_1_24, 1);
int board_mmc_init(bd_t *bis)
{
- int ret = 0;
+ int ret = -ENODEV;
#ifdef CONFIG_SH_MMCIF
/* MMC0 */
gpio_request(GPIO_GP_4_31, NULL);
- gpio_set_value(GPIO_GP_4_31, 1);
+ gpio_direction_output(GPIO_GP_4_31, 1);
ret = mmcif_mmc_init();
#endif
+
+#ifdef CONFIG_SH_SDHI
+ gpio_request(GPIO_FN_SD1_DATA0, NULL);
+ gpio_request(GPIO_FN_SD1_DATA1, NULL);
+ gpio_request(GPIO_FN_SD1_DATA2, NULL);
+ gpio_request(GPIO_FN_SD1_DATA3, NULL);
+ gpio_request(GPIO_FN_SD1_CLK, NULL);
+ gpio_request(GPIO_FN_SD1_CMD, NULL);
+ gpio_request(GPIO_FN_SD1_CD, NULL);
+
+ /* SDHI 1 */
+ gpio_request(GPIO_GP_4_26, NULL);
+ gpio_request(GPIO_GP_4_29, NULL);
+ gpio_direction_output(GPIO_GP_4_26, 1);
+ gpio_direction_output(GPIO_GP_4_29, 1);
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
+#endif
return ret;
}
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}
+
+static const struct sh_serial_platdata serial_platdata = {
+ .base = SCIF2_BASE,
+ .type = PORT_SCIF,
+ .clk = 14745600,
+ .clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(silk_serials) = {
+ .name = "serial_sh",
+ .platdata = &serial_platdata,
+};
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
-#ifdef CONFIG_SET_DFU_ALT_INFO
- set_dfu_alt_info();
-#endif
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
set_board_info();
#endif
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SET_DFU_ALT_INFO
-void set_dfu_alt_info(void)
+void set_dfu_alt_info(char *interface, char *devstr)
{
size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN;
ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size);
puts("DFU alt info setting: ");
- alt_setting = get_dfu_alt_boot();
+ alt_setting = get_dfu_alt_boot(interface, devstr);
if (alt_setting) {
setenv("dfu_alt_boot", alt_setting);
offset = snprintf(buf, buf_size, "%s", alt_setting);
}
- alt_setting = get_dfu_alt_system();
+ alt_setting = get_dfu_alt_system(interface, devstr);
if (alt_setting) {
if (offset)
alt_sep = ";";
#include <power/pmic.h>
#include <power/max77686_pmic.h>
#include <errno.h>
+#include <mmc.h>
#include <usb.h>
#include <usb/s3c_udc.h>
#include <samsung/misc.h>
#endif
#ifdef CONFIG_SET_DFU_ALT_INFO
-char *get_dfu_alt_system(void)
+char *get_dfu_alt_system(char *interface, char *devstr)
{
return getenv("dfu_alt_system");
}
-char *get_dfu_alt_boot(void)
+char *get_dfu_alt_boot(char *interface, char *devstr)
{
+ struct mmc *mmc;
char *alt_boot;
+ int dev_num;
+
+ dev_num = simple_strtoul(devstr, NULL, 10);
+
+ mmc = find_mmc_device(dev_num);
+ if (!mmc)
+ return NULL;
+
+ if (mmc_init(mmc))
+ return NULL;
+
+ alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
+ CONFIG_DFU_ALT_BOOT_EMMC;
- switch (get_boot_mode()) {
- case BOOT_MODE_SD:
- alt_boot = CONFIG_DFU_ALT_BOOT_SD;
- break;
- case BOOT_MODE_EMMC:
- case BOOT_MODE_EMMC_SD:
- alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
- break;
- default:
- alt_boot = NULL;
- break;
- }
return alt_boot;
}
#endif
AM335X BOARD
-M: Tom Rini <trini@ti.com>
+M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/am335x/
F: include/configs/am335x_evm.h
F: configs/am335x_evm_nor_defconfig
F: configs/am335x_evm_norboot_defconfig
F: configs/am335x_evm_spiboot_defconfig
-F: configs/am335x_evm_uart1_defconfig
-F: configs/am335x_evm_uart2_defconfig
-F: configs/am335x_evm_uart3_defconfig
-F: configs/am335x_evm_uart4_defconfig
-F: configs/am335x_evm_uart5_defconfig
F: configs/am335x_evm_usbspl_defconfig
BEAGLE BOARD
-M: Tom Rini <trini@ti.com>
+M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/beagle/
F: include/configs/omap3_beagle.h
EVM BOARD
-M: Tom Rini <trini@ti.com>
+M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/evm/
F: include/configs/omap3_evm.h
-F: configs/omap3_evm_defconfig
-
-OMAP3_EVM_QUICK_MMC BOARD
-#M: -
-S: Maintained
F: include/configs/omap3_evm_quick_mmc.h
-F: configs/omap3_evm_quick_mmc_defconfig
F: include/configs/omap3_evm_quick_nand.h
+F: configs/omap3_evm_defconfig
+F: configs/omap3_evm_quick_mmc_defconfig
F: configs/omap3_evm_quick_nand_defconfig
dcache_disable();
icache_disable();
- /* arch number of vpac270 */
+ /* arch number of Toradex Colibri PXA270 */
gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
/* adress of boot parameters */
if (ret)
return ret;
+ if (!g_dnl_board_usb_cable_connected()) {
+ puts("\rUSB cable not detected.\n" \
+ "Command exit.\n");
+ return CMD_RET_FAILURE;
+ }
+
while (1) {
if (g_dnl_detach())
break;
#include <part.h>
#include <aboot.h>
#include <sparse_format.h>
+#include <mmc.h>
#ifndef CONFIG_FASTBOOT_GPT_NAME
#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
void fastboot_fail(const char *s)
{
- strncpy(response_str, "FAIL", 4);
+ strncpy(response_str, "FAIL\0", 5);
strncat(response_str, s, RESPONSE_LEN - 4 - 1);
}
void fastboot_okay(const char *s)
{
- strncpy(response_str, "OKAY", 4);
+ strncpy(response_str, "OKAY\0", 5);
strncat(response_str, s, RESPONSE_LEN - 4 - 1);
}
write_raw_image(dev_desc, &info, cmd, download_buffer,
download_bytes);
}
+
+void fb_mmc_erase(const char *cmd, char *response)
+{
+ int ret;
+ block_dev_desc_t *dev_desc;
+ disk_partition_t info;
+ lbaint_t blks, blks_start, blks_size, grp_size;
+ struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
+ if (mmc == NULL) {
+ error("invalid mmc device");
+ fastboot_fail("invalid mmc device");
+ return;
+ }
+
+ /* initialize the response buffer */
+ response_str = response;
+
+ dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+ error("invalid mmc device");
+ fastboot_fail("invalid mmc device");
+ return;
+ }
+
+ ret = get_partition_info_efi_by_name(dev_desc, cmd, &info);
+ if (ret) {
+ error("cannot find partition: '%s'", cmd);
+ fastboot_fail("cannot find partition");
+ return;
+ }
+
+ /* Align blocks to erase group size to avoid erasing other partitions */
+ grp_size = mmc->erase_grp_size;
+ blks_start = (info.start + grp_size - 1) & ~(grp_size - 1);
+ if (info.size >= grp_size)
+ blks_size = (info.size - (blks_start - info.start)) &
+ (~(grp_size - 1));
+ else
+ blks_size = 0;
+
+ printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n",
+ blks_start, blks_start + blks_size);
+
+ blks = dev_desc->block_erase(dev_desc->dev, blks_start, blks_size);
+ if (blks != blks_size) {
+ error("failed erasing from device %d", dev_desc->dev);
+ fastboot_fail("failed erasing from device");
+ return;
+ }
+
+ printf("........ erased " LBAFU " bytes from '%s'\n",
+ blks_size * info.blksz, cmd);
+ fastboot_okay("");
+}
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_ALT=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SH_SDHI=y
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_GOSE=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SH_SDHI=y
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_KOELSCH=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SH_SDHI=y
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_LAGER=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SH_SDHI=y
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_I2C=y
+CONFIG_MACH_PH1_LD4=y
+CONFIG_PFC_MICRO_SUPPORT_CARD=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_UNIPHIER=y
-+S:CONFIG_MACH_PH1_LD4=y
-+S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BDI=y
CONFIG_CMD_CONSOLE=y
CONFIG_CMD_NFS=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
-CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_DM_SERIAL=y
+CONFIG_SPL_NAND_DENALI=y
CONFIG_UNIPHIER_SERIAL=y
-CONFIG_DM_I2C=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_SPL_NAND_DENALI=y
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_I2C=y
+CONFIG_MACH_PH1_PRO4=y
+CONFIG_PFC_MICRO_SUPPORT_CARD=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_UNIPHIER=y
-+S:CONFIG_MACH_PH1_PRO4=y
-+S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BDI=y
CONFIG_CMD_CONSOLE=y
CONFIG_CMD_NFS=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
-CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_DM_SERIAL=y
+CONFIG_SPL_NAND_DENALI=y
CONFIG_UNIPHIER_SERIAL=y
-CONFIG_DM_I2C=y
CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_SPL_NAND_DENALI=y
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_I2C=y
+CONFIG_MACH_PH1_SLD8=y
+CONFIG_PFC_MICRO_SUPPORT_CARD=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_UNIPHIER=y
-+S:CONFIG_MACH_PH1_SLD8=y
-+S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BDI=y
CONFIG_CMD_CONSOLE=y
CONFIG_CMD_NFS=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
-CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_DM_SERIAL=y
+CONFIG_SPL_NAND_DENALI=y
CONFIG_UNIPHIER_SERIAL=y
-CONFIG_DM_I2C=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_SPL_NAND_DENALI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_RMOBILE=y
+CONFIG_TARGET_PORTER=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SH_SDHI=y
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_SILK=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SH_SDHI=y
The protocol that is used over USB is described in
README.android-fastboot-protocol in same directory.
-The current implementation does not yet support the erase command or the
-"oem format" command, and there is minimal support for the flash command;
-it only supports eMMC devices.
+The current implementation is a minimal support of the erase command,the
+"oem format" command and flash command;it only supports eMMC devices.
Client installation
===================
- UART (on-chip)
- NAND
- - USB (2.0)
+ - USB 2.0 (EHCI)
+ - USB 3.0 (xHCI)
- LAN (on-board SMSC9118)
- I2C
- EEPROM (connected to the on-board I2C bus)
alias smcnutt Scott McNutt <smcnutt@psyent.com>
alias sonic Sonic Zhang <sonic.adi@gmail.com>
alias stroese Stefan Roese <sr@denx.de>
-alias trini Tom Rini <trini@ti.com>
+alias trini Tom Rini <trini@konsulko.com>
alias vapier Mike Frysinger <vapier@gentoo.org>
alias wd Wolfgang Denk <wd@denx.de>
char *env_bkp;
int ret;
+#ifdef CONFIG_SET_DFU_ALT_INFO
+ set_dfu_alt_info(interface, devstr);
+#endif
str_env = getenv("dfu_alt_info");
if (!str_env) {
error("\"dfu_alt_info\" env variable not defined!\n");
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
return in_be32(addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
- return readb(addr + (1 << reg_shift) - 1);
+ return readb(addr + (1 << shift) - 1);
#else
return readb(addr);
#endif
if (port->clk_mode == EXT_CLK) {
unsigned short dl = DL_VALUE(baudrate, clk);
sci_out(port, DL, dl);
- /* Need wait: Clock * 1/dl \e$B!_\e(B 1/16 */
+ /* Need wait: Clock * 1/dl * 1/16 */
udelay((1000000 * dl * 16 / clk) * 1000 + 1);
} else {
sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ORER 0x0001
-# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
+# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
+ /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
# error CPU subtype not defined
#endif
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */
+#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
/*
- * Copyright (C) 2012-2014 Panasonic Corporation
+ * Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
#include <serial.h>
#include <fdtdec.h>
-#define UART_REG(x) \
- u8 x; \
- u8 postpad_##x[3];
-
/*
* Note: Register map is slightly different from that of 16550.
*/
struct uniphier_serial {
- UART_REG(rbr); /* 0x00 */
- UART_REG(ier); /* 0x04 */
- UART_REG(iir); /* 0x08 */
- UART_REG(fcr); /* 0x0c */
- u8 mcr; /* 0x10 */
- u8 lcr;
- u16 __postpad;
- UART_REG(lsr); /* 0x14 */
- UART_REG(msr); /* 0x18 */
- u32 __none1;
- u32 __none2;
- u16 dlr;
- u16 __postpad2;
+ u32 rx; /* In: Receive buffer */
+#define tx rx /* Out: Transmit buffer */
+ u32 ier; /* Interrupt Enable Register */
+ u32 iir; /* In: Interrupt ID Register */
+ u32 char_fcr; /* Charactor / FIFO Control Register */
+ u32 lcr_mcr; /* Line/Modem Control Register */
+#define LCR_SHIFT 8
+#define LCR_MASK (0xff << (LCR_SHIFT))
+ u32 lsr; /* In: Line Status Register */
+ u32 msr; /* In: Modem Status Register */
+ u32 __rsv0;
+ u32 __rsv1;
+ u32 dlr; /* Divisor Latch Register */
};
-#define thr rbr
-
struct uniphier_serial_private_data {
struct uniphier_serial __iomem *membase;
};
const unsigned int mode_x_div = 16;
unsigned int divisor;
- writeb(UART_LCR_WLEN8, &port->lcr);
-
divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
- writew(divisor, &port->dlr);
+ writel(divisor, &port->dlr);
return 0;
}
{
struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
- if (!(readb(&port->lsr) & UART_LSR_DR))
+ if (!(readl(&port->lsr) & UART_LSR_DR))
return -EAGAIN;
- return readb(&port->rbr);
+ return readl(&port->rx);
}
static int uniphier_serial_putc(struct udevice *dev, const char c)
{
struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
- if (!(readb(&port->lsr) & UART_LSR_THRE))
+ if (!(readl(&port->lsr) & UART_LSR_THRE))
return -EAGAIN;
- writeb(c, &port->thr);
+ writel(c, &port->tx);
return 0;
}
struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
if (input)
- return readb(&port->lsr) & UART_LSR_DR;
+ return readl(&port->lsr) & UART_LSR_DR;
else
- return !(readb(&port->lsr) & UART_LSR_THRE);
+ return !(readl(&port->lsr) & UART_LSR_THRE);
}
static int uniphier_serial_probe(struct udevice *dev)
{
+ u32 tmp;
struct uniphier_serial_private_data *priv = dev_get_priv(dev);
struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+ struct uniphier_serial __iomem *port;
- priv->membase = map_sysmem(plat->base, sizeof(struct uniphier_serial));
-
- if (!priv->membase)
+ port = map_sysmem(plat->base, sizeof(struct uniphier_serial));
+ if (!port)
return -ENOMEM;
+ priv->membase = port;
+
+ tmp = readl(&port->lcr_mcr);
+ tmp &= ~LCR_MASK;
+ tmp |= UART_LCR_WLEN8 << LCR_SHIFT;
+ writel(tmp, &port->lcr_mcr);
+
return 0;
}
static struct f_fastboot *fastboot_func;
static unsigned int download_size;
static unsigned int download_bytes;
+static bool is_high_speed;
static struct usb_endpoint_descriptor fs_ep_in = {
.bLength = USB_DT_ENDPOINT_SIZE,
int id;
struct usb_gadget *gadget = c->cdev->gadget;
struct f_fastboot *f_fb = func_to_fastboot(f);
+ const char *s;
/* DYNAMIC interface numbers assignments */
id = usb_interface_id(c, f);
hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
+ s = getenv("serial#");
+ if (s)
+ g_dnl_set_serialnumber((char *)s);
+
return 0;
}
__func__, f->name, interface, alt);
/* make sure we don't enable the ep twice */
- if (gadget->speed == USB_SPEED_HIGH)
+ if (gadget->speed == USB_SPEED_HIGH) {
ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out);
- else
+ is_high_speed = true;
+ } else {
ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out);
+ is_high_speed = false;
+ }
if (ret) {
puts("failed to enable out ep\n");
return ret;
fastboot_tx_write_str(response);
}
-static unsigned int rx_bytes_expected(void)
+static unsigned int rx_bytes_expected(unsigned int maxpacket)
{
int rx_remain = download_size - download_bytes;
+ int rem = 0;
if (rx_remain < 0)
return 0;
if (rx_remain > EP_BUFFER_SIZE)
return EP_BUFFER_SIZE;
+ if (rx_remain < maxpacket) {
+ rx_remain = maxpacket;
+ } else if (rx_remain % maxpacket != 0) {
+ rem = rx_remain % maxpacket;
+ rx_remain = rx_remain + (maxpacket - rem);
+ }
return rx_remain;
}
const unsigned char *buffer = req->buf;
unsigned int buffer_size = req->actual;
unsigned int pre_dot_num, now_dot_num;
+ unsigned int max;
if (req->status != 0) {
printf("Bad status: %d\n", req->status);
printf("\ndownloading of %d bytes finished\n", download_bytes);
} else {
- req->length = rx_bytes_expected();
+ max = is_high_speed ? hs_ep_out.wMaxPacketSize :
+ fs_ep_out.wMaxPacketSize;
+ req->length = rx_bytes_expected(max);
if (req->length < ep->maxpacket)
req->length = ep->maxpacket;
}
{
char *cmd = req->buf;
char response[RESPONSE_LEN];
+ unsigned int max;
strsep(&cmd, ":");
download_size = simple_strtoul(cmd, NULL, 16);
} else {
sprintf(response, "DATA%08x", download_size);
req->complete = rx_handler_dl_image;
- req->length = rx_bytes_expected();
+ max = is_high_speed ? hs_ep_out.wMaxPacketSize :
+ fs_ep_out.wMaxPacketSize;
+ req->length = rx_bytes_expected(max);
if (req->length < ep->maxpacket)
req->length = ep->maxpacket;
}
}
#endif
+static void cb_oem(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+#ifdef CONFIG_FASTBOOT_FLASH
+ if (strncmp("format", cmd + 4, 6) == 0) {
+ char cmdbuf[32];
+ sprintf(cmdbuf, "gpt write mmc %x $partitions",
+ CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (run_command(cmdbuf, 0))
+ fastboot_tx_write_str("FAIL");
+ else
+ fastboot_tx_write_str("OKAY");
+ } else
+#endif
+ if (strncmp("unlock", cmd + 4, 8) == 0) {
+ fastboot_tx_write_str("FAILnot implemented");
+ }
+ else {
+ fastboot_tx_write_str("FAILunknown oem command");
+ }
+}
+
+#ifdef CONFIG_FASTBOOT_FLASH
+static void cb_erase(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+ char response[RESPONSE_LEN];
+
+ strsep(&cmd, ":");
+ if (!cmd) {
+ error("missing partition name");
+ fastboot_tx_write_str("FAILmissing partition name");
+ return;
+ }
+
+ strcpy(response, "FAILno flash device defined");
+
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+ fb_mmc_erase(cmd, response);
+#endif
+ fastboot_tx_write_str(response);
+}
+#endif
+
struct cmd_dispatch_info {
char *cmd;
void (*cb)(struct usb_ep *ep, struct usb_request *req);
{
.cmd = "flash",
.cb = cb_flash,
+ }, {
+ .cmd = "erase",
+ .cb = cb_erase,
},
#endif
+ {
+ .cmd = "oem",
+ .cb = cb_oem,
+ },
};
static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
if USB_XHCI_HCD
+config USB_XHCI_UNIPHIER
+ bool "Support for Panasonic UniPhier on-chip xHCI USB controller"
+ depends on ARCH_UNIPHIER
+ default y
+ ---help---
+ Enables support for the on-chip xHCI controller on Panasonic
+ UniPhier SoCs.
+
endif
config USB_EHCI_HCD
config USB_EHCI_UNIPHIER
bool "Support for Panasonic UniPhier on-chip EHCI USB controller"
- depends on ARCH_UNIPHIER
+ depends on ARCH_UNIPHIER && OF_CONTROL
default y
---help---
Enables support for the on-chip EHCI controller on Panasonic
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
+obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
#include <common.h>
#include <linux/err.h>
+#include <asm/io.h>
#include <usb.h>
-#include <asm/arch/ehci-uniphier.h>
+#include <mach/mio-regs.h>
+#include <fdtdec.h>
#include "ehci.h"
-#ifdef CONFIG_OF_CONTROL
-#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
#define FDT gd->fdt_blob
return -ENODEV; /* not found */
}
-#else
-static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+
+static void uniphier_ehci_reset(int index, int on)
{
- *base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base;
- return 0;
+ u32 tmp;
+
+ tmp = readl(MIO_USB_RSTCTRL(index));
+ if (on)
+ tmp &= ~MIO_USB_RSTCTRL_XRST;
+ else
+ tmp |= MIO_USB_RSTCTRL_XRST;
+ writel(tmp, MIO_USB_RSTCTRL(index));
}
-#endif
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
{
set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
}
-void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(&dwc3_reg->g_ctl,
DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
--- /dev/null
+/*
+ * Copyright (C) 2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <usb.h>
+#include <fdtdec.h>
+#include "xhci.h"
+
+static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ int node_list[2];
+ fdt_addr_t addr;
+ int count;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
+ COMPAT_PANASONIC_XHCI, node_list,
+ ARRAY_SIZE(node_list));
+
+ if (index >= count)
+ return -ENODEV;
+
+ addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ *base = (struct xhci_hccr *)addr;
+
+ return 0;
+}
+
+#define USB3_RST_CTRL 0x00100040
+#define IOMMU_RST_N (1 << 5)
+#define LINK_RST_N (1 << 4)
+
+static void uniphier_xhci_reset(void __iomem *base, int on)
+{
+ u32 tmp;
+
+ tmp = readl(base + USB3_RST_CTRL);
+
+ if (on)
+ tmp &= ~(IOMMU_RST_N | LINK_RST_N);
+ else
+ tmp |= IOMMU_RST_N | LINK_RST_N;
+
+ writel(tmp, base + USB3_RST_CTRL);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ int ret;
+ struct xhci_hccr *cr;
+ struct xhci_hcor *or;
+
+ ret = get_uniphier_xhci_base(index, &cr);
+ if (ret < 0)
+ return ret;
+
+ uniphier_xhci_reset(cr, 0);
+
+ or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
+
+ *hccr = cr;
+ *hcor = or;
+
+ return 0;
+}
+
+void xhci_hcd_stop(int index)
+{
+ int ret;
+ struct xhci_hccr *cr;
+
+ ret = get_uniphier_xhci_base(index, &cr);
+ if (ret < 0)
+ return;
+
+ uniphier_xhci_reset(cr, 1);
+}
{
u32 l;
int status = 0;
+ unsigned long int start;
#ifndef __UBOOT__
struct device *dev = musb->controller;
struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
(struct omap_musb_board_data *)musb->controller;
#endif
+ /* Reset the controller */
+ musb_writel(musb->mregs, OTG_SYSCONFIG, SOFTRST);
+
+ start = get_timer(0);
+
+ while (1) {
+ l = musb_readl(musb->mregs, OTG_SYSCONFIG);
+ if ((l & SOFTRST) == 0)
+ break;
+
+ if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ dev_err(musb->controller, "MUSB reset is taking too long\n");
+ return -ENODEV;
+ }
+ }
#ifndef __UBOOT__
/* We require some kind of external transceiver, hooked
/* SCIF */
#define CONFIG_SCIF_CONSOLE
-#define CONFIG_CONS_SCIF2
-#define CONFIG_SCIF_USE_EXT_CLK
/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
-#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */
#define CONFIG_SYS_TMU_CLK_DIV 4
/* SCIF2 */
#define CONFIG_SMSTP7_ENA 0x00080000
+/* SDHI */
+#define CONFIG_SH_SDHI_FREQ 97500000
+
#endif /* __ALT_H */
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100MKII
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
* High Level Board Configuration Options
*/
#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-#define CONFIG_BALLOON3 1 /* Balloon3 board */
+#define CONFIG_BALLOON3 1 /* Balloon3 board */
/*
* Environment settings
/*
* Clock Configuration
*/
-#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
/*
* DRAM Map
*/
-#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
-#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
#define CONFIG_ENV_IS_IN_FLASH
#else
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_SYS_MONITOR_BASE 0x000000
#define CONFIG_SYS_MDMRS_VAL 0x00220022
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-#define CONFIG_SYS_MEM_BUF_IMP 0x0f
/*
* PCMCIA and CF Interfaces
* Toradex Colibri PXA270 configuration file
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_H
+#define __CONFIG_H
/*
* High Level Board Configuration Options
*/
#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_TEXT_BASE 0x0
+/* Avoid overwriting factory configuration block */
+#define CONFIG_BOARD_SIZE_LIMIT 0x40000
/*
* Environment settings
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
- "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \
+ "if fatload mmc 0 0xa0000000 uImage; then " \
"bootm 0xa0000000; " \
"fi; " \
"if usb reset && fatload usb 0 0xa0000000 uImage; then " \
"bootm 0xa0000000; " \
"fi; " \
- "bootm 0x80000;"
+ "bootm 0xc0000;"
#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
#define CONFIG_TIMESTAMP
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
*/
#include <config_cmd_default.h>
+#undef CONFIG_CMD_LOADB /* Both together */
+#undef CONFIG_CMD_LOADS /* saves 10 KB */
#define CONFIG_CMD_NET
#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS
/*
* Networking Configuration
- * chip on the Voipac PXA270 board
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_PING
*/
#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_LONGHELP
+#undef CONFIG_SYS_LONGHELP /* Saves 10 KB */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ "
#else
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE 1
-
/*
* Clock Configuration
*/
#else /* No flash */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_SYS_MONITOR_BASE 0x0
-#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+/* Skip factory configuration block */
#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
#define CONFIG_ENV_SIZE 0x40000
#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/*
* GPIO settings
*/
#define CONFIG_SYS_GPSR0_VAL 0x00000000
#define CONFIG_SYS_GPSR1_VAL 0x00020000
-#define CONFIG_SYS_GPSR2_VAL 0x0002C000
+#define CONFIG_SYS_GPSR2_VAL 0x0002c000
#define CONFIG_SYS_GPSR3_VAL 0x00000000
#define CONFIG_SYS_GPCR0_VAL 0x00000000
#define CONFIG_SYS_GPCR2_VAL 0x00000000
#define CONFIG_SYS_GPCR3_VAL 0x00000000
-#define CONFIG_SYS_GPDR0_VAL 0x08000000
-#define CONFIG_SYS_GPDR1_VAL 0x0002A981
-#define CONFIG_SYS_GPDR2_VAL 0x0202FC00
-#define CONFIG_SYS_GPDR3_VAL 0x00000000
+#define CONFIG_SYS_GPDR0_VAL 0xc8008000
+#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
+#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
+#define CONFIG_SYS_GPDR3_VAL 0x0061e804
-#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
-#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010
-#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A
-#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008
-#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
-#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000
-#define CONFIG_SYS_GAFR3_L_VAL 0x54000300
-#define CONFIG_SYS_GAFR3_U_VAL 0x00024001
+#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
+#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
+#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
+#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
+#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
#define CONFIG_SYS_PSSR_VAL 0x30
/*
* Memory settings
*/
-#define CONFIG_SYS_MSC0_VAL 0x000095f2
-#define CONFIG_SYS_MSC1_VAL 0x00007ff4
-#define CONFIG_SYS_MSC2_VAL 0x00000000
-#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9
-#define CONFIG_SYS_MDREFR_VAL 0x2013e01e
-#define CONFIG_SYS_MDMRS_VAL 0x00320032
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
+#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
+#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
+#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
+#define CONFIG_SYS_MDREFR_VAL 0x2003a031
+#define CONFIG_SYS_MDMRS_VAL 0x00220022
+#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
/*
* PCMCIA and CF Interfaces
*/
-#define CONFIG_SYS_MECR_VAL 0x00000001
-#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MECR_VAL 0x00000000
+#define CONFIG_SYS_MCMEM0_VAL 0x00028307
#define CONFIG_SYS_MCMEM1_VAL 0x00014307
-#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT0_VAL 0x00038787
#define CONFIG_SYS_MCATT1_VAL 0x0001c787
-#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO0_VAL 0x0002830f
#define CONFIG_SYS_MCIO1_VAL 0x0001430f
#include "pxa-common.h"
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_H */
#define CONFIG_BOARD_REV_GPIO_COUNT 2
+#define CONFIG_PHY_IRAM_BASE 0x02020000
+
+/* Address for relocating helper code (Last 4 KB of IRAM) */
+#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000)
+
+/*
+ * Low Power settings
+ */
+#define CONFIG_LOWPOWER_FLAG 0x02020028
+#define CONFIG_LOWPOWER_ADDR 0x0202002C
+
+/*
+ * Number of CPUs available
+ */
+#define CONFIG_CORE_COUNT 0x8
+
#endif /* __CONFIG_EXYNOS5420_H */
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10000
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*
/* SCIF */
#define CONFIG_SCIF_CONSOLE
-#define CONFIG_CONS_SCIF0
-#define CONFIG_SCIF_USE_EXT_CLK
/* FLASH */
#define CONFIG_SYS_NO_FLASH
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_SH_SCIF_CLK_FREQ 14745600
#define CONFIG_SYS_TMU_CLK_DIV 4
/* I2C */
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
+/* SDHI */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SH_SDHI_FREQ 97500000
+
#endif /* __GOSE_H */
/* SCIF */
#define CONFIG_SCIF_CONSOLE
-#define CONFIG_CONS_SCIF0
-#define CONFIG_SCIF_USE_EXT_CLK
/* FLASH */
#define CONFIG_SYS_NO_FLASH
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_SH_SCIF_CLK_FREQ 14745600
#define CONFIG_SYS_TMU_CLK_DIV 4
/* i2c */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
-
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
+/* SD */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SH_SDHI_FREQ 97500000
+
#endif /* __KOELSCH_H */
/* SCIF */
#define CONFIG_SCIF_CONSOLE
-#define CONFIG_CONS_SCIF0
-#define CONFIG_SCIF_USE_EXT_CLK
/* SPI */
#define CONFIG_SPI
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
-#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */
#define CONFIG_SYS_TMU_CLK_DIV 4
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
+/* SDHI */
+#define CONFIG_SH_SDHI_FREQ 97500000
+
#endif /* __LAGER_H */
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10000
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*
/*
* Clock Configuration
*/
-#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
/*
/*
* Clock Configuration
*/
-#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
/*
/*
* Clock Configuration
*/
-#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
/*
--- /dev/null
+/*
+ * include/configs/porter.h
+ * This file is Porter board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __PORTER_H
+#define __PORTER_H
+
+#undef DEBUG
+#define CONFIG_R8A7791
+#define CONFIG_RMOBILE_BOARD_STRING "Porter"
+
+#include "rcar-gen2-common.h"
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x70000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0xE6304000
+#endif
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
+#endif
+#define STACK_AREA_SIZE 0xC000
+#define LOW_LEVEL_MERAM_STACK \
+ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE 0x40000000
+#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+
+/* FLASH */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_QUAD
+#define CONFIG_SYS_NO_FLASH
+
+/* SH Ether */
+#define CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK 20000000u
+#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
+#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
+#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
+
+#define CONFIG_SYS_TMU_CLK_DIV 4
+
+/* i2c */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
+#define CONFIG_SYS_I2C_SH_SPEED0 400000
+#define CONFIG_SYS_I2C_SH_SPEED1 400000
+#define CONFIG_SYS_I2C_SH_SPEED2 400000
+#define CONFIG_SH_I2C_DATA_HIGH 4
+#define CONFIG_SH_I2C_DATA_LOW 5
+#define CONFIG_SH_I2C_CLOCK 10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_RMOBILE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_STORAGE
+
+/* SD */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SH_SDHI_FREQ 97500000
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA 0x00400000
+/* MSIF */
+#define CONFIG_SMSTP2_ENA 0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA 0x00000180
+/* SCIF0 */
+#define CONFIG_SMSTP7_ENA 0x00200000
+
+#endif /* __PORTER_H */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+
/* Support File sytems */
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION
/* SCIF */
#define CONFIG_SCIF_CONSOLE
-#define CONFIG_CONS_SCIF2
-#define CONFIG_SCIF_USE_EXT_CLK
/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
-#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SH_MMCIF_ADDR 0xee200000
#define CONFIG_SH_MMCIF_CLK 48000000
+/* SDHI */
+#define CONFIG_SH_SDHI_FREQ 97500000
+
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
-#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
#define CONFIG_CMD_ASKEN
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
#define CONFIG_SYS_LOADS_BAUD_CHANGE
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
/* Comment out the following to enable L2 cache */
#define CONFIG_UNIPHIER_L2CACHE_ON
/* USB */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
/* Miscellaneous configurable options */
-#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
#define CONFIG_BOOTDELAY 2
#else /* No flash */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_NOWHERE
#endif
/*
#define CONFIG_SYS_MDMRS_VAL 0x00000000
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-#define CONFIG_SYS_MEM_BUF_IMP 0x0f
/*
* PCMCIA and CF Interfaces
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10000
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*
/*
* Clock Configuration
*/
-#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
/*
unsigned int inited:1;
};
+#ifdef CONFIG_SET_DFU_ALT_INFO
+void set_dfu_alt_info(char *interface, char *devstr);
+#endif
int dfu_config_entities(char *s, char *interface, char *devstr);
void dfu_free_entities(void);
void dfu_show_entities(void);
void fb_mmc_flash_write(const char *cmd, void *download_buffer,
unsigned int download_bytes, char *response);
+void fb_mmc_erase(const char *cmd, char *response);
COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */
COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
+ COMPAT_PANASONIC_XHCI, /* Panasonic UniPhier xHCI */
COMPAT_COUNT,
};
#endif
#ifdef CONFIG_SET_DFU_ALT_INFO
-char *get_dfu_alt_system(void);
-char *get_dfu_alt_boot(void);
-void set_dfu_alt_info(void);
+char *get_dfu_alt_system(char *interface, char *devstr);
+char *get_dfu_alt_boot(char *interface, char *devstr);
#endif
#ifdef CONFIG_BOARD_TYPES
void set_board_type(void);
COMPAT(AMS_AS3722, "ams,as3722"),
COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
+ COMPAT(PANASONIC_XHCI, "panasonic,uniphier-xhci"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
FILE *out, *tristate, *out_h;
int i;
- /*
- * Added for U-Boot SPL/TPL
- */
- name = getenv("KCONFIG_OBJDIR");
- if (name && name[0])
- if (chdir(name))
- return 1;
-
sym_clear_all_valid();
file_write_dep("include/config/auto.conf.cmd");
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