arm: socfpga: config: Move SPL GD and malloc to RAM

Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for SPL because it is 3kiB smaller
in terms of code size than regular malloc which was used thus far.

Signed-off-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 82570f86174fd8b003158102cea0a0196aa4fead..13ec24bc169ef2ffb32fe4affa58985756dee5c6 100644 (file)
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -178,5 +178,8 @@ void board_init_f(ulong dummy)
 
        socfpga_bridges_reset(1);
 
+       /* Configure simple malloc base pointer into RAM. */
+       gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
+
        board_init_r(NULL, 0);
 }

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index ee03156046a420c567aceaedf173e4367b894ac8..4d1cd21c1510b726fcc0c4e7d3f96cd3b0959df6 100644 (file)
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -14,3 +14,6 @@ CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000

diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 75ed347f0ecc20827b089aaa8facf4908572b908..ae3a1dea91197b3c7e2a7487f73a790b3e8eb9ea 100644 (file)
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -17,3 +17,6 @@ CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000

diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 2e50ce9a2c601067b7b8fb8261c2bf38210fecba..71d47116791a041dd996a877143dbe1c810a47e7 100644 (file)
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -17,3 +17,6 @@ CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index bed8600a94a109559744bc8283d5120c33b67a26..60a602517f97e4793fe7796e1d606ad862d5396a 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -39,10 +39,11 @@
 #define CONFIG_SYS_MEMTEST_END         PHYS_SDRAM_1_SIZE
 
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE       (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR                                        \
-       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -  \
-       GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       0x10000
+#define CONFIG_SYS_INIT_SP_OFFSET              \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR                        \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
@@ -290,9 +291,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_RAM_DEVICE
 #define CONFIG_SPL_TEXT_BASE           CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_SPL_MALLOC_START    CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_SPL_MALLOC_SIZE     (5 * 1024)
 #define CONFIG_SPL_MAX_SIZE            (64 * 1024)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
 
 #define CHUNKSZ_CRC32                  (1 * 1024)      /* FIXME: ewww */
 #define CONFIG_CRC32_VERIFY