AT91SAM9RLEK: hook up the ATMEL LCD driver

This patch makes the necessary adaptations (PIO configurations and
defines in config header file) to hook up the Atmel LCD driver to the
AT91SAM9RLEK board.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 8deecfd8ce54e008a039aeffa48397de9509cb96..10423d25928128b8090a27de87678a01f3dad916 100644 (file)
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -30,6 +30,8 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
@@ -124,6 +126,64 @@ static void at91sam9rlek_spi_hw_init(void)
 }
 #endif
 
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+       vl_col:         240,
+       vl_row:         320,
+       vl_clk:         4965000,
+       vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
+                       ATMEL_LCDC_INVFRAME_INVERTED,
+       vl_bpix:        3,
+       vl_tft:         1,
+       vl_hsync_len:   5,
+       vl_left_margin: 1,
+       vl_right_margin:33,
+       vl_vsync_len:   1,
+       vl_upper_margin:1,
+       vl_lower_margin:0,
+       mmio:           AT91SAM9RL_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+       at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+       at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
+}
+static void at91sam9rlek_lcd_hw_init(void)
+{
+       at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
+       at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
+       at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
+       at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
+       at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
+       at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
+       at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
+       at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
+       at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
+       at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
+       at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
+       at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
+       at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
+       at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
+       at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
+       at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
+       at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
+       at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
+       at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
+       at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
+       at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
+
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
+
+       gd->fb_base = 0;
+}
+#endif
+
+
 int board_init(void)
 {
        /* Enable Ctrlc */
@@ -140,6 +200,9 @@ int board_init(void)
 #endif
 #ifdef CONFIG_HAS_DATAFLASH
        at91sam9rlek_spi_hw_init();
+#endif
+#ifdef CONFIG_LCD
+       at91sam9rlek_lcd_hw_init();
 #endif
        return 0;
 }

diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 773f954ddcfd5f7a0fef19045e2fa274fbd071f8..33d934f08cdd895cc0dd6e5a43a726dd15ac02e9 100644 (file)
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -28,6 +28,7 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
+#define AT91_CPU_NAME          "AT91SAM9RL"
 #define AT91_MAIN_CLOCK                200000000       /* from 12.000 MHz crystal */
 #define AT91_MASTER_CLOCK      100000000       /* peripheral = main / 2 */
 #define CFG_HZ                 1000000         /* 1us resolution */
@@ -55,6 +56,18 @@
 #undef CONFIG_USART2
 #define CONFIG_USART3          1       /* USART 3 is DBGU */
 
+/* LCD */
+#define CONFIG_LCD                     1
+#define LCD_BPP                                LCD_COLOR8
+#define CONFIG_LCD_LOGO                        1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO                        1
+#define CONFIG_LCD_INFO_BELOW_LOGO     1
+#define CFG_WHITE_ON_BLACK             1
+#define CONFIG_ATMEL_LCD               1
+#define CONFIG_ATMEL_LCD_RGB565                1
+#define CFG_CONSOLE_IS_IN_ENV          1
+
 #define CONFIG_BOOTDELAY       3
 
 /* #define CONFIG_ENV_OVERWRITE        1 */